drivers/spi/spi-mt65xx.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Leilk Liu <leilk.liu@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/platform_data/spi-mt65xx.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/spi/spi.h>
  28
  29 #define SPI_CFG0_REG                      0x0000
  30 #define SPI_CFG1_REG                      0x0004
  31 #define SPI_TX_SRC_REG                    0x0008
  32 #define SPI_RX_DST_REG                    0x000c
  33 #define SPI_TX_DATA_REG                   0x0010
  34 #define SPI_RX_DATA_REG                   0x0014
  35 #define SPI_CMD_REG                       0x0018
  36 #define SPI_STATUS0_REG                   0x001c
  37 #define SPI_PAD_SEL_REG                   0x0024
  38 #define SPI_CFG2_REG                      0x0028
  39
  40 #define SPI_CFG0_SCK_HIGH_OFFSET          0
  41 #define SPI_CFG0_SCK_LOW_OFFSET           8
  42 #define SPI_CFG0_CS_HOLD_OFFSET           16
  43 #define SPI_CFG0_CS_SETUP_OFFSET          24
  44 #define SPI_ADJUST_CFG0_SCK_LOW_OFFSET    16
  45 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET    0
  46 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET   16
  47
  48 #define SPI_CFG1_CS_IDLE_OFFSET           0
  49 #define SPI_CFG1_PACKET_LOOP_OFFSET       8
  50 #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
  51 #define SPI_CFG1_GET_TICK_DLY_OFFSET      30
  52
  53 #define SPI_CFG1_CS_IDLE_MASK             0xff
  54 #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
  55 #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
  56
  57 #define SPI_CMD_ACT                  BIT(0)
  58 #define SPI_CMD_RESUME               BIT(1)
  59 #define SPI_CMD_RST                  BIT(2)
  60 #define SPI_CMD_PAUSE_EN             BIT(4)
  61 #define SPI_CMD_DEASSERT             BIT(5)
  62 #define SPI_CMD_SAMPLE_SEL           BIT(6)
  63 #define SPI_CMD_CS_POL               BIT(7)
  64 #define SPI_CMD_CPHA                 BIT(8)
  65 #define SPI_CMD_CPOL                 BIT(9)
  66 #define SPI_CMD_RX_DMA               BIT(10)
  67 #define SPI_CMD_TX_DMA               BIT(11)
  68 #define SPI_CMD_TXMSBF               BIT(12)
  69 #define SPI_CMD_RXMSBF               BIT(13)
  70 #define SPI_CMD_RX_ENDIAN            BIT(14)
  71 #define SPI_CMD_TX_ENDIAN            BIT(15)
  72 #define SPI_CMD_FINISH_IE            BIT(16)
  73 #define SPI_CMD_PAUSE_IE             BIT(17)
  74
  75 #define MT8173_SPI_MAX_PAD_SEL 3
  76
  77 #define MTK_SPI_PAUSE_INT_STATUS 0x2
  78
  79 #define MTK_SPI_IDLE 0
  80 #define MTK_SPI_PAUSED 1
  81
  82 #define MTK_SPI_MAX_FIFO_SIZE 32U
  83 #define MTK_SPI_PACKET_SIZE 1024
  84
  85 struct mtk_spi_compatible {
  86         bool need_pad_sel;
  87         /* Must explicitly send dummy Tx bytes to do Rx only transfer */
  88         bool must_tx;
  89         /* some IC design adjust cfg register to enhance time accuracy */
  90         bool enhance_timing;
  91 };
  92
  93 struct mtk_spi {
  94         void __iomem *base;
  95         u32 state;
  96         int pad_num;
  97         u32 *pad_sel;
  98         struct clk *parent_clk, *sel_clk, *spi_clk;
  99         struct spi_transfer *cur_transfer;
 100         u32 xfer_len;
 101         u32 num_xfered;
 102         struct scatterlist *tx_sgl, *rx_sgl;
 103         u32 tx_sgl_len, rx_sgl_len;
 104         const struct mtk_spi_compatible *dev_comp;
 105 };
 106
 107 static const struct mtk_spi_compatible mtk_common_compat;
 108
 109 static const struct mtk_spi_compatible mt2712_compat = {
 110         .must_tx = true,
 111 };
 112
 113 static const struct mtk_spi_compatible mt7622_compat = {
 114         .must_tx = true,
 115         .enhance_timing = true,
 116 };
 117
 118 static const struct mtk_spi_compatible mt8173_compat = {
 119         .need_pad_sel = true,
 120         .must_tx = true,
 121 };
 122
 123 /*
 124  * A piece of default chip info unless the platform
 125  * supplies it.
 126  */
 127 static const struct mtk_chip_config mtk_default_chip_info = {
 128         .rx_mlsb = 1,
 129         .tx_mlsb = 1,
 130         .cs_pol = 0,
 131         .sample_sel = 0,
 132 };
 133
 134 static const struct of_device_id mtk_spi_of_match[] = {
 135         { .compatible = "mediatek,mt2701-spi",
 136                 .data = (void *)&mtk_common_compat,
 137         },
 138         { .compatible = "mediatek,mt2712-spi",
 139                 .data = (void *)&mt2712_compat,
 140         },
 141         { .compatible = "mediatek,mt6589-spi",
 142                 .data = (void *)&mtk_common_compat,
 143         },
 144         { .compatible = "mediatek,mt7622-spi",
 145                 .data = (void *)&mt7622_compat,
 146         },
 147         { .compatible = "mediatek,mt8135-spi",
 148                 .data = (void *)&mtk_common_compat,
 149         },
 150         { .compatible = "mediatek,mt8173-spi",
 151                 .data = (void *)&mt8173_compat,
 152         },
 153         {}
 154 };
 155 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
 156
 157 static void mtk_spi_reset(struct mtk_spi *mdata)
 158 {
 159         u32 reg_val;
 160
 161         /* set the software reset bit in SPI_CMD_REG. */
 162         reg_val = readl(mdata->base + SPI_CMD_REG);
 163         reg_val |= SPI_CMD_RST;
 164         writel(reg_val, mdata->base + SPI_CMD_REG);
 165
 166         reg_val = readl(mdata->base + SPI_CMD_REG);
 167         reg_val &= ~SPI_CMD_RST;
 168         writel(reg_val, mdata->base + SPI_CMD_REG);
 169 }
 170
 171 static int mtk_spi_prepare_message(struct spi_master *master,
 172                                    struct spi_message *msg)
 173 {
 174         u16 cpha, cpol;
 175         u32 reg_val;
 176         struct spi_device *spi = msg->spi;
 177         struct mtk_chip_config *chip_config = spi->controller_data;
 178         struct mtk_spi *mdata = spi_master_get_devdata(master);
 179
 180         cpha = spi->mode & SPI_CPHA ? 1 : 0;
 181         cpol = spi->mode & SPI_CPOL ? 1 : 0;
 182
 183         reg_val = readl(mdata->base + SPI_CMD_REG);
 184         if (cpha)
 185                 reg_val |= SPI_CMD_CPHA;
 186         else
 187                 reg_val &= ~SPI_CMD_CPHA;
 188         if (cpol)
 189                 reg_val |= SPI_CMD_CPOL;
 190         else
 191                 reg_val &= ~SPI_CMD_CPOL;
 192
 193         /* set the mlsbx and mlsbtx */
 194         if (chip_config->tx_mlsb)
 195                 reg_val |= SPI_CMD_TXMSBF;
 196         else
 197                 reg_val &= ~SPI_CMD_TXMSBF;
 198         if (chip_config->rx_mlsb)
 199                 reg_val |= SPI_CMD_RXMSBF;
 200         else
 201                 reg_val &= ~SPI_CMD_RXMSBF;
 202
 203         /* set the tx/rx endian */
 204 #ifdef __LITTLE_ENDIAN
 205         reg_val &= ~SPI_CMD_TX_ENDIAN;
 206         reg_val &= ~SPI_CMD_RX_ENDIAN;
 207 #else
 208         reg_val |= SPI_CMD_TX_ENDIAN;
 209         reg_val |= SPI_CMD_RX_ENDIAN;
 210 #endif
 211
 212         if (mdata->dev_comp->enhance_timing) {
 213                 if (chip_config->cs_pol)
 214                         reg_val |= SPI_CMD_CS_POL;
 215                 else
 216                         reg_val &= ~SPI_CMD_CS_POL;
 217                 if (chip_config->sample_sel)
 218                         reg_val |= SPI_CMD_SAMPLE_SEL;
 219                 else
 220                         reg_val &= ~SPI_CMD_SAMPLE_SEL;
 221         }
 222
 223         /* set finish and pause interrupt always enable */
 224         reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
 225
 226         /* disable dma mode */
 227         reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
 228
 229         /* disable deassert mode */
 230         reg_val &= ~SPI_CMD_DEASSERT;
 231
 232         writel(reg_val, mdata->base + SPI_CMD_REG);
 233
 234         /* pad select */
 235         if (mdata->dev_comp->need_pad_sel)
 236                 writel(mdata->pad_sel[spi->chip_select],
 237                        mdata->base + SPI_PAD_SEL_REG);
 238
 239         return 0;
 240 }
 241
 242 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
 243 {
 244         u32 reg_val;
 245         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 246
 247         reg_val = readl(mdata->base + SPI_CMD_REG);
 248         if (!enable) {
 249                 reg_val |= SPI_CMD_PAUSE_EN;
 250                 writel(reg_val, mdata->base + SPI_CMD_REG);
 251         } else {
 252                 reg_val &= ~SPI_CMD_PAUSE_EN;
 253                 writel(reg_val, mdata->base + SPI_CMD_REG);
 254                 mdata->state = MTK_SPI_IDLE;
 255                 mtk_spi_reset(mdata);
 256         }
 257 }
 258
 259 static void mtk_spi_prepare_transfer(struct spi_master *master,
 260                                      struct spi_transfer *xfer)
 261 {
 262         u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
 263         struct mtk_spi *mdata = spi_master_get_devdata(master);
 264
 265         spi_clk_hz = clk_get_rate(mdata->spi_clk);
 266         if (xfer->speed_hz < spi_clk_hz / 2)
 267                 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
 268         else
 269                 div = 1;
 270
 271         sck_time = (div + 1) / 2;
 272         cs_time = sck_time * 2;
 273
 274         if (mdata->dev_comp->enhance_timing) {
 275                 reg_val |= (((sck_time - 1) & 0xffff)
 276                            << SPI_CFG0_SCK_HIGH_OFFSET);
 277                 reg_val |= (((sck_time - 1) & 0xffff)
 278                            << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
 279                 writel(reg_val, mdata->base + SPI_CFG2_REG);
 280                 reg_val |= (((cs_time - 1) & 0xffff)
 281                            << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
 282                 reg_val |= (((cs_time - 1) & 0xffff)
 283                            << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
 284                 writel(reg_val, mdata->base + SPI_CFG0_REG);
 285         } else {
 286                 reg_val |= (((sck_time - 1) & 0xff)
 287                            << SPI_CFG0_SCK_HIGH_OFFSET);
 288                 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
 289                 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
 290                 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
 291                 writel(reg_val, mdata->base + SPI_CFG0_REG);
 292         }
 293
 294         reg_val = readl(mdata->base + SPI_CFG1_REG);
 295         reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
 296         reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
 297         writel(reg_val, mdata->base + SPI_CFG1_REG);
 298 }
 299
 300 static void mtk_spi_setup_packet(struct spi_master *master)
 301 {
 302         u32 packet_size, packet_loop, reg_val;
 303         struct mtk_spi *mdata = spi_master_get_devdata(master);
 304
 305         packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
 306         packet_loop = mdata->xfer_len / packet_size;
 307
 308         reg_val = readl(mdata->base + SPI_CFG1_REG);
 309         reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
 310         reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
 311         reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
 312         writel(reg_val, mdata->base + SPI_CFG1_REG);
 313 }
 314
 315 static void mtk_spi_enable_transfer(struct spi_master *master)
 316 {
 317         u32 cmd;
 318         struct mtk_spi *mdata = spi_master_get_devdata(master);
 319
 320         cmd = readl(mdata->base + SPI_CMD_REG);
 321         if (mdata->state == MTK_SPI_IDLE)
 322                 cmd |= SPI_CMD_ACT;
 323         else
 324                 cmd |= SPI_CMD_RESUME;
 325         writel(cmd, mdata->base + SPI_CMD_REG);
 326 }
 327
 328 static int mtk_spi_get_mult_delta(u32 xfer_len)
 329 {
 330         u32 mult_delta;
 331
 332         if (xfer_len > MTK_SPI_PACKET_SIZE)
 333                 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
 334         else
 335                 mult_delta = 0;
 336
 337         return mult_delta;
 338 }
 339
 340 static void mtk_spi_update_mdata_len(struct spi_master *master)
 341 {
 342         int mult_delta;
 343         struct mtk_spi *mdata = spi_master_get_devdata(master);
 344
 345         if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
 346                 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
 347                         mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 348                         mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 349                         mdata->rx_sgl_len = mult_delta;
 350                         mdata->tx_sgl_len -= mdata->xfer_len;
 351                 } else {
 352                         mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 353                         mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 354                         mdata->tx_sgl_len = mult_delta;
 355                         mdata->rx_sgl_len -= mdata->xfer_len;
 356                 }
 357         } else if (mdata->tx_sgl_len) {
 358                 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
 359                 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
 360                 mdata->tx_sgl_len = mult_delta;
 361         } else if (mdata->rx_sgl_len) {
 362                 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
 363                 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
 364                 mdata->rx_sgl_len = mult_delta;
 365         }
 366 }
 367
 368 static void mtk_spi_setup_dma_addr(struct spi_master *master,
 369                                    struct spi_transfer *xfer)
 370 {
 371         struct mtk_spi *mdata = spi_master_get_devdata(master);
 372
 373         if (mdata->tx_sgl)
 374                 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
 375         if (mdata->rx_sgl)
 376                 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
 377 }
 378
 379 static int mtk_spi_fifo_transfer(struct spi_master *master,
 380                                  struct spi_device *spi,
 381                                  struct spi_transfer *xfer)
 382 {
 383         int cnt, remainder;
 384         u32 reg_val;
 385         struct mtk_spi *mdata = spi_master_get_devdata(master);
 386
 387         mdata->cur_transfer = xfer;
 388         mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
 389         mdata->num_xfered = 0;
 390         mtk_spi_prepare_transfer(master, xfer);
 391         mtk_spi_setup_packet(master);
 392
 393         cnt = xfer->len / 4;
 394         iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
 395
 396         remainder = xfer->len % 4;
 397         if (remainder > 0) {
 398                 reg_val = 0;
 399                 memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
 400                 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
 401         }
 402
 403         mtk_spi_enable_transfer(master);
 404
 405         return 1;
 406 }
 407
 408 static int mtk_spi_dma_transfer(struct spi_master *master,
 409                                 struct spi_device *spi,
 410                                 struct spi_transfer *xfer)
 411 {
 412         int cmd;
 413         struct mtk_spi *mdata = spi_master_get_devdata(master);
 414
 415         mdata->tx_sgl = NULL;
 416         mdata->rx_sgl = NULL;
 417         mdata->tx_sgl_len = 0;
 418         mdata->rx_sgl_len = 0;
 419         mdata->cur_transfer = xfer;
 420         mdata->num_xfered = 0;
 421
 422         mtk_spi_prepare_transfer(master, xfer);
 423
 424         cmd = readl(mdata->base + SPI_CMD_REG);
 425         if (xfer->tx_buf)
 426                 cmd |= SPI_CMD_TX_DMA;
 427         if (xfer->rx_buf)
 428                 cmd |= SPI_CMD_RX_DMA;
 429         writel(cmd, mdata->base + SPI_CMD_REG);
 430
 431         if (xfer->tx_buf)
 432                 mdata->tx_sgl = xfer->tx_sg.sgl;
 433         if (xfer->rx_buf)
 434                 mdata->rx_sgl = xfer->rx_sg.sgl;
 435
 436         if (mdata->tx_sgl) {
 437                 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
 438                 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 439         }
 440         if (mdata->rx_sgl) {
 441                 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
 442                 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 443         }
 444
 445         mtk_spi_update_mdata_len(master);
 446         mtk_spi_setup_packet(master);
 447         mtk_spi_setup_dma_addr(master, xfer);
 448         mtk_spi_enable_transfer(master);
 449
 450         return 1;
 451 }
 452
 453 static int mtk_spi_transfer_one(struct spi_master *master,
 454                                 struct spi_device *spi,
 455                                 struct spi_transfer *xfer)
 456 {
 457         if (master->can_dma(master, spi, xfer))
 458                 return mtk_spi_dma_transfer(master, spi, xfer);
 459         else
 460                 return mtk_spi_fifo_transfer(master, spi, xfer);
 461 }
 462
 463 static bool mtk_spi_can_dma(struct spi_master *master,
 464                             struct spi_device *spi,
 465                             struct spi_transfer *xfer)
 466 {
 467         /* Buffers for DMA transactions must be 4-byte aligned */
 468         return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
 469                 (unsigned long)xfer->tx_buf % 4 == 0 &&
 470                 (unsigned long)xfer->rx_buf % 4 == 0);
 471 }
 472
 473 static int mtk_spi_setup(struct spi_device *spi)
 474 {
 475         struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
 476
 477         if (!spi->controller_data)
 478                 spi->controller_data = (void *)&mtk_default_chip_info;
 479
 480         if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
 481                 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
 482
 483         return 0;
 484 }
 485
 486 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
 487 {
 488         u32 cmd, reg_val, cnt, remainder, len;
 489         struct spi_master *master = dev_id;
 490         struct mtk_spi *mdata = spi_master_get_devdata(master);
 491         struct spi_transfer *trans = mdata->cur_transfer;
 492
 493         reg_val = readl(mdata->base + SPI_STATUS0_REG);
 494         if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
 495                 mdata->state = MTK_SPI_PAUSED;
 496         else
 497                 mdata->state = MTK_SPI_IDLE;
 498
 499         if (!master->can_dma(master, master->cur_msg->spi, trans)) {
 500                 if (trans->rx_buf) {
 501                         cnt = mdata->xfer_len / 4;
 502                         ioread32_rep(mdata->base + SPI_RX_DATA_REG,
 503                                      trans->rx_buf + mdata->num_xfered, cnt);
 504                         remainder = mdata->xfer_len % 4;
 505                         if (remainder > 0) {
 506                                 reg_val = readl(mdata->base + SPI_RX_DATA_REG);
 507                                 memcpy(trans->rx_buf +
 508                                         mdata->num_xfered +
 509                                         (cnt * 4),
 510                                         &reg_val,
 511                                         remainder);
 512                         }
 513                 }
 514
 515                 mdata->num_xfered += mdata->xfer_len;
 516                 if (mdata->num_xfered == trans->len) {
 517                         spi_finalize_current_transfer(master);
 518                         return IRQ_HANDLED;
 519                 }
 520
 521                 len = trans->len - mdata->num_xfered;
 522                 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
 523                 mtk_spi_setup_packet(master);
 524
 525                 cnt = len / 4;
 526                 iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
 527                                 trans->tx_buf + mdata->num_xfered, cnt);
 528
 529                 remainder = len % 4;
 530                 if (remainder > 0) {
 531                         reg_val = 0;
 532                         memcpy(&reg_val,
 533                                 trans->tx_buf + (cnt * 4) + mdata->num_xfered,
 534                                 remainder);
 535                         writel(reg_val, mdata->base + SPI_TX_DATA_REG);
 536                 }
 537
 538                 mtk_spi_enable_transfer(master);
 539
 540                 return IRQ_HANDLED;
 541         }
 542
 543         if (mdata->tx_sgl)
 544                 trans->tx_dma += mdata->xfer_len;
 545         if (mdata->rx_sgl)
 546                 trans->rx_dma += mdata->xfer_len;
 547
 548         if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
 549                 mdata->tx_sgl = sg_next(mdata->tx_sgl);
 550                 if (mdata->tx_sgl) {
 551                         trans->tx_dma = sg_dma_address(mdata->tx_sgl);
 552                         mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
 553                 }
 554         }
 555         if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
 556                 mdata->rx_sgl = sg_next(mdata->rx_sgl);
 557                 if (mdata->rx_sgl) {
 558                         trans->rx_dma = sg_dma_address(mdata->rx_sgl);
 559                         mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
 560                 }
 561         }
 562
 563         if (!mdata->tx_sgl && !mdata->rx_sgl) {
 564                 /* spi disable dma */
 565                 cmd = readl(mdata->base + SPI_CMD_REG);
 566                 cmd &= ~SPI_CMD_TX_DMA;
 567                 cmd &= ~SPI_CMD_RX_DMA;
 568                 writel(cmd, mdata->base + SPI_CMD_REG);
 569
 570                 spi_finalize_current_transfer(master);
 571                 return IRQ_HANDLED;
 572         }
 573
 574         mtk_spi_update_mdata_len(master);
 575         mtk_spi_setup_packet(master);
 576         mtk_spi_setup_dma_addr(master, trans);
 577         mtk_spi_enable_transfer(master);
 578
 579         return IRQ_HANDLED;
 580 }
 581
 582 static int mtk_spi_probe(struct platform_device *pdev)
 583 {
 584         struct spi_master *master;
 585         struct mtk_spi *mdata;
 586         const struct of_device_id *of_id;
 587         struct resource *res;
 588         int i, irq, ret;
 589
 590         master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
 591         if (!master) {
 592                 dev_err(&pdev->dev, "failed to alloc spi master\n");
 593                 return -ENOMEM;
 594         }
 595
 596         master->auto_runtime_pm = true;
 597         master->dev.of_node = pdev->dev.of_node;
 598         master->mode_bits = SPI_CPOL | SPI_CPHA;
 599
 600         master->set_cs = mtk_spi_set_cs;
 601         master->prepare_message = mtk_spi_prepare_message;
 602         master->transfer_one = mtk_spi_transfer_one;
 603         master->can_dma = mtk_spi_can_dma;
 604         master->setup = mtk_spi_setup;
 605
 606         of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
 607         if (!of_id) {
 608                 dev_err(&pdev->dev, "failed to probe of_node\n");
 609                 ret = -EINVAL;
 610                 goto err_put_master;
 611         }
 612
 613         mdata = spi_master_get_devdata(master);
 614         mdata->dev_comp = of_id->data;
 615         if (mdata->dev_comp->must_tx)
 616                 master->flags = SPI_MASTER_MUST_TX;
 617
 618         if (mdata->dev_comp->need_pad_sel) {
 619                 mdata->pad_num = of_property_count_u32_elems(
 620                         pdev->dev.of_node,
 621                         "mediatek,pad-select");
 622                 if (mdata->pad_num < 0) {
 623                         dev_err(&pdev->dev,
 624                                 "No 'mediatek,pad-select' property\n");
 625                         ret = -EINVAL;
 626                         goto err_put_master;
 627                 }
 628
 629                 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
 630                                                     sizeof(u32), GFP_KERNEL);
 631                 if (!mdata->pad_sel) {
 632                         ret = -ENOMEM;
 633                         goto err_put_master;
 634                 }
 635
 636                 for (i = 0; i < mdata->pad_num; i++) {
 637                         of_property_read_u32_index(pdev->dev.of_node,
 638                                                    "mediatek,pad-select",
 639                                                    i, &mdata->pad_sel[i]);
 640                         if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
 641                                 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
 642                                         i, mdata->pad_sel[i]);
 643                                 ret = -EINVAL;
 644                                 goto err_put_master;
 645                         }
 646                 }
 647         }
 648
 649         platform_set_drvdata(pdev, master);
 650
 651         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 652         if (!res) {
 653                 ret = -ENODEV;
 654                 dev_err(&pdev->dev, "failed to determine base address\n");
 655                 goto err_put_master;
 656         }
 657
 658         mdata->base = devm_ioremap_resource(&pdev->dev, res);
 659         if (IS_ERR(mdata->base)) {
 660                 ret = PTR_ERR(mdata->base);
 661                 goto err_put_master;
 662         }
 663
 664         irq = platform_get_irq(pdev, 0);
 665         if (irq < 0) {
 666                 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
 667                 ret = irq;
 668                 goto err_put_master;
 669         }
 670
 671         if (!pdev->dev.dma_mask)
 672                 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 673
 674         ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
 675                                IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
 676         if (ret) {
 677                 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
 678                 goto err_put_master;
 679         }
 680
 681         mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
 682         if (IS_ERR(mdata->parent_clk)) {
 683                 ret = PTR_ERR(mdata->parent_clk);
 684                 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
 685                 goto err_put_master;
 686         }
 687
 688         mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
 689         if (IS_ERR(mdata->sel_clk)) {
 690                 ret = PTR_ERR(mdata->sel_clk);
 691                 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
 692                 goto err_put_master;
 693         }
 694
 695         mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
 696         if (IS_ERR(mdata->spi_clk)) {
 697                 ret = PTR_ERR(mdata->spi_clk);
 698                 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
 699                 goto err_put_master;
 700         }
 701
 702         ret = clk_prepare_enable(mdata->spi_clk);
 703         if (ret < 0) {
 704                 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
 705                 goto err_put_master;
 706         }
 707
 708         ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
 709         if (ret < 0) {
 710                 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
 711                 clk_disable_unprepare(mdata->spi_clk);
 712                 goto err_put_master;
 713         }
 714
 715         clk_disable_unprepare(mdata->spi_clk);
 716
 717         pm_runtime_enable(&pdev->dev);
 718
 719         ret = devm_spi_register_master(&pdev->dev, master);
 720         if (ret) {
 721                 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
 722                 goto err_disable_runtime_pm;
 723         }
 724
 725         if (mdata->dev_comp->need_pad_sel) {
 726                 if (mdata->pad_num != master->num_chipselect) {
 727                         dev_err(&pdev->dev,
 728                                 "pad_num does not match num_chipselect(%d != %d)\n",
 729                                 mdata->pad_num, master->num_chipselect);
 730                         ret = -EINVAL;
 731                         goto err_disable_runtime_pm;
 732                 }
 733
 734                 if (!master->cs_gpios && master->num_chipselect > 1) {
 735                         dev_err(&pdev->dev,
 736                                 "cs_gpios not specified and num_chipselect > 1\n");
 737                         ret = -EINVAL;
 738                         goto err_disable_runtime_pm;
 739                 }
 740
 741                 if (master->cs_gpios) {
 742                         for (i = 0; i < master->num_chipselect; i++) {
 743                                 ret = devm_gpio_request(&pdev->dev,
 744                                                         master->cs_gpios[i],
 745                                                         dev_name(&pdev->dev));
 746                                 if (ret) {
 747                                         dev_err(&pdev->dev,
 748                                                 "can't get CS GPIO %i\n", i);
 749                                         goto err_disable_runtime_pm;
 750                                 }
 751                         }
 752                 }
 753         }
 754
 755         return 0;
 756
 757 err_disable_runtime_pm:
 758         pm_runtime_disable(&pdev->dev);
 759 err_put_master:
 760         spi_master_put(master);
 761
 762         return ret;
 763 }
 764
 765 static int mtk_spi_remove(struct platform_device *pdev)
 766 {
 767         struct spi_master *master = platform_get_drvdata(pdev);
 768         struct mtk_spi *mdata = spi_master_get_devdata(master);
 769
 770         pm_runtime_disable(&pdev->dev);
 771
 772         mtk_spi_reset(mdata);
 773
 774         return 0;
 775 }
 776
 777 #ifdef CONFIG_PM_SLEEP
 778 static int mtk_spi_suspend(struct device *dev)
 779 {
 780         int ret;
 781         struct spi_master *master = dev_get_drvdata(dev);
 782         struct mtk_spi *mdata = spi_master_get_devdata(master);
 783
 784         ret = spi_master_suspend(master);
 785         if (ret)
 786                 return ret;
 787
 788         if (!pm_runtime_suspended(dev))
 789                 clk_disable_unprepare(mdata->spi_clk);
 790
 791         return ret;
 792 }
 793
 794 static int mtk_spi_resume(struct device *dev)
 795 {
 796         int ret;
 797         struct spi_master *master = dev_get_drvdata(dev);
 798         struct mtk_spi *mdata = spi_master_get_devdata(master);
 799
 800         if (!pm_runtime_suspended(dev)) {
 801                 ret = clk_prepare_enable(mdata->spi_clk);
 802                 if (ret < 0) {
 803                         dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 804                         return ret;
 805                 }
 806         }
 807
 808         ret = spi_master_resume(master);
 809         if (ret < 0)
 810                 clk_disable_unprepare(mdata->spi_clk);
 811
 812         return ret;
 813 }
 814 #endif /* CONFIG_PM_SLEEP */
 815
 816 #ifdef CONFIG_PM
 817 static int mtk_spi_runtime_suspend(struct device *dev)
 818 {
 819         struct spi_master *master = dev_get_drvdata(dev);
 820         struct mtk_spi *mdata = spi_master_get_devdata(master);
 821
 822         clk_disable_unprepare(mdata->spi_clk);
 823
 824         return 0;
 825 }
 826
 827 static int mtk_spi_runtime_resume(struct device *dev)
 828 {
 829         struct spi_master *master = dev_get_drvdata(dev);
 830         struct mtk_spi *mdata = spi_master_get_devdata(master);
 831         int ret;
 832
 833         ret = clk_prepare_enable(mdata->spi_clk);
 834         if (ret < 0) {
 835                 dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
 836                 return ret;
 837         }
 838
 839         return 0;
 840 }
 841 #endif /* CONFIG_PM */
 842
 843 static const struct dev_pm_ops mtk_spi_pm = {
 844         SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
 845         SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
 846                            mtk_spi_runtime_resume, NULL)
 847 };
 848
 849 static struct platform_driver mtk_spi_driver = {
 850         .driver = {
 851                 .name = "mtk-spi",
 852                 .pm     = &mtk_spi_pm,
 853                 .of_match_table = mtk_spi_of_match,
 854         },
 855         .probe = mtk_spi_probe,
 856         .remove = mtk_spi_remove,
 857 };
 858
 859 module_platform_driver(mtk_spi_driver);
 860
 861 MODULE_DESCRIPTION("MTK SPI Controller driver");
 862 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
 863 MODULE_LICENSE("GPL v2");
 864 MODULE_ALIAS("platform:mtk-spi");