1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
42 #define SPI_CFG1_CS_IDLE_OFFSET 0
43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29
47 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
48 #define SPI_CFG1_CS_IDLE_MASK 0xff
49 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51 #define SPI_CFG2_SCK_HIGH_OFFSET 0
52 #define SPI_CFG2_SCK_LOW_OFFSET 16
54 #define SPI_CMD_ACT BIT(0)
55 #define SPI_CMD_RESUME BIT(1)
56 #define SPI_CMD_RST BIT(2)
57 #define SPI_CMD_PAUSE_EN BIT(4)
58 #define SPI_CMD_DEASSERT BIT(5)
59 #define SPI_CMD_SAMPLE_SEL BIT(6)
60 #define SPI_CMD_CS_POL BIT(7)
61 #define SPI_CMD_CPHA BIT(8)
62 #define SPI_CMD_CPOL BIT(9)
63 #define SPI_CMD_RX_DMA BIT(10)
64 #define SPI_CMD_TX_DMA BIT(11)
65 #define SPI_CMD_TXMSBF BIT(12)
66 #define SPI_CMD_RXMSBF BIT(13)
67 #define SPI_CMD_RX_ENDIAN BIT(14)
68 #define SPI_CMD_TX_ENDIAN BIT(15)
69 #define SPI_CMD_FINISH_IE BIT(16)
70 #define SPI_CMD_PAUSE_IE BIT(17)
72 #define MT8173_SPI_MAX_PAD_SEL 3
74 #define MTK_SPI_PAUSE_INT_STATUS 0x2
76 #define MTK_SPI_IDLE 0
77 #define MTK_SPI_PAUSED 1
79 #define MTK_SPI_MAX_FIFO_SIZE 32U
80 #define MTK_SPI_PACKET_SIZE 1024
81 #define MTK_SPI_32BITS_MASK (0xffffffff)
83 #define DMA_ADDR_EXT_BITS (36)
84 #define DMA_ADDR_DEF_BITS (32)
86 struct mtk_spi_compatible
{
88 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
90 /* some IC design adjust cfg register to enhance time accuracy */
92 /* some IC support DMA addr extension */
94 /* some IC no need unprepare SPI clk */
95 bool no_need_unprepare
;
103 struct clk
*parent_clk
, *sel_clk
, *spi_clk
;
104 struct spi_transfer
*cur_transfer
;
107 struct scatterlist
*tx_sgl
, *rx_sgl
;
108 u32 tx_sgl_len
, rx_sgl_len
;
109 const struct mtk_spi_compatible
*dev_comp
;
113 static const struct mtk_spi_compatible mtk_common_compat
;
115 static const struct mtk_spi_compatible mt2712_compat
= {
119 static const struct mtk_spi_compatible mt6765_compat
= {
120 .need_pad_sel
= true,
122 .enhance_timing
= true,
126 static const struct mtk_spi_compatible mt7622_compat
= {
128 .enhance_timing
= true,
131 static const struct mtk_spi_compatible mt8173_compat
= {
132 .need_pad_sel
= true,
136 static const struct mtk_spi_compatible mt8183_compat
= {
137 .need_pad_sel
= true,
139 .enhance_timing
= true,
142 static const struct mtk_spi_compatible mt6893_compat
= {
143 .need_pad_sel
= true,
145 .enhance_timing
= true,
147 .no_need_unprepare
= true,
151 * A piece of default chip info unless the platform
154 static const struct mtk_chip_config mtk_default_chip_info
= {
159 static const struct of_device_id mtk_spi_of_match
[] = {
160 { .compatible
= "mediatek,mt2701-spi",
161 .data
= (void *)&mtk_common_compat
,
163 { .compatible
= "mediatek,mt2712-spi",
164 .data
= (void *)&mt2712_compat
,
166 { .compatible
= "mediatek,mt6589-spi",
167 .data
= (void *)&mtk_common_compat
,
169 { .compatible
= "mediatek,mt6765-spi",
170 .data
= (void *)&mt6765_compat
,
172 { .compatible
= "mediatek,mt7622-spi",
173 .data
= (void *)&mt7622_compat
,
175 { .compatible
= "mediatek,mt7629-spi",
176 .data
= (void *)&mt7622_compat
,
178 { .compatible
= "mediatek,mt8135-spi",
179 .data
= (void *)&mtk_common_compat
,
181 { .compatible
= "mediatek,mt8173-spi",
182 .data
= (void *)&mt8173_compat
,
184 { .compatible
= "mediatek,mt8183-spi",
185 .data
= (void *)&mt8183_compat
,
187 { .compatible
= "mediatek,mt8192-spi",
188 .data
= (void *)&mt6765_compat
,
190 { .compatible
= "mediatek,mt6893-spi",
191 .data
= (void *)&mt6893_compat
,
195 MODULE_DEVICE_TABLE(of
, mtk_spi_of_match
);
197 static void mtk_spi_reset(struct mtk_spi
*mdata
)
201 /* set the software reset bit in SPI_CMD_REG. */
202 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
203 reg_val
|= SPI_CMD_RST
;
204 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
206 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
207 reg_val
&= ~SPI_CMD_RST
;
208 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
211 static int mtk_spi_set_hw_cs_timing(struct spi_device
*spi
)
213 struct mtk_spi
*mdata
= spi_master_get_devdata(spi
->master
);
214 struct spi_delay
*cs_setup
= &spi
->cs_setup
;
215 struct spi_delay
*cs_hold
= &spi
->cs_hold
;
216 struct spi_delay
*cs_inactive
= &spi
->cs_inactive
;
217 u32 setup
, hold
, inactive
;
221 delay
= spi_delay_to_ns(cs_setup
, NULL
);
224 setup
= (delay
* DIV_ROUND_UP(mdata
->spi_clk_hz
, 1000000)) / 1000;
226 delay
= spi_delay_to_ns(cs_hold
, NULL
);
229 hold
= (delay
* DIV_ROUND_UP(mdata
->spi_clk_hz
, 1000000)) / 1000;
231 delay
= spi_delay_to_ns(cs_inactive
, NULL
);
234 inactive
= (delay
* DIV_ROUND_UP(mdata
->spi_clk_hz
, 1000000)) / 1000;
237 reg_val
= readl(mdata
->base
+ SPI_CFG0_REG
);
238 if (mdata
->dev_comp
->enhance_timing
) {
240 hold
= min_t(u32
, hold
, 0x10000);
241 reg_val
&= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET
);
242 reg_val
|= (((hold
- 1) & 0xffff)
243 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET
);
246 setup
= min_t(u32
, setup
, 0x10000);
247 reg_val
&= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET
);
248 reg_val
|= (((setup
- 1) & 0xffff)
249 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET
);
253 hold
= min_t(u32
, hold
, 0x100);
254 reg_val
&= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET
);
255 reg_val
|= (((hold
- 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET
);
258 setup
= min_t(u32
, setup
, 0x100);
259 reg_val
&= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET
);
260 reg_val
|= (((setup
- 1) & 0xff)
261 << SPI_CFG0_CS_SETUP_OFFSET
);
264 writel(reg_val
, mdata
->base
+ SPI_CFG0_REG
);
268 inactive
= min_t(u32
, inactive
, 0x100);
269 reg_val
= readl(mdata
->base
+ SPI_CFG1_REG
);
270 reg_val
&= ~SPI_CFG1_CS_IDLE_MASK
;
271 reg_val
|= (((inactive
- 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET
);
272 writel(reg_val
, mdata
->base
+ SPI_CFG1_REG
);
278 static int mtk_spi_prepare_message(struct spi_master
*master
,
279 struct spi_message
*msg
)
283 struct spi_device
*spi
= msg
->spi
;
284 struct mtk_chip_config
*chip_config
= spi
->controller_data
;
285 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
287 cpha
= spi
->mode
& SPI_CPHA
? 1 : 0;
288 cpol
= spi
->mode
& SPI_CPOL
? 1 : 0;
290 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
292 reg_val
|= SPI_CMD_CPHA
;
294 reg_val
&= ~SPI_CMD_CPHA
;
296 reg_val
|= SPI_CMD_CPOL
;
298 reg_val
&= ~SPI_CMD_CPOL
;
300 /* set the mlsbx and mlsbtx */
301 if (spi
->mode
& SPI_LSB_FIRST
) {
302 reg_val
&= ~SPI_CMD_TXMSBF
;
303 reg_val
&= ~SPI_CMD_RXMSBF
;
305 reg_val
|= SPI_CMD_TXMSBF
;
306 reg_val
|= SPI_CMD_RXMSBF
;
309 /* set the tx/rx endian */
310 #ifdef __LITTLE_ENDIAN
311 reg_val
&= ~SPI_CMD_TX_ENDIAN
;
312 reg_val
&= ~SPI_CMD_RX_ENDIAN
;
314 reg_val
|= SPI_CMD_TX_ENDIAN
;
315 reg_val
|= SPI_CMD_RX_ENDIAN
;
318 if (mdata
->dev_comp
->enhance_timing
) {
319 /* set CS polarity */
320 if (spi
->mode
& SPI_CS_HIGH
)
321 reg_val
|= SPI_CMD_CS_POL
;
323 reg_val
&= ~SPI_CMD_CS_POL
;
325 if (chip_config
->sample_sel
)
326 reg_val
|= SPI_CMD_SAMPLE_SEL
;
328 reg_val
&= ~SPI_CMD_SAMPLE_SEL
;
331 /* set finish and pause interrupt always enable */
332 reg_val
|= SPI_CMD_FINISH_IE
| SPI_CMD_PAUSE_IE
;
334 /* disable dma mode */
335 reg_val
&= ~(SPI_CMD_TX_DMA
| SPI_CMD_RX_DMA
);
337 /* disable deassert mode */
338 reg_val
&= ~SPI_CMD_DEASSERT
;
340 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
343 if (mdata
->dev_comp
->need_pad_sel
)
344 writel(mdata
->pad_sel
[spi
->chip_select
],
345 mdata
->base
+ SPI_PAD_SEL_REG
);
348 reg_val
= readl(mdata
->base
+ SPI_CFG1_REG
);
349 reg_val
&= ~SPI_CFG1_GET_TICK_DLY_MASK
;
350 reg_val
|= ((chip_config
->tick_delay
& 0x7)
351 << SPI_CFG1_GET_TICK_DLY_OFFSET
);
352 writel(reg_val
, mdata
->base
+ SPI_CFG1_REG
);
354 /* set hw cs timing */
355 mtk_spi_set_hw_cs_timing(spi
);
359 static void mtk_spi_set_cs(struct spi_device
*spi
, bool enable
)
362 struct mtk_spi
*mdata
= spi_master_get_devdata(spi
->master
);
364 if (spi
->mode
& SPI_CS_HIGH
)
367 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
369 reg_val
|= SPI_CMD_PAUSE_EN
;
370 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
372 reg_val
&= ~SPI_CMD_PAUSE_EN
;
373 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
374 mdata
->state
= MTK_SPI_IDLE
;
375 mtk_spi_reset(mdata
);
379 static void mtk_spi_prepare_transfer(struct spi_master
*master
,
380 struct spi_transfer
*xfer
)
382 u32 div
, sck_time
, reg_val
;
383 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
385 if (xfer
->speed_hz
< mdata
->spi_clk_hz
/ 2)
386 div
= DIV_ROUND_UP(mdata
->spi_clk_hz
, xfer
->speed_hz
);
390 sck_time
= (div
+ 1) / 2;
392 if (mdata
->dev_comp
->enhance_timing
) {
393 reg_val
= readl(mdata
->base
+ SPI_CFG2_REG
);
394 reg_val
&= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET
);
395 reg_val
|= (((sck_time
- 1) & 0xffff)
396 << SPI_CFG2_SCK_HIGH_OFFSET
);
397 reg_val
&= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET
);
398 reg_val
|= (((sck_time
- 1) & 0xffff)
399 << SPI_CFG2_SCK_LOW_OFFSET
);
400 writel(reg_val
, mdata
->base
+ SPI_CFG2_REG
);
402 reg_val
= readl(mdata
->base
+ SPI_CFG0_REG
);
403 reg_val
&= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET
);
404 reg_val
|= (((sck_time
- 1) & 0xff)
405 << SPI_CFG0_SCK_HIGH_OFFSET
);
406 reg_val
&= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET
);
407 reg_val
|= (((sck_time
- 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET
);
408 writel(reg_val
, mdata
->base
+ SPI_CFG0_REG
);
412 static void mtk_spi_setup_packet(struct spi_master
*master
)
414 u32 packet_size
, packet_loop
, reg_val
;
415 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
417 packet_size
= min_t(u32
, mdata
->xfer_len
, MTK_SPI_PACKET_SIZE
);
418 packet_loop
= mdata
->xfer_len
/ packet_size
;
420 reg_val
= readl(mdata
->base
+ SPI_CFG1_REG
);
421 reg_val
&= ~(SPI_CFG1_PACKET_LENGTH_MASK
| SPI_CFG1_PACKET_LOOP_MASK
);
422 reg_val
|= (packet_size
- 1) << SPI_CFG1_PACKET_LENGTH_OFFSET
;
423 reg_val
|= (packet_loop
- 1) << SPI_CFG1_PACKET_LOOP_OFFSET
;
424 writel(reg_val
, mdata
->base
+ SPI_CFG1_REG
);
427 static void mtk_spi_enable_transfer(struct spi_master
*master
)
430 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
432 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
433 if (mdata
->state
== MTK_SPI_IDLE
)
436 cmd
|= SPI_CMD_RESUME
;
437 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
440 static int mtk_spi_get_mult_delta(u32 xfer_len
)
444 if (xfer_len
> MTK_SPI_PACKET_SIZE
)
445 mult_delta
= xfer_len
% MTK_SPI_PACKET_SIZE
;
452 static void mtk_spi_update_mdata_len(struct spi_master
*master
)
455 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
457 if (mdata
->tx_sgl_len
&& mdata
->rx_sgl_len
) {
458 if (mdata
->tx_sgl_len
> mdata
->rx_sgl_len
) {
459 mult_delta
= mtk_spi_get_mult_delta(mdata
->rx_sgl_len
);
460 mdata
->xfer_len
= mdata
->rx_sgl_len
- mult_delta
;
461 mdata
->rx_sgl_len
= mult_delta
;
462 mdata
->tx_sgl_len
-= mdata
->xfer_len
;
464 mult_delta
= mtk_spi_get_mult_delta(mdata
->tx_sgl_len
);
465 mdata
->xfer_len
= mdata
->tx_sgl_len
- mult_delta
;
466 mdata
->tx_sgl_len
= mult_delta
;
467 mdata
->rx_sgl_len
-= mdata
->xfer_len
;
469 } else if (mdata
->tx_sgl_len
) {
470 mult_delta
= mtk_spi_get_mult_delta(mdata
->tx_sgl_len
);
471 mdata
->xfer_len
= mdata
->tx_sgl_len
- mult_delta
;
472 mdata
->tx_sgl_len
= mult_delta
;
473 } else if (mdata
->rx_sgl_len
) {
474 mult_delta
= mtk_spi_get_mult_delta(mdata
->rx_sgl_len
);
475 mdata
->xfer_len
= mdata
->rx_sgl_len
- mult_delta
;
476 mdata
->rx_sgl_len
= mult_delta
;
480 static void mtk_spi_setup_dma_addr(struct spi_master
*master
,
481 struct spi_transfer
*xfer
)
483 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
486 writel((u32
)(xfer
->tx_dma
& MTK_SPI_32BITS_MASK
),
487 mdata
->base
+ SPI_TX_SRC_REG
);
488 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
489 if (mdata
->dev_comp
->dma_ext
)
490 writel((u32
)(xfer
->tx_dma
>> 32),
491 mdata
->base
+ SPI_TX_SRC_REG_64
);
496 writel((u32
)(xfer
->rx_dma
& MTK_SPI_32BITS_MASK
),
497 mdata
->base
+ SPI_RX_DST_REG
);
498 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
499 if (mdata
->dev_comp
->dma_ext
)
500 writel((u32
)(xfer
->rx_dma
>> 32),
501 mdata
->base
+ SPI_RX_DST_REG_64
);
506 static int mtk_spi_fifo_transfer(struct spi_master
*master
,
507 struct spi_device
*spi
,
508 struct spi_transfer
*xfer
)
512 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
514 mdata
->cur_transfer
= xfer
;
515 mdata
->xfer_len
= min(MTK_SPI_MAX_FIFO_SIZE
, xfer
->len
);
516 mdata
->num_xfered
= 0;
517 mtk_spi_prepare_transfer(master
, xfer
);
518 mtk_spi_setup_packet(master
);
522 iowrite32_rep(mdata
->base
+ SPI_TX_DATA_REG
, xfer
->tx_buf
, cnt
);
523 remainder
= xfer
->len
% 4;
526 memcpy(®_val
, xfer
->tx_buf
+ (cnt
* 4), remainder
);
527 writel(reg_val
, mdata
->base
+ SPI_TX_DATA_REG
);
531 mtk_spi_enable_transfer(master
);
536 static int mtk_spi_dma_transfer(struct spi_master
*master
,
537 struct spi_device
*spi
,
538 struct spi_transfer
*xfer
)
541 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
543 mdata
->tx_sgl
= NULL
;
544 mdata
->rx_sgl
= NULL
;
545 mdata
->tx_sgl_len
= 0;
546 mdata
->rx_sgl_len
= 0;
547 mdata
->cur_transfer
= xfer
;
548 mdata
->num_xfered
= 0;
550 mtk_spi_prepare_transfer(master
, xfer
);
552 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
554 cmd
|= SPI_CMD_TX_DMA
;
556 cmd
|= SPI_CMD_RX_DMA
;
557 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
560 mdata
->tx_sgl
= xfer
->tx_sg
.sgl
;
562 mdata
->rx_sgl
= xfer
->rx_sg
.sgl
;
565 xfer
->tx_dma
= sg_dma_address(mdata
->tx_sgl
);
566 mdata
->tx_sgl_len
= sg_dma_len(mdata
->tx_sgl
);
569 xfer
->rx_dma
= sg_dma_address(mdata
->rx_sgl
);
570 mdata
->rx_sgl_len
= sg_dma_len(mdata
->rx_sgl
);
573 mtk_spi_update_mdata_len(master
);
574 mtk_spi_setup_packet(master
);
575 mtk_spi_setup_dma_addr(master
, xfer
);
576 mtk_spi_enable_transfer(master
);
581 static int mtk_spi_transfer_one(struct spi_master
*master
,
582 struct spi_device
*spi
,
583 struct spi_transfer
*xfer
)
585 if (master
->can_dma(master
, spi
, xfer
))
586 return mtk_spi_dma_transfer(master
, spi
, xfer
);
588 return mtk_spi_fifo_transfer(master
, spi
, xfer
);
591 static bool mtk_spi_can_dma(struct spi_master
*master
,
592 struct spi_device
*spi
,
593 struct spi_transfer
*xfer
)
595 /* Buffers for DMA transactions must be 4-byte aligned */
596 return (xfer
->len
> MTK_SPI_MAX_FIFO_SIZE
&&
597 (unsigned long)xfer
->tx_buf
% 4 == 0 &&
598 (unsigned long)xfer
->rx_buf
% 4 == 0);
601 static int mtk_spi_setup(struct spi_device
*spi
)
603 struct mtk_spi
*mdata
= spi_master_get_devdata(spi
->master
);
605 if (!spi
->controller_data
)
606 spi
->controller_data
= (void *)&mtk_default_chip_info
;
608 if (mdata
->dev_comp
->need_pad_sel
&& gpio_is_valid(spi
->cs_gpio
))
609 gpio_direction_output(spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
614 static irqreturn_t
mtk_spi_interrupt(int irq
, void *dev_id
)
616 u32 cmd
, reg_val
, cnt
, remainder
, len
;
617 struct spi_master
*master
= dev_id
;
618 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
619 struct spi_transfer
*trans
= mdata
->cur_transfer
;
621 reg_val
= readl(mdata
->base
+ SPI_STATUS0_REG
);
622 if (reg_val
& MTK_SPI_PAUSE_INT_STATUS
)
623 mdata
->state
= MTK_SPI_PAUSED
;
625 mdata
->state
= MTK_SPI_IDLE
;
627 if (!master
->can_dma(master
, master
->cur_msg
->spi
, trans
)) {
629 cnt
= mdata
->xfer_len
/ 4;
630 ioread32_rep(mdata
->base
+ SPI_RX_DATA_REG
,
631 trans
->rx_buf
+ mdata
->num_xfered
, cnt
);
632 remainder
= mdata
->xfer_len
% 4;
634 reg_val
= readl(mdata
->base
+ SPI_RX_DATA_REG
);
635 memcpy(trans
->rx_buf
+
643 mdata
->num_xfered
+= mdata
->xfer_len
;
644 if (mdata
->num_xfered
== trans
->len
) {
645 spi_finalize_current_transfer(master
);
649 len
= trans
->len
- mdata
->num_xfered
;
650 mdata
->xfer_len
= min(MTK_SPI_MAX_FIFO_SIZE
, len
);
651 mtk_spi_setup_packet(master
);
653 cnt
= mdata
->xfer_len
/ 4;
654 iowrite32_rep(mdata
->base
+ SPI_TX_DATA_REG
,
655 trans
->tx_buf
+ mdata
->num_xfered
, cnt
);
657 remainder
= mdata
->xfer_len
% 4;
661 trans
->tx_buf
+ (cnt
* 4) + mdata
->num_xfered
,
663 writel(reg_val
, mdata
->base
+ SPI_TX_DATA_REG
);
666 mtk_spi_enable_transfer(master
);
672 trans
->tx_dma
+= mdata
->xfer_len
;
674 trans
->rx_dma
+= mdata
->xfer_len
;
676 if (mdata
->tx_sgl
&& (mdata
->tx_sgl_len
== 0)) {
677 mdata
->tx_sgl
= sg_next(mdata
->tx_sgl
);
679 trans
->tx_dma
= sg_dma_address(mdata
->tx_sgl
);
680 mdata
->tx_sgl_len
= sg_dma_len(mdata
->tx_sgl
);
683 if (mdata
->rx_sgl
&& (mdata
->rx_sgl_len
== 0)) {
684 mdata
->rx_sgl
= sg_next(mdata
->rx_sgl
);
686 trans
->rx_dma
= sg_dma_address(mdata
->rx_sgl
);
687 mdata
->rx_sgl_len
= sg_dma_len(mdata
->rx_sgl
);
691 if (!mdata
->tx_sgl
&& !mdata
->rx_sgl
) {
692 /* spi disable dma */
693 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
694 cmd
&= ~SPI_CMD_TX_DMA
;
695 cmd
&= ~SPI_CMD_RX_DMA
;
696 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
698 spi_finalize_current_transfer(master
);
702 mtk_spi_update_mdata_len(master
);
703 mtk_spi_setup_packet(master
);
704 mtk_spi_setup_dma_addr(master
, trans
);
705 mtk_spi_enable_transfer(master
);
710 static int mtk_spi_probe(struct platform_device
*pdev
)
712 struct spi_master
*master
;
713 struct mtk_spi
*mdata
;
714 const struct of_device_id
*of_id
;
715 int i
, irq
, ret
, addr_bits
;
717 master
= spi_alloc_master(&pdev
->dev
, sizeof(*mdata
));
719 dev_err(&pdev
->dev
, "failed to alloc spi master\n");
723 master
->auto_runtime_pm
= true;
724 master
->dev
.of_node
= pdev
->dev
.of_node
;
725 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
727 master
->set_cs
= mtk_spi_set_cs
;
728 master
->prepare_message
= mtk_spi_prepare_message
;
729 master
->transfer_one
= mtk_spi_transfer_one
;
730 master
->can_dma
= mtk_spi_can_dma
;
731 master
->setup
= mtk_spi_setup
;
732 master
->set_cs_timing
= mtk_spi_set_hw_cs_timing
;
734 of_id
= of_match_node(mtk_spi_of_match
, pdev
->dev
.of_node
);
736 dev_err(&pdev
->dev
, "failed to probe of_node\n");
741 mdata
= spi_master_get_devdata(master
);
742 mdata
->dev_comp
= of_id
->data
;
744 if (mdata
->dev_comp
->enhance_timing
)
745 master
->mode_bits
|= SPI_CS_HIGH
;
747 if (mdata
->dev_comp
->must_tx
)
748 master
->flags
= SPI_MASTER_MUST_TX
;
750 if (mdata
->dev_comp
->need_pad_sel
) {
751 mdata
->pad_num
= of_property_count_u32_elems(
753 "mediatek,pad-select");
754 if (mdata
->pad_num
< 0) {
756 "No 'mediatek,pad-select' property\n");
761 mdata
->pad_sel
= devm_kmalloc_array(&pdev
->dev
, mdata
->pad_num
,
762 sizeof(u32
), GFP_KERNEL
);
763 if (!mdata
->pad_sel
) {
768 for (i
= 0; i
< mdata
->pad_num
; i
++) {
769 of_property_read_u32_index(pdev
->dev
.of_node
,
770 "mediatek,pad-select",
771 i
, &mdata
->pad_sel
[i
]);
772 if (mdata
->pad_sel
[i
] > MT8173_SPI_MAX_PAD_SEL
) {
773 dev_err(&pdev
->dev
, "wrong pad-sel[%d]: %u\n",
774 i
, mdata
->pad_sel
[i
]);
781 platform_set_drvdata(pdev
, master
);
782 mdata
->base
= devm_platform_ioremap_resource(pdev
, 0);
783 if (IS_ERR(mdata
->base
)) {
784 ret
= PTR_ERR(mdata
->base
);
788 irq
= platform_get_irq(pdev
, 0);
794 if (!pdev
->dev
.dma_mask
)
795 pdev
->dev
.dma_mask
= &pdev
->dev
.coherent_dma_mask
;
797 ret
= devm_request_irq(&pdev
->dev
, irq
, mtk_spi_interrupt
,
798 IRQF_TRIGGER_NONE
, dev_name(&pdev
->dev
), master
);
800 dev_err(&pdev
->dev
, "failed to register irq (%d)\n", ret
);
804 mdata
->parent_clk
= devm_clk_get(&pdev
->dev
, "parent-clk");
805 if (IS_ERR(mdata
->parent_clk
)) {
806 ret
= PTR_ERR(mdata
->parent_clk
);
807 dev_err(&pdev
->dev
, "failed to get parent-clk: %d\n", ret
);
811 mdata
->sel_clk
= devm_clk_get(&pdev
->dev
, "sel-clk");
812 if (IS_ERR(mdata
->sel_clk
)) {
813 ret
= PTR_ERR(mdata
->sel_clk
);
814 dev_err(&pdev
->dev
, "failed to get sel-clk: %d\n", ret
);
818 mdata
->spi_clk
= devm_clk_get(&pdev
->dev
, "spi-clk");
819 if (IS_ERR(mdata
->spi_clk
)) {
820 ret
= PTR_ERR(mdata
->spi_clk
);
821 dev_err(&pdev
->dev
, "failed to get spi-clk: %d\n", ret
);
825 ret
= clk_prepare_enable(mdata
->spi_clk
);
827 dev_err(&pdev
->dev
, "failed to enable spi_clk (%d)\n", ret
);
831 ret
= clk_set_parent(mdata
->sel_clk
, mdata
->parent_clk
);
833 dev_err(&pdev
->dev
, "failed to clk_set_parent (%d)\n", ret
);
834 clk_disable_unprepare(mdata
->spi_clk
);
838 mdata
->spi_clk_hz
= clk_get_rate(mdata
->spi_clk
);
840 if (mdata
->dev_comp
->no_need_unprepare
)
841 clk_disable(mdata
->spi_clk
);
843 clk_disable_unprepare(mdata
->spi_clk
);
845 pm_runtime_enable(&pdev
->dev
);
847 if (mdata
->dev_comp
->need_pad_sel
) {
848 if (mdata
->pad_num
!= master
->num_chipselect
) {
850 "pad_num does not match num_chipselect(%d != %d)\n",
851 mdata
->pad_num
, master
->num_chipselect
);
853 goto err_disable_runtime_pm
;
856 if (!master
->cs_gpios
&& master
->num_chipselect
> 1) {
858 "cs_gpios not specified and num_chipselect > 1\n");
860 goto err_disable_runtime_pm
;
863 if (master
->cs_gpios
) {
864 for (i
= 0; i
< master
->num_chipselect
; i
++) {
865 ret
= devm_gpio_request(&pdev
->dev
,
867 dev_name(&pdev
->dev
));
870 "can't get CS GPIO %i\n", i
);
871 goto err_disable_runtime_pm
;
877 if (mdata
->dev_comp
->dma_ext
)
878 addr_bits
= DMA_ADDR_EXT_BITS
;
880 addr_bits
= DMA_ADDR_DEF_BITS
;
881 ret
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(addr_bits
));
883 dev_notice(&pdev
->dev
, "SPI dma_set_mask(%d) failed, ret:%d\n",
886 ret
= devm_spi_register_master(&pdev
->dev
, master
);
888 dev_err(&pdev
->dev
, "failed to register master (%d)\n", ret
);
889 goto err_disable_runtime_pm
;
894 err_disable_runtime_pm
:
895 pm_runtime_disable(&pdev
->dev
);
897 spi_master_put(master
);
902 static int mtk_spi_remove(struct platform_device
*pdev
)
904 struct spi_master
*master
= platform_get_drvdata(pdev
);
905 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
907 pm_runtime_disable(&pdev
->dev
);
909 mtk_spi_reset(mdata
);
911 if (mdata
->dev_comp
->no_need_unprepare
)
912 clk_unprepare(mdata
->spi_clk
);
917 #ifdef CONFIG_PM_SLEEP
918 static int mtk_spi_suspend(struct device
*dev
)
921 struct spi_master
*master
= dev_get_drvdata(dev
);
922 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
924 ret
= spi_master_suspend(master
);
928 if (!pm_runtime_suspended(dev
))
929 clk_disable_unprepare(mdata
->spi_clk
);
934 static int mtk_spi_resume(struct device
*dev
)
937 struct spi_master
*master
= dev_get_drvdata(dev
);
938 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
940 if (!pm_runtime_suspended(dev
)) {
941 ret
= clk_prepare_enable(mdata
->spi_clk
);
943 dev_err(dev
, "failed to enable spi_clk (%d)\n", ret
);
948 ret
= spi_master_resume(master
);
950 clk_disable_unprepare(mdata
->spi_clk
);
954 #endif /* CONFIG_PM_SLEEP */
957 static int mtk_spi_runtime_suspend(struct device
*dev
)
959 struct spi_master
*master
= dev_get_drvdata(dev
);
960 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
962 if (mdata
->dev_comp
->no_need_unprepare
)
963 clk_disable(mdata
->spi_clk
);
965 clk_disable_unprepare(mdata
->spi_clk
);
970 static int mtk_spi_runtime_resume(struct device
*dev
)
972 struct spi_master
*master
= dev_get_drvdata(dev
);
973 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
976 if (mdata
->dev_comp
->no_need_unprepare
)
977 ret
= clk_enable(mdata
->spi_clk
);
979 ret
= clk_prepare_enable(mdata
->spi_clk
);
981 dev_err(dev
, "failed to enable spi_clk (%d)\n", ret
);
987 #endif /* CONFIG_PM */
989 static const struct dev_pm_ops mtk_spi_pm
= {
990 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend
, mtk_spi_resume
)
991 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend
,
992 mtk_spi_runtime_resume
, NULL
)
995 static struct platform_driver mtk_spi_driver
= {
999 .of_match_table
= mtk_spi_of_match
,
1001 .probe
= mtk_spi_probe
,
1002 .remove
= mtk_spi_remove
,
1005 module_platform_driver(mtk_spi_driver
);
1007 MODULE_DESCRIPTION("MTK SPI Controller driver");
1008 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1009 MODULE_LICENSE("GPL v2");
1010 MODULE_ALIAS("platform:mtk-spi");