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Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-omap2-mcspi.c
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/gcd.h>
42
43 #include <linux/spi/spi.h>
44
45 #include <linux/platform_data/spi-omap2-mcspi.h>
46
47 #define OMAP2_MCSPI_MAX_FREQ 48000000
48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50 #define SPI_AUTOSUSPEND_TIMEOUT 2000
51
52 #define OMAP2_MCSPI_REVISION 0x00
53 #define OMAP2_MCSPI_SYSSTATUS 0x14
54 #define OMAP2_MCSPI_IRQSTATUS 0x18
55 #define OMAP2_MCSPI_IRQENABLE 0x1c
56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
57 #define OMAP2_MCSPI_SYST 0x24
58 #define OMAP2_MCSPI_MODULCTRL 0x28
59 #define OMAP2_MCSPI_XFERLEVEL 0x7c
60
61 /* per-channel banks, 0x14 bytes each, first is: */
62 #define OMAP2_MCSPI_CHCONF0 0x2c
63 #define OMAP2_MCSPI_CHSTAT0 0x30
64 #define OMAP2_MCSPI_CHCTRL0 0x34
65 #define OMAP2_MCSPI_TX0 0x38
66 #define OMAP2_MCSPI_RX0 0x3c
67
68 /* per-register bitmasks: */
69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
70
71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
74
75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
76 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
87 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
96 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
97
98 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
99
100 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101
102 /* We have 2 DMA channels per CS, one for RX and one for TX */
103 struct omap2_mcspi_dma {
104 struct dma_chan *dma_tx;
105 struct dma_chan *dma_rx;
106
107 int dma_tx_sync_dev;
108 int dma_rx_sync_dev;
109
110 struct completion dma_tx_completion;
111 struct completion dma_rx_completion;
112
113 char dma_rx_ch_name[14];
114 char dma_tx_ch_name[14];
115 };
116
117 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
118 * cache operations; better heuristics consider wordsize and bitrate.
119 */
120 #define DMA_MIN_BYTES 160
121
122
123 /*
124 * Used for context save and restore, structure members to be updated whenever
125 * corresponding registers are modified.
126 */
127 struct omap2_mcspi_regs {
128 u32 modulctrl;
129 u32 wakeupenable;
130 struct list_head cs;
131 };
132
133 struct omap2_mcspi {
134 struct spi_master *master;
135 /* Virtual base address of the controller */
136 void __iomem *base;
137 unsigned long phys;
138 /* SPI1 has 4 channels, while SPI2 has 2 */
139 struct omap2_mcspi_dma *dma_channels;
140 struct device *dev;
141 struct omap2_mcspi_regs ctx;
142 int fifo_depth;
143 unsigned int pin_dir:1;
144 };
145
146 struct omap2_mcspi_cs {
147 void __iomem *base;
148 unsigned long phys;
149 int word_len;
150 struct list_head node;
151 /* Context save and restore shadow register */
152 u32 chconf0;
153 };
154
155 static inline void mcspi_write_reg(struct spi_master *master,
156 int idx, u32 val)
157 {
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
159
160 __raw_writel(val, mcspi->base + idx);
161 }
162
163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
164 {
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
166
167 return __raw_readl(mcspi->base + idx);
168 }
169
170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
171 int idx, u32 val)
172 {
173 struct omap2_mcspi_cs *cs = spi->controller_state;
174
175 __raw_writel(val, cs->base + idx);
176 }
177
178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
179 {
180 struct omap2_mcspi_cs *cs = spi->controller_state;
181
182 return __raw_readl(cs->base + idx);
183 }
184
185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
186 {
187 struct omap2_mcspi_cs *cs = spi->controller_state;
188
189 return cs->chconf0;
190 }
191
192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
193 {
194 struct omap2_mcspi_cs *cs = spi->controller_state;
195
196 cs->chconf0 = val;
197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
199 }
200
201 static inline int mcspi_bytes_per_word(int word_len)
202 {
203 if (word_len <= 8)
204 return 1;
205 else if (word_len <= 16)
206 return 2;
207 else /* word_len <= 32 */
208 return 4;
209 }
210
211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
212 int is_read, int enable)
213 {
214 u32 l, rw;
215
216 l = mcspi_cached_chconf0(spi);
217
218 if (is_read) /* 1 is read, 0 write */
219 rw = OMAP2_MCSPI_CHCONF_DMAR;
220 else
221 rw = OMAP2_MCSPI_CHCONF_DMAW;
222
223 if (enable)
224 l |= rw;
225 else
226 l &= ~rw;
227
228 mcspi_write_chconf0(spi, l);
229 }
230
231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
232 {
233 u32 l;
234
235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
237 /* Flash post-writes */
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
239 }
240
241 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
242 {
243 u32 l;
244
245 l = mcspi_cached_chconf0(spi);
246 if (cs_active)
247 l |= OMAP2_MCSPI_CHCONF_FORCE;
248 else
249 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
250
251 mcspi_write_chconf0(spi, l);
252 }
253
254 static void omap2_mcspi_set_master_mode(struct spi_master *master)
255 {
256 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
257 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
258 u32 l;
259
260 /*
261 * Setup when switching from (reset default) slave mode
262 * to single-channel master mode
263 */
264 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
265 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
266 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
267 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
268
269 ctx->modulctrl = l;
270 }
271
272 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
273 struct spi_transfer *t, int enable)
274 {
275 struct spi_master *master = spi->master;
276 struct omap2_mcspi_cs *cs = spi->controller_state;
277 struct omap2_mcspi *mcspi;
278 unsigned int wcnt;
279 int fifo_depth, bytes_per_word;
280 u32 chconf, xferlevel;
281
282 mcspi = spi_master_get_devdata(master);
283
284 chconf = mcspi_cached_chconf0(spi);
285 if (enable) {
286 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
287 if (t->len % bytes_per_word != 0)
288 goto disable_fifo;
289
290 fifo_depth = gcd(t->len, OMAP2_MCSPI_MAX_FIFODEPTH);
291 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
292 goto disable_fifo;
293
294 wcnt = t->len / bytes_per_word;
295 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
296 goto disable_fifo;
297
298 xferlevel = wcnt << 16;
299 if (t->rx_buf != NULL) {
300 chconf |= OMAP2_MCSPI_CHCONF_FFER;
301 xferlevel |= (fifo_depth - 1) << 8;
302 } else {
303 chconf |= OMAP2_MCSPI_CHCONF_FFET;
304 xferlevel |= fifo_depth - 1;
305 }
306
307 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
308 mcspi_write_chconf0(spi, chconf);
309 mcspi->fifo_depth = fifo_depth;
310
311 return;
312 }
313
314 disable_fifo:
315 if (t->rx_buf != NULL)
316 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
317 else
318 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
319
320 mcspi_write_chconf0(spi, chconf);
321 mcspi->fifo_depth = 0;
322 }
323
324 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
325 {
326 struct spi_master *spi_cntrl = mcspi->master;
327 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
328 struct omap2_mcspi_cs *cs;
329
330 /* McSPI: context restore */
331 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
332 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
333
334 list_for_each_entry(cs, &ctx->cs, node)
335 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
336 }
337
338 static int omap2_prepare_transfer(struct spi_master *master)
339 {
340 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
341
342 pm_runtime_get_sync(mcspi->dev);
343 return 0;
344 }
345
346 static int omap2_unprepare_transfer(struct spi_master *master)
347 {
348 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
349
350 pm_runtime_mark_last_busy(mcspi->dev);
351 pm_runtime_put_autosuspend(mcspi->dev);
352 return 0;
353 }
354
355 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
356 {
357 unsigned long timeout;
358
359 timeout = jiffies + msecs_to_jiffies(1000);
360 while (!(__raw_readl(reg) & bit)) {
361 if (time_after(jiffies, timeout)) {
362 if (!(__raw_readl(reg) & bit))
363 return -ETIMEDOUT;
364 else
365 return 0;
366 }
367 cpu_relax();
368 }
369 return 0;
370 }
371
372 static void omap2_mcspi_rx_callback(void *data)
373 {
374 struct spi_device *spi = data;
375 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
376 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
377
378 /* We must disable the DMA RX request */
379 omap2_mcspi_set_dma_req(spi, 1, 0);
380
381 complete(&mcspi_dma->dma_rx_completion);
382 }
383
384 static void omap2_mcspi_tx_callback(void *data)
385 {
386 struct spi_device *spi = data;
387 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
388 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
389
390 /* We must disable the DMA TX request */
391 omap2_mcspi_set_dma_req(spi, 0, 0);
392
393 complete(&mcspi_dma->dma_tx_completion);
394 }
395
396 static void omap2_mcspi_tx_dma(struct spi_device *spi,
397 struct spi_transfer *xfer,
398 struct dma_slave_config cfg)
399 {
400 struct omap2_mcspi *mcspi;
401 struct omap2_mcspi_dma *mcspi_dma;
402 unsigned int count;
403
404 mcspi = spi_master_get_devdata(spi->master);
405 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
406 count = xfer->len;
407
408 if (mcspi_dma->dma_tx) {
409 struct dma_async_tx_descriptor *tx;
410 struct scatterlist sg;
411
412 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
413
414 sg_init_table(&sg, 1);
415 sg_dma_address(&sg) = xfer->tx_dma;
416 sg_dma_len(&sg) = xfer->len;
417
418 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
419 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
420 if (tx) {
421 tx->callback = omap2_mcspi_tx_callback;
422 tx->callback_param = spi;
423 dmaengine_submit(tx);
424 } else {
425 /* FIXME: fall back to PIO? */
426 }
427 }
428 dma_async_issue_pending(mcspi_dma->dma_tx);
429 omap2_mcspi_set_dma_req(spi, 0, 1);
430
431 }
432
433 static unsigned
434 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
435 struct dma_slave_config cfg,
436 unsigned es)
437 {
438 struct omap2_mcspi *mcspi;
439 struct omap2_mcspi_dma *mcspi_dma;
440 unsigned int count, dma_count;
441 u32 l;
442 int elements = 0;
443 int word_len, element_count;
444 struct omap2_mcspi_cs *cs = spi->controller_state;
445 mcspi = spi_master_get_devdata(spi->master);
446 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
447 count = xfer->len;
448 dma_count = xfer->len;
449
450 if (mcspi->fifo_depth == 0)
451 dma_count -= es;
452
453 word_len = cs->word_len;
454 l = mcspi_cached_chconf0(spi);
455
456 if (word_len <= 8)
457 element_count = count;
458 else if (word_len <= 16)
459 element_count = count >> 1;
460 else /* word_len <= 32 */
461 element_count = count >> 2;
462
463 if (mcspi_dma->dma_rx) {
464 struct dma_async_tx_descriptor *tx;
465 struct scatterlist sg;
466
467 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
468
469 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
470 dma_count -= es;
471
472 sg_init_table(&sg, 1);
473 sg_dma_address(&sg) = xfer->rx_dma;
474 sg_dma_len(&sg) = dma_count;
475
476 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
477 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
478 DMA_CTRL_ACK);
479 if (tx) {
480 tx->callback = omap2_mcspi_rx_callback;
481 tx->callback_param = spi;
482 dmaengine_submit(tx);
483 } else {
484 /* FIXME: fall back to PIO? */
485 }
486 }
487
488 dma_async_issue_pending(mcspi_dma->dma_rx);
489 omap2_mcspi_set_dma_req(spi, 1, 1);
490
491 wait_for_completion(&mcspi_dma->dma_rx_completion);
492 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
493 DMA_FROM_DEVICE);
494
495 if (mcspi->fifo_depth > 0)
496 return count;
497
498 omap2_mcspi_set_enable(spi, 0);
499
500 elements = element_count - 1;
501
502 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
503 elements--;
504
505 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
506 & OMAP2_MCSPI_CHSTAT_RXS)) {
507 u32 w;
508
509 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
510 if (word_len <= 8)
511 ((u8 *)xfer->rx_buf)[elements++] = w;
512 else if (word_len <= 16)
513 ((u16 *)xfer->rx_buf)[elements++] = w;
514 else /* word_len <= 32 */
515 ((u32 *)xfer->rx_buf)[elements++] = w;
516 } else {
517 int bytes_per_word = mcspi_bytes_per_word(word_len);
518 dev_err(&spi->dev, "DMA RX penultimate word empty");
519 count -= (bytes_per_word << 1);
520 omap2_mcspi_set_enable(spi, 1);
521 return count;
522 }
523 }
524 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
525 & OMAP2_MCSPI_CHSTAT_RXS)) {
526 u32 w;
527
528 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
529 if (word_len <= 8)
530 ((u8 *)xfer->rx_buf)[elements] = w;
531 else if (word_len <= 16)
532 ((u16 *)xfer->rx_buf)[elements] = w;
533 else /* word_len <= 32 */
534 ((u32 *)xfer->rx_buf)[elements] = w;
535 } else {
536 dev_err(&spi->dev, "DMA RX last word empty");
537 count -= mcspi_bytes_per_word(word_len);
538 }
539 omap2_mcspi_set_enable(spi, 1);
540 return count;
541 }
542
543 static unsigned
544 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
545 {
546 struct omap2_mcspi *mcspi;
547 struct omap2_mcspi_cs *cs = spi->controller_state;
548 struct omap2_mcspi_dma *mcspi_dma;
549 unsigned int count;
550 u32 l;
551 u8 *rx;
552 const u8 *tx;
553 struct dma_slave_config cfg;
554 enum dma_slave_buswidth width;
555 unsigned es;
556 u32 burst;
557 void __iomem *chstat_reg;
558 void __iomem *irqstat_reg;
559 int wait_res;
560
561 mcspi = spi_master_get_devdata(spi->master);
562 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
563 l = mcspi_cached_chconf0(spi);
564
565
566 if (cs->word_len <= 8) {
567 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
568 es = 1;
569 } else if (cs->word_len <= 16) {
570 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
571 es = 2;
572 } else {
573 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
574 es = 4;
575 }
576
577 count = xfer->len;
578 burst = 1;
579
580 if (mcspi->fifo_depth > 0) {
581 if (count > mcspi->fifo_depth)
582 burst = mcspi->fifo_depth / es;
583 else
584 burst = count / es;
585 }
586
587 memset(&cfg, 0, sizeof(cfg));
588 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
589 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
590 cfg.src_addr_width = width;
591 cfg.dst_addr_width = width;
592 cfg.src_maxburst = burst;
593 cfg.dst_maxburst = burst;
594
595 rx = xfer->rx_buf;
596 tx = xfer->tx_buf;
597
598 if (tx != NULL)
599 omap2_mcspi_tx_dma(spi, xfer, cfg);
600
601 if (rx != NULL)
602 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
603
604 if (tx != NULL) {
605 wait_for_completion(&mcspi_dma->dma_tx_completion);
606 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
607 DMA_TO_DEVICE);
608
609 if (mcspi->fifo_depth > 0) {
610 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
611
612 if (mcspi_wait_for_reg_bit(irqstat_reg,
613 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
614 dev_err(&spi->dev, "EOW timed out\n");
615
616 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
617 OMAP2_MCSPI_IRQSTATUS_EOW);
618 }
619
620 /* for TX_ONLY mode, be sure all words have shifted out */
621 if (rx == NULL) {
622 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
623 if (mcspi->fifo_depth > 0) {
624 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
625 OMAP2_MCSPI_CHSTAT_TXFFE);
626 if (wait_res < 0)
627 dev_err(&spi->dev, "TXFFE timed out\n");
628 } else {
629 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
630 OMAP2_MCSPI_CHSTAT_TXS);
631 if (wait_res < 0)
632 dev_err(&spi->dev, "TXS timed out\n");
633 }
634 if (wait_res >= 0 &&
635 (mcspi_wait_for_reg_bit(chstat_reg,
636 OMAP2_MCSPI_CHSTAT_EOT) < 0))
637 dev_err(&spi->dev, "EOT timed out\n");
638 }
639 }
640 return count;
641 }
642
643 static unsigned
644 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
645 {
646 struct omap2_mcspi *mcspi;
647 struct omap2_mcspi_cs *cs = spi->controller_state;
648 unsigned int count, c;
649 u32 l;
650 void __iomem *base = cs->base;
651 void __iomem *tx_reg;
652 void __iomem *rx_reg;
653 void __iomem *chstat_reg;
654 int word_len;
655
656 mcspi = spi_master_get_devdata(spi->master);
657 count = xfer->len;
658 c = count;
659 word_len = cs->word_len;
660
661 l = mcspi_cached_chconf0(spi);
662
663 /* We store the pre-calculated register addresses on stack to speed
664 * up the transfer loop. */
665 tx_reg = base + OMAP2_MCSPI_TX0;
666 rx_reg = base + OMAP2_MCSPI_RX0;
667 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
668
669 if (c < (word_len>>3))
670 return 0;
671
672 if (word_len <= 8) {
673 u8 *rx;
674 const u8 *tx;
675
676 rx = xfer->rx_buf;
677 tx = xfer->tx_buf;
678
679 do {
680 c -= 1;
681 if (tx != NULL) {
682 if (mcspi_wait_for_reg_bit(chstat_reg,
683 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
684 dev_err(&spi->dev, "TXS timed out\n");
685 goto out;
686 }
687 dev_vdbg(&spi->dev, "write-%d %02x\n",
688 word_len, *tx);
689 __raw_writel(*tx++, tx_reg);
690 }
691 if (rx != NULL) {
692 if (mcspi_wait_for_reg_bit(chstat_reg,
693 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
694 dev_err(&spi->dev, "RXS timed out\n");
695 goto out;
696 }
697
698 if (c == 1 && tx == NULL &&
699 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
700 omap2_mcspi_set_enable(spi, 0);
701 *rx++ = __raw_readl(rx_reg);
702 dev_vdbg(&spi->dev, "read-%d %02x\n",
703 word_len, *(rx - 1));
704 if (mcspi_wait_for_reg_bit(chstat_reg,
705 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
706 dev_err(&spi->dev,
707 "RXS timed out\n");
708 goto out;
709 }
710 c = 0;
711 } else if (c == 0 && tx == NULL) {
712 omap2_mcspi_set_enable(spi, 0);
713 }
714
715 *rx++ = __raw_readl(rx_reg);
716 dev_vdbg(&spi->dev, "read-%d %02x\n",
717 word_len, *(rx - 1));
718 }
719 } while (c);
720 } else if (word_len <= 16) {
721 u16 *rx;
722 const u16 *tx;
723
724 rx = xfer->rx_buf;
725 tx = xfer->tx_buf;
726 do {
727 c -= 2;
728 if (tx != NULL) {
729 if (mcspi_wait_for_reg_bit(chstat_reg,
730 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
731 dev_err(&spi->dev, "TXS timed out\n");
732 goto out;
733 }
734 dev_vdbg(&spi->dev, "write-%d %04x\n",
735 word_len, *tx);
736 __raw_writel(*tx++, tx_reg);
737 }
738 if (rx != NULL) {
739 if (mcspi_wait_for_reg_bit(chstat_reg,
740 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
741 dev_err(&spi->dev, "RXS timed out\n");
742 goto out;
743 }
744
745 if (c == 2 && tx == NULL &&
746 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
747 omap2_mcspi_set_enable(spi, 0);
748 *rx++ = __raw_readl(rx_reg);
749 dev_vdbg(&spi->dev, "read-%d %04x\n",
750 word_len, *(rx - 1));
751 if (mcspi_wait_for_reg_bit(chstat_reg,
752 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
753 dev_err(&spi->dev,
754 "RXS timed out\n");
755 goto out;
756 }
757 c = 0;
758 } else if (c == 0 && tx == NULL) {
759 omap2_mcspi_set_enable(spi, 0);
760 }
761
762 *rx++ = __raw_readl(rx_reg);
763 dev_vdbg(&spi->dev, "read-%d %04x\n",
764 word_len, *(rx - 1));
765 }
766 } while (c >= 2);
767 } else if (word_len <= 32) {
768 u32 *rx;
769 const u32 *tx;
770
771 rx = xfer->rx_buf;
772 tx = xfer->tx_buf;
773 do {
774 c -= 4;
775 if (tx != NULL) {
776 if (mcspi_wait_for_reg_bit(chstat_reg,
777 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
778 dev_err(&spi->dev, "TXS timed out\n");
779 goto out;
780 }
781 dev_vdbg(&spi->dev, "write-%d %08x\n",
782 word_len, *tx);
783 __raw_writel(*tx++, tx_reg);
784 }
785 if (rx != NULL) {
786 if (mcspi_wait_for_reg_bit(chstat_reg,
787 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
788 dev_err(&spi->dev, "RXS timed out\n");
789 goto out;
790 }
791
792 if (c == 4 && tx == NULL &&
793 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
794 omap2_mcspi_set_enable(spi, 0);
795 *rx++ = __raw_readl(rx_reg);
796 dev_vdbg(&spi->dev, "read-%d %08x\n",
797 word_len, *(rx - 1));
798 if (mcspi_wait_for_reg_bit(chstat_reg,
799 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
800 dev_err(&spi->dev,
801 "RXS timed out\n");
802 goto out;
803 }
804 c = 0;
805 } else if (c == 0 && tx == NULL) {
806 omap2_mcspi_set_enable(spi, 0);
807 }
808
809 *rx++ = __raw_readl(rx_reg);
810 dev_vdbg(&spi->dev, "read-%d %08x\n",
811 word_len, *(rx - 1));
812 }
813 } while (c >= 4);
814 }
815
816 /* for TX_ONLY mode, be sure all words have shifted out */
817 if (xfer->rx_buf == NULL) {
818 if (mcspi_wait_for_reg_bit(chstat_reg,
819 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
820 dev_err(&spi->dev, "TXS timed out\n");
821 } else if (mcspi_wait_for_reg_bit(chstat_reg,
822 OMAP2_MCSPI_CHSTAT_EOT) < 0)
823 dev_err(&spi->dev, "EOT timed out\n");
824
825 /* disable chan to purge rx datas received in TX_ONLY transfer,
826 * otherwise these rx datas will affect the direct following
827 * RX_ONLY transfer.
828 */
829 omap2_mcspi_set_enable(spi, 0);
830 }
831 out:
832 omap2_mcspi_set_enable(spi, 1);
833 return count - c;
834 }
835
836 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
837 {
838 u32 div;
839
840 for (div = 0; div < 15; div++)
841 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
842 return div;
843
844 return 15;
845 }
846
847 /* called only when no transfer is active to this device */
848 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
849 struct spi_transfer *t)
850 {
851 struct omap2_mcspi_cs *cs = spi->controller_state;
852 struct omap2_mcspi *mcspi;
853 struct spi_master *spi_cntrl;
854 u32 l = 0, div = 0;
855 u8 word_len = spi->bits_per_word;
856 u32 speed_hz = spi->max_speed_hz;
857
858 mcspi = spi_master_get_devdata(spi->master);
859 spi_cntrl = mcspi->master;
860
861 if (t != NULL && t->bits_per_word)
862 word_len = t->bits_per_word;
863
864 cs->word_len = word_len;
865
866 if (t && t->speed_hz)
867 speed_hz = t->speed_hz;
868
869 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
870 div = omap2_mcspi_calc_divisor(speed_hz);
871
872 l = mcspi_cached_chconf0(spi);
873
874 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
875 * REVISIT: this controller could support SPI_3WIRE mode.
876 */
877 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
878 l &= ~OMAP2_MCSPI_CHCONF_IS;
879 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
880 l |= OMAP2_MCSPI_CHCONF_DPE0;
881 } else {
882 l |= OMAP2_MCSPI_CHCONF_IS;
883 l |= OMAP2_MCSPI_CHCONF_DPE1;
884 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
885 }
886
887 /* wordlength */
888 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
889 l |= (word_len - 1) << 7;
890
891 /* set chipselect polarity; manage with FORCE */
892 if (!(spi->mode & SPI_CS_HIGH))
893 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
894 else
895 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
896
897 /* set clock divisor */
898 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
899 l |= div << 2;
900
901 /* set SPI mode 0..3 */
902 if (spi->mode & SPI_CPOL)
903 l |= OMAP2_MCSPI_CHCONF_POL;
904 else
905 l &= ~OMAP2_MCSPI_CHCONF_POL;
906 if (spi->mode & SPI_CPHA)
907 l |= OMAP2_MCSPI_CHCONF_PHA;
908 else
909 l &= ~OMAP2_MCSPI_CHCONF_PHA;
910
911 mcspi_write_chconf0(spi, l);
912
913 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
914 OMAP2_MCSPI_MAX_FREQ >> div,
915 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
916 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
917
918 return 0;
919 }
920
921 /*
922 * Note that we currently allow DMA only if we get a channel
923 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
924 */
925 static int omap2_mcspi_request_dma(struct spi_device *spi)
926 {
927 struct spi_master *master = spi->master;
928 struct omap2_mcspi *mcspi;
929 struct omap2_mcspi_dma *mcspi_dma;
930 dma_cap_mask_t mask;
931 unsigned sig;
932
933 mcspi = spi_master_get_devdata(master);
934 mcspi_dma = mcspi->dma_channels + spi->chip_select;
935
936 init_completion(&mcspi_dma->dma_rx_completion);
937 init_completion(&mcspi_dma->dma_tx_completion);
938
939 dma_cap_zero(mask);
940 dma_cap_set(DMA_SLAVE, mask);
941 sig = mcspi_dma->dma_rx_sync_dev;
942
943 mcspi_dma->dma_rx =
944 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
945 &sig, &master->dev,
946 mcspi_dma->dma_rx_ch_name);
947 if (!mcspi_dma->dma_rx)
948 goto no_dma;
949
950 sig = mcspi_dma->dma_tx_sync_dev;
951 mcspi_dma->dma_tx =
952 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
953 &sig, &master->dev,
954 mcspi_dma->dma_tx_ch_name);
955
956 if (!mcspi_dma->dma_tx) {
957 dma_release_channel(mcspi_dma->dma_rx);
958 mcspi_dma->dma_rx = NULL;
959 goto no_dma;
960 }
961
962 return 0;
963
964 no_dma:
965 dev_warn(&spi->dev, "not using DMA for McSPI\n");
966 return -EAGAIN;
967 }
968
969 static int omap2_mcspi_setup(struct spi_device *spi)
970 {
971 int ret;
972 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
973 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
974 struct omap2_mcspi_dma *mcspi_dma;
975 struct omap2_mcspi_cs *cs = spi->controller_state;
976
977 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
978
979 if (!cs) {
980 cs = kzalloc(sizeof *cs, GFP_KERNEL);
981 if (!cs)
982 return -ENOMEM;
983 cs->base = mcspi->base + spi->chip_select * 0x14;
984 cs->phys = mcspi->phys + spi->chip_select * 0x14;
985 cs->chconf0 = 0;
986 spi->controller_state = cs;
987 /* Link this to context save list */
988 list_add_tail(&cs->node, &ctx->cs);
989 }
990
991 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
992 ret = omap2_mcspi_request_dma(spi);
993 if (ret < 0 && ret != -EAGAIN)
994 return ret;
995 }
996
997 ret = pm_runtime_get_sync(mcspi->dev);
998 if (ret < 0)
999 return ret;
1000
1001 ret = omap2_mcspi_setup_transfer(spi, NULL);
1002 pm_runtime_mark_last_busy(mcspi->dev);
1003 pm_runtime_put_autosuspend(mcspi->dev);
1004
1005 return ret;
1006 }
1007
1008 static void omap2_mcspi_cleanup(struct spi_device *spi)
1009 {
1010 struct omap2_mcspi *mcspi;
1011 struct omap2_mcspi_dma *mcspi_dma;
1012 struct omap2_mcspi_cs *cs;
1013
1014 mcspi = spi_master_get_devdata(spi->master);
1015
1016 if (spi->controller_state) {
1017 /* Unlink controller state from context save list */
1018 cs = spi->controller_state;
1019 list_del(&cs->node);
1020
1021 kfree(cs);
1022 }
1023
1024 if (spi->chip_select < spi->master->num_chipselect) {
1025 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1026
1027 if (mcspi_dma->dma_rx) {
1028 dma_release_channel(mcspi_dma->dma_rx);
1029 mcspi_dma->dma_rx = NULL;
1030 }
1031 if (mcspi_dma->dma_tx) {
1032 dma_release_channel(mcspi_dma->dma_tx);
1033 mcspi_dma->dma_tx = NULL;
1034 }
1035 }
1036 }
1037
1038 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1039 {
1040
1041 /* We only enable one channel at a time -- the one whose message is
1042 * -- although this controller would gladly
1043 * arbitrate among multiple channels. This corresponds to "single
1044 * channel" master mode. As a side effect, we need to manage the
1045 * chipselect with the FORCE bit ... CS != channel enable.
1046 */
1047
1048 struct spi_device *spi;
1049 struct spi_transfer *t = NULL;
1050 struct spi_master *master;
1051 struct omap2_mcspi_dma *mcspi_dma;
1052 int cs_active = 0;
1053 struct omap2_mcspi_cs *cs;
1054 struct omap2_mcspi_device_config *cd;
1055 int par_override = 0;
1056 int status = 0;
1057 u32 chconf;
1058
1059 spi = m->spi;
1060 master = spi->master;
1061 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1062 cs = spi->controller_state;
1063 cd = spi->controller_data;
1064
1065 omap2_mcspi_set_enable(spi, 0);
1066 list_for_each_entry(t, &m->transfers, transfer_list) {
1067 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1068 status = -EINVAL;
1069 break;
1070 }
1071 if (par_override || t->speed_hz || t->bits_per_word) {
1072 par_override = 1;
1073 status = omap2_mcspi_setup_transfer(spi, t);
1074 if (status < 0)
1075 break;
1076 if (!t->speed_hz && !t->bits_per_word)
1077 par_override = 0;
1078 }
1079 if (cd && cd->cs_per_word) {
1080 chconf = mcspi->ctx.modulctrl;
1081 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1082 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1083 mcspi->ctx.modulctrl =
1084 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1085 }
1086
1087
1088 if (!cs_active) {
1089 omap2_mcspi_force_cs(spi, 1);
1090 cs_active = 1;
1091 }
1092
1093 chconf = mcspi_cached_chconf0(spi);
1094 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1095 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1096
1097 if (t->tx_buf == NULL)
1098 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1099 else if (t->rx_buf == NULL)
1100 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1101
1102 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1103 /* Turbo mode is for more than one word */
1104 if (t->len > ((cs->word_len + 7) >> 3))
1105 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1106 }
1107
1108 mcspi_write_chconf0(spi, chconf);
1109
1110 if (t->len) {
1111 unsigned count;
1112
1113 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1114 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1115 omap2_mcspi_set_fifo(spi, t, 1);
1116
1117 omap2_mcspi_set_enable(spi, 1);
1118
1119 /* RX_ONLY mode needs dummy data in TX reg */
1120 if (t->tx_buf == NULL)
1121 __raw_writel(0, cs->base
1122 + OMAP2_MCSPI_TX0);
1123
1124 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1125 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1126 count = omap2_mcspi_txrx_dma(spi, t);
1127 else
1128 count = omap2_mcspi_txrx_pio(spi, t);
1129 m->actual_length += count;
1130
1131 if (count != t->len) {
1132 status = -EIO;
1133 break;
1134 }
1135 }
1136
1137 if (t->delay_usecs)
1138 udelay(t->delay_usecs);
1139
1140 /* ignore the "leave it on after last xfer" hint */
1141 if (t->cs_change) {
1142 omap2_mcspi_force_cs(spi, 0);
1143 cs_active = 0;
1144 }
1145
1146 omap2_mcspi_set_enable(spi, 0);
1147
1148 if (mcspi->fifo_depth > 0)
1149 omap2_mcspi_set_fifo(spi, t, 0);
1150 }
1151 /* Restore defaults if they were overriden */
1152 if (par_override) {
1153 par_override = 0;
1154 status = omap2_mcspi_setup_transfer(spi, NULL);
1155 }
1156
1157 if (cs_active)
1158 omap2_mcspi_force_cs(spi, 0);
1159
1160 if (cd && cd->cs_per_word) {
1161 chconf = mcspi->ctx.modulctrl;
1162 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1163 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1164 mcspi->ctx.modulctrl =
1165 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1166 }
1167
1168 omap2_mcspi_set_enable(spi, 0);
1169
1170 if (mcspi->fifo_depth > 0 && t)
1171 omap2_mcspi_set_fifo(spi, t, 0);
1172
1173 m->status = status;
1174 }
1175
1176 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1177 struct spi_message *m)
1178 {
1179 struct spi_device *spi;
1180 struct omap2_mcspi *mcspi;
1181 struct omap2_mcspi_dma *mcspi_dma;
1182 struct spi_transfer *t;
1183
1184 spi = m->spi;
1185 mcspi = spi_master_get_devdata(master);
1186 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1187 m->actual_length = 0;
1188 m->status = 0;
1189
1190 /* reject invalid messages and transfers */
1191 if (list_empty(&m->transfers))
1192 return -EINVAL;
1193 list_for_each_entry(t, &m->transfers, transfer_list) {
1194 const void *tx_buf = t->tx_buf;
1195 void *rx_buf = t->rx_buf;
1196 unsigned len = t->len;
1197
1198 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1199 || (len && !(rx_buf || tx_buf))) {
1200 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1201 t->speed_hz,
1202 len,
1203 tx_buf ? "tx" : "",
1204 rx_buf ? "rx" : "",
1205 t->bits_per_word);
1206 return -EINVAL;
1207 }
1208 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1209 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1210 t->speed_hz,
1211 OMAP2_MCSPI_MAX_FREQ >> 15);
1212 return -EINVAL;
1213 }
1214
1215 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1216 continue;
1217
1218 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1219 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1220 len, DMA_TO_DEVICE);
1221 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1222 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1223 'T', len);
1224 return -EINVAL;
1225 }
1226 }
1227 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1228 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1229 DMA_FROM_DEVICE);
1230 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1231 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1232 'R', len);
1233 if (tx_buf != NULL)
1234 dma_unmap_single(mcspi->dev, t->tx_dma,
1235 len, DMA_TO_DEVICE);
1236 return -EINVAL;
1237 }
1238 }
1239 }
1240
1241 omap2_mcspi_work(mcspi, m);
1242 spi_finalize_current_message(master);
1243 return 0;
1244 }
1245
1246 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1247 {
1248 struct spi_master *master = mcspi->master;
1249 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1250 int ret = 0;
1251
1252 ret = pm_runtime_get_sync(mcspi->dev);
1253 if (ret < 0)
1254 return ret;
1255
1256 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1257 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1258 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1259
1260 omap2_mcspi_set_master_mode(master);
1261 pm_runtime_mark_last_busy(mcspi->dev);
1262 pm_runtime_put_autosuspend(mcspi->dev);
1263 return 0;
1264 }
1265
1266 static int omap_mcspi_runtime_resume(struct device *dev)
1267 {
1268 struct omap2_mcspi *mcspi;
1269 struct spi_master *master;
1270
1271 master = dev_get_drvdata(dev);
1272 mcspi = spi_master_get_devdata(master);
1273 omap2_mcspi_restore_ctx(mcspi);
1274
1275 return 0;
1276 }
1277
1278 static struct omap2_mcspi_platform_config omap2_pdata = {
1279 .regs_offset = 0,
1280 };
1281
1282 static struct omap2_mcspi_platform_config omap4_pdata = {
1283 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1284 };
1285
1286 static const struct of_device_id omap_mcspi_of_match[] = {
1287 {
1288 .compatible = "ti,omap2-mcspi",
1289 .data = &omap2_pdata,
1290 },
1291 {
1292 .compatible = "ti,omap4-mcspi",
1293 .data = &omap4_pdata,
1294 },
1295 { },
1296 };
1297 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1298
1299 static int omap2_mcspi_probe(struct platform_device *pdev)
1300 {
1301 struct spi_master *master;
1302 const struct omap2_mcspi_platform_config *pdata;
1303 struct omap2_mcspi *mcspi;
1304 struct resource *r;
1305 int status = 0, i;
1306 u32 regs_offset = 0;
1307 static int bus_num = 1;
1308 struct device_node *node = pdev->dev.of_node;
1309 const struct of_device_id *match;
1310
1311 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1312 if (master == NULL) {
1313 dev_dbg(&pdev->dev, "master allocation failed\n");
1314 return -ENOMEM;
1315 }
1316
1317 /* the spi->mode bits understood by this driver: */
1318 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1319 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1320 master->setup = omap2_mcspi_setup;
1321 master->prepare_transfer_hardware = omap2_prepare_transfer;
1322 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1323 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1324 master->cleanup = omap2_mcspi_cleanup;
1325 master->dev.of_node = node;
1326
1327 platform_set_drvdata(pdev, master);
1328
1329 mcspi = spi_master_get_devdata(master);
1330 mcspi->master = master;
1331
1332 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1333 if (match) {
1334 u32 num_cs = 1; /* default number of chipselect */
1335 pdata = match->data;
1336
1337 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1338 master->num_chipselect = num_cs;
1339 master->bus_num = bus_num++;
1340 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1341 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1342 } else {
1343 pdata = pdev->dev.platform_data;
1344 master->num_chipselect = pdata->num_cs;
1345 if (pdev->id != -1)
1346 master->bus_num = pdev->id;
1347 mcspi->pin_dir = pdata->pin_dir;
1348 }
1349 regs_offset = pdata->regs_offset;
1350
1351 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352 if (r == NULL) {
1353 status = -ENODEV;
1354 goto free_master;
1355 }
1356
1357 r->start += regs_offset;
1358 r->end += regs_offset;
1359 mcspi->phys = r->start;
1360
1361 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1362 if (IS_ERR(mcspi->base)) {
1363 status = PTR_ERR(mcspi->base);
1364 goto free_master;
1365 }
1366
1367 mcspi->dev = &pdev->dev;
1368
1369 INIT_LIST_HEAD(&mcspi->ctx.cs);
1370
1371 mcspi->dma_channels = kcalloc(master->num_chipselect,
1372 sizeof(struct omap2_mcspi_dma),
1373 GFP_KERNEL);
1374
1375 if (mcspi->dma_channels == NULL)
1376 goto free_master;
1377
1378 for (i = 0; i < master->num_chipselect; i++) {
1379 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1380 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1381 struct resource *dma_res;
1382
1383 sprintf(dma_rx_ch_name, "rx%d", i);
1384 if (!pdev->dev.of_node) {
1385 dma_res =
1386 platform_get_resource_byname(pdev,
1387 IORESOURCE_DMA,
1388 dma_rx_ch_name);
1389 if (!dma_res) {
1390 dev_dbg(&pdev->dev,
1391 "cannot get DMA RX channel\n");
1392 status = -ENODEV;
1393 break;
1394 }
1395
1396 mcspi->dma_channels[i].dma_rx_sync_dev =
1397 dma_res->start;
1398 }
1399 sprintf(dma_tx_ch_name, "tx%d", i);
1400 if (!pdev->dev.of_node) {
1401 dma_res =
1402 platform_get_resource_byname(pdev,
1403 IORESOURCE_DMA,
1404 dma_tx_ch_name);
1405 if (!dma_res) {
1406 dev_dbg(&pdev->dev,
1407 "cannot get DMA TX channel\n");
1408 status = -ENODEV;
1409 break;
1410 }
1411
1412 mcspi->dma_channels[i].dma_tx_sync_dev =
1413 dma_res->start;
1414 }
1415 }
1416
1417 if (status < 0)
1418 goto dma_chnl_free;
1419
1420 pm_runtime_use_autosuspend(&pdev->dev);
1421 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1422 pm_runtime_enable(&pdev->dev);
1423
1424 status = omap2_mcspi_master_setup(mcspi);
1425 if (status < 0)
1426 goto disable_pm;
1427
1428 status = spi_register_master(master);
1429 if (status < 0)
1430 goto disable_pm;
1431
1432 return status;
1433
1434 disable_pm:
1435 pm_runtime_disable(&pdev->dev);
1436 dma_chnl_free:
1437 kfree(mcspi->dma_channels);
1438 free_master:
1439 spi_master_put(master);
1440 return status;
1441 }
1442
1443 static int omap2_mcspi_remove(struct platform_device *pdev)
1444 {
1445 struct spi_master *master;
1446 struct omap2_mcspi *mcspi;
1447 struct omap2_mcspi_dma *dma_channels;
1448
1449 master = platform_get_drvdata(pdev);
1450 mcspi = spi_master_get_devdata(master);
1451 dma_channels = mcspi->dma_channels;
1452
1453 pm_runtime_put_sync(mcspi->dev);
1454 pm_runtime_disable(&pdev->dev);
1455
1456 spi_unregister_master(master);
1457 kfree(dma_channels);
1458
1459 return 0;
1460 }
1461
1462 /* work with hotplug and coldplug */
1463 MODULE_ALIAS("platform:omap2_mcspi");
1464
1465 #ifdef CONFIG_SUSPEND
1466 /*
1467 * When SPI wake up from off-mode, CS is in activate state. If it was in
1468 * unactive state when driver was suspend, then force it to unactive state at
1469 * wake up.
1470 */
1471 static int omap2_mcspi_resume(struct device *dev)
1472 {
1473 struct spi_master *master = dev_get_drvdata(dev);
1474 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1475 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1476 struct omap2_mcspi_cs *cs;
1477
1478 pm_runtime_get_sync(mcspi->dev);
1479 list_for_each_entry(cs, &ctx->cs, node) {
1480 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1481 /*
1482 * We need to toggle CS state for OMAP take this
1483 * change in account.
1484 */
1485 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1486 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1487 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1488 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1489 }
1490 }
1491 pm_runtime_mark_last_busy(mcspi->dev);
1492 pm_runtime_put_autosuspend(mcspi->dev);
1493 return 0;
1494 }
1495 #else
1496 #define omap2_mcspi_resume NULL
1497 #endif
1498
1499 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1500 .resume = omap2_mcspi_resume,
1501 .runtime_resume = omap_mcspi_runtime_resume,
1502 };
1503
1504 static struct platform_driver omap2_mcspi_driver = {
1505 .driver = {
1506 .name = "omap2_mcspi",
1507 .owner = THIS_MODULE,
1508 .pm = &omap2_mcspi_pm_ops,
1509 .of_match_table = omap_mcspi_of_match,
1510 },
1511 .probe = omap2_mcspi_probe,
1512 .remove = omap2_mcspi_remove,
1513 };
1514
1515 module_platform_driver(omap2_mcspi_driver);
1516 MODULE_LICENSE("GPL");
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