2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_device.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24 #include <asm/unaligned.h>
26 #define DRIVER_NAME "orion_spi"
28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
29 #define SPI_AUTOSUSPEND_TIMEOUT 200
31 /* Some SoCs using this driver support up to 8 chip selects.
32 * It is up to the implementer to only use the chip selects
35 #define ORION_NUM_CHIPSELECTS 8
37 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
39 #define ORION_SPI_IF_CTRL_REG 0x00
40 #define ORION_SPI_IF_CONFIG_REG 0x04
41 #define ORION_SPI_DATA_OUT_REG 0x08
42 #define ORION_SPI_DATA_IN_REG 0x0c
43 #define ORION_SPI_INT_CAUSE_REG 0x10
45 #define ORION_SPI_MODE_CPOL (1 << 11)
46 #define ORION_SPI_MODE_CPHA (1 << 12)
47 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
48 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
49 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
50 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
52 #define ORION_SPI_CS_MASK 0x1C
53 #define ORION_SPI_CS_SHIFT 2
54 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
62 struct orion_spi_dev
{
63 enum orion_spi_type typ
;
64 unsigned int min_divisor
;
65 unsigned int max_divisor
;
70 struct spi_master
*master
;
73 const struct orion_spi_dev
*devdata
;
76 static inline void __iomem
*spi_reg(struct orion_spi
*orion_spi
, u32 reg
)
78 return orion_spi
->base
+ reg
;
82 orion_spi_setbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
84 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
87 val
= readl(reg_addr
);
89 writel(val
, reg_addr
);
93 orion_spi_clrbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
95 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
98 val
= readl(reg_addr
);
100 writel(val
, reg_addr
);
103 static int orion_spi_baudrate_set(struct spi_device
*spi
, unsigned int speed
)
109 struct orion_spi
*orion_spi
;
110 const struct orion_spi_dev
*devdata
;
112 orion_spi
= spi_master_get_devdata(spi
->master
);
113 devdata
= orion_spi
->devdata
;
115 tclk_hz
= clk_get_rate(orion_spi
->clk
);
117 if (devdata
->typ
== ARMADA_SPI
) {
118 unsigned int clk
, spr
, sppr
, sppr2
, err
;
119 unsigned int best_spr
, best_sppr
, best_err
;
125 /* Iterate over the valid range looking for best fit */
126 for (sppr
= 0; sppr
< 8; sppr
++) {
129 spr
= tclk_hz
/ sppr2
;
130 spr
= DIV_ROUND_UP(spr
, speed
);
131 if ((spr
== 0) || (spr
> 15))
134 clk
= tclk_hz
/ (spr
* sppr2
);
137 if (err
< best_err
) {
144 if ((best_sppr
== 0) && (best_spr
== 0))
147 prescale
= ((best_sppr
& 0x6) << 5) |
148 ((best_sppr
& 0x1) << 4) | best_spr
;
151 * the supported rates are: 4,6,8...30
152 * round up as we look for equal or less speed
154 rate
= DIV_ROUND_UP(tclk_hz
, speed
);
155 rate
= roundup(rate
, 2);
157 /* check if requested speed is too small */
164 /* Convert the rate to SPI clock divisor value. */
165 prescale
= 0x10 + rate
/2;
168 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
169 reg
= ((reg
& ~devdata
->prescale_mask
) | prescale
);
170 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
176 orion_spi_mode_set(struct spi_device
*spi
)
179 struct orion_spi
*orion_spi
;
181 orion_spi
= spi_master_get_devdata(spi
->master
);
183 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
184 reg
&= ~ORION_SPI_MODE_MASK
;
185 if (spi
->mode
& SPI_CPOL
)
186 reg
|= ORION_SPI_MODE_CPOL
;
187 if (spi
->mode
& SPI_CPHA
)
188 reg
|= ORION_SPI_MODE_CPHA
;
189 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
193 * called only when no transfer is active on the bus
196 orion_spi_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
198 struct orion_spi
*orion_spi
;
199 unsigned int speed
= spi
->max_speed_hz
;
200 unsigned int bits_per_word
= spi
->bits_per_word
;
203 orion_spi
= spi_master_get_devdata(spi
->master
);
205 if ((t
!= NULL
) && t
->speed_hz
)
208 if ((t
!= NULL
) && t
->bits_per_word
)
209 bits_per_word
= t
->bits_per_word
;
211 orion_spi_mode_set(spi
);
213 rc
= orion_spi_baudrate_set(spi
, speed
);
217 if (bits_per_word
== 16)
218 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
219 ORION_SPI_IF_8_16_BIT_MODE
);
221 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
222 ORION_SPI_IF_8_16_BIT_MODE
);
227 static void orion_spi_set_cs(struct spi_device
*spi
, bool enable
)
229 struct orion_spi
*orion_spi
;
231 orion_spi
= spi_master_get_devdata(spi
->master
);
233 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, ORION_SPI_CS_MASK
);
234 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
,
235 ORION_SPI_CS(spi
->chip_select
));
237 /* Chip select logic is inverted from spi_set_cs */
239 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
241 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
244 static inline int orion_spi_wait_till_ready(struct orion_spi
*orion_spi
)
248 for (i
= 0; i
< ORION_SPI_WAIT_RDY_MAX_LOOP
; i
++) {
249 if (readl(spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
)))
259 orion_spi_write_read_8bit(struct spi_device
*spi
,
260 const u8
**tx_buf
, u8
**rx_buf
)
262 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
263 struct orion_spi
*orion_spi
;
265 orion_spi
= spi_master_get_devdata(spi
->master
);
266 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
267 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
268 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
270 /* clear the interrupt cause register */
271 writel(0x0, int_reg
);
273 if (tx_buf
&& *tx_buf
)
274 writel(*(*tx_buf
)++, tx_reg
);
278 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
279 dev_err(&spi
->dev
, "TXS timed out\n");
283 if (rx_buf
&& *rx_buf
)
284 *(*rx_buf
)++ = readl(rx_reg
);
290 orion_spi_write_read_16bit(struct spi_device
*spi
,
291 const u16
**tx_buf
, u16
**rx_buf
)
293 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
294 struct orion_spi
*orion_spi
;
296 orion_spi
= spi_master_get_devdata(spi
->master
);
297 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
298 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
299 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
301 /* clear the interrupt cause register */
302 writel(0x0, int_reg
);
304 if (tx_buf
&& *tx_buf
)
305 writel(__cpu_to_le16(get_unaligned((*tx_buf
)++)), tx_reg
);
309 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
310 dev_err(&spi
->dev
, "TXS timed out\n");
314 if (rx_buf
&& *rx_buf
)
315 put_unaligned(__le16_to_cpu(readl(rx_reg
)), (*rx_buf
)++);
321 orion_spi_write_read(struct spi_device
*spi
, struct spi_transfer
*xfer
)
326 word_len
= spi
->bits_per_word
;
330 const u8
*tx
= xfer
->tx_buf
;
331 u8
*rx
= xfer
->rx_buf
;
334 if (orion_spi_write_read_8bit(spi
, &tx
, &rx
) < 0)
338 } else if (word_len
== 16) {
339 const u16
*tx
= xfer
->tx_buf
;
340 u16
*rx
= xfer
->rx_buf
;
343 if (orion_spi_write_read_16bit(spi
, &tx
, &rx
) < 0)
350 return xfer
->len
- count
;
353 static int orion_spi_transfer_one(struct spi_master
*master
,
354 struct spi_device
*spi
,
355 struct spi_transfer
*t
)
359 status
= orion_spi_setup_transfer(spi
, t
);
364 orion_spi_write_read(spi
, t
);
369 static int orion_spi_setup(struct spi_device
*spi
)
371 return orion_spi_setup_transfer(spi
, NULL
);
374 static int orion_spi_reset(struct orion_spi
*orion_spi
)
376 /* Verify that the CS is deasserted */
377 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
381 static const struct orion_spi_dev orion_spi_dev_data
= {
385 .prescale_mask
= ORION_SPI_CLK_PRESCALE_MASK
,
388 static const struct orion_spi_dev armada_spi_dev_data
= {
392 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
395 static const struct of_device_id orion_spi_of_match_table
[] = {
396 { .compatible
= "marvell,orion-spi", .data
= &orion_spi_dev_data
, },
397 { .compatible
= "marvell,armada-370-spi", .data
= &armada_spi_dev_data
, },
400 MODULE_DEVICE_TABLE(of
, orion_spi_of_match_table
);
402 static int orion_spi_probe(struct platform_device
*pdev
)
404 const struct of_device_id
*of_id
;
405 const struct orion_spi_dev
*devdata
;
406 struct spi_master
*master
;
407 struct orion_spi
*spi
;
409 unsigned long tclk_hz
;
412 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
413 if (master
== NULL
) {
414 dev_dbg(&pdev
->dev
, "master allocation failed\n");
419 master
->bus_num
= pdev
->id
;
420 if (pdev
->dev
.of_node
) {
423 if (!of_property_read_u32(pdev
->dev
.of_node
, "cell-index",
425 master
->bus_num
= cell_index
;
428 /* we support only mode 0, and no options */
429 master
->mode_bits
= SPI_CPHA
| SPI_CPOL
;
430 master
->set_cs
= orion_spi_set_cs
;
431 master
->transfer_one
= orion_spi_transfer_one
;
432 master
->num_chipselect
= ORION_NUM_CHIPSELECTS
;
433 master
->setup
= orion_spi_setup
;
434 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
435 master
->auto_runtime_pm
= true;
437 platform_set_drvdata(pdev
, master
);
439 spi
= spi_master_get_devdata(master
);
440 spi
->master
= master
;
442 of_id
= of_match_device(orion_spi_of_match_table
, &pdev
->dev
);
443 devdata
= (of_id
) ? of_id
->data
: &orion_spi_dev_data
;
444 spi
->devdata
= devdata
;
446 spi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
447 if (IS_ERR(spi
->clk
)) {
448 status
= PTR_ERR(spi
->clk
);
452 status
= clk_prepare_enable(spi
->clk
);
456 tclk_hz
= clk_get_rate(spi
->clk
);
457 master
->max_speed_hz
= DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
);
458 master
->min_speed_hz
= DIV_ROUND_UP(tclk_hz
, devdata
->max_divisor
);
460 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
461 spi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
462 if (IS_ERR(spi
->base
)) {
463 status
= PTR_ERR(spi
->base
);
467 pm_runtime_set_active(&pdev
->dev
);
468 pm_runtime_use_autosuspend(&pdev
->dev
);
469 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
470 pm_runtime_enable(&pdev
->dev
);
472 status
= orion_spi_reset(spi
);
476 pm_runtime_mark_last_busy(&pdev
->dev
);
477 pm_runtime_put_autosuspend(&pdev
->dev
);
479 master
->dev
.of_node
= pdev
->dev
.of_node
;
480 status
= spi_register_master(master
);
487 pm_runtime_disable(&pdev
->dev
);
489 clk_disable_unprepare(spi
->clk
);
491 spi_master_put(master
);
496 static int orion_spi_remove(struct platform_device
*pdev
)
498 struct spi_master
*master
= platform_get_drvdata(pdev
);
499 struct orion_spi
*spi
= spi_master_get_devdata(master
);
501 pm_runtime_get_sync(&pdev
->dev
);
502 clk_disable_unprepare(spi
->clk
);
504 spi_unregister_master(master
);
505 pm_runtime_disable(&pdev
->dev
);
510 MODULE_ALIAS("platform:" DRIVER_NAME
);
513 static int orion_spi_runtime_suspend(struct device
*dev
)
515 struct spi_master
*master
= dev_get_drvdata(dev
);
516 struct orion_spi
*spi
= spi_master_get_devdata(master
);
518 clk_disable_unprepare(spi
->clk
);
522 static int orion_spi_runtime_resume(struct device
*dev
)
524 struct spi_master
*master
= dev_get_drvdata(dev
);
525 struct orion_spi
*spi
= spi_master_get_devdata(master
);
527 return clk_prepare_enable(spi
->clk
);
531 static const struct dev_pm_ops orion_spi_pm_ops
= {
532 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend
,
533 orion_spi_runtime_resume
,
537 static struct platform_driver orion_spi_driver
= {
540 .pm
= &orion_spi_pm_ops
,
541 .of_match_table
= of_match_ptr(orion_spi_of_match_table
),
543 .probe
= orion_spi_probe
,
544 .remove
= orion_spi_remove
,
547 module_platform_driver(orion_spi_driver
);
549 MODULE_DESCRIPTION("Orion SPI driver");
550 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
551 MODULE_LICENSE("GPL");