2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/clk.h>
24 #include <linux/sizes.h>
25 #include <asm/unaligned.h>
27 #define DRIVER_NAME "orion_spi"
29 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
30 #define SPI_AUTOSUSPEND_TIMEOUT 200
32 /* Some SoCs using this driver support up to 8 chip selects.
33 * It is up to the implementer to only use the chip selects
36 #define ORION_NUM_CHIPSELECTS 8
38 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
40 #define ORION_SPI_IF_CTRL_REG 0x00
41 #define ORION_SPI_IF_CONFIG_REG 0x04
42 #define ORION_SPI_DATA_OUT_REG 0x08
43 #define ORION_SPI_DATA_IN_REG 0x0c
44 #define ORION_SPI_INT_CAUSE_REG 0x10
45 #define ORION_SPI_TIMING_PARAMS_REG 0x18
47 /* Register for the "Direct Mode" */
48 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
50 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
51 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
52 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
54 #define ORION_SPI_MODE_CPOL (1 << 11)
55 #define ORION_SPI_MODE_CPHA (1 << 12)
56 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
57 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
58 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
59 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
61 #define ORION_SPI_CS_MASK 0x1C
62 #define ORION_SPI_CS_SHIFT 2
63 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
71 struct orion_spi_dev
{
72 enum orion_spi_type typ
;
74 * min_divisor and max_hz should be exclusive, the only we can
75 * have both is for managing the armada-370-spi case with old
79 unsigned int min_divisor
;
80 unsigned int max_divisor
;
82 bool is_errata_50mhz_ac
;
85 struct orion_direct_acc
{
91 struct spi_master
*master
;
94 const struct orion_spi_dev
*devdata
;
96 struct orion_direct_acc direct_access
[ORION_NUM_CHIPSELECTS
];
99 static inline void __iomem
*spi_reg(struct orion_spi
*orion_spi
, u32 reg
)
101 return orion_spi
->base
+ reg
;
105 orion_spi_setbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
107 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
110 val
= readl(reg_addr
);
112 writel(val
, reg_addr
);
116 orion_spi_clrbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
118 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
121 val
= readl(reg_addr
);
123 writel(val
, reg_addr
);
126 static int orion_spi_baudrate_set(struct spi_device
*spi
, unsigned int speed
)
132 struct orion_spi
*orion_spi
;
133 const struct orion_spi_dev
*devdata
;
135 orion_spi
= spi_master_get_devdata(spi
->master
);
136 devdata
= orion_spi
->devdata
;
138 tclk_hz
= clk_get_rate(orion_spi
->clk
);
140 if (devdata
->typ
== ARMADA_SPI
) {
142 * Given the core_clk (tclk_hz) and the target rate (speed) we
143 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
146 * core_clk / (SPR * 2 ** SPPR)
148 * is as big as possible but not bigger than speed.
151 /* best integer divider: */
152 unsigned divider
= DIV_ROUND_UP(tclk_hz
, speed
);
156 /* This is the easy case, divider is less than 16 */
161 unsigned two_pow_sppr
;
163 * Find the highest bit set in divider. This and the
164 * three next bits define SPR (apart from rounding).
165 * SPPR is then the number of zero bits that must be
168 sppr
= fls(divider
) - 4;
171 * As SPR only has 4 bits, we have to round divider up
172 * to the next multiple of 2 ** sppr.
174 two_pow_sppr
= 1 << sppr
;
175 divider
= (divider
+ two_pow_sppr
- 1) & -two_pow_sppr
;
178 * recalculate sppr as rounding up divider might have
179 * increased it enough to change the position of the
180 * highest set bit. In this case the bit that now
181 * doesn't make it into SPR is 0, so there is no need to
184 sppr
= fls(divider
) - 4;
185 spr
= divider
>> sppr
;
188 * Now do range checking. SPR is constructed to have a
189 * width of 4 bits, so this is fine for sure. So we
190 * still need to check for sppr to fit into 3 bits:
196 prescale
= ((sppr
& 0x6) << 5) | ((sppr
& 0x1) << 4) | spr
;
199 * the supported rates are: 4,6,8...30
200 * round up as we look for equal or less speed
202 rate
= DIV_ROUND_UP(tclk_hz
, speed
);
203 rate
= roundup(rate
, 2);
205 /* check if requested speed is too small */
212 /* Convert the rate to SPI clock divisor value. */
213 prescale
= 0x10 + rate
/2;
216 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
217 reg
= ((reg
& ~devdata
->prescale_mask
) | prescale
);
218 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
224 orion_spi_mode_set(struct spi_device
*spi
)
227 struct orion_spi
*orion_spi
;
229 orion_spi
= spi_master_get_devdata(spi
->master
);
231 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
232 reg
&= ~ORION_SPI_MODE_MASK
;
233 if (spi
->mode
& SPI_CPOL
)
234 reg
|= ORION_SPI_MODE_CPOL
;
235 if (spi
->mode
& SPI_CPHA
)
236 reg
|= ORION_SPI_MODE_CPHA
;
237 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
241 orion_spi_50mhz_ac_timing_erratum(struct spi_device
*spi
, unsigned int speed
)
244 struct orion_spi
*orion_spi
;
246 orion_spi
= spi_master_get_devdata(spi
->master
);
249 * Erratum description: (Erratum NO. FE-9144572) The device
250 * SPI interface supports frequencies of up to 50 MHz.
251 * However, due to this erratum, when the device core clock is
252 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
253 * clock and CPOL=CPHA=1 there might occur data corruption on
254 * reads from the SPI device.
255 * Erratum Workaround:
256 * Work in one of the following configurations:
257 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
259 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
260 * Register" before setting the interface.
262 reg
= readl(spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
263 reg
&= ~ORION_SPI_TMISO_SAMPLE_MASK
;
265 if (clk_get_rate(orion_spi
->clk
) == 250000000 &&
266 speed
== 50000000 && spi
->mode
& SPI_CPOL
&&
267 spi
->mode
& SPI_CPHA
)
268 reg
|= ORION_SPI_TMISO_SAMPLE_2
;
270 reg
|= ORION_SPI_TMISO_SAMPLE_1
; /* This is the default value */
272 writel(reg
, spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
276 * called only when no transfer is active on the bus
279 orion_spi_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
281 struct orion_spi
*orion_spi
;
282 unsigned int speed
= spi
->max_speed_hz
;
283 unsigned int bits_per_word
= spi
->bits_per_word
;
286 orion_spi
= spi_master_get_devdata(spi
->master
);
288 if ((t
!= NULL
) && t
->speed_hz
)
291 if ((t
!= NULL
) && t
->bits_per_word
)
292 bits_per_word
= t
->bits_per_word
;
294 orion_spi_mode_set(spi
);
296 if (orion_spi
->devdata
->is_errata_50mhz_ac
)
297 orion_spi_50mhz_ac_timing_erratum(spi
, speed
);
299 rc
= orion_spi_baudrate_set(spi
, speed
);
303 if (bits_per_word
== 16)
304 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
305 ORION_SPI_IF_8_16_BIT_MODE
);
307 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
308 ORION_SPI_IF_8_16_BIT_MODE
);
313 static void orion_spi_set_cs(struct spi_device
*spi
, bool enable
)
315 struct orion_spi
*orion_spi
;
317 orion_spi
= spi_master_get_devdata(spi
->master
);
319 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, ORION_SPI_CS_MASK
);
320 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
,
321 ORION_SPI_CS(spi
->chip_select
));
323 /* Chip select logic is inverted from spi_set_cs */
325 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
327 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
330 static inline int orion_spi_wait_till_ready(struct orion_spi
*orion_spi
)
334 for (i
= 0; i
< ORION_SPI_WAIT_RDY_MAX_LOOP
; i
++) {
335 if (readl(spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
)))
345 orion_spi_write_read_8bit(struct spi_device
*spi
,
346 const u8
**tx_buf
, u8
**rx_buf
)
348 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
349 struct orion_spi
*orion_spi
;
351 orion_spi
= spi_master_get_devdata(spi
->master
);
352 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
353 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
354 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
356 /* clear the interrupt cause register */
357 writel(0x0, int_reg
);
359 if (tx_buf
&& *tx_buf
)
360 writel(*(*tx_buf
)++, tx_reg
);
364 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
365 dev_err(&spi
->dev
, "TXS timed out\n");
369 if (rx_buf
&& *rx_buf
)
370 *(*rx_buf
)++ = readl(rx_reg
);
376 orion_spi_write_read_16bit(struct spi_device
*spi
,
377 const u16
**tx_buf
, u16
**rx_buf
)
379 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
380 struct orion_spi
*orion_spi
;
382 orion_spi
= spi_master_get_devdata(spi
->master
);
383 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
384 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
385 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
387 /* clear the interrupt cause register */
388 writel(0x0, int_reg
);
390 if (tx_buf
&& *tx_buf
)
391 writel(__cpu_to_le16(get_unaligned((*tx_buf
)++)), tx_reg
);
395 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
396 dev_err(&spi
->dev
, "TXS timed out\n");
400 if (rx_buf
&& *rx_buf
)
401 put_unaligned(__le16_to_cpu(readl(rx_reg
)), (*rx_buf
)++);
407 orion_spi_write_read(struct spi_device
*spi
, struct spi_transfer
*xfer
)
411 struct orion_spi
*orion_spi
;
412 int cs
= spi
->chip_select
;
414 word_len
= spi
->bits_per_word
;
417 orion_spi
= spi_master_get_devdata(spi
->master
);
420 * Use SPI direct write mode if base address is available. Otherwise
421 * fall back to PIO mode for this transfer.
423 if ((orion_spi
->direct_access
[cs
].vaddr
) && (xfer
->tx_buf
) &&
425 unsigned int cnt
= count
/ 4;
426 unsigned int rem
= count
% 4;
429 * Send the TX-data to the SPI device via the direct
430 * mapped address window
432 iowrite32_rep(orion_spi
->direct_access
[cs
].vaddr
,
435 u32
*buf
= (u32
*)xfer
->tx_buf
;
437 iowrite8_rep(orion_spi
->direct_access
[cs
].vaddr
,
445 const u8
*tx
= xfer
->tx_buf
;
446 u8
*rx
= xfer
->rx_buf
;
449 if (orion_spi_write_read_8bit(spi
, &tx
, &rx
) < 0)
453 } else if (word_len
== 16) {
454 const u16
*tx
= xfer
->tx_buf
;
455 u16
*rx
= xfer
->rx_buf
;
458 if (orion_spi_write_read_16bit(spi
, &tx
, &rx
) < 0)
465 return xfer
->len
- count
;
468 static int orion_spi_transfer_one(struct spi_master
*master
,
469 struct spi_device
*spi
,
470 struct spi_transfer
*t
)
474 status
= orion_spi_setup_transfer(spi
, t
);
479 orion_spi_write_read(spi
, t
);
484 static int orion_spi_setup(struct spi_device
*spi
)
486 return orion_spi_setup_transfer(spi
, NULL
);
489 static int orion_spi_reset(struct orion_spi
*orion_spi
)
491 /* Verify that the CS is deasserted */
492 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
494 /* Don't deassert CS between the direct mapped SPI transfers */
495 writel(0, spi_reg(orion_spi
, SPI_DIRECT_WRITE_CONFIG_REG
));
500 static const struct orion_spi_dev orion_spi_dev_data
= {
504 .prescale_mask
= ORION_SPI_CLK_PRESCALE_MASK
,
507 static const struct orion_spi_dev armada_370_spi_dev_data
= {
512 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
515 static const struct orion_spi_dev armada_xp_spi_dev_data
= {
519 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
522 static const struct orion_spi_dev armada_375_spi_dev_data
= {
526 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
529 static const struct orion_spi_dev armada_380_spi_dev_data
= {
533 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
534 .is_errata_50mhz_ac
= true,
537 static const struct of_device_id orion_spi_of_match_table
[] = {
539 .compatible
= "marvell,orion-spi",
540 .data
= &orion_spi_dev_data
,
543 .compatible
= "marvell,armada-370-spi",
544 .data
= &armada_370_spi_dev_data
,
547 .compatible
= "marvell,armada-375-spi",
548 .data
= &armada_375_spi_dev_data
,
551 .compatible
= "marvell,armada-380-spi",
552 .data
= &armada_380_spi_dev_data
,
555 .compatible
= "marvell,armada-390-spi",
556 .data
= &armada_xp_spi_dev_data
,
559 .compatible
= "marvell,armada-xp-spi",
560 .data
= &armada_xp_spi_dev_data
,
565 MODULE_DEVICE_TABLE(of
, orion_spi_of_match_table
);
567 static int orion_spi_probe(struct platform_device
*pdev
)
569 const struct of_device_id
*of_id
;
570 const struct orion_spi_dev
*devdata
;
571 struct spi_master
*master
;
572 struct orion_spi
*spi
;
574 unsigned long tclk_hz
;
576 struct device_node
*np
;
578 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
579 if (master
== NULL
) {
580 dev_dbg(&pdev
->dev
, "master allocation failed\n");
585 master
->bus_num
= pdev
->id
;
586 if (pdev
->dev
.of_node
) {
589 if (!of_property_read_u32(pdev
->dev
.of_node
, "cell-index",
591 master
->bus_num
= cell_index
;
594 /* we support only mode 0, and no options */
595 master
->mode_bits
= SPI_CPHA
| SPI_CPOL
;
596 master
->set_cs
= orion_spi_set_cs
;
597 master
->transfer_one
= orion_spi_transfer_one
;
598 master
->num_chipselect
= ORION_NUM_CHIPSELECTS
;
599 master
->setup
= orion_spi_setup
;
600 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
601 master
->auto_runtime_pm
= true;
603 platform_set_drvdata(pdev
, master
);
605 spi
= spi_master_get_devdata(master
);
606 spi
->master
= master
;
608 of_id
= of_match_device(orion_spi_of_match_table
, &pdev
->dev
);
609 devdata
= (of_id
) ? of_id
->data
: &orion_spi_dev_data
;
610 spi
->devdata
= devdata
;
612 spi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
613 if (IS_ERR(spi
->clk
)) {
614 status
= PTR_ERR(spi
->clk
);
618 status
= clk_prepare_enable(spi
->clk
);
622 tclk_hz
= clk_get_rate(spi
->clk
);
625 * With old device tree, armada-370-spi could be used with
626 * Armada XP, however for this SoC the maximum frequency is
627 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
628 * higher than 200MHz. So, in order to be able to handle both
629 * SoCs, we can take the minimum of 50MHz and tclk/4.
631 if (of_device_is_compatible(pdev
->dev
.of_node
,
632 "marvell,armada-370-spi"))
633 master
->max_speed_hz
= min(devdata
->max_hz
,
634 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
));
635 else if (devdata
->min_divisor
)
636 master
->max_speed_hz
=
637 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
);
639 master
->max_speed_hz
= devdata
->max_hz
;
640 master
->min_speed_hz
= DIV_ROUND_UP(tclk_hz
, devdata
->max_divisor
);
642 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
643 spi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
644 if (IS_ERR(spi
->base
)) {
645 status
= PTR_ERR(spi
->base
);
649 /* Scan all SPI devices of this controller for direct mapped devices */
650 for_each_available_child_of_node(pdev
->dev
.of_node
, np
) {
653 /* Get chip-select number from the "reg" property */
654 status
= of_property_read_u32(np
, "reg", &cs
);
657 "%s has no valid 'reg' property (%d)\n",
658 np
->full_name
, status
);
664 * Check if an address is configured for this SPI device. If
665 * not, the MBus mapping via the 'ranges' property in the 'soc'
666 * node is not configured and this device should not use the
667 * direct mode. In this case, just continue with the next
670 status
= of_address_to_resource(pdev
->dev
.of_node
, cs
+ 1, r
);
675 * Only map one page for direct access. This is enough for the
676 * simple TX transfer which only writes to the first word.
677 * This needs to get extended for the direct SPI-NOR / SPI-NAND
678 * support, once this gets implemented.
680 spi
->direct_access
[cs
].vaddr
= devm_ioremap(&pdev
->dev
,
683 if (!spi
->direct_access
[cs
].vaddr
) {
687 spi
->direct_access
[cs
].size
= PAGE_SIZE
;
689 dev_info(&pdev
->dev
, "CS%d configured for direct access\n", cs
);
692 pm_runtime_set_active(&pdev
->dev
);
693 pm_runtime_use_autosuspend(&pdev
->dev
);
694 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
695 pm_runtime_enable(&pdev
->dev
);
697 status
= orion_spi_reset(spi
);
701 pm_runtime_mark_last_busy(&pdev
->dev
);
702 pm_runtime_put_autosuspend(&pdev
->dev
);
704 master
->dev
.of_node
= pdev
->dev
.of_node
;
705 status
= spi_register_master(master
);
712 pm_runtime_disable(&pdev
->dev
);
714 clk_disable_unprepare(spi
->clk
);
716 spi_master_put(master
);
721 static int orion_spi_remove(struct platform_device
*pdev
)
723 struct spi_master
*master
= platform_get_drvdata(pdev
);
724 struct orion_spi
*spi
= spi_master_get_devdata(master
);
726 pm_runtime_get_sync(&pdev
->dev
);
727 clk_disable_unprepare(spi
->clk
);
729 spi_unregister_master(master
);
730 pm_runtime_disable(&pdev
->dev
);
735 MODULE_ALIAS("platform:" DRIVER_NAME
);
738 static int orion_spi_runtime_suspend(struct device
*dev
)
740 struct spi_master
*master
= dev_get_drvdata(dev
);
741 struct orion_spi
*spi
= spi_master_get_devdata(master
);
743 clk_disable_unprepare(spi
->clk
);
747 static int orion_spi_runtime_resume(struct device
*dev
)
749 struct spi_master
*master
= dev_get_drvdata(dev
);
750 struct orion_spi
*spi
= spi_master_get_devdata(master
);
752 return clk_prepare_enable(spi
->clk
);
756 static const struct dev_pm_ops orion_spi_pm_ops
= {
757 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend
,
758 orion_spi_runtime_resume
,
762 static struct platform_driver orion_spi_driver
= {
765 .pm
= &orion_spi_pm_ops
,
766 .of_match_table
= of_match_ptr(orion_spi_of_match_table
),
768 .probe
= orion_spi_probe
,
769 .remove
= orion_spi_remove
,
772 module_platform_driver(orion_spi_driver
);
774 MODULE_DESCRIPTION("Orion SPI driver");
775 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
776 MODULE_LICENSE("GPL");