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spi: spi-pic32: Fix issue with uninitialized dma_slave_config
[mirror_ubuntu-hirsute-kernel.git] / drivers / spi / spi-pic32.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Microchip PIC32 SPI controller driver.
4 *
5 * Purna Chandra Mandal <purna.mandal@microchip.com>
6 * Copyright (c) 2016, Microchip Technology Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clkdev.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/spi/spi.h>
24
25 /* SPI controller registers */
26 struct pic32_spi_regs {
27 u32 ctrl;
28 u32 ctrl_clr;
29 u32 ctrl_set;
30 u32 ctrl_inv;
31 u32 status;
32 u32 status_clr;
33 u32 status_set;
34 u32 status_inv;
35 u32 buf;
36 u32 dontuse[3];
37 u32 baud;
38 u32 dontuse2[3];
39 u32 ctrl2;
40 u32 ctrl2_clr;
41 u32 ctrl2_set;
42 u32 ctrl2_inv;
43 };
44
45 /* Bit fields of SPI Control Register */
46 #define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
47 #define RX_FIFO_EMPTY 0
48 #define RX_FIFO_NOT_EMPTY 1 /* not empty */
49 #define RX_FIFO_HALF_FULL 2 /* full by half or more */
50 #define RX_FIFO_FULL 3 /* completely full */
51
52 #define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
53 #define TX_FIFO_ALL_EMPTY 0 /* completely empty */
54 #define TX_FIFO_EMPTY 1 /* empty */
55 #define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */
56 #define TX_FIFO_NOT_FULL 3 /* atleast one empty */
57
58 #define CTRL_MSTEN BIT(5) /* enable master mode */
59 #define CTRL_CKP BIT(6) /* active low */
60 #define CTRL_CKE BIT(8) /* Tx on falling edge */
61 #define CTRL_SMP BIT(9) /* Rx at middle or end of tx */
62 #define CTRL_BPW_MASK 0x03 /* bits per word/sample */
63 #define CTRL_BPW_SHIFT 10
64 #define PIC32_BPW_8 0
65 #define PIC32_BPW_16 1
66 #define PIC32_BPW_32 2
67 #define CTRL_SIDL BIT(13) /* sleep when idle */
68 #define CTRL_ON BIT(15) /* enable macro */
69 #define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */
70 #define CTRL_MCLKSEL BIT(23) /* select clock source */
71 #define CTRL_MSSEN BIT(28) /* macro driven /SS */
72 #define CTRL_FRMEN BIT(31) /* enable framing mode */
73
74 /* Bit fields of SPI Status Register */
75 #define STAT_RF_EMPTY BIT(5) /* RX Fifo empty */
76 #define STAT_RX_OV BIT(6) /* err, s/w needs to clear */
77 #define STAT_TX_UR BIT(8) /* UR in Framed SPI modes */
78 #define STAT_FRM_ERR BIT(12) /* Multiple Frame Sync pulse */
79 #define STAT_TF_LVL_MASK 0x1F
80 #define STAT_TF_LVL_SHIFT 16
81 #define STAT_RF_LVL_MASK 0x1F
82 #define STAT_RF_LVL_SHIFT 24
83
84 /* Bit fields of SPI Baud Register */
85 #define BAUD_MASK 0x1ff
86
87 /* Bit fields of SPI Control2 Register */
88 #define CTRL2_TX_UR_EN BIT(10) /* Enable int on Tx under-run */
89 #define CTRL2_RX_OV_EN BIT(11) /* Enable int on Rx over-run */
90 #define CTRL2_FRM_ERR_EN BIT(12) /* Enable frame err int */
91
92 /* Minimum DMA transfer size */
93 #define PIC32_DMA_LEN_MIN 64
94
95 struct pic32_spi {
96 dma_addr_t dma_base;
97 struct pic32_spi_regs __iomem *regs;
98 int fault_irq;
99 int rx_irq;
100 int tx_irq;
101 u32 fifo_n_byte; /* FIFO depth in bytes */
102 struct clk *clk;
103 struct spi_master *master;
104 /* Current controller setting */
105 u32 speed_hz; /* spi-clk rate */
106 u32 mode;
107 u32 bits_per_word;
108 u32 fifo_n_elm; /* FIFO depth in words */
109 #define PIC32F_DMA_PREP 0 /* DMA chnls configured */
110 unsigned long flags;
111 /* Current transfer state */
112 struct completion xfer_done;
113 /* PIO transfer specific */
114 const void *tx;
115 const void *tx_end;
116 const void *rx;
117 const void *rx_end;
118 int len;
119 void (*rx_fifo)(struct pic32_spi *);
120 void (*tx_fifo)(struct pic32_spi *);
121 };
122
123 static inline void pic32_spi_enable(struct pic32_spi *pic32s)
124 {
125 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
126 }
127
128 static inline void pic32_spi_disable(struct pic32_spi *pic32s)
129 {
130 writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
131
132 /* avoid SPI registers read/write at immediate next CPU clock */
133 ndelay(20);
134 }
135
136 static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
137 {
138 u32 div;
139
140 /* div = (clk_in / 2 * spi_ck) - 1 */
141 div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
142
143 writel(div & BAUD_MASK, &pic32s->regs->baud);
144 }
145
146 static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
147 {
148 u32 sr = readl(&pic32s->regs->status);
149
150 return (sr >> STAT_RF_LVL_SHIFT) & STAT_RF_LVL_MASK;
151 }
152
153 static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
154 {
155 u32 sr = readl(&pic32s->regs->status);
156
157 return (sr >> STAT_TF_LVL_SHIFT) & STAT_TF_LVL_MASK;
158 }
159
160 /* Return the max entries we can fill into tx fifo */
161 static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
162 {
163 u32 tx_left, tx_room, rxtx_gap;
164
165 tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
166 tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
167
168 /*
169 * Another concern is about the tx/rx mismatch, we
170 * though to use (pic32s->fifo_n_byte - rxfl - txfl) as
171 * one maximum value for tx, but it doesn't cover the
172 * data which is out of tx/rx fifo and inside the
173 * shift registers. So a ctrl from sw point of
174 * view is taken.
175 */
176 rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
177 (pic32s->tx_end - pic32s->tx)) / n_bytes;
178 return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
179 }
180
181 /* Return the max entries we should read out of rx fifo */
182 static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
183 {
184 u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
185
186 return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
187 }
188
189 #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
190 static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \
191 { \
192 __type v; \
193 u32 mx = pic32_rx_max(pic32s, sizeof(__type)); \
194 for (; mx; mx--) { \
195 v = read##__bwl(&pic32s->regs->buf); \
196 if (pic32s->rx_end - pic32s->len) \
197 *(__type *)(pic32s->rx) = v; \
198 pic32s->rx += sizeof(__type); \
199 } \
200 } \
201 \
202 static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \
203 { \
204 __type v; \
205 u32 mx = pic32_tx_max(pic32s, sizeof(__type)); \
206 for (; mx ; mx--) { \
207 v = (__type)~0U; \
208 if (pic32s->tx_end - pic32s->len) \
209 v = *(__type *)(pic32s->tx); \
210 write##__bwl(v, &pic32s->regs->buf); \
211 pic32s->tx += sizeof(__type); \
212 } \
213 }
214
215 BUILD_SPI_FIFO_RW(byte, u8, b);
216 BUILD_SPI_FIFO_RW(word, u16, w);
217 BUILD_SPI_FIFO_RW(dword, u32, l);
218
219 static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
220 {
221 /* disable all interrupts */
222 disable_irq_nosync(pic32s->fault_irq);
223 disable_irq_nosync(pic32s->rx_irq);
224 disable_irq_nosync(pic32s->tx_irq);
225
226 /* Show err message and abort xfer with err */
227 dev_err(&pic32s->master->dev, "%s\n", msg);
228 if (pic32s->master->cur_msg)
229 pic32s->master->cur_msg->status = -EIO;
230 complete(&pic32s->xfer_done);
231 }
232
233 static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id)
234 {
235 struct pic32_spi *pic32s = dev_id;
236 u32 status;
237
238 status = readl(&pic32s->regs->status);
239
240 /* Error handling */
241 if (status & (STAT_RX_OV | STAT_TX_UR)) {
242 writel(STAT_RX_OV, &pic32s->regs->status_clr);
243 writel(STAT_TX_UR, &pic32s->regs->status_clr);
244 pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n");
245 return IRQ_HANDLED;
246 }
247
248 if (status & STAT_FRM_ERR) {
249 pic32_err_stop(pic32s, "err_irq: frame error");
250 return IRQ_HANDLED;
251 }
252
253 if (!pic32s->master->cur_msg) {
254 pic32_err_stop(pic32s, "err_irq: no mesg");
255 return IRQ_NONE;
256 }
257
258 return IRQ_NONE;
259 }
260
261 static irqreturn_t pic32_spi_rx_irq(int irq, void *dev_id)
262 {
263 struct pic32_spi *pic32s = dev_id;
264
265 pic32s->rx_fifo(pic32s);
266
267 /* rx complete ? */
268 if (pic32s->rx_end == pic32s->rx) {
269 /* disable all interrupts */
270 disable_irq_nosync(pic32s->fault_irq);
271 disable_irq_nosync(pic32s->rx_irq);
272
273 /* complete current xfer */
274 complete(&pic32s->xfer_done);
275 }
276
277 return IRQ_HANDLED;
278 }
279
280 static irqreturn_t pic32_spi_tx_irq(int irq, void *dev_id)
281 {
282 struct pic32_spi *pic32s = dev_id;
283
284 pic32s->tx_fifo(pic32s);
285
286 /* tx complete? disable tx interrupt */
287 if (pic32s->tx_end == pic32s->tx)
288 disable_irq_nosync(pic32s->tx_irq);
289
290 return IRQ_HANDLED;
291 }
292
293 static void pic32_spi_dma_rx_notify(void *data)
294 {
295 struct pic32_spi *pic32s = data;
296
297 complete(&pic32s->xfer_done);
298 }
299
300 static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
301 struct spi_transfer *xfer)
302 {
303 struct spi_master *master = pic32s->master;
304 struct dma_async_tx_descriptor *desc_rx;
305 struct dma_async_tx_descriptor *desc_tx;
306 dma_cookie_t cookie;
307 int ret;
308
309 if (!master->dma_rx || !master->dma_tx)
310 return -ENODEV;
311
312 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
313 xfer->rx_sg.sgl,
314 xfer->rx_sg.nents,
315 DMA_DEV_TO_MEM,
316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
317 if (!desc_rx) {
318 ret = -EINVAL;
319 goto err_dma;
320 }
321
322 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
323 xfer->tx_sg.sgl,
324 xfer->tx_sg.nents,
325 DMA_MEM_TO_DEV,
326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
327 if (!desc_tx) {
328 ret = -EINVAL;
329 goto err_dma;
330 }
331
332 /* Put callback on the RX transfer, that should finish last */
333 desc_rx->callback = pic32_spi_dma_rx_notify;
334 desc_rx->callback_param = pic32s;
335
336 cookie = dmaengine_submit(desc_rx);
337 ret = dma_submit_error(cookie);
338 if (ret)
339 goto err_dma;
340
341 cookie = dmaengine_submit(desc_tx);
342 ret = dma_submit_error(cookie);
343 if (ret)
344 goto err_dma_tx;
345
346 dma_async_issue_pending(master->dma_rx);
347 dma_async_issue_pending(master->dma_tx);
348
349 return 0;
350
351 err_dma_tx:
352 dmaengine_terminate_all(master->dma_rx);
353 err_dma:
354 return ret;
355 }
356
357 static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
358 {
359 int buf_offset = offsetof(struct pic32_spi_regs, buf);
360 struct spi_master *master = pic32s->master;
361 struct dma_slave_config cfg;
362 int ret;
363
364 memset(&cfg, 0, sizeof(cfg));
365 cfg.device_fc = true;
366 cfg.src_addr = pic32s->dma_base + buf_offset;
367 cfg.dst_addr = pic32s->dma_base + buf_offset;
368 cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */
369 cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */
370 cfg.src_addr_width = dma_width;
371 cfg.dst_addr_width = dma_width;
372 /* tx channel */
373 cfg.slave_id = pic32s->tx_irq;
374 cfg.direction = DMA_MEM_TO_DEV;
375 ret = dmaengine_slave_config(master->dma_tx, &cfg);
376 if (ret) {
377 dev_err(&master->dev, "tx channel setup failed\n");
378 return ret;
379 }
380 /* rx channel */
381 cfg.slave_id = pic32s->rx_irq;
382 cfg.direction = DMA_DEV_TO_MEM;
383 ret = dmaengine_slave_config(master->dma_rx, &cfg);
384 if (ret)
385 dev_err(&master->dev, "rx channel setup failed\n");
386
387 return ret;
388 }
389
390 static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
391 {
392 enum dma_slave_buswidth dmawidth;
393 u32 buswidth, v;
394
395 switch (bits_per_word) {
396 case 8:
397 pic32s->rx_fifo = pic32_spi_rx_byte;
398 pic32s->tx_fifo = pic32_spi_tx_byte;
399 buswidth = PIC32_BPW_8;
400 dmawidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
401 break;
402 case 16:
403 pic32s->rx_fifo = pic32_spi_rx_word;
404 pic32s->tx_fifo = pic32_spi_tx_word;
405 buswidth = PIC32_BPW_16;
406 dmawidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
407 break;
408 case 32:
409 pic32s->rx_fifo = pic32_spi_rx_dword;
410 pic32s->tx_fifo = pic32_spi_tx_dword;
411 buswidth = PIC32_BPW_32;
412 dmawidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
413 break;
414 default:
415 /* not supported */
416 return -EINVAL;
417 }
418
419 /* calculate maximum number of words fifos can hold */
420 pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte,
421 bits_per_word / 8);
422 /* set word size */
423 v = readl(&pic32s->regs->ctrl);
424 v &= ~(CTRL_BPW_MASK << CTRL_BPW_SHIFT);
425 v |= buswidth << CTRL_BPW_SHIFT;
426 writel(v, &pic32s->regs->ctrl);
427
428 /* re-configure dma width, if required */
429 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
430 pic32_spi_dma_config(pic32s, dmawidth);
431
432 return 0;
433 }
434
435 static int pic32_spi_prepare_hardware(struct spi_master *master)
436 {
437 struct pic32_spi *pic32s = spi_master_get_devdata(master);
438
439 pic32_spi_enable(pic32s);
440
441 return 0;
442 }
443
444 static int pic32_spi_prepare_message(struct spi_master *master,
445 struct spi_message *msg)
446 {
447 struct pic32_spi *pic32s = spi_master_get_devdata(master);
448 struct spi_device *spi = msg->spi;
449 u32 val;
450
451 /* set device specific bits_per_word */
452 if (pic32s->bits_per_word != spi->bits_per_word) {
453 pic32_spi_set_word_size(pic32s, spi->bits_per_word);
454 pic32s->bits_per_word = spi->bits_per_word;
455 }
456
457 /* device specific speed change */
458 if (pic32s->speed_hz != spi->max_speed_hz) {
459 pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz);
460 pic32s->speed_hz = spi->max_speed_hz;
461 }
462
463 /* device specific mode change */
464 if (pic32s->mode != spi->mode) {
465 val = readl(&pic32s->regs->ctrl);
466 /* active low */
467 if (spi->mode & SPI_CPOL)
468 val |= CTRL_CKP;
469 else
470 val &= ~CTRL_CKP;
471 /* tx on rising edge */
472 if (spi->mode & SPI_CPHA)
473 val &= ~CTRL_CKE;
474 else
475 val |= CTRL_CKE;
476
477 /* rx at end of tx */
478 val |= CTRL_SMP;
479 writel(val, &pic32s->regs->ctrl);
480 pic32s->mode = spi->mode;
481 }
482
483 return 0;
484 }
485
486 static bool pic32_spi_can_dma(struct spi_master *master,
487 struct spi_device *spi,
488 struct spi_transfer *xfer)
489 {
490 struct pic32_spi *pic32s = spi_master_get_devdata(master);
491
492 /* skip using DMA on small size transfer to avoid overhead.*/
493 return (xfer->len >= PIC32_DMA_LEN_MIN) &&
494 test_bit(PIC32F_DMA_PREP, &pic32s->flags);
495 }
496
497 static int pic32_spi_one_transfer(struct spi_master *master,
498 struct spi_device *spi,
499 struct spi_transfer *transfer)
500 {
501 struct pic32_spi *pic32s;
502 bool dma_issued = false;
503 unsigned long timeout;
504 int ret;
505
506 pic32s = spi_master_get_devdata(master);
507
508 /* handle transfer specific word size change */
509 if (transfer->bits_per_word &&
510 (transfer->bits_per_word != pic32s->bits_per_word)) {
511 ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word);
512 if (ret)
513 return ret;
514 pic32s->bits_per_word = transfer->bits_per_word;
515 }
516
517 /* handle transfer specific speed change */
518 if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) {
519 pic32_spi_set_clk_rate(pic32s, transfer->speed_hz);
520 pic32s->speed_hz = transfer->speed_hz;
521 }
522
523 reinit_completion(&pic32s->xfer_done);
524
525 /* transact by DMA mode */
526 if (transfer->rx_sg.nents && transfer->tx_sg.nents) {
527 ret = pic32_spi_dma_transfer(pic32s, transfer);
528 if (ret) {
529 dev_err(&spi->dev, "dma submit error\n");
530 return ret;
531 }
532
533 /* DMA issued */
534 dma_issued = true;
535 } else {
536 /* set current transfer information */
537 pic32s->tx = (const void *)transfer->tx_buf;
538 pic32s->rx = (const void *)transfer->rx_buf;
539 pic32s->tx_end = pic32s->tx + transfer->len;
540 pic32s->rx_end = pic32s->rx + transfer->len;
541 pic32s->len = transfer->len;
542
543 /* transact by interrupt driven PIO */
544 enable_irq(pic32s->fault_irq);
545 enable_irq(pic32s->rx_irq);
546 enable_irq(pic32s->tx_irq);
547 }
548
549 /* wait for completion */
550 timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ);
551 if (timeout == 0) {
552 dev_err(&spi->dev, "wait error/timedout\n");
553 if (dma_issued) {
554 dmaengine_terminate_all(master->dma_rx);
555 dmaengine_terminate_all(master->dma_tx);
556 }
557 ret = -ETIMEDOUT;
558 } else {
559 ret = 0;
560 }
561
562 return ret;
563 }
564
565 static int pic32_spi_unprepare_message(struct spi_master *master,
566 struct spi_message *msg)
567 {
568 /* nothing to do */
569 return 0;
570 }
571
572 static int pic32_spi_unprepare_hardware(struct spi_master *master)
573 {
574 struct pic32_spi *pic32s = spi_master_get_devdata(master);
575
576 pic32_spi_disable(pic32s);
577
578 return 0;
579 }
580
581 /* This may be called multiple times by same spi dev */
582 static int pic32_spi_setup(struct spi_device *spi)
583 {
584 if (!spi->max_speed_hz) {
585 dev_err(&spi->dev, "No max speed HZ parameter\n");
586 return -EINVAL;
587 }
588
589 /* PIC32 spi controller can drive /CS during transfer depending
590 * on tx fifo fill-level. /CS will stay asserted as long as TX
591 * fifo is non-empty, else will be deasserted indicating
592 * completion of the ongoing transfer. This might result into
593 * unreliable/erroneous SPI transactions.
594 * To avoid that we will always handle /CS by toggling GPIO.
595 */
596 if (!gpio_is_valid(spi->cs_gpio))
597 return -EINVAL;
598
599 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
600
601 return 0;
602 }
603
604 static void pic32_spi_cleanup(struct spi_device *spi)
605 {
606 /* de-activate cs-gpio */
607 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
608 }
609
610 static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
611 {
612 struct spi_master *master = pic32s->master;
613 int ret = 0;
614
615 master->dma_rx = dma_request_chan(dev, "spi-rx");
616 if (IS_ERR(master->dma_rx)) {
617 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
618 ret = -EPROBE_DEFER;
619 else
620 dev_warn(dev, "RX channel not found.\n");
621
622 master->dma_rx = NULL;
623 goto out_err;
624 }
625
626 master->dma_tx = dma_request_chan(dev, "spi-tx");
627 if (IS_ERR(master->dma_tx)) {
628 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
629 ret = -EPROBE_DEFER;
630 else
631 dev_warn(dev, "TX channel not found.\n");
632
633 master->dma_tx = NULL;
634 goto out_err;
635 }
636
637 if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE))
638 goto out_err;
639
640 /* DMA chnls allocated and prepared */
641 set_bit(PIC32F_DMA_PREP, &pic32s->flags);
642
643 return 0;
644
645 out_err:
646 if (master->dma_rx) {
647 dma_release_channel(master->dma_rx);
648 master->dma_rx = NULL;
649 }
650
651 if (master->dma_tx) {
652 dma_release_channel(master->dma_tx);
653 master->dma_tx = NULL;
654 }
655
656 return ret;
657 }
658
659 static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
660 {
661 if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags))
662 return;
663
664 clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
665 if (pic32s->master->dma_rx)
666 dma_release_channel(pic32s->master->dma_rx);
667
668 if (pic32s->master->dma_tx)
669 dma_release_channel(pic32s->master->dma_tx);
670 }
671
672 static void pic32_spi_hw_init(struct pic32_spi *pic32s)
673 {
674 u32 ctrl;
675
676 /* disable hardware */
677 pic32_spi_disable(pic32s);
678
679 ctrl = readl(&pic32s->regs->ctrl);
680 /* enable enhanced fifo of 128bit deep */
681 ctrl |= CTRL_ENHBUF;
682 pic32s->fifo_n_byte = 16;
683
684 /* disable framing mode */
685 ctrl &= ~CTRL_FRMEN;
686
687 /* enable master mode while disabled */
688 ctrl |= CTRL_MSTEN;
689
690 /* set tx fifo threshold interrupt */
691 ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT);
692 ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT);
693
694 /* set rx fifo threshold interrupt */
695 ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT);
696 ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT);
697
698 /* select clk source */
699 ctrl &= ~CTRL_MCLKSEL;
700
701 /* set manual /CS mode */
702 ctrl &= ~CTRL_MSSEN;
703
704 writel(ctrl, &pic32s->regs->ctrl);
705
706 /* enable error reporting */
707 ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN;
708 writel(ctrl, &pic32s->regs->ctrl2_set);
709 }
710
711 static int pic32_spi_hw_probe(struct platform_device *pdev,
712 struct pic32_spi *pic32s)
713 {
714 struct resource *mem;
715 int ret;
716
717 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
718 pic32s->regs = devm_ioremap_resource(&pdev->dev, mem);
719 if (IS_ERR(pic32s->regs))
720 return PTR_ERR(pic32s->regs);
721
722 pic32s->dma_base = mem->start;
723
724 /* get irq resources: err-irq, rx-irq, tx-irq */
725 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
726 if (pic32s->fault_irq < 0)
727 return pic32s->fault_irq;
728
729 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
730 if (pic32s->rx_irq < 0)
731 return pic32s->rx_irq;
732
733 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
734 if (pic32s->tx_irq < 0)
735 return pic32s->tx_irq;
736
737 /* get clock */
738 pic32s->clk = devm_clk_get(&pdev->dev, "mck0");
739 if (IS_ERR(pic32s->clk)) {
740 dev_err(&pdev->dev, "clk not found\n");
741 ret = PTR_ERR(pic32s->clk);
742 goto err_unmap_mem;
743 }
744
745 ret = clk_prepare_enable(pic32s->clk);
746 if (ret)
747 goto err_unmap_mem;
748
749 pic32_spi_hw_init(pic32s);
750
751 return 0;
752
753 err_unmap_mem:
754 dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret);
755 return ret;
756 }
757
758 static int pic32_spi_probe(struct platform_device *pdev)
759 {
760 struct spi_master *master;
761 struct pic32_spi *pic32s;
762 int ret;
763
764 master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
765 if (!master)
766 return -ENOMEM;
767
768 pic32s = spi_master_get_devdata(master);
769 pic32s->master = master;
770
771 ret = pic32_spi_hw_probe(pdev, pic32s);
772 if (ret)
773 goto err_master;
774
775 master->dev.of_node = pdev->dev.of_node;
776 master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
777 master->num_chipselect = 1; /* single chip-select */
778 master->max_speed_hz = clk_get_rate(pic32s->clk);
779 master->setup = pic32_spi_setup;
780 master->cleanup = pic32_spi_cleanup;
781 master->flags = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX;
782 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
783 SPI_BPW_MASK(32);
784 master->transfer_one = pic32_spi_one_transfer;
785 master->prepare_message = pic32_spi_prepare_message;
786 master->unprepare_message = pic32_spi_unprepare_message;
787 master->prepare_transfer_hardware = pic32_spi_prepare_hardware;
788 master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
789
790 /* optional DMA support */
791 ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
792 if (ret)
793 goto err_bailout;
794
795 if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
796 master->can_dma = pic32_spi_can_dma;
797
798 init_completion(&pic32s->xfer_done);
799 pic32s->mode = -1;
800
801 /* install irq handlers (with irq-disabled) */
802 irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN);
803 ret = devm_request_irq(&pdev->dev, pic32s->fault_irq,
804 pic32_spi_fault_irq, IRQF_NO_THREAD,
805 dev_name(&pdev->dev), pic32s);
806 if (ret < 0) {
807 dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq);
808 goto err_bailout;
809 }
810
811 /* receive interrupt handler */
812 irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN);
813 ret = devm_request_irq(&pdev->dev, pic32s->rx_irq,
814 pic32_spi_rx_irq, IRQF_NO_THREAD,
815 dev_name(&pdev->dev), pic32s);
816 if (ret < 0) {
817 dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq);
818 goto err_bailout;
819 }
820
821 /* transmit interrupt handler */
822 irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN);
823 ret = devm_request_irq(&pdev->dev, pic32s->tx_irq,
824 pic32_spi_tx_irq, IRQF_NO_THREAD,
825 dev_name(&pdev->dev), pic32s);
826 if (ret < 0) {
827 dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq);
828 goto err_bailout;
829 }
830
831 /* register master */
832 ret = devm_spi_register_master(&pdev->dev, master);
833 if (ret) {
834 dev_err(&master->dev, "failed registering spi master\n");
835 goto err_bailout;
836 }
837
838 platform_set_drvdata(pdev, pic32s);
839
840 return 0;
841
842 err_bailout:
843 pic32_spi_dma_unprep(pic32s);
844 clk_disable_unprepare(pic32s->clk);
845 err_master:
846 spi_master_put(master);
847 return ret;
848 }
849
850 static int pic32_spi_remove(struct platform_device *pdev)
851 {
852 struct pic32_spi *pic32s;
853
854 pic32s = platform_get_drvdata(pdev);
855 pic32_spi_disable(pic32s);
856 clk_disable_unprepare(pic32s->clk);
857 pic32_spi_dma_unprep(pic32s);
858
859 return 0;
860 }
861
862 static const struct of_device_id pic32_spi_of_match[] = {
863 {.compatible = "microchip,pic32mzda-spi",},
864 {},
865 };
866 MODULE_DEVICE_TABLE(of, pic32_spi_of_match);
867
868 static struct platform_driver pic32_spi_driver = {
869 .driver = {
870 .name = "spi-pic32",
871 .of_match_table = of_match_ptr(pic32_spi_of_match),
872 },
873 .probe = pic32_spi_probe,
874 .remove = pic32_spi_remove,
875 };
876
877 module_platform_driver(pic32_spi_driver);
878
879 MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
880 MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SPI controller.");
881 MODULE_LICENSE("GPL v2");
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