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[mirror_ubuntu-zesty-kernel.git] / drivers / spi / spi-pxa2xx.c
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
35
36 #include "spi-pxa2xx.h"
37
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
42
43 #define TIMOUT_DFLT 1000
44
45 /*
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
51 */
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CAPS_CS_EN_SHIFT 9
69 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
70
71 struct lpss_config {
72 /* LPSS offset from drv_data->ioaddr */
73 unsigned offset;
74 /* Register offsets from drv_data->lpss_base or -1 */
75 int reg_general;
76 int reg_ssp;
77 int reg_cs_ctrl;
78 int reg_capabilities;
79 /* FIFO thresholds */
80 u32 rx_threshold;
81 u32 tx_threshold_lo;
82 u32 tx_threshold_hi;
83 /* Chip select control */
84 unsigned cs_sel_shift;
85 unsigned cs_sel_mask;
86 unsigned cs_num;
87 };
88
89 /* Keep these sorted with enum pxa_ssp_type */
90 static const struct lpss_config lpss_platforms[] = {
91 { /* LPSS_LPT_SSP */
92 .offset = 0x800,
93 .reg_general = 0x08,
94 .reg_ssp = 0x0c,
95 .reg_cs_ctrl = 0x18,
96 .reg_capabilities = -1,
97 .rx_threshold = 64,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
100 },
101 { /* LPSS_BYT_SSP */
102 .offset = 0x400,
103 .reg_general = 0x08,
104 .reg_ssp = 0x0c,
105 .reg_cs_ctrl = 0x18,
106 .reg_capabilities = -1,
107 .rx_threshold = 64,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
110 },
111 { /* LPSS_BSW_SSP */
112 .offset = 0x400,
113 .reg_general = 0x08,
114 .reg_ssp = 0x0c,
115 .reg_cs_ctrl = 0x18,
116 .reg_capabilities = -1,
117 .rx_threshold = 64,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
120 .cs_sel_shift = 2,
121 .cs_sel_mask = 1 << 2,
122 .cs_num = 2,
123 },
124 { /* LPSS_SPT_SSP */
125 .offset = 0x200,
126 .reg_general = -1,
127 .reg_ssp = 0x20,
128 .reg_cs_ctrl = 0x24,
129 .reg_capabilities = -1,
130 .rx_threshold = 1,
131 .tx_threshold_lo = 32,
132 .tx_threshold_hi = 56,
133 },
134 { /* LPSS_BXT_SSP */
135 .offset = 0x200,
136 .reg_general = -1,
137 .reg_ssp = 0x20,
138 .reg_cs_ctrl = 0x24,
139 .reg_capabilities = 0xfc,
140 .rx_threshold = 1,
141 .tx_threshold_lo = 16,
142 .tx_threshold_hi = 48,
143 .cs_sel_shift = 8,
144 .cs_sel_mask = 3 << 8,
145 },
146 };
147
148 static inline const struct lpss_config
149 *lpss_get_config(const struct driver_data *drv_data)
150 {
151 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
152 }
153
154 static bool is_lpss_ssp(const struct driver_data *drv_data)
155 {
156 switch (drv_data->ssp_type) {
157 case LPSS_LPT_SSP:
158 case LPSS_BYT_SSP:
159 case LPSS_BSW_SSP:
160 case LPSS_SPT_SSP:
161 case LPSS_BXT_SSP:
162 return true;
163 default:
164 return false;
165 }
166 }
167
168 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
169 {
170 return drv_data->ssp_type == QUARK_X1000_SSP;
171 }
172
173 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
174 {
175 switch (drv_data->ssp_type) {
176 case QUARK_X1000_SSP:
177 return QUARK_X1000_SSCR1_CHANGE_MASK;
178 default:
179 return SSCR1_CHANGE_MASK;
180 }
181 }
182
183 static u32
184 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
185 {
186 switch (drv_data->ssp_type) {
187 case QUARK_X1000_SSP:
188 return RX_THRESH_QUARK_X1000_DFLT;
189 default:
190 return RX_THRESH_DFLT;
191 }
192 }
193
194 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
195 {
196 u32 mask;
197
198 switch (drv_data->ssp_type) {
199 case QUARK_X1000_SSP:
200 mask = QUARK_X1000_SSSR_TFL_MASK;
201 break;
202 default:
203 mask = SSSR_TFL_MASK;
204 break;
205 }
206
207 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
208 }
209
210 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
211 u32 *sccr1_reg)
212 {
213 u32 mask;
214
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 mask = QUARK_X1000_SSCR1_RFT;
218 break;
219 default:
220 mask = SSCR1_RFT;
221 break;
222 }
223 *sccr1_reg &= ~mask;
224 }
225
226 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
227 u32 *sccr1_reg, u32 threshold)
228 {
229 switch (drv_data->ssp_type) {
230 case QUARK_X1000_SSP:
231 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
232 break;
233 default:
234 *sccr1_reg |= SSCR1_RxTresh(threshold);
235 break;
236 }
237 }
238
239 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
240 u32 clk_div, u8 bits)
241 {
242 switch (drv_data->ssp_type) {
243 case QUARK_X1000_SSP:
244 return clk_div
245 | QUARK_X1000_SSCR0_Motorola
246 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
247 | SSCR0_SSE;
248 default:
249 return clk_div
250 | SSCR0_Motorola
251 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
252 | SSCR0_SSE
253 | (bits > 16 ? SSCR0_EDSS : 0);
254 }
255 }
256
257 /*
258 * Read and write LPSS SSP private registers. Caller must first check that
259 * is_lpss_ssp() returns true before these can be called.
260 */
261 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
262 {
263 WARN_ON(!drv_data->lpss_base);
264 return readl(drv_data->lpss_base + offset);
265 }
266
267 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
268 unsigned offset, u32 value)
269 {
270 WARN_ON(!drv_data->lpss_base);
271 writel(value, drv_data->lpss_base + offset);
272 }
273
274 /*
275 * lpss_ssp_setup - perform LPSS SSP specific setup
276 * @drv_data: pointer to the driver private data
277 *
278 * Perform LPSS SSP specific setup. This function must be called first if
279 * one is going to use LPSS SSP private registers.
280 */
281 static void lpss_ssp_setup(struct driver_data *drv_data)
282 {
283 const struct lpss_config *config;
284 u32 value;
285
286 config = lpss_get_config(drv_data);
287 drv_data->lpss_base = drv_data->ioaddr + config->offset;
288
289 /* Enable software chip select control */
290 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
291 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
292 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
293 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
294
295 /* Enable multiblock DMA transfers */
296 if (drv_data->master_info->enable_dma) {
297 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
298
299 if (config->reg_general >= 0) {
300 value = __lpss_ssp_read_priv(drv_data,
301 config->reg_general);
302 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
303 __lpss_ssp_write_priv(drv_data,
304 config->reg_general, value);
305 }
306 }
307 }
308
309 static void lpss_ssp_select_cs(struct driver_data *drv_data,
310 const struct lpss_config *config)
311 {
312 u32 value, cs;
313
314 if (!config->cs_sel_mask)
315 return;
316
317 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
318
319 cs = drv_data->cur_msg->spi->chip_select;
320 cs <<= config->cs_sel_shift;
321 if (cs != (value & config->cs_sel_mask)) {
322 /*
323 * When switching another chip select output active the
324 * output must be selected first and wait 2 ssp_clk cycles
325 * before changing state to active. Otherwise a short
326 * glitch will occur on the previous chip select since
327 * output select is latched but state control is not.
328 */
329 value &= ~config->cs_sel_mask;
330 value |= cs;
331 __lpss_ssp_write_priv(drv_data,
332 config->reg_cs_ctrl, value);
333 ndelay(1000000000 /
334 (drv_data->master->max_speed_hz / 2));
335 }
336 }
337
338 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
339 {
340 const struct lpss_config *config;
341 u32 value;
342
343 config = lpss_get_config(drv_data);
344
345 if (enable)
346 lpss_ssp_select_cs(drv_data, config);
347
348 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
349 if (enable)
350 value &= ~LPSS_CS_CONTROL_CS_HIGH;
351 else
352 value |= LPSS_CS_CONTROL_CS_HIGH;
353 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
354 }
355
356 static void cs_assert(struct driver_data *drv_data)
357 {
358 struct chip_data *chip = drv_data->cur_chip;
359
360 if (drv_data->ssp_type == CE4100_SSP) {
361 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
362 return;
363 }
364
365 if (chip->cs_control) {
366 chip->cs_control(PXA2XX_CS_ASSERT);
367 return;
368 }
369
370 if (gpio_is_valid(chip->gpio_cs)) {
371 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
372 return;
373 }
374
375 if (is_lpss_ssp(drv_data))
376 lpss_ssp_cs_control(drv_data, true);
377 }
378
379 static void cs_deassert(struct driver_data *drv_data)
380 {
381 struct chip_data *chip = drv_data->cur_chip;
382
383 if (drv_data->ssp_type == CE4100_SSP)
384 return;
385
386 if (chip->cs_control) {
387 chip->cs_control(PXA2XX_CS_DEASSERT);
388 return;
389 }
390
391 if (gpio_is_valid(chip->gpio_cs)) {
392 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
393 return;
394 }
395
396 if (is_lpss_ssp(drv_data))
397 lpss_ssp_cs_control(drv_data, false);
398 }
399
400 int pxa2xx_spi_flush(struct driver_data *drv_data)
401 {
402 unsigned long limit = loops_per_jiffy << 1;
403
404 do {
405 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 pxa2xx_spi_read(drv_data, SSDR);
407 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
408 write_SSSR_CS(drv_data, SSSR_ROR);
409
410 return limit;
411 }
412
413 static int null_writer(struct driver_data *drv_data)
414 {
415 u8 n_bytes = drv_data->n_bytes;
416
417 if (pxa2xx_spi_txfifo_full(drv_data)
418 || (drv_data->tx == drv_data->tx_end))
419 return 0;
420
421 pxa2xx_spi_write(drv_data, SSDR, 0);
422 drv_data->tx += n_bytes;
423
424 return 1;
425 }
426
427 static int null_reader(struct driver_data *drv_data)
428 {
429 u8 n_bytes = drv_data->n_bytes;
430
431 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
432 && (drv_data->rx < drv_data->rx_end)) {
433 pxa2xx_spi_read(drv_data, SSDR);
434 drv_data->rx += n_bytes;
435 }
436
437 return drv_data->rx == drv_data->rx_end;
438 }
439
440 static int u8_writer(struct driver_data *drv_data)
441 {
442 if (pxa2xx_spi_txfifo_full(drv_data)
443 || (drv_data->tx == drv_data->tx_end))
444 return 0;
445
446 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
447 ++drv_data->tx;
448
449 return 1;
450 }
451
452 static int u8_reader(struct driver_data *drv_data)
453 {
454 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
455 && (drv_data->rx < drv_data->rx_end)) {
456 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
457 ++drv_data->rx;
458 }
459
460 return drv_data->rx == drv_data->rx_end;
461 }
462
463 static int u16_writer(struct driver_data *drv_data)
464 {
465 if (pxa2xx_spi_txfifo_full(drv_data)
466 || (drv_data->tx == drv_data->tx_end))
467 return 0;
468
469 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
470 drv_data->tx += 2;
471
472 return 1;
473 }
474
475 static int u16_reader(struct driver_data *drv_data)
476 {
477 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
478 && (drv_data->rx < drv_data->rx_end)) {
479 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
480 drv_data->rx += 2;
481 }
482
483 return drv_data->rx == drv_data->rx_end;
484 }
485
486 static int u32_writer(struct driver_data *drv_data)
487 {
488 if (pxa2xx_spi_txfifo_full(drv_data)
489 || (drv_data->tx == drv_data->tx_end))
490 return 0;
491
492 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
493 drv_data->tx += 4;
494
495 return 1;
496 }
497
498 static int u32_reader(struct driver_data *drv_data)
499 {
500 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
501 && (drv_data->rx < drv_data->rx_end)) {
502 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
503 drv_data->rx += 4;
504 }
505
506 return drv_data->rx == drv_data->rx_end;
507 }
508
509 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
510 {
511 struct spi_message *msg = drv_data->cur_msg;
512 struct spi_transfer *trans = drv_data->cur_transfer;
513
514 /* Move to next transfer */
515 if (trans->transfer_list.next != &msg->transfers) {
516 drv_data->cur_transfer =
517 list_entry(trans->transfer_list.next,
518 struct spi_transfer,
519 transfer_list);
520 return RUNNING_STATE;
521 } else
522 return DONE_STATE;
523 }
524
525 /* caller already set message->status; dma and pio irqs are blocked */
526 static void giveback(struct driver_data *drv_data)
527 {
528 struct spi_transfer* last_transfer;
529 struct spi_message *msg;
530 unsigned long timeout;
531
532 msg = drv_data->cur_msg;
533 drv_data->cur_msg = NULL;
534 drv_data->cur_transfer = NULL;
535
536 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
537 transfer_list);
538
539 /* Delay if requested before any change in chip select */
540 if (last_transfer->delay_usecs)
541 udelay(last_transfer->delay_usecs);
542
543 /* Wait until SSP becomes idle before deasserting the CS */
544 timeout = jiffies + msecs_to_jiffies(10);
545 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
546 !time_after(jiffies, timeout))
547 cpu_relax();
548
549 /* Drop chip select UNLESS cs_change is true or we are returning
550 * a message with an error, or next message is for another chip
551 */
552 if (!last_transfer->cs_change)
553 cs_deassert(drv_data);
554 else {
555 struct spi_message *next_msg;
556
557 /* Holding of cs was hinted, but we need to make sure
558 * the next message is for the same chip. Don't waste
559 * time with the following tests unless this was hinted.
560 *
561 * We cannot postpone this until pump_messages, because
562 * after calling msg->complete (below) the driver that
563 * sent the current message could be unloaded, which
564 * could invalidate the cs_control() callback...
565 */
566
567 /* get a pointer to the next message, if any */
568 next_msg = spi_get_next_queued_message(drv_data->master);
569
570 /* see if the next and current messages point
571 * to the same chip
572 */
573 if ((next_msg && next_msg->spi != msg->spi) ||
574 msg->state == ERROR_STATE)
575 cs_deassert(drv_data);
576 }
577
578 drv_data->cur_chip = NULL;
579 spi_finalize_current_message(drv_data->master);
580 }
581
582 static void reset_sccr1(struct driver_data *drv_data)
583 {
584 struct chip_data *chip = drv_data->cur_chip;
585 u32 sccr1_reg;
586
587 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
588 sccr1_reg &= ~SSCR1_RFT;
589 sccr1_reg |= chip->threshold;
590 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
591 }
592
593 static void int_error_stop(struct driver_data *drv_data, const char* msg)
594 {
595 /* Stop and reset SSP */
596 write_SSSR_CS(drv_data, drv_data->clear_sr);
597 reset_sccr1(drv_data);
598 if (!pxa25x_ssp_comp(drv_data))
599 pxa2xx_spi_write(drv_data, SSTO, 0);
600 pxa2xx_spi_flush(drv_data);
601 pxa2xx_spi_write(drv_data, SSCR0,
602 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
603
604 dev_err(&drv_data->pdev->dev, "%s\n", msg);
605
606 drv_data->cur_msg->state = ERROR_STATE;
607 tasklet_schedule(&drv_data->pump_transfers);
608 }
609
610 static void int_transfer_complete(struct driver_data *drv_data)
611 {
612 /* Clear and disable interrupts */
613 write_SSSR_CS(drv_data, drv_data->clear_sr);
614 reset_sccr1(drv_data);
615 if (!pxa25x_ssp_comp(drv_data))
616 pxa2xx_spi_write(drv_data, SSTO, 0);
617
618 /* Update total byte transferred return count actual bytes read */
619 drv_data->cur_msg->actual_length += drv_data->len -
620 (drv_data->rx_end - drv_data->rx);
621
622 /* Transfer delays and chip select release are
623 * handled in pump_transfers or giveback
624 */
625
626 /* Move to next transfer */
627 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
628
629 /* Schedule transfer tasklet */
630 tasklet_schedule(&drv_data->pump_transfers);
631 }
632
633 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
634 {
635 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
636 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
637
638 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
639
640 if (irq_status & SSSR_ROR) {
641 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
642 return IRQ_HANDLED;
643 }
644
645 if (irq_status & SSSR_TINT) {
646 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
647 if (drv_data->read(drv_data)) {
648 int_transfer_complete(drv_data);
649 return IRQ_HANDLED;
650 }
651 }
652
653 /* Drain rx fifo, Fill tx fifo and prevent overruns */
654 do {
655 if (drv_data->read(drv_data)) {
656 int_transfer_complete(drv_data);
657 return IRQ_HANDLED;
658 }
659 } while (drv_data->write(drv_data));
660
661 if (drv_data->read(drv_data)) {
662 int_transfer_complete(drv_data);
663 return IRQ_HANDLED;
664 }
665
666 if (drv_data->tx == drv_data->tx_end) {
667 u32 bytes_left;
668 u32 sccr1_reg;
669
670 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
671 sccr1_reg &= ~SSCR1_TIE;
672
673 /*
674 * PXA25x_SSP has no timeout, set up rx threshould for the
675 * remaining RX bytes.
676 */
677 if (pxa25x_ssp_comp(drv_data)) {
678 u32 rx_thre;
679
680 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
681
682 bytes_left = drv_data->rx_end - drv_data->rx;
683 switch (drv_data->n_bytes) {
684 case 4:
685 bytes_left >>= 1;
686 case 2:
687 bytes_left >>= 1;
688 }
689
690 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
691 if (rx_thre > bytes_left)
692 rx_thre = bytes_left;
693
694 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
695 }
696 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
697 }
698
699 /* We did something */
700 return IRQ_HANDLED;
701 }
702
703 static irqreturn_t ssp_int(int irq, void *dev_id)
704 {
705 struct driver_data *drv_data = dev_id;
706 u32 sccr1_reg;
707 u32 mask = drv_data->mask_sr;
708 u32 status;
709
710 /*
711 * The IRQ might be shared with other peripherals so we must first
712 * check that are we RPM suspended or not. If we are we assume that
713 * the IRQ was not for us (we shouldn't be RPM suspended when the
714 * interrupt is enabled).
715 */
716 if (pm_runtime_suspended(&drv_data->pdev->dev))
717 return IRQ_NONE;
718
719 /*
720 * If the device is not yet in RPM suspended state and we get an
721 * interrupt that is meant for another device, check if status bits
722 * are all set to one. That means that the device is already
723 * powered off.
724 */
725 status = pxa2xx_spi_read(drv_data, SSSR);
726 if (status == ~0)
727 return IRQ_NONE;
728
729 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
730
731 /* Ignore possible writes if we don't need to write */
732 if (!(sccr1_reg & SSCR1_TIE))
733 mask &= ~SSSR_TFS;
734
735 /* Ignore RX timeout interrupt if it is disabled */
736 if (!(sccr1_reg & SSCR1_TINTE))
737 mask &= ~SSSR_TINT;
738
739 if (!(status & mask))
740 return IRQ_NONE;
741
742 if (!drv_data->cur_msg) {
743
744 pxa2xx_spi_write(drv_data, SSCR0,
745 pxa2xx_spi_read(drv_data, SSCR0)
746 & ~SSCR0_SSE);
747 pxa2xx_spi_write(drv_data, SSCR1,
748 pxa2xx_spi_read(drv_data, SSCR1)
749 & ~drv_data->int_cr1);
750 if (!pxa25x_ssp_comp(drv_data))
751 pxa2xx_spi_write(drv_data, SSTO, 0);
752 write_SSSR_CS(drv_data, drv_data->clear_sr);
753
754 dev_err(&drv_data->pdev->dev,
755 "bad message state in interrupt handler\n");
756
757 /* Never fail */
758 return IRQ_HANDLED;
759 }
760
761 return drv_data->transfer_handler(drv_data);
762 }
763
764 /*
765 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
766 * input frequency by fractions of 2^24. It also has a divider by 5.
767 *
768 * There are formulas to get baud rate value for given input frequency and
769 * divider parameters, such as DDS_CLK_RATE and SCR:
770 *
771 * Fsys = 200MHz
772 *
773 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
774 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
775 *
776 * DDS_CLK_RATE either 2^n or 2^n / 5.
777 * SCR is in range 0 .. 255
778 *
779 * Divisor = 5^i * 2^j * 2 * k
780 * i = [0, 1] i = 1 iff j = 0 or j > 3
781 * j = [0, 23] j = 0 iff i = 1
782 * k = [1, 256]
783 * Special case: j = 0, i = 1: Divisor = 2 / 5
784 *
785 * Accordingly to the specification the recommended values for DDS_CLK_RATE
786 * are:
787 * Case 1: 2^n, n = [0, 23]
788 * Case 2: 2^24 * 2 / 5 (0x666666)
789 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
790 *
791 * In all cases the lowest possible value is better.
792 *
793 * The function calculates parameters for all cases and chooses the one closest
794 * to the asked baud rate.
795 */
796 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
797 {
798 unsigned long xtal = 200000000;
799 unsigned long fref = xtal / 2; /* mandatory division by 2,
800 see (2) */
801 /* case 3 */
802 unsigned long fref1 = fref / 2; /* case 1 */
803 unsigned long fref2 = fref * 2 / 5; /* case 2 */
804 unsigned long scale;
805 unsigned long q, q1, q2;
806 long r, r1, r2;
807 u32 mul;
808
809 /* Case 1 */
810
811 /* Set initial value for DDS_CLK_RATE */
812 mul = (1 << 24) >> 1;
813
814 /* Calculate initial quot */
815 q1 = DIV_ROUND_UP(fref1, rate);
816
817 /* Scale q1 if it's too big */
818 if (q1 > 256) {
819 /* Scale q1 to range [1, 512] */
820 scale = fls_long(q1 - 1);
821 if (scale > 9) {
822 q1 >>= scale - 9;
823 mul >>= scale - 9;
824 }
825
826 /* Round the result if we have a remainder */
827 q1 += q1 & 1;
828 }
829
830 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
831 scale = __ffs(q1);
832 q1 >>= scale;
833 mul >>= scale;
834
835 /* Get the remainder */
836 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
837
838 /* Case 2 */
839
840 q2 = DIV_ROUND_UP(fref2, rate);
841 r2 = abs(fref2 / q2 - rate);
842
843 /*
844 * Choose the best between two: less remainder we have the better. We
845 * can't go case 2 if q2 is greater than 256 since SCR register can
846 * hold only values 0 .. 255.
847 */
848 if (r2 >= r1 || q2 > 256) {
849 /* case 1 is better */
850 r = r1;
851 q = q1;
852 } else {
853 /* case 2 is better */
854 r = r2;
855 q = q2;
856 mul = (1 << 24) * 2 / 5;
857 }
858
859 /* Check case 3 only if the divisor is big enough */
860 if (fref / rate >= 80) {
861 u64 fssp;
862 u32 m;
863
864 /* Calculate initial quot */
865 q1 = DIV_ROUND_UP(fref, rate);
866 m = (1 << 24) / q1;
867
868 /* Get the remainder */
869 fssp = (u64)fref * m;
870 do_div(fssp, 1 << 24);
871 r1 = abs(fssp - rate);
872
873 /* Choose this one if it suits better */
874 if (r1 < r) {
875 /* case 3 is better */
876 q = 1;
877 mul = m;
878 }
879 }
880
881 *dds = mul;
882 return q - 1;
883 }
884
885 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
886 {
887 unsigned long ssp_clk = drv_data->master->max_speed_hz;
888 const struct ssp_device *ssp = drv_data->ssp;
889
890 rate = min_t(int, ssp_clk, rate);
891
892 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
893 return (ssp_clk / (2 * rate) - 1) & 0xff;
894 else
895 return (ssp_clk / rate - 1) & 0xfff;
896 }
897
898 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
899 int rate)
900 {
901 struct chip_data *chip = drv_data->cur_chip;
902 unsigned int clk_div;
903
904 switch (drv_data->ssp_type) {
905 case QUARK_X1000_SSP:
906 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
907 break;
908 default:
909 clk_div = ssp_get_clk_div(drv_data, rate);
910 break;
911 }
912 return clk_div << 8;
913 }
914
915 static void pump_transfers(unsigned long data)
916 {
917 struct driver_data *drv_data = (struct driver_data *)data;
918 struct spi_message *message = NULL;
919 struct spi_transfer *transfer = NULL;
920 struct spi_transfer *previous = NULL;
921 struct chip_data *chip = NULL;
922 u32 clk_div = 0;
923 u8 bits = 0;
924 u32 speed = 0;
925 u32 cr0;
926 u32 cr1;
927 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
928 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
929 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
930 int err;
931
932 /* Get current state information */
933 message = drv_data->cur_msg;
934 transfer = drv_data->cur_transfer;
935 chip = drv_data->cur_chip;
936
937 /* Handle for abort */
938 if (message->state == ERROR_STATE) {
939 message->status = -EIO;
940 giveback(drv_data);
941 return;
942 }
943
944 /* Handle end of message */
945 if (message->state == DONE_STATE) {
946 message->status = 0;
947 giveback(drv_data);
948 return;
949 }
950
951 /* Delay if requested at end of transfer before CS change */
952 if (message->state == RUNNING_STATE) {
953 previous = list_entry(transfer->transfer_list.prev,
954 struct spi_transfer,
955 transfer_list);
956 if (previous->delay_usecs)
957 udelay(previous->delay_usecs);
958
959 /* Drop chip select only if cs_change is requested */
960 if (previous->cs_change)
961 cs_deassert(drv_data);
962 }
963
964 /* Check if we can DMA this transfer */
965 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
966
967 /* reject already-mapped transfers; PIO won't always work */
968 if (message->is_dma_mapped
969 || transfer->rx_dma || transfer->tx_dma) {
970 dev_err(&drv_data->pdev->dev,
971 "pump_transfers: mapped transfer length of "
972 "%u is greater than %d\n",
973 transfer->len, MAX_DMA_LEN);
974 message->status = -EINVAL;
975 giveback(drv_data);
976 return;
977 }
978
979 /* warn ... we force this to PIO mode */
980 dev_warn_ratelimited(&message->spi->dev,
981 "pump_transfers: DMA disabled for transfer length %ld "
982 "greater than %d\n",
983 (long)drv_data->len, MAX_DMA_LEN);
984 }
985
986 /* Setup the transfer state based on the type of transfer */
987 if (pxa2xx_spi_flush(drv_data) == 0) {
988 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
989 message->status = -EIO;
990 giveback(drv_data);
991 return;
992 }
993 drv_data->n_bytes = chip->n_bytes;
994 drv_data->tx = (void *)transfer->tx_buf;
995 drv_data->tx_end = drv_data->tx + transfer->len;
996 drv_data->rx = transfer->rx_buf;
997 drv_data->rx_end = drv_data->rx + transfer->len;
998 drv_data->len = transfer->len;
999 drv_data->write = drv_data->tx ? chip->write : null_writer;
1000 drv_data->read = drv_data->rx ? chip->read : null_reader;
1001
1002 /* Change speed and bit per word on a per transfer */
1003 bits = transfer->bits_per_word;
1004 speed = transfer->speed_hz;
1005
1006 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1007
1008 if (bits <= 8) {
1009 drv_data->n_bytes = 1;
1010 drv_data->read = drv_data->read != null_reader ?
1011 u8_reader : null_reader;
1012 drv_data->write = drv_data->write != null_writer ?
1013 u8_writer : null_writer;
1014 } else if (bits <= 16) {
1015 drv_data->n_bytes = 2;
1016 drv_data->read = drv_data->read != null_reader ?
1017 u16_reader : null_reader;
1018 drv_data->write = drv_data->write != null_writer ?
1019 u16_writer : null_writer;
1020 } else if (bits <= 32) {
1021 drv_data->n_bytes = 4;
1022 drv_data->read = drv_data->read != null_reader ?
1023 u32_reader : null_reader;
1024 drv_data->write = drv_data->write != null_writer ?
1025 u32_writer : null_writer;
1026 }
1027 /*
1028 * if bits/word is changed in dma mode, then must check the
1029 * thresholds and burst also
1030 */
1031 if (chip->enable_dma) {
1032 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1033 message->spi,
1034 bits, &dma_burst,
1035 &dma_thresh))
1036 dev_warn_ratelimited(&message->spi->dev,
1037 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1038 }
1039
1040 message->state = RUNNING_STATE;
1041
1042 drv_data->dma_mapped = 0;
1043 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1044 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
1045 if (drv_data->dma_mapped) {
1046
1047 /* Ensure we have the correct interrupt handler */
1048 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1049
1050 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1051 if (err) {
1052 message->status = err;
1053 giveback(drv_data);
1054 return;
1055 }
1056
1057 /* Clear status and start DMA engine */
1058 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1059 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1060
1061 pxa2xx_spi_dma_start(drv_data);
1062 } else {
1063 /* Ensure we have the correct interrupt handler */
1064 drv_data->transfer_handler = interrupt_transfer;
1065
1066 /* Clear status */
1067 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1068 write_SSSR_CS(drv_data, drv_data->clear_sr);
1069 }
1070
1071 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1072 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1073 if (!pxa25x_ssp_comp(drv_data))
1074 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1075 drv_data->master->max_speed_hz
1076 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1077 drv_data->dma_mapped ? "DMA" : "PIO");
1078 else
1079 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1080 drv_data->master->max_speed_hz / 2
1081 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1082 drv_data->dma_mapped ? "DMA" : "PIO");
1083
1084 if (is_lpss_ssp(drv_data)) {
1085 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1086 != chip->lpss_rx_threshold)
1087 pxa2xx_spi_write(drv_data, SSIRF,
1088 chip->lpss_rx_threshold);
1089 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1090 != chip->lpss_tx_threshold)
1091 pxa2xx_spi_write(drv_data, SSITF,
1092 chip->lpss_tx_threshold);
1093 }
1094
1095 if (is_quark_x1000_ssp(drv_data) &&
1096 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1097 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1098
1099 /* see if we need to reload the config registers */
1100 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1101 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1102 != (cr1 & change_mask)) {
1103 /* stop the SSP, and update the other bits */
1104 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1105 if (!pxa25x_ssp_comp(drv_data))
1106 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1107 /* first set CR1 without interrupt and service enables */
1108 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1109 /* restart the SSP */
1110 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1111
1112 } else {
1113 if (!pxa25x_ssp_comp(drv_data))
1114 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1115 }
1116
1117 cs_assert(drv_data);
1118
1119 /* after chip select, release the data by enabling service
1120 * requests and interrupts, without changing any mode bits */
1121 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1122 }
1123
1124 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1125 struct spi_message *msg)
1126 {
1127 struct driver_data *drv_data = spi_master_get_devdata(master);
1128
1129 drv_data->cur_msg = msg;
1130 /* Initial message state*/
1131 drv_data->cur_msg->state = START_STATE;
1132 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1133 struct spi_transfer,
1134 transfer_list);
1135
1136 /* prepare to setup the SSP, in pump_transfers, using the per
1137 * chip configuration */
1138 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1139
1140 /* Mark as busy and launch transfers */
1141 tasklet_schedule(&drv_data->pump_transfers);
1142 return 0;
1143 }
1144
1145 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1146 {
1147 struct driver_data *drv_data = spi_master_get_devdata(master);
1148
1149 /* Disable the SSP now */
1150 pxa2xx_spi_write(drv_data, SSCR0,
1151 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1152
1153 return 0;
1154 }
1155
1156 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1157 struct pxa2xx_spi_chip *chip_info)
1158 {
1159 int err = 0;
1160
1161 if (chip == NULL || chip_info == NULL)
1162 return 0;
1163
1164 /* NOTE: setup() can be called multiple times, possibly with
1165 * different chip_info, release previously requested GPIO
1166 */
1167 if (gpio_is_valid(chip->gpio_cs))
1168 gpio_free(chip->gpio_cs);
1169
1170 /* If (*cs_control) is provided, ignore GPIO chip select */
1171 if (chip_info->cs_control) {
1172 chip->cs_control = chip_info->cs_control;
1173 return 0;
1174 }
1175
1176 if (gpio_is_valid(chip_info->gpio_cs)) {
1177 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1178 if (err) {
1179 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1180 chip_info->gpio_cs);
1181 return err;
1182 }
1183
1184 chip->gpio_cs = chip_info->gpio_cs;
1185 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1186
1187 err = gpio_direction_output(chip->gpio_cs,
1188 !chip->gpio_cs_inverted);
1189 }
1190
1191 return err;
1192 }
1193
1194 static int setup(struct spi_device *spi)
1195 {
1196 struct pxa2xx_spi_chip *chip_info = NULL;
1197 struct chip_data *chip;
1198 const struct lpss_config *config;
1199 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1200 uint tx_thres, tx_hi_thres, rx_thres;
1201
1202 switch (drv_data->ssp_type) {
1203 case QUARK_X1000_SSP:
1204 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1205 tx_hi_thres = 0;
1206 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1207 break;
1208 case LPSS_LPT_SSP:
1209 case LPSS_BYT_SSP:
1210 case LPSS_BSW_SSP:
1211 case LPSS_SPT_SSP:
1212 case LPSS_BXT_SSP:
1213 config = lpss_get_config(drv_data);
1214 tx_thres = config->tx_threshold_lo;
1215 tx_hi_thres = config->tx_threshold_hi;
1216 rx_thres = config->rx_threshold;
1217 break;
1218 default:
1219 tx_thres = TX_THRESH_DFLT;
1220 tx_hi_thres = 0;
1221 rx_thres = RX_THRESH_DFLT;
1222 break;
1223 }
1224
1225 /* Only alloc on first setup */
1226 chip = spi_get_ctldata(spi);
1227 if (!chip) {
1228 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1229 if (!chip)
1230 return -ENOMEM;
1231
1232 if (drv_data->ssp_type == CE4100_SSP) {
1233 if (spi->chip_select > 4) {
1234 dev_err(&spi->dev,
1235 "failed setup: cs number must not be > 4.\n");
1236 kfree(chip);
1237 return -EINVAL;
1238 }
1239
1240 chip->frm = spi->chip_select;
1241 } else
1242 chip->gpio_cs = -1;
1243 chip->enable_dma = 0;
1244 chip->timeout = TIMOUT_DFLT;
1245 }
1246
1247 /* protocol drivers may change the chip settings, so...
1248 * if chip_info exists, use it */
1249 chip_info = spi->controller_data;
1250
1251 /* chip_info isn't always needed */
1252 chip->cr1 = 0;
1253 if (chip_info) {
1254 if (chip_info->timeout)
1255 chip->timeout = chip_info->timeout;
1256 if (chip_info->tx_threshold)
1257 tx_thres = chip_info->tx_threshold;
1258 if (chip_info->tx_hi_threshold)
1259 tx_hi_thres = chip_info->tx_hi_threshold;
1260 if (chip_info->rx_threshold)
1261 rx_thres = chip_info->rx_threshold;
1262 chip->enable_dma = drv_data->master_info->enable_dma;
1263 chip->dma_threshold = 0;
1264 if (chip_info->enable_loopback)
1265 chip->cr1 = SSCR1_LBM;
1266 } else if (ACPI_HANDLE(&spi->dev)) {
1267 /*
1268 * Slave devices enumerated from ACPI namespace don't
1269 * usually have chip_info but we still might want to use
1270 * DMA with them.
1271 */
1272 chip->enable_dma = drv_data->master_info->enable_dma;
1273 }
1274
1275 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1276 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1277 | SSITF_TxHiThresh(tx_hi_thres);
1278
1279 /* set dma burst and threshold outside of chip_info path so that if
1280 * chip_info goes away after setting chip->enable_dma, the
1281 * burst and threshold can still respond to changes in bits_per_word */
1282 if (chip->enable_dma) {
1283 /* set up legal burst and threshold for dma */
1284 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1285 spi->bits_per_word,
1286 &chip->dma_burst_size,
1287 &chip->dma_threshold)) {
1288 dev_warn(&spi->dev,
1289 "in setup: DMA burst size reduced to match bits_per_word\n");
1290 }
1291 }
1292
1293 switch (drv_data->ssp_type) {
1294 case QUARK_X1000_SSP:
1295 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1296 & QUARK_X1000_SSCR1_RFT)
1297 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1298 & QUARK_X1000_SSCR1_TFT);
1299 break;
1300 default:
1301 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1302 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1303 break;
1304 }
1305
1306 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1307 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1308 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1309
1310 if (spi->mode & SPI_LOOP)
1311 chip->cr1 |= SSCR1_LBM;
1312
1313 if (spi->bits_per_word <= 8) {
1314 chip->n_bytes = 1;
1315 chip->read = u8_reader;
1316 chip->write = u8_writer;
1317 } else if (spi->bits_per_word <= 16) {
1318 chip->n_bytes = 2;
1319 chip->read = u16_reader;
1320 chip->write = u16_writer;
1321 } else if (spi->bits_per_word <= 32) {
1322 chip->n_bytes = 4;
1323 chip->read = u32_reader;
1324 chip->write = u32_writer;
1325 }
1326
1327 spi_set_ctldata(spi, chip);
1328
1329 if (drv_data->ssp_type == CE4100_SSP)
1330 return 0;
1331
1332 return setup_cs(spi, chip, chip_info);
1333 }
1334
1335 static void cleanup(struct spi_device *spi)
1336 {
1337 struct chip_data *chip = spi_get_ctldata(spi);
1338 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1339
1340 if (!chip)
1341 return;
1342
1343 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1344 gpio_free(chip->gpio_cs);
1345
1346 kfree(chip);
1347 }
1348
1349 #ifdef CONFIG_PCI
1350 #ifdef CONFIG_ACPI
1351
1352 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1353 { "INT33C0", LPSS_LPT_SSP },
1354 { "INT33C1", LPSS_LPT_SSP },
1355 { "INT3430", LPSS_LPT_SSP },
1356 { "INT3431", LPSS_LPT_SSP },
1357 { "80860F0E", LPSS_BYT_SSP },
1358 { "8086228E", LPSS_BSW_SSP },
1359 { },
1360 };
1361 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1362
1363 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1364 {
1365 unsigned int devid;
1366 int port_id = -1;
1367
1368 if (adev && adev->pnp.unique_id &&
1369 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1370 port_id = devid;
1371 return port_id;
1372 }
1373 #else /* !CONFIG_ACPI */
1374 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1375 {
1376 return -1;
1377 }
1378 #endif
1379
1380 /*
1381 * PCI IDs of compound devices that integrate both host controller and private
1382 * integrated DMA engine. Please note these are not used in module
1383 * autoloading and probing in this module but matching the LPSS SSP type.
1384 */
1385 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1386 /* SPT-LP */
1387 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1388 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1389 /* SPT-H */
1390 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1391 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1392 /* BXT A-Step */
1393 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1394 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1395 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1396 /* BXT B-Step */
1397 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1398 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1399 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1400 /* APL */
1401 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1402 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1403 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1404 { },
1405 };
1406
1407 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1408 {
1409 struct device *dev = param;
1410
1411 if (dev != chan->device->dev->parent)
1412 return false;
1413
1414 return true;
1415 }
1416
1417 static struct pxa2xx_spi_master *
1418 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1419 {
1420 struct pxa2xx_spi_master *pdata;
1421 struct acpi_device *adev;
1422 struct ssp_device *ssp;
1423 struct resource *res;
1424 const struct acpi_device_id *adev_id = NULL;
1425 const struct pci_device_id *pcidev_id = NULL;
1426 int type;
1427
1428 adev = ACPI_COMPANION(&pdev->dev);
1429
1430 if (dev_is_pci(pdev->dev.parent))
1431 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1432 to_pci_dev(pdev->dev.parent));
1433 else if (adev)
1434 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1435 &pdev->dev);
1436 else
1437 return NULL;
1438
1439 if (adev_id)
1440 type = (int)adev_id->driver_data;
1441 else if (pcidev_id)
1442 type = (int)pcidev_id->driver_data;
1443 else
1444 return NULL;
1445
1446 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1447 if (!pdata)
1448 return NULL;
1449
1450 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1451 if (!res)
1452 return NULL;
1453
1454 ssp = &pdata->ssp;
1455
1456 ssp->phys_base = res->start;
1457 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1458 if (IS_ERR(ssp->mmio_base))
1459 return NULL;
1460
1461 if (pcidev_id) {
1462 pdata->tx_param = pdev->dev.parent;
1463 pdata->rx_param = pdev->dev.parent;
1464 pdata->dma_filter = pxa2xx_spi_idma_filter;
1465 }
1466
1467 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1468 ssp->irq = platform_get_irq(pdev, 0);
1469 ssp->type = type;
1470 ssp->pdev = pdev;
1471 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1472
1473 pdata->num_chipselect = 1;
1474 pdata->enable_dma = true;
1475
1476 return pdata;
1477 }
1478
1479 #else /* !CONFIG_PCI */
1480 static inline struct pxa2xx_spi_master *
1481 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1482 {
1483 return NULL;
1484 }
1485 #endif
1486
1487 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1488 {
1489 struct driver_data *drv_data = spi_master_get_devdata(master);
1490
1491 if (has_acpi_companion(&drv_data->pdev->dev)) {
1492 switch (drv_data->ssp_type) {
1493 /*
1494 * For Atoms the ACPI DeviceSelection used by the Windows
1495 * driver starts from 1 instead of 0 so translate it here
1496 * to match what Linux expects.
1497 */
1498 case LPSS_BYT_SSP:
1499 case LPSS_BSW_SSP:
1500 return cs - 1;
1501
1502 default:
1503 break;
1504 }
1505 }
1506
1507 return cs;
1508 }
1509
1510 static int pxa2xx_spi_probe(struct platform_device *pdev)
1511 {
1512 struct device *dev = &pdev->dev;
1513 struct pxa2xx_spi_master *platform_info;
1514 struct spi_master *master;
1515 struct driver_data *drv_data;
1516 struct ssp_device *ssp;
1517 const struct lpss_config *config;
1518 int status;
1519 u32 tmp;
1520
1521 platform_info = dev_get_platdata(dev);
1522 if (!platform_info) {
1523 platform_info = pxa2xx_spi_init_pdata(pdev);
1524 if (!platform_info) {
1525 dev_err(&pdev->dev, "missing platform data\n");
1526 return -ENODEV;
1527 }
1528 }
1529
1530 ssp = pxa_ssp_request(pdev->id, pdev->name);
1531 if (!ssp)
1532 ssp = &platform_info->ssp;
1533
1534 if (!ssp->mmio_base) {
1535 dev_err(&pdev->dev, "failed to get ssp\n");
1536 return -ENODEV;
1537 }
1538
1539 master = spi_alloc_master(dev, sizeof(struct driver_data));
1540 if (!master) {
1541 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1542 pxa_ssp_free(ssp);
1543 return -ENOMEM;
1544 }
1545 drv_data = spi_master_get_devdata(master);
1546 drv_data->master = master;
1547 drv_data->master_info = platform_info;
1548 drv_data->pdev = pdev;
1549 drv_data->ssp = ssp;
1550
1551 master->dev.of_node = pdev->dev.of_node;
1552 /* the spi->mode bits understood by this driver: */
1553 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1554
1555 master->bus_num = ssp->port_id;
1556 master->dma_alignment = DMA_ALIGNMENT;
1557 master->cleanup = cleanup;
1558 master->setup = setup;
1559 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1560 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1561 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1562 master->auto_runtime_pm = true;
1563 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1564
1565 drv_data->ssp_type = ssp->type;
1566
1567 drv_data->ioaddr = ssp->mmio_base;
1568 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1569 if (pxa25x_ssp_comp(drv_data)) {
1570 switch (drv_data->ssp_type) {
1571 case QUARK_X1000_SSP:
1572 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1573 break;
1574 default:
1575 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1576 break;
1577 }
1578
1579 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1580 drv_data->dma_cr1 = 0;
1581 drv_data->clear_sr = SSSR_ROR;
1582 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1583 } else {
1584 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1585 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1586 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1587 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1588 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1589 }
1590
1591 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1592 drv_data);
1593 if (status < 0) {
1594 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1595 goto out_error_master_alloc;
1596 }
1597
1598 /* Setup DMA if requested */
1599 if (platform_info->enable_dma) {
1600 status = pxa2xx_spi_dma_setup(drv_data);
1601 if (status) {
1602 dev_dbg(dev, "no DMA channels available, using PIO\n");
1603 platform_info->enable_dma = false;
1604 }
1605 }
1606
1607 /* Enable SOC clock */
1608 clk_prepare_enable(ssp->clk);
1609
1610 master->max_speed_hz = clk_get_rate(ssp->clk);
1611
1612 /* Load default SSP configuration */
1613 pxa2xx_spi_write(drv_data, SSCR0, 0);
1614 switch (drv_data->ssp_type) {
1615 case QUARK_X1000_SSP:
1616 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1617 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1618 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1619
1620 /* using the Motorola SPI protocol and use 8 bit frame */
1621 pxa2xx_spi_write(drv_data, SSCR0,
1622 QUARK_X1000_SSCR0_Motorola
1623 | QUARK_X1000_SSCR0_DataSize(8));
1624 break;
1625 default:
1626 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1627 SSCR1_TxTresh(TX_THRESH_DFLT);
1628 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1629 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1630 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1631 break;
1632 }
1633
1634 if (!pxa25x_ssp_comp(drv_data))
1635 pxa2xx_spi_write(drv_data, SSTO, 0);
1636
1637 if (!is_quark_x1000_ssp(drv_data))
1638 pxa2xx_spi_write(drv_data, SSPSP, 0);
1639
1640 if (is_lpss_ssp(drv_data)) {
1641 lpss_ssp_setup(drv_data);
1642 config = lpss_get_config(drv_data);
1643 if (config->reg_capabilities >= 0) {
1644 tmp = __lpss_ssp_read_priv(drv_data,
1645 config->reg_capabilities);
1646 tmp &= LPSS_CAPS_CS_EN_MASK;
1647 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1648 platform_info->num_chipselect = ffz(tmp);
1649 } else if (config->cs_num) {
1650 platform_info->num_chipselect = config->cs_num;
1651 }
1652 }
1653 master->num_chipselect = platform_info->num_chipselect;
1654
1655 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1656 (unsigned long)drv_data);
1657
1658 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1659 pm_runtime_use_autosuspend(&pdev->dev);
1660 pm_runtime_set_active(&pdev->dev);
1661 pm_runtime_enable(&pdev->dev);
1662
1663 /* Register with the SPI framework */
1664 platform_set_drvdata(pdev, drv_data);
1665 status = devm_spi_register_master(&pdev->dev, master);
1666 if (status != 0) {
1667 dev_err(&pdev->dev, "problem registering spi master\n");
1668 goto out_error_clock_enabled;
1669 }
1670
1671 return status;
1672
1673 out_error_clock_enabled:
1674 clk_disable_unprepare(ssp->clk);
1675 pxa2xx_spi_dma_release(drv_data);
1676 free_irq(ssp->irq, drv_data);
1677
1678 out_error_master_alloc:
1679 spi_master_put(master);
1680 pxa_ssp_free(ssp);
1681 return status;
1682 }
1683
1684 static int pxa2xx_spi_remove(struct platform_device *pdev)
1685 {
1686 struct driver_data *drv_data = platform_get_drvdata(pdev);
1687 struct ssp_device *ssp;
1688
1689 if (!drv_data)
1690 return 0;
1691 ssp = drv_data->ssp;
1692
1693 pm_runtime_get_sync(&pdev->dev);
1694
1695 /* Disable the SSP at the peripheral and SOC level */
1696 pxa2xx_spi_write(drv_data, SSCR0, 0);
1697 clk_disable_unprepare(ssp->clk);
1698
1699 /* Release DMA */
1700 if (drv_data->master_info->enable_dma)
1701 pxa2xx_spi_dma_release(drv_data);
1702
1703 pm_runtime_put_noidle(&pdev->dev);
1704 pm_runtime_disable(&pdev->dev);
1705
1706 /* Release IRQ */
1707 free_irq(ssp->irq, drv_data);
1708
1709 /* Release SSP */
1710 pxa_ssp_free(ssp);
1711
1712 return 0;
1713 }
1714
1715 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1716 {
1717 int status = 0;
1718
1719 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1720 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1721 }
1722
1723 #ifdef CONFIG_PM_SLEEP
1724 static int pxa2xx_spi_suspend(struct device *dev)
1725 {
1726 struct driver_data *drv_data = dev_get_drvdata(dev);
1727 struct ssp_device *ssp = drv_data->ssp;
1728 int status = 0;
1729
1730 status = spi_master_suspend(drv_data->master);
1731 if (status != 0)
1732 return status;
1733 pxa2xx_spi_write(drv_data, SSCR0, 0);
1734
1735 if (!pm_runtime_suspended(dev))
1736 clk_disable_unprepare(ssp->clk);
1737
1738 return 0;
1739 }
1740
1741 static int pxa2xx_spi_resume(struct device *dev)
1742 {
1743 struct driver_data *drv_data = dev_get_drvdata(dev);
1744 struct ssp_device *ssp = drv_data->ssp;
1745 int status = 0;
1746
1747 /* Enable the SSP clock */
1748 if (!pm_runtime_suspended(dev))
1749 clk_prepare_enable(ssp->clk);
1750
1751 /* Restore LPSS private register bits */
1752 if (is_lpss_ssp(drv_data))
1753 lpss_ssp_setup(drv_data);
1754
1755 /* Start the queue running */
1756 status = spi_master_resume(drv_data->master);
1757 if (status != 0) {
1758 dev_err(dev, "problem starting queue (%d)\n", status);
1759 return status;
1760 }
1761
1762 return 0;
1763 }
1764 #endif
1765
1766 #ifdef CONFIG_PM
1767 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1768 {
1769 struct driver_data *drv_data = dev_get_drvdata(dev);
1770
1771 clk_disable_unprepare(drv_data->ssp->clk);
1772 return 0;
1773 }
1774
1775 static int pxa2xx_spi_runtime_resume(struct device *dev)
1776 {
1777 struct driver_data *drv_data = dev_get_drvdata(dev);
1778
1779 clk_prepare_enable(drv_data->ssp->clk);
1780 return 0;
1781 }
1782 #endif
1783
1784 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1785 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1786 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1787 pxa2xx_spi_runtime_resume, NULL)
1788 };
1789
1790 static struct platform_driver driver = {
1791 .driver = {
1792 .name = "pxa2xx-spi",
1793 .pm = &pxa2xx_spi_pm_ops,
1794 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1795 },
1796 .probe = pxa2xx_spi_probe,
1797 .remove = pxa2xx_spi_remove,
1798 .shutdown = pxa2xx_spi_shutdown,
1799 };
1800
1801 static int __init pxa2xx_spi_init(void)
1802 {
1803 return platform_driver_register(&driver);
1804 }
1805 subsys_initcall(pxa2xx_spi_init);
1806
1807 static void __exit pxa2xx_spi_exit(void)
1808 {
1809 platform_driver_unregister(&driver);
1810 }
1811 module_exit(pxa2xx_spi_exit);
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