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[mirror_ubuntu-zesty-kernel.git] / drivers / spi / spi-pxa2xx.h
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #ifndef SPI_PXA2XX_H
11 #define SPI_PXA2XX_H
12
13 #include <linux/atomic.h>
14 #include <linux/dmaengine.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/pxa2xx_ssp.h>
20 #include <linux/scatterlist.h>
21 #include <linux/sizes.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/pxa2xx_spi.h>
24
25 struct driver_data {
26 /* Driver model hookup */
27 struct platform_device *pdev;
28
29 /* SSP Info */
30 struct ssp_device *ssp;
31
32 /* SPI framework hookup */
33 enum pxa_ssp_type ssp_type;
34 struct spi_master *master;
35
36 /* PXA hookup */
37 struct pxa2xx_spi_master *master_info;
38
39 /* SSP register addresses */
40 void __iomem *ioaddr;
41 u32 ssdr_physical;
42
43 /* SSP masks*/
44 u32 dma_cr1;
45 u32 int_cr1;
46 u32 clear_sr;
47 u32 mask_sr;
48
49 /* Maximun clock rate */
50 unsigned long max_clk_rate;
51
52 /* Message Transfer pump */
53 struct tasklet_struct pump_transfers;
54
55 /* DMA engine support */
56 struct dma_chan *rx_chan;
57 struct dma_chan *tx_chan;
58 struct sg_table rx_sgt;
59 struct sg_table tx_sgt;
60 int rx_nents;
61 int tx_nents;
62 void *dummy;
63 atomic_t dma_running;
64
65 /* Current message transfer state info */
66 struct spi_message *cur_msg;
67 struct spi_transfer *cur_transfer;
68 struct chip_data *cur_chip;
69 size_t len;
70 void *tx;
71 void *tx_end;
72 void *rx;
73 void *rx_end;
74 int dma_mapped;
75 dma_addr_t rx_dma;
76 dma_addr_t tx_dma;
77 size_t rx_map_len;
78 size_t tx_map_len;
79 u8 n_bytes;
80 int (*write)(struct driver_data *drv_data);
81 int (*read)(struct driver_data *drv_data);
82 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
83 void (*cs_control)(u32 command);
84
85 void __iomem *lpss_base;
86 };
87
88 struct chip_data {
89 u32 cr0;
90 u32 cr1;
91 u32 dds_rate;
92 u32 psp;
93 u32 timeout;
94 u8 n_bytes;
95 u32 dma_burst_size;
96 u32 threshold;
97 u32 dma_threshold;
98 u16 lpss_rx_threshold;
99 u16 lpss_tx_threshold;
100 u8 enable_dma;
101 u8 bits_per_word;
102 u32 speed_hz;
103 union {
104 int gpio_cs;
105 unsigned int frm;
106 };
107 int gpio_cs_inverted;
108 int (*write)(struct driver_data *drv_data);
109 int (*read)(struct driver_data *drv_data);
110 void (*cs_control)(u32 command);
111 };
112
113 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
114 unsigned reg)
115 {
116 return __raw_readl(drv_data->ioaddr + reg);
117 }
118
119 static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
120 unsigned reg, u32 val)
121 {
122 __raw_writel(val, drv_data->ioaddr + reg);
123 }
124
125 #define START_STATE ((void *)0)
126 #define RUNNING_STATE ((void *)1)
127 #define DONE_STATE ((void *)2)
128 #define ERROR_STATE ((void *)-1)
129
130 #define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
131 #define DMA_ALIGNMENT 8
132
133 static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
134 {
135 switch (drv_data->ssp_type) {
136 case PXA25x_SSP:
137 case CE4100_SSP:
138 case QUARK_X1000_SSP:
139 return 1;
140 default:
141 return 0;
142 }
143 }
144
145 static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
146 {
147 if (drv_data->ssp_type == CE4100_SSP ||
148 drv_data->ssp_type == QUARK_X1000_SSP)
149 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
150
151 pxa2xx_spi_write(drv_data, SSSR, val);
152 }
153
154 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
155 extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
156
157 /*
158 * Select the right DMA implementation.
159 */
160 #if defined(CONFIG_SPI_PXA2XX_DMA)
161 #define SPI_PXA2XX_USE_DMA 1
162 #define MAX_DMA_LEN SZ_64K
163 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
164 #else
165 #undef SPI_PXA2XX_USE_DMA
166 #define MAX_DMA_LEN 0
167 #define DEFAULT_DMA_CR1 0
168 #endif
169
170 #ifdef SPI_PXA2XX_USE_DMA
171 extern bool pxa2xx_spi_dma_is_possible(size_t len);
172 extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
173 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
174 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
175 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
176 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
177 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
178 extern void pxa2xx_spi_dma_resume(struct driver_data *drv_data);
179 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
180 struct spi_device *spi,
181 u8 bits_per_word,
182 u32 *burst_code,
183 u32 *threshold);
184 #else
185 static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; }
186 static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
187 {
188 return 0;
189 }
190 #define pxa2xx_spi_dma_transfer NULL
191 static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
192 u32 dma_burst) {}
193 static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {}
194 static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
195 {
196 return 0;
197 }
198 static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {}
199 static inline void pxa2xx_spi_dma_resume(struct driver_data *drv_data) {}
200 static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
201 struct spi_device *spi,
202 u8 bits_per_word,
203 u32 *burst_code,
204 u32 *threshold)
205 {
206 return -ENODEV;
207 }
208 #endif
209
210 #endif /* SPI_PXA2XX_H */