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Merge back earlier 'acpi-pci' material for v4.2.
[mirror_ubuntu-artful-kernel.git] / drivers / spi / spi-sh-msiof.c
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
33
34 #include <asm/unaligned.h>
35
36
37 struct sh_msiof_chipdata {
38 u16 tx_fifo_size;
39 u16 rx_fifo_size;
40 u16 master_flags;
41 };
42
43 struct sh_msiof_spi_priv {
44 struct spi_master *master;
45 void __iomem *mapbase;
46 struct clk *clk;
47 struct platform_device *pdev;
48 const struct sh_msiof_chipdata *chipdata;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 int tx_fifo_size;
52 int rx_fifo_size;
53 void *tx_dma_page;
54 void *rx_dma_page;
55 dma_addr_t tx_dma_addr;
56 dma_addr_t rx_dma_addr;
57 };
58
59 #define TMDR1 0x00 /* Transmit Mode Register 1 */
60 #define TMDR2 0x04 /* Transmit Mode Register 2 */
61 #define TMDR3 0x08 /* Transmit Mode Register 3 */
62 #define RMDR1 0x10 /* Receive Mode Register 1 */
63 #define RMDR2 0x14 /* Receive Mode Register 2 */
64 #define RMDR3 0x18 /* Receive Mode Register 3 */
65 #define TSCR 0x20 /* Transmit Clock Select Register */
66 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
67 #define CTR 0x28 /* Control Register */
68 #define FCTR 0x30 /* FIFO Control Register */
69 #define STR 0x40 /* Status Register */
70 #define IER 0x44 /* Interrupt Enable Register */
71 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
72 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
73 #define TFDR 0x50 /* Transmit FIFO Data Register */
74 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
75 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
76 #define RFDR 0x60 /* Receive FIFO Data Register */
77
78 /* TMDR1 and RMDR1 */
79 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
80 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
81 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
82 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
83 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
84 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
85 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
86 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
87 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
88 #define MDR1_FLD_SHIFT 2
89 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
90 /* TMDR1 */
91 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
92
93 /* TMDR2 and RMDR2 */
94 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
95 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
96 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
97
98 #define MAX_WDLEN 256U
99
100 /* TSCR and RSCR */
101 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
102 #define SCR_BRPS(i) (((i) - 1) << 8)
103 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
104 #define SCR_BRDV_DIV_2 0x0000
105 #define SCR_BRDV_DIV_4 0x0001
106 #define SCR_BRDV_DIV_8 0x0002
107 #define SCR_BRDV_DIV_16 0x0003
108 #define SCR_BRDV_DIV_32 0x0004
109 #define SCR_BRDV_DIV_1 0x0007
110
111 /* CTR */
112 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
113 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
114 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
115 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
116 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
117 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
118 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
119 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
120 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
121 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
122 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
123 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
124 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
125 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
126 #define CTR_TXE 0x00000200 /* Transmit Enable */
127 #define CTR_RXE 0x00000100 /* Receive Enable */
128
129 /* FCTR */
130 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
131 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
132 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
133 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
134 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
135 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
136 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
137 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
138 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
139 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
140 #define FCTR_TFUA_SHIFT 20
141 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
142 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
143 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
144 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
145 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
146 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
147 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
148 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
149 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
150 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
151 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
152 #define FCTR_RFUA_SHIFT 4
153 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
154
155 /* STR */
156 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
157 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
158 #define STR_TEOF 0x00800000 /* Frame Transmission End */
159 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
160 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
161 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
162 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
163 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
164 #define STR_REOF 0x00000080 /* Frame Reception End */
165 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
166 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
167 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
168
169 /* IER */
170 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
171 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
172 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
173 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
174 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
175 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
176 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
177 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
178 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
179 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
180 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
181 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
182 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
183 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
184
185
186 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
187 {
188 switch (reg_offs) {
189 case TSCR:
190 case RSCR:
191 return ioread16(p->mapbase + reg_offs);
192 default:
193 return ioread32(p->mapbase + reg_offs);
194 }
195 }
196
197 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
198 u32 value)
199 {
200 switch (reg_offs) {
201 case TSCR:
202 case RSCR:
203 iowrite16(value, p->mapbase + reg_offs);
204 break;
205 default:
206 iowrite32(value, p->mapbase + reg_offs);
207 break;
208 }
209 }
210
211 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
212 u32 clr, u32 set)
213 {
214 u32 mask = clr | set;
215 u32 data;
216 int k;
217
218 data = sh_msiof_read(p, CTR);
219 data &= ~clr;
220 data |= set;
221 sh_msiof_write(p, CTR, data);
222
223 for (k = 100; k > 0; k--) {
224 if ((sh_msiof_read(p, CTR) & mask) == set)
225 break;
226
227 udelay(10);
228 }
229
230 return k > 0 ? 0 : -ETIMEDOUT;
231 }
232
233 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
234 {
235 struct sh_msiof_spi_priv *p = data;
236
237 /* just disable the interrupt and wake up */
238 sh_msiof_write(p, IER, 0);
239 complete(&p->done);
240
241 return IRQ_HANDLED;
242 }
243
244 static struct {
245 unsigned short div;
246 unsigned short brdv;
247 } const sh_msiof_spi_div_table[] = {
248 { 1, SCR_BRDV_DIV_1 },
249 { 2, SCR_BRDV_DIV_2 },
250 { 4, SCR_BRDV_DIV_4 },
251 { 8, SCR_BRDV_DIV_8 },
252 { 16, SCR_BRDV_DIV_16 },
253 { 32, SCR_BRDV_DIV_32 },
254 };
255
256 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
257 unsigned long parent_rate, u32 spi_hz)
258 {
259 unsigned long div = 1024;
260 u32 brps, scr;
261 size_t k;
262
263 if (!WARN_ON(!spi_hz || !parent_rate))
264 div = DIV_ROUND_UP(parent_rate, spi_hz);
265
266 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
267 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
268 if (brps <= 32) /* max of brdv is 32 */
269 break;
270 }
271
272 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
273
274 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
275 sh_msiof_write(p, TSCR, scr);
276 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
277 sh_msiof_write(p, RSCR, scr);
278 }
279
280 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
281 {
282 /*
283 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
284 * b'000 : 0
285 * b'001 : 100
286 * b'010 : 200
287 * b'011 (SYNCDL only) : 300
288 * b'101 : 50
289 * b'110 : 150
290 */
291 if (dtdl_or_syncdl % 100)
292 return dtdl_or_syncdl / 100 + 5;
293 else
294 return dtdl_or_syncdl / 100;
295 }
296
297 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
298 {
299 u32 val;
300
301 if (!p->info)
302 return 0;
303
304 /* check if DTDL and SYNCDL is allowed value */
305 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
306 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
307 return 0;
308 }
309
310 /* check if the sum of DTDL and SYNCDL becomes an integer value */
311 if ((p->info->dtdl + p->info->syncdl) % 100) {
312 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
313 return 0;
314 }
315
316 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
317 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
318
319 return val;
320 }
321
322 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
323 u32 cpol, u32 cpha,
324 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
325 {
326 u32 tmp;
327 int edge;
328
329 /*
330 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
331 * 0 0 10 10 1 1
332 * 0 1 10 10 0 0
333 * 1 0 11 11 0 0
334 * 1 1 11 11 1 1
335 */
336 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
337 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
338 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
339 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
340 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
341 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
342 /* These bits are reserved if RX needs TX */
343 tmp &= ~0x0000ffff;
344 }
345 sh_msiof_write(p, RMDR1, tmp);
346
347 tmp = 0;
348 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
349 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
350
351 edge = cpol ^ !cpha;
352
353 tmp |= edge << CTR_TEDG_SHIFT;
354 tmp |= edge << CTR_REDG_SHIFT;
355 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
356 sh_msiof_write(p, CTR, tmp);
357 }
358
359 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
360 const void *tx_buf, void *rx_buf,
361 u32 bits, u32 words)
362 {
363 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
364
365 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
366 sh_msiof_write(p, TMDR2, dr2);
367 else
368 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
369
370 if (rx_buf)
371 sh_msiof_write(p, RMDR2, dr2);
372 }
373
374 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
375 {
376 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
377 }
378
379 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
380 const void *tx_buf, int words, int fs)
381 {
382 const u8 *buf_8 = tx_buf;
383 int k;
384
385 for (k = 0; k < words; k++)
386 sh_msiof_write(p, TFDR, buf_8[k] << fs);
387 }
388
389 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
390 const void *tx_buf, int words, int fs)
391 {
392 const u16 *buf_16 = tx_buf;
393 int k;
394
395 for (k = 0; k < words; k++)
396 sh_msiof_write(p, TFDR, buf_16[k] << fs);
397 }
398
399 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
400 const void *tx_buf, int words, int fs)
401 {
402 const u16 *buf_16 = tx_buf;
403 int k;
404
405 for (k = 0; k < words; k++)
406 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
407 }
408
409 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
410 const void *tx_buf, int words, int fs)
411 {
412 const u32 *buf_32 = tx_buf;
413 int k;
414
415 for (k = 0; k < words; k++)
416 sh_msiof_write(p, TFDR, buf_32[k] << fs);
417 }
418
419 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
420 const void *tx_buf, int words, int fs)
421 {
422 const u32 *buf_32 = tx_buf;
423 int k;
424
425 for (k = 0; k < words; k++)
426 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
427 }
428
429 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
430 const void *tx_buf, int words, int fs)
431 {
432 const u32 *buf_32 = tx_buf;
433 int k;
434
435 for (k = 0; k < words; k++)
436 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
437 }
438
439 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
440 const void *tx_buf, int words, int fs)
441 {
442 const u32 *buf_32 = tx_buf;
443 int k;
444
445 for (k = 0; k < words; k++)
446 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
447 }
448
449 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
450 void *rx_buf, int words, int fs)
451 {
452 u8 *buf_8 = rx_buf;
453 int k;
454
455 for (k = 0; k < words; k++)
456 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
457 }
458
459 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
460 void *rx_buf, int words, int fs)
461 {
462 u16 *buf_16 = rx_buf;
463 int k;
464
465 for (k = 0; k < words; k++)
466 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
467 }
468
469 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
470 void *rx_buf, int words, int fs)
471 {
472 u16 *buf_16 = rx_buf;
473 int k;
474
475 for (k = 0; k < words; k++)
476 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
477 }
478
479 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
480 void *rx_buf, int words, int fs)
481 {
482 u32 *buf_32 = rx_buf;
483 int k;
484
485 for (k = 0; k < words; k++)
486 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
487 }
488
489 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
490 void *rx_buf, int words, int fs)
491 {
492 u32 *buf_32 = rx_buf;
493 int k;
494
495 for (k = 0; k < words; k++)
496 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
497 }
498
499 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
500 void *rx_buf, int words, int fs)
501 {
502 u32 *buf_32 = rx_buf;
503 int k;
504
505 for (k = 0; k < words; k++)
506 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
507 }
508
509 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
510 void *rx_buf, int words, int fs)
511 {
512 u32 *buf_32 = rx_buf;
513 int k;
514
515 for (k = 0; k < words; k++)
516 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
517 }
518
519 static int sh_msiof_spi_setup(struct spi_device *spi)
520 {
521 struct device_node *np = spi->master->dev.of_node;
522 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
523
524 pm_runtime_get_sync(&p->pdev->dev);
525
526 if (!np) {
527 /*
528 * Use spi->controller_data for CS (same strategy as spi_gpio),
529 * if any. otherwise let HW control CS
530 */
531 spi->cs_gpio = (uintptr_t)spi->controller_data;
532 }
533
534 /* Configure pins before deasserting CS */
535 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
536 !!(spi->mode & SPI_CPHA),
537 !!(spi->mode & SPI_3WIRE),
538 !!(spi->mode & SPI_LSB_FIRST),
539 !!(spi->mode & SPI_CS_HIGH));
540
541 if (spi->cs_gpio >= 0)
542 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
543
544
545 pm_runtime_put(&p->pdev->dev);
546
547 return 0;
548 }
549
550 static int sh_msiof_prepare_message(struct spi_master *master,
551 struct spi_message *msg)
552 {
553 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
554 const struct spi_device *spi = msg->spi;
555
556 /* Configure pins before asserting CS */
557 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
558 !!(spi->mode & SPI_CPHA),
559 !!(spi->mode & SPI_3WIRE),
560 !!(spi->mode & SPI_LSB_FIRST),
561 !!(spi->mode & SPI_CS_HIGH));
562 return 0;
563 }
564
565 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
566 {
567 int ret;
568
569 /* setup clock and rx/tx signals */
570 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
571 if (rx_buf && !ret)
572 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
573 if (!ret)
574 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
575
576 /* start by setting frame bit */
577 if (!ret)
578 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
579
580 return ret;
581 }
582
583 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
584 {
585 int ret;
586
587 /* shut down frame, rx/tx and clock signals */
588 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
589 if (!ret)
590 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
591 if (rx_buf && !ret)
592 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
593 if (!ret)
594 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
595
596 return ret;
597 }
598
599 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
600 void (*tx_fifo)(struct sh_msiof_spi_priv *,
601 const void *, int, int),
602 void (*rx_fifo)(struct sh_msiof_spi_priv *,
603 void *, int, int),
604 const void *tx_buf, void *rx_buf,
605 int words, int bits)
606 {
607 int fifo_shift;
608 int ret;
609
610 /* limit maximum word transfer to rx/tx fifo size */
611 if (tx_buf)
612 words = min_t(int, words, p->tx_fifo_size);
613 if (rx_buf)
614 words = min_t(int, words, p->rx_fifo_size);
615
616 /* the fifo contents need shifting */
617 fifo_shift = 32 - bits;
618
619 /* default FIFO watermarks for PIO */
620 sh_msiof_write(p, FCTR, 0);
621
622 /* setup msiof transfer mode registers */
623 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
624 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
625
626 /* write tx fifo */
627 if (tx_buf)
628 tx_fifo(p, tx_buf, words, fifo_shift);
629
630 reinit_completion(&p->done);
631
632 ret = sh_msiof_spi_start(p, rx_buf);
633 if (ret) {
634 dev_err(&p->pdev->dev, "failed to start hardware\n");
635 goto stop_ier;
636 }
637
638 /* wait for tx fifo to be emptied / rx fifo to be filled */
639 if (!wait_for_completion_timeout(&p->done, HZ)) {
640 dev_err(&p->pdev->dev, "PIO timeout\n");
641 ret = -ETIMEDOUT;
642 goto stop_reset;
643 }
644
645 /* read rx fifo */
646 if (rx_buf)
647 rx_fifo(p, rx_buf, words, fifo_shift);
648
649 /* clear status bits */
650 sh_msiof_reset_str(p);
651
652 ret = sh_msiof_spi_stop(p, rx_buf);
653 if (ret) {
654 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
655 return ret;
656 }
657
658 return words;
659
660 stop_reset:
661 sh_msiof_reset_str(p);
662 sh_msiof_spi_stop(p, rx_buf);
663 stop_ier:
664 sh_msiof_write(p, IER, 0);
665 return ret;
666 }
667
668 static void sh_msiof_dma_complete(void *arg)
669 {
670 struct sh_msiof_spi_priv *p = arg;
671
672 sh_msiof_write(p, IER, 0);
673 complete(&p->done);
674 }
675
676 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
677 void *rx, unsigned int len)
678 {
679 u32 ier_bits = 0;
680 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
681 dma_cookie_t cookie;
682 int ret;
683
684 /* First prepare and submit the DMA request(s), as this may fail */
685 if (rx) {
686 ier_bits |= IER_RDREQE | IER_RDMAE;
687 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
688 p->rx_dma_addr, len, DMA_FROM_DEVICE,
689 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
690 if (!desc_rx)
691 return -EAGAIN;
692
693 desc_rx->callback = sh_msiof_dma_complete;
694 desc_rx->callback_param = p;
695 cookie = dmaengine_submit(desc_rx);
696 if (dma_submit_error(cookie))
697 return cookie;
698 }
699
700 if (tx) {
701 ier_bits |= IER_TDREQE | IER_TDMAE;
702 dma_sync_single_for_device(p->master->dma_tx->device->dev,
703 p->tx_dma_addr, len, DMA_TO_DEVICE);
704 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
705 p->tx_dma_addr, len, DMA_TO_DEVICE,
706 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
707 if (!desc_tx) {
708 ret = -EAGAIN;
709 goto no_dma_tx;
710 }
711
712 if (rx) {
713 /* No callback */
714 desc_tx->callback = NULL;
715 } else {
716 desc_tx->callback = sh_msiof_dma_complete;
717 desc_tx->callback_param = p;
718 }
719 cookie = dmaengine_submit(desc_tx);
720 if (dma_submit_error(cookie)) {
721 ret = cookie;
722 goto no_dma_tx;
723 }
724 }
725
726 /* 1 stage FIFO watermarks for DMA */
727 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
728
729 /* setup msiof transfer mode registers (32-bit words) */
730 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
731
732 sh_msiof_write(p, IER, ier_bits);
733
734 reinit_completion(&p->done);
735
736 /* Now start DMA */
737 if (rx)
738 dma_async_issue_pending(p->master->dma_rx);
739 if (tx)
740 dma_async_issue_pending(p->master->dma_tx);
741
742 ret = sh_msiof_spi_start(p, rx);
743 if (ret) {
744 dev_err(&p->pdev->dev, "failed to start hardware\n");
745 goto stop_dma;
746 }
747
748 /* wait for tx fifo to be emptied / rx fifo to be filled */
749 if (!wait_for_completion_timeout(&p->done, HZ)) {
750 dev_err(&p->pdev->dev, "DMA timeout\n");
751 ret = -ETIMEDOUT;
752 goto stop_reset;
753 }
754
755 /* clear status bits */
756 sh_msiof_reset_str(p);
757
758 ret = sh_msiof_spi_stop(p, rx);
759 if (ret) {
760 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
761 return ret;
762 }
763
764 if (rx)
765 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
766 p->rx_dma_addr, len,
767 DMA_FROM_DEVICE);
768
769 return 0;
770
771 stop_reset:
772 sh_msiof_reset_str(p);
773 sh_msiof_spi_stop(p, rx);
774 stop_dma:
775 if (tx)
776 dmaengine_terminate_all(p->master->dma_tx);
777 no_dma_tx:
778 if (rx)
779 dmaengine_terminate_all(p->master->dma_rx);
780 sh_msiof_write(p, IER, 0);
781 return ret;
782 }
783
784 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
785 {
786 /* src or dst can be unaligned, but not both */
787 if ((unsigned long)src & 3) {
788 while (words--) {
789 *dst++ = swab32(get_unaligned(src));
790 src++;
791 }
792 } else if ((unsigned long)dst & 3) {
793 while (words--) {
794 put_unaligned(swab32(*src++), dst);
795 dst++;
796 }
797 } else {
798 while (words--)
799 *dst++ = swab32(*src++);
800 }
801 }
802
803 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
804 {
805 /* src or dst can be unaligned, but not both */
806 if ((unsigned long)src & 3) {
807 while (words--) {
808 *dst++ = swahw32(get_unaligned(src));
809 src++;
810 }
811 } else if ((unsigned long)dst & 3) {
812 while (words--) {
813 put_unaligned(swahw32(*src++), dst);
814 dst++;
815 }
816 } else {
817 while (words--)
818 *dst++ = swahw32(*src++);
819 }
820 }
821
822 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
823 {
824 memcpy(dst, src, words * 4);
825 }
826
827 static int sh_msiof_transfer_one(struct spi_master *master,
828 struct spi_device *spi,
829 struct spi_transfer *t)
830 {
831 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
832 void (*copy32)(u32 *, const u32 *, unsigned int);
833 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
834 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
835 const void *tx_buf = t->tx_buf;
836 void *rx_buf = t->rx_buf;
837 unsigned int len = t->len;
838 unsigned int bits = t->bits_per_word;
839 unsigned int bytes_per_word;
840 unsigned int words;
841 int n;
842 bool swab;
843 int ret;
844
845 /* setup clocks (clock already enabled in chipselect()) */
846 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
847
848 while (master->dma_tx && len > 15) {
849 /*
850 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
851 * words, with byte resp. word swapping.
852 */
853 unsigned int l = min(len, MAX_WDLEN * 4);
854
855 if (bits <= 8) {
856 if (l & 3)
857 break;
858 copy32 = copy_bswap32;
859 } else if (bits <= 16) {
860 if (l & 1)
861 break;
862 copy32 = copy_wswap32;
863 } else {
864 copy32 = copy_plain32;
865 }
866
867 if (tx_buf)
868 copy32(p->tx_dma_page, tx_buf, l / 4);
869
870 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
871 if (ret == -EAGAIN) {
872 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
873 dev_driver_string(&p->pdev->dev),
874 dev_name(&p->pdev->dev));
875 break;
876 }
877 if (ret)
878 return ret;
879
880 if (rx_buf) {
881 copy32(rx_buf, p->rx_dma_page, l / 4);
882 rx_buf += l;
883 }
884 if (tx_buf)
885 tx_buf += l;
886
887 len -= l;
888 if (!len)
889 return 0;
890 }
891
892 if (bits <= 8 && len > 15 && !(len & 3)) {
893 bits = 32;
894 swab = true;
895 } else {
896 swab = false;
897 }
898
899 /* setup bytes per word and fifo read/write functions */
900 if (bits <= 8) {
901 bytes_per_word = 1;
902 tx_fifo = sh_msiof_spi_write_fifo_8;
903 rx_fifo = sh_msiof_spi_read_fifo_8;
904 } else if (bits <= 16) {
905 bytes_per_word = 2;
906 if ((unsigned long)tx_buf & 0x01)
907 tx_fifo = sh_msiof_spi_write_fifo_16u;
908 else
909 tx_fifo = sh_msiof_spi_write_fifo_16;
910
911 if ((unsigned long)rx_buf & 0x01)
912 rx_fifo = sh_msiof_spi_read_fifo_16u;
913 else
914 rx_fifo = sh_msiof_spi_read_fifo_16;
915 } else if (swab) {
916 bytes_per_word = 4;
917 if ((unsigned long)tx_buf & 0x03)
918 tx_fifo = sh_msiof_spi_write_fifo_s32u;
919 else
920 tx_fifo = sh_msiof_spi_write_fifo_s32;
921
922 if ((unsigned long)rx_buf & 0x03)
923 rx_fifo = sh_msiof_spi_read_fifo_s32u;
924 else
925 rx_fifo = sh_msiof_spi_read_fifo_s32;
926 } else {
927 bytes_per_word = 4;
928 if ((unsigned long)tx_buf & 0x03)
929 tx_fifo = sh_msiof_spi_write_fifo_32u;
930 else
931 tx_fifo = sh_msiof_spi_write_fifo_32;
932
933 if ((unsigned long)rx_buf & 0x03)
934 rx_fifo = sh_msiof_spi_read_fifo_32u;
935 else
936 rx_fifo = sh_msiof_spi_read_fifo_32;
937 }
938
939 /* transfer in fifo sized chunks */
940 words = len / bytes_per_word;
941
942 while (words > 0) {
943 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
944 words, bits);
945 if (n < 0)
946 return n;
947
948 if (tx_buf)
949 tx_buf += n * bytes_per_word;
950 if (rx_buf)
951 rx_buf += n * bytes_per_word;
952 words -= n;
953 }
954
955 return 0;
956 }
957
958 static const struct sh_msiof_chipdata sh_data = {
959 .tx_fifo_size = 64,
960 .rx_fifo_size = 64,
961 .master_flags = 0,
962 };
963
964 static const struct sh_msiof_chipdata r8a779x_data = {
965 .tx_fifo_size = 64,
966 .rx_fifo_size = 256,
967 .master_flags = SPI_MASTER_MUST_TX,
968 };
969
970 static const struct of_device_id sh_msiof_match[] = {
971 { .compatible = "renesas,sh-msiof", .data = &sh_data },
972 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
973 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
974 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
975 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data },
976 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data },
977 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data },
978 {},
979 };
980 MODULE_DEVICE_TABLE(of, sh_msiof_match);
981
982 #ifdef CONFIG_OF
983 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
984 {
985 struct sh_msiof_spi_info *info;
986 struct device_node *np = dev->of_node;
987 u32 num_cs = 1;
988
989 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
990 if (!info)
991 return NULL;
992
993 /* Parse the MSIOF properties */
994 of_property_read_u32(np, "num-cs", &num_cs);
995 of_property_read_u32(np, "renesas,tx-fifo-size",
996 &info->tx_fifo_override);
997 of_property_read_u32(np, "renesas,rx-fifo-size",
998 &info->rx_fifo_override);
999 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1000 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1001
1002 info->num_chipselect = num_cs;
1003
1004 return info;
1005 }
1006 #else
1007 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1008 {
1009 return NULL;
1010 }
1011 #endif
1012
1013 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1014 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1015 {
1016 dma_cap_mask_t mask;
1017 struct dma_chan *chan;
1018 struct dma_slave_config cfg;
1019 int ret;
1020
1021 dma_cap_zero(mask);
1022 dma_cap_set(DMA_SLAVE, mask);
1023
1024 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1025 (void *)(unsigned long)id, dev,
1026 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1027 if (!chan) {
1028 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1029 return NULL;
1030 }
1031
1032 memset(&cfg, 0, sizeof(cfg));
1033 cfg.direction = dir;
1034 if (dir == DMA_MEM_TO_DEV) {
1035 cfg.dst_addr = port_addr;
1036 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1037 } else {
1038 cfg.src_addr = port_addr;
1039 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1040 }
1041
1042 ret = dmaengine_slave_config(chan, &cfg);
1043 if (ret) {
1044 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1045 dma_release_channel(chan);
1046 return NULL;
1047 }
1048
1049 return chan;
1050 }
1051
1052 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1053 {
1054 struct platform_device *pdev = p->pdev;
1055 struct device *dev = &pdev->dev;
1056 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1057 unsigned int dma_tx_id, dma_rx_id;
1058 const struct resource *res;
1059 struct spi_master *master;
1060 struct device *tx_dev, *rx_dev;
1061
1062 if (dev->of_node) {
1063 /* In the OF case we will get the slave IDs from the DT */
1064 dma_tx_id = 0;
1065 dma_rx_id = 0;
1066 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1067 dma_tx_id = info->dma_tx_id;
1068 dma_rx_id = info->dma_rx_id;
1069 } else {
1070 /* The driver assumes no error */
1071 return 0;
1072 }
1073
1074 /* The DMA engine uses the second register set, if present */
1075 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1076 if (!res)
1077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1078
1079 master = p->master;
1080 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1081 dma_tx_id,
1082 res->start + TFDR);
1083 if (!master->dma_tx)
1084 return -ENODEV;
1085
1086 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1087 dma_rx_id,
1088 res->start + RFDR);
1089 if (!master->dma_rx)
1090 goto free_tx_chan;
1091
1092 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1093 if (!p->tx_dma_page)
1094 goto free_rx_chan;
1095
1096 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1097 if (!p->rx_dma_page)
1098 goto free_tx_page;
1099
1100 tx_dev = master->dma_tx->device->dev;
1101 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1102 DMA_TO_DEVICE);
1103 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1104 goto free_rx_page;
1105
1106 rx_dev = master->dma_rx->device->dev;
1107 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1108 DMA_FROM_DEVICE);
1109 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1110 goto unmap_tx_page;
1111
1112 dev_info(dev, "DMA available");
1113 return 0;
1114
1115 unmap_tx_page:
1116 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1117 free_rx_page:
1118 free_page((unsigned long)p->rx_dma_page);
1119 free_tx_page:
1120 free_page((unsigned long)p->tx_dma_page);
1121 free_rx_chan:
1122 dma_release_channel(master->dma_rx);
1123 free_tx_chan:
1124 dma_release_channel(master->dma_tx);
1125 master->dma_tx = NULL;
1126 return -ENODEV;
1127 }
1128
1129 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1130 {
1131 struct spi_master *master = p->master;
1132 struct device *dev;
1133
1134 if (!master->dma_tx)
1135 return;
1136
1137 dev = &p->pdev->dev;
1138 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1139 PAGE_SIZE, DMA_FROM_DEVICE);
1140 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1141 PAGE_SIZE, DMA_TO_DEVICE);
1142 free_page((unsigned long)p->rx_dma_page);
1143 free_page((unsigned long)p->tx_dma_page);
1144 dma_release_channel(master->dma_rx);
1145 dma_release_channel(master->dma_tx);
1146 }
1147
1148 static int sh_msiof_spi_probe(struct platform_device *pdev)
1149 {
1150 struct resource *r;
1151 struct spi_master *master;
1152 const struct of_device_id *of_id;
1153 struct sh_msiof_spi_priv *p;
1154 int i;
1155 int ret;
1156
1157 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1158 if (master == NULL) {
1159 dev_err(&pdev->dev, "failed to allocate spi master\n");
1160 return -ENOMEM;
1161 }
1162
1163 p = spi_master_get_devdata(master);
1164
1165 platform_set_drvdata(pdev, p);
1166 p->master = master;
1167
1168 of_id = of_match_device(sh_msiof_match, &pdev->dev);
1169 if (of_id) {
1170 p->chipdata = of_id->data;
1171 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
1172 } else {
1173 p->chipdata = (const void *)pdev->id_entry->driver_data;
1174 p->info = dev_get_platdata(&pdev->dev);
1175 }
1176
1177 if (!p->info) {
1178 dev_err(&pdev->dev, "failed to obtain device info\n");
1179 ret = -ENXIO;
1180 goto err1;
1181 }
1182
1183 init_completion(&p->done);
1184
1185 p->clk = devm_clk_get(&pdev->dev, NULL);
1186 if (IS_ERR(p->clk)) {
1187 dev_err(&pdev->dev, "cannot get clock\n");
1188 ret = PTR_ERR(p->clk);
1189 goto err1;
1190 }
1191
1192 i = platform_get_irq(pdev, 0);
1193 if (i < 0) {
1194 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1195 ret = -ENOENT;
1196 goto err1;
1197 }
1198
1199 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1201 if (IS_ERR(p->mapbase)) {
1202 ret = PTR_ERR(p->mapbase);
1203 goto err1;
1204 }
1205
1206 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1207 dev_name(&pdev->dev), p);
1208 if (ret) {
1209 dev_err(&pdev->dev, "unable to request irq\n");
1210 goto err1;
1211 }
1212
1213 p->pdev = pdev;
1214 pm_runtime_enable(&pdev->dev);
1215
1216 /* Platform data may override FIFO sizes */
1217 p->tx_fifo_size = p->chipdata->tx_fifo_size;
1218 p->rx_fifo_size = p->chipdata->rx_fifo_size;
1219 if (p->info->tx_fifo_override)
1220 p->tx_fifo_size = p->info->tx_fifo_override;
1221 if (p->info->rx_fifo_override)
1222 p->rx_fifo_size = p->info->rx_fifo_override;
1223
1224 /* init master code */
1225 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1226 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1227 master->flags = p->chipdata->master_flags;
1228 master->bus_num = pdev->id;
1229 master->dev.of_node = pdev->dev.of_node;
1230 master->num_chipselect = p->info->num_chipselect;
1231 master->setup = sh_msiof_spi_setup;
1232 master->prepare_message = sh_msiof_prepare_message;
1233 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1234 master->auto_runtime_pm = true;
1235 master->transfer_one = sh_msiof_transfer_one;
1236
1237 ret = sh_msiof_request_dma(p);
1238 if (ret < 0)
1239 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1240
1241 ret = devm_spi_register_master(&pdev->dev, master);
1242 if (ret < 0) {
1243 dev_err(&pdev->dev, "spi_register_master error.\n");
1244 goto err2;
1245 }
1246
1247 return 0;
1248
1249 err2:
1250 sh_msiof_release_dma(p);
1251 pm_runtime_disable(&pdev->dev);
1252 err1:
1253 spi_master_put(master);
1254 return ret;
1255 }
1256
1257 static int sh_msiof_spi_remove(struct platform_device *pdev)
1258 {
1259 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1260
1261 sh_msiof_release_dma(p);
1262 pm_runtime_disable(&pdev->dev);
1263 return 0;
1264 }
1265
1266 static struct platform_device_id spi_driver_ids[] = {
1267 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1268 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
1269 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
1270 { "spi_r8a7792_msiof", (kernel_ulong_t)&r8a779x_data },
1271 { "spi_r8a7793_msiof", (kernel_ulong_t)&r8a779x_data },
1272 { "spi_r8a7794_msiof", (kernel_ulong_t)&r8a779x_data },
1273 {},
1274 };
1275 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1276
1277 static struct platform_driver sh_msiof_spi_drv = {
1278 .probe = sh_msiof_spi_probe,
1279 .remove = sh_msiof_spi_remove,
1280 .id_table = spi_driver_ids,
1281 .driver = {
1282 .name = "spi_sh_msiof",
1283 .of_match_table = of_match_ptr(sh_msiof_match),
1284 },
1285 };
1286 module_platform_driver(sh_msiof_spi_drv);
1287
1288 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1289 MODULE_AUTHOR("Magnus Damm");
1290 MODULE_LICENSE("GPL v2");
1291 MODULE_ALIAS("platform:spi_sh_msiof");
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