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[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-sh-msiof.c
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/sh_dma.h>
31
32 #include <linux/spi/sh_msiof.h>
33 #include <linux/spi/spi.h>
34
35 #include <asm/unaligned.h>
36
37 struct sh_msiof_chipdata {
38 u16 tx_fifo_size;
39 u16 rx_fifo_size;
40 u16 master_flags;
41 u16 min_div;
42 };
43
44 struct sh_msiof_spi_priv {
45 struct spi_master *master;
46 void __iomem *mapbase;
47 struct clk *clk;
48 struct platform_device *pdev;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 unsigned int tx_fifo_size;
52 unsigned int rx_fifo_size;
53 unsigned int min_div;
54 void *tx_dma_page;
55 void *rx_dma_page;
56 dma_addr_t tx_dma_addr;
57 dma_addr_t rx_dma_addr;
58 bool native_cs_inited;
59 bool native_cs_high;
60 bool slave_aborted;
61 };
62
63 #define TMDR1 0x00 /* Transmit Mode Register 1 */
64 #define TMDR2 0x04 /* Transmit Mode Register 2 */
65 #define TMDR3 0x08 /* Transmit Mode Register 3 */
66 #define RMDR1 0x10 /* Receive Mode Register 1 */
67 #define RMDR2 0x14 /* Receive Mode Register 2 */
68 #define RMDR3 0x18 /* Receive Mode Register 3 */
69 #define TSCR 0x20 /* Transmit Clock Select Register */
70 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
71 #define CTR 0x28 /* Control Register */
72 #define FCTR 0x30 /* FIFO Control Register */
73 #define STR 0x40 /* Status Register */
74 #define IER 0x44 /* Interrupt Enable Register */
75 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
76 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
77 #define TFDR 0x50 /* Transmit FIFO Data Register */
78 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
79 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
80 #define RFDR 0x60 /* Receive FIFO Data Register */
81
82 /* TMDR1 and RMDR1 */
83 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
84 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
85 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
86 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
87 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
88 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
89 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
90 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
91 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
92 #define MDR1_FLD_SHIFT 2
93 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
94 /* TMDR1 */
95 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
96
97 /* TMDR2 and RMDR2 */
98 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
99 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
100 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
101
102 /* TSCR and RSCR */
103 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
104 #define SCR_BRPS(i) (((i) - 1) << 8)
105 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
106 #define SCR_BRDV_DIV_2 0x0000
107 #define SCR_BRDV_DIV_4 0x0001
108 #define SCR_BRDV_DIV_8 0x0002
109 #define SCR_BRDV_DIV_16 0x0003
110 #define SCR_BRDV_DIV_32 0x0004
111 #define SCR_BRDV_DIV_1 0x0007
112
113 /* CTR */
114 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
115 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
116 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
117 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
118 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
119 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
120 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
121 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
122 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
123 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
124 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
125 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
126 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
127 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
128 #define CTR_TXE 0x00000200 /* Transmit Enable */
129 #define CTR_RXE 0x00000100 /* Receive Enable */
130
131 /* FCTR */
132 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
133 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
134 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
135 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
136 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
137 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
138 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
139 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
140 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
141 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
142 #define FCTR_TFUA_SHIFT 20
143 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
144 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
145 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
146 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
147 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
148 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
149 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
150 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
151 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
152 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
153 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
154 #define FCTR_RFUA_SHIFT 4
155 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
156
157 /* STR */
158 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
159 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
160 #define STR_TEOF 0x00800000 /* Frame Transmission End */
161 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
162 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
163 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
164 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
165 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
166 #define STR_REOF 0x00000080 /* Frame Reception End */
167 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
168 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
169 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
170
171 /* IER */
172 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
173 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
174 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
175 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
176 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
177 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
178 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
179 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
180 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
181 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
182 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
183 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
184 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
185 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
186
187
188 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
189 {
190 switch (reg_offs) {
191 case TSCR:
192 case RSCR:
193 return ioread16(p->mapbase + reg_offs);
194 default:
195 return ioread32(p->mapbase + reg_offs);
196 }
197 }
198
199 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
200 u32 value)
201 {
202 switch (reg_offs) {
203 case TSCR:
204 case RSCR:
205 iowrite16(value, p->mapbase + reg_offs);
206 break;
207 default:
208 iowrite32(value, p->mapbase + reg_offs);
209 break;
210 }
211 }
212
213 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
214 u32 clr, u32 set)
215 {
216 u32 mask = clr | set;
217 u32 data;
218 int k;
219
220 data = sh_msiof_read(p, CTR);
221 data &= ~clr;
222 data |= set;
223 sh_msiof_write(p, CTR, data);
224
225 for (k = 100; k > 0; k--) {
226 if ((sh_msiof_read(p, CTR) & mask) == set)
227 break;
228
229 udelay(10);
230 }
231
232 return k > 0 ? 0 : -ETIMEDOUT;
233 }
234
235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
236 {
237 struct sh_msiof_spi_priv *p = data;
238
239 /* just disable the interrupt and wake up */
240 sh_msiof_write(p, IER, 0);
241 complete(&p->done);
242
243 return IRQ_HANDLED;
244 }
245
246 static struct {
247 unsigned short div;
248 unsigned short brdv;
249 } const sh_msiof_spi_div_table[] = {
250 { 1, SCR_BRDV_DIV_1 },
251 { 2, SCR_BRDV_DIV_2 },
252 { 4, SCR_BRDV_DIV_4 },
253 { 8, SCR_BRDV_DIV_8 },
254 { 16, SCR_BRDV_DIV_16 },
255 { 32, SCR_BRDV_DIV_32 },
256 };
257
258 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
259 unsigned long parent_rate, u32 spi_hz)
260 {
261 unsigned long div = 1024;
262 u32 brps, scr;
263 size_t k;
264
265 if (!WARN_ON(!spi_hz || !parent_rate))
266 div = DIV_ROUND_UP(parent_rate, spi_hz);
267
268 div = max_t(unsigned long, div, p->min_div);
269
270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
271 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
272 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
273 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
274 continue;
275 if (brps <= 32) /* max of brdv is 32 */
276 break;
277 }
278
279 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
280 brps = min_t(int, brps, 32);
281
282 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
283 sh_msiof_write(p, TSCR, scr);
284 if (!(p->master->flags & SPI_MASTER_MUST_TX))
285 sh_msiof_write(p, RSCR, scr);
286 }
287
288 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
289 {
290 /*
291 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
292 * b'000 : 0
293 * b'001 : 100
294 * b'010 : 200
295 * b'011 (SYNCDL only) : 300
296 * b'101 : 50
297 * b'110 : 150
298 */
299 if (dtdl_or_syncdl % 100)
300 return dtdl_or_syncdl / 100 + 5;
301 else
302 return dtdl_or_syncdl / 100;
303 }
304
305 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
306 {
307 u32 val;
308
309 if (!p->info)
310 return 0;
311
312 /* check if DTDL and SYNCDL is allowed value */
313 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
314 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
315 return 0;
316 }
317
318 /* check if the sum of DTDL and SYNCDL becomes an integer value */
319 if ((p->info->dtdl + p->info->syncdl) % 100) {
320 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
321 return 0;
322 }
323
324 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
325 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
326
327 return val;
328 }
329
330 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
331 u32 cpol, u32 cpha,
332 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
333 {
334 u32 tmp;
335 int edge;
336
337 /*
338 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
339 * 0 0 10 10 1 1
340 * 0 1 10 10 0 0
341 * 1 0 11 11 0 0
342 * 1 1 11 11 1 1
343 */
344 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
345 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
346 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
347 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
348 if (spi_controller_is_slave(p->master))
349 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
350 else
351 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
352 if (p->master->flags & SPI_MASTER_MUST_TX) {
353 /* These bits are reserved if RX needs TX */
354 tmp &= ~0x0000ffff;
355 }
356 sh_msiof_write(p, RMDR1, tmp);
357
358 tmp = 0;
359 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
360 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
361
362 edge = cpol ^ !cpha;
363
364 tmp |= edge << CTR_TEDG_SHIFT;
365 tmp |= edge << CTR_REDG_SHIFT;
366 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
367 sh_msiof_write(p, CTR, tmp);
368 }
369
370 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
371 const void *tx_buf, void *rx_buf,
372 u32 bits, u32 words)
373 {
374 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
375
376 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
377 sh_msiof_write(p, TMDR2, dr2);
378 else
379 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
380
381 if (rx_buf)
382 sh_msiof_write(p, RMDR2, dr2);
383 }
384
385 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
386 {
387 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
388 }
389
390 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
391 const void *tx_buf, int words, int fs)
392 {
393 const u8 *buf_8 = tx_buf;
394 int k;
395
396 for (k = 0; k < words; k++)
397 sh_msiof_write(p, TFDR, buf_8[k] << fs);
398 }
399
400 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
401 const void *tx_buf, int words, int fs)
402 {
403 const u16 *buf_16 = tx_buf;
404 int k;
405
406 for (k = 0; k < words; k++)
407 sh_msiof_write(p, TFDR, buf_16[k] << fs);
408 }
409
410 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
412 {
413 const u16 *buf_16 = tx_buf;
414 int k;
415
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
418 }
419
420 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
422 {
423 const u32 *buf_32 = tx_buf;
424 int k;
425
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, TFDR, buf_32[k] << fs);
428 }
429
430 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
432 {
433 const u32 *buf_32 = tx_buf;
434 int k;
435
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
438 }
439
440 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
442 {
443 const u32 *buf_32 = tx_buf;
444 int k;
445
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
448 }
449
450 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
451 const void *tx_buf, int words, int fs)
452 {
453 const u32 *buf_32 = tx_buf;
454 int k;
455
456 for (k = 0; k < words; k++)
457 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
458 }
459
460 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
461 void *rx_buf, int words, int fs)
462 {
463 u8 *buf_8 = rx_buf;
464 int k;
465
466 for (k = 0; k < words; k++)
467 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
468 }
469
470 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
471 void *rx_buf, int words, int fs)
472 {
473 u16 *buf_16 = rx_buf;
474 int k;
475
476 for (k = 0; k < words; k++)
477 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
478 }
479
480 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
482 {
483 u16 *buf_16 = rx_buf;
484 int k;
485
486 for (k = 0; k < words; k++)
487 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
488 }
489
490 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
492 {
493 u32 *buf_32 = rx_buf;
494 int k;
495
496 for (k = 0; k < words; k++)
497 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
498 }
499
500 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
502 {
503 u32 *buf_32 = rx_buf;
504 int k;
505
506 for (k = 0; k < words; k++)
507 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
508 }
509
510 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
512 {
513 u32 *buf_32 = rx_buf;
514 int k;
515
516 for (k = 0; k < words; k++)
517 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
518 }
519
520 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
521 void *rx_buf, int words, int fs)
522 {
523 u32 *buf_32 = rx_buf;
524 int k;
525
526 for (k = 0; k < words; k++)
527 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
528 }
529
530 static int sh_msiof_spi_setup(struct spi_device *spi)
531 {
532 struct device_node *np = spi->master->dev.of_node;
533 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
534 u32 clr, set, tmp;
535
536 if (!np) {
537 /*
538 * Use spi->controller_data for CS (same strategy as spi_gpio),
539 * if any. otherwise let HW control CS
540 */
541 spi->cs_gpio = (uintptr_t)spi->controller_data;
542 }
543
544 if (spi->cs_gpio >= 0) {
545 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
546 return 0;
547 }
548
549 if (spi_controller_is_slave(p->master))
550 return 0;
551
552 if (p->native_cs_inited &&
553 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
554 return 0;
555
556 /* Configure native chip select mode/polarity early */
557 clr = MDR1_SYNCMD_MASK;
558 set = MDR1_SYNCMD_SPI;
559 if (spi->mode & SPI_CS_HIGH)
560 clr |= BIT(MDR1_SYNCAC_SHIFT);
561 else
562 set |= BIT(MDR1_SYNCAC_SHIFT);
563 pm_runtime_get_sync(&p->pdev->dev);
564 tmp = sh_msiof_read(p, TMDR1) & ~clr;
565 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
566 tmp = sh_msiof_read(p, RMDR1) & ~clr;
567 sh_msiof_write(p, RMDR1, tmp | set);
568 pm_runtime_put(&p->pdev->dev);
569 p->native_cs_high = spi->mode & SPI_CS_HIGH;
570 p->native_cs_inited = true;
571 return 0;
572 }
573
574 static int sh_msiof_prepare_message(struct spi_master *master,
575 struct spi_message *msg)
576 {
577 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
578 const struct spi_device *spi = msg->spi;
579
580 /* Configure pins before asserting CS */
581 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
582 !!(spi->mode & SPI_CPHA),
583 !!(spi->mode & SPI_3WIRE),
584 !!(spi->mode & SPI_LSB_FIRST),
585 !!(spi->mode & SPI_CS_HIGH));
586 return 0;
587 }
588
589 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
590 {
591 bool slave = spi_controller_is_slave(p->master);
592 int ret = 0;
593
594 /* setup clock and rx/tx signals */
595 if (!slave)
596 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
597 if (rx_buf && !ret)
598 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
599 if (!ret)
600 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
601
602 /* start by setting frame bit */
603 if (!ret && !slave)
604 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
605
606 return ret;
607 }
608
609 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
610 {
611 bool slave = spi_controller_is_slave(p->master);
612 int ret = 0;
613
614 /* shut down frame, rx/tx and clock signals */
615 if (!slave)
616 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
617 if (!ret)
618 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
619 if (rx_buf && !ret)
620 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
621 if (!ret && !slave)
622 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
623
624 return ret;
625 }
626
627 static int sh_msiof_slave_abort(struct spi_master *master)
628 {
629 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
630
631 p->slave_aborted = true;
632 complete(&p->done);
633 return 0;
634 }
635
636 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p)
637 {
638 if (spi_controller_is_slave(p->master)) {
639 if (wait_for_completion_interruptible(&p->done) ||
640 p->slave_aborted) {
641 dev_dbg(&p->pdev->dev, "interrupted\n");
642 return -EINTR;
643 }
644 } else {
645 if (!wait_for_completion_timeout(&p->done, HZ)) {
646 dev_err(&p->pdev->dev, "timeout\n");
647 return -ETIMEDOUT;
648 }
649 }
650
651 return 0;
652 }
653
654 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
655 void (*tx_fifo)(struct sh_msiof_spi_priv *,
656 const void *, int, int),
657 void (*rx_fifo)(struct sh_msiof_spi_priv *,
658 void *, int, int),
659 const void *tx_buf, void *rx_buf,
660 int words, int bits)
661 {
662 int fifo_shift;
663 int ret;
664
665 /* limit maximum word transfer to rx/tx fifo size */
666 if (tx_buf)
667 words = min_t(int, words, p->tx_fifo_size);
668 if (rx_buf)
669 words = min_t(int, words, p->rx_fifo_size);
670
671 /* the fifo contents need shifting */
672 fifo_shift = 32 - bits;
673
674 /* default FIFO watermarks for PIO */
675 sh_msiof_write(p, FCTR, 0);
676
677 /* setup msiof transfer mode registers */
678 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
679 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
680
681 /* write tx fifo */
682 if (tx_buf)
683 tx_fifo(p, tx_buf, words, fifo_shift);
684
685 reinit_completion(&p->done);
686 p->slave_aborted = false;
687
688 ret = sh_msiof_spi_start(p, rx_buf);
689 if (ret) {
690 dev_err(&p->pdev->dev, "failed to start hardware\n");
691 goto stop_ier;
692 }
693
694 /* wait for tx fifo to be emptied / rx fifo to be filled */
695 ret = sh_msiof_wait_for_completion(p);
696 if (ret)
697 goto stop_reset;
698
699 /* read rx fifo */
700 if (rx_buf)
701 rx_fifo(p, rx_buf, words, fifo_shift);
702
703 /* clear status bits */
704 sh_msiof_reset_str(p);
705
706 ret = sh_msiof_spi_stop(p, rx_buf);
707 if (ret) {
708 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
709 return ret;
710 }
711
712 return words;
713
714 stop_reset:
715 sh_msiof_reset_str(p);
716 sh_msiof_spi_stop(p, rx_buf);
717 stop_ier:
718 sh_msiof_write(p, IER, 0);
719 return ret;
720 }
721
722 static void sh_msiof_dma_complete(void *arg)
723 {
724 struct sh_msiof_spi_priv *p = arg;
725
726 sh_msiof_write(p, IER, 0);
727 complete(&p->done);
728 }
729
730 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
731 void *rx, unsigned int len)
732 {
733 u32 ier_bits = 0;
734 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
735 dma_cookie_t cookie;
736 int ret;
737
738 /* First prepare and submit the DMA request(s), as this may fail */
739 if (rx) {
740 ier_bits |= IER_RDREQE | IER_RDMAE;
741 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
742 p->rx_dma_addr, len, DMA_FROM_DEVICE,
743 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
744 if (!desc_rx)
745 return -EAGAIN;
746
747 desc_rx->callback = sh_msiof_dma_complete;
748 desc_rx->callback_param = p;
749 cookie = dmaengine_submit(desc_rx);
750 if (dma_submit_error(cookie))
751 return cookie;
752 }
753
754 if (tx) {
755 ier_bits |= IER_TDREQE | IER_TDMAE;
756 dma_sync_single_for_device(p->master->dma_tx->device->dev,
757 p->tx_dma_addr, len, DMA_TO_DEVICE);
758 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
759 p->tx_dma_addr, len, DMA_TO_DEVICE,
760 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
761 if (!desc_tx) {
762 ret = -EAGAIN;
763 goto no_dma_tx;
764 }
765
766 if (rx) {
767 /* No callback */
768 desc_tx->callback = NULL;
769 } else {
770 desc_tx->callback = sh_msiof_dma_complete;
771 desc_tx->callback_param = p;
772 }
773 cookie = dmaengine_submit(desc_tx);
774 if (dma_submit_error(cookie)) {
775 ret = cookie;
776 goto no_dma_tx;
777 }
778 }
779
780 /* 1 stage FIFO watermarks for DMA */
781 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
782
783 /* setup msiof transfer mode registers (32-bit words) */
784 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
785
786 sh_msiof_write(p, IER, ier_bits);
787
788 reinit_completion(&p->done);
789 p->slave_aborted = false;
790
791 /* Now start DMA */
792 if (rx)
793 dma_async_issue_pending(p->master->dma_rx);
794 if (tx)
795 dma_async_issue_pending(p->master->dma_tx);
796
797 ret = sh_msiof_spi_start(p, rx);
798 if (ret) {
799 dev_err(&p->pdev->dev, "failed to start hardware\n");
800 goto stop_dma;
801 }
802
803 /* wait for tx/rx DMA completion */
804 ret = sh_msiof_wait_for_completion(p);
805 if (ret)
806 goto stop_reset;
807
808 if (!rx) {
809 reinit_completion(&p->done);
810 sh_msiof_write(p, IER, IER_TEOFE);
811
812 /* wait for tx fifo to be emptied */
813 ret = sh_msiof_wait_for_completion(p);
814 if (ret)
815 goto stop_reset;
816 }
817
818 /* clear status bits */
819 sh_msiof_reset_str(p);
820
821 ret = sh_msiof_spi_stop(p, rx);
822 if (ret) {
823 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
824 return ret;
825 }
826
827 if (rx)
828 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
829 p->rx_dma_addr, len,
830 DMA_FROM_DEVICE);
831
832 return 0;
833
834 stop_reset:
835 sh_msiof_reset_str(p);
836 sh_msiof_spi_stop(p, rx);
837 stop_dma:
838 if (tx)
839 dmaengine_terminate_all(p->master->dma_tx);
840 no_dma_tx:
841 if (rx)
842 dmaengine_terminate_all(p->master->dma_rx);
843 sh_msiof_write(p, IER, 0);
844 return ret;
845 }
846
847 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
848 {
849 /* src or dst can be unaligned, but not both */
850 if ((unsigned long)src & 3) {
851 while (words--) {
852 *dst++ = swab32(get_unaligned(src));
853 src++;
854 }
855 } else if ((unsigned long)dst & 3) {
856 while (words--) {
857 put_unaligned(swab32(*src++), dst);
858 dst++;
859 }
860 } else {
861 while (words--)
862 *dst++ = swab32(*src++);
863 }
864 }
865
866 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
867 {
868 /* src or dst can be unaligned, but not both */
869 if ((unsigned long)src & 3) {
870 while (words--) {
871 *dst++ = swahw32(get_unaligned(src));
872 src++;
873 }
874 } else if ((unsigned long)dst & 3) {
875 while (words--) {
876 put_unaligned(swahw32(*src++), dst);
877 dst++;
878 }
879 } else {
880 while (words--)
881 *dst++ = swahw32(*src++);
882 }
883 }
884
885 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
886 {
887 memcpy(dst, src, words * 4);
888 }
889
890 static int sh_msiof_transfer_one(struct spi_master *master,
891 struct spi_device *spi,
892 struct spi_transfer *t)
893 {
894 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
895 void (*copy32)(u32 *, const u32 *, unsigned int);
896 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
897 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
898 const void *tx_buf = t->tx_buf;
899 void *rx_buf = t->rx_buf;
900 unsigned int len = t->len;
901 unsigned int bits = t->bits_per_word;
902 unsigned int bytes_per_word;
903 unsigned int words;
904 int n;
905 bool swab;
906 int ret;
907
908 /* setup clocks (clock already enabled in chipselect()) */
909 if (!spi_controller_is_slave(p->master))
910 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
911
912 while (master->dma_tx && len > 15) {
913 /*
914 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
915 * words, with byte resp. word swapping.
916 */
917 unsigned int l = 0;
918
919 if (tx_buf)
920 l = min(len, p->tx_fifo_size * 4);
921 if (rx_buf)
922 l = min(len, p->rx_fifo_size * 4);
923
924 if (bits <= 8) {
925 if (l & 3)
926 break;
927 copy32 = copy_bswap32;
928 } else if (bits <= 16) {
929 if (l & 3)
930 break;
931 copy32 = copy_wswap32;
932 } else {
933 copy32 = copy_plain32;
934 }
935
936 if (tx_buf)
937 copy32(p->tx_dma_page, tx_buf, l / 4);
938
939 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
940 if (ret == -EAGAIN) {
941 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
942 dev_driver_string(&p->pdev->dev),
943 dev_name(&p->pdev->dev));
944 break;
945 }
946 if (ret)
947 return ret;
948
949 if (rx_buf) {
950 copy32(rx_buf, p->rx_dma_page, l / 4);
951 rx_buf += l;
952 }
953 if (tx_buf)
954 tx_buf += l;
955
956 len -= l;
957 if (!len)
958 return 0;
959 }
960
961 if (bits <= 8 && len > 15 && !(len & 3)) {
962 bits = 32;
963 swab = true;
964 } else {
965 swab = false;
966 }
967
968 /* setup bytes per word and fifo read/write functions */
969 if (bits <= 8) {
970 bytes_per_word = 1;
971 tx_fifo = sh_msiof_spi_write_fifo_8;
972 rx_fifo = sh_msiof_spi_read_fifo_8;
973 } else if (bits <= 16) {
974 bytes_per_word = 2;
975 if ((unsigned long)tx_buf & 0x01)
976 tx_fifo = sh_msiof_spi_write_fifo_16u;
977 else
978 tx_fifo = sh_msiof_spi_write_fifo_16;
979
980 if ((unsigned long)rx_buf & 0x01)
981 rx_fifo = sh_msiof_spi_read_fifo_16u;
982 else
983 rx_fifo = sh_msiof_spi_read_fifo_16;
984 } else if (swab) {
985 bytes_per_word = 4;
986 if ((unsigned long)tx_buf & 0x03)
987 tx_fifo = sh_msiof_spi_write_fifo_s32u;
988 else
989 tx_fifo = sh_msiof_spi_write_fifo_s32;
990
991 if ((unsigned long)rx_buf & 0x03)
992 rx_fifo = sh_msiof_spi_read_fifo_s32u;
993 else
994 rx_fifo = sh_msiof_spi_read_fifo_s32;
995 } else {
996 bytes_per_word = 4;
997 if ((unsigned long)tx_buf & 0x03)
998 tx_fifo = sh_msiof_spi_write_fifo_32u;
999 else
1000 tx_fifo = sh_msiof_spi_write_fifo_32;
1001
1002 if ((unsigned long)rx_buf & 0x03)
1003 rx_fifo = sh_msiof_spi_read_fifo_32u;
1004 else
1005 rx_fifo = sh_msiof_spi_read_fifo_32;
1006 }
1007
1008 /* transfer in fifo sized chunks */
1009 words = len / bytes_per_word;
1010
1011 while (words > 0) {
1012 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1013 words, bits);
1014 if (n < 0)
1015 return n;
1016
1017 if (tx_buf)
1018 tx_buf += n * bytes_per_word;
1019 if (rx_buf)
1020 rx_buf += n * bytes_per_word;
1021 words -= n;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static const struct sh_msiof_chipdata sh_data = {
1028 .tx_fifo_size = 64,
1029 .rx_fifo_size = 64,
1030 .master_flags = 0,
1031 .min_div = 1,
1032 };
1033
1034 static const struct sh_msiof_chipdata rcar_gen2_data = {
1035 .tx_fifo_size = 64,
1036 .rx_fifo_size = 64,
1037 .master_flags = SPI_MASTER_MUST_TX,
1038 .min_div = 1,
1039 };
1040
1041 static const struct sh_msiof_chipdata rcar_gen3_data = {
1042 .tx_fifo_size = 64,
1043 .rx_fifo_size = 64,
1044 .master_flags = SPI_MASTER_MUST_TX,
1045 .min_div = 2,
1046 };
1047
1048 static const struct of_device_id sh_msiof_match[] = {
1049 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1050 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1051 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1052 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1053 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1054 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1055 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1056 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1057 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1058 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1059 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1060 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1061 {},
1062 };
1063 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1064
1065 #ifdef CONFIG_OF
1066 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1067 {
1068 struct sh_msiof_spi_info *info;
1069 struct device_node *np = dev->of_node;
1070 u32 num_cs = 1;
1071
1072 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1073 if (!info)
1074 return NULL;
1075
1076 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1077 : MSIOF_SPI_MASTER;
1078
1079 /* Parse the MSIOF properties */
1080 if (info->mode == MSIOF_SPI_MASTER)
1081 of_property_read_u32(np, "num-cs", &num_cs);
1082 of_property_read_u32(np, "renesas,tx-fifo-size",
1083 &info->tx_fifo_override);
1084 of_property_read_u32(np, "renesas,rx-fifo-size",
1085 &info->rx_fifo_override);
1086 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1087 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1088
1089 info->num_chipselect = num_cs;
1090
1091 return info;
1092 }
1093 #else
1094 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1095 {
1096 return NULL;
1097 }
1098 #endif
1099
1100 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1101 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1102 {
1103 dma_cap_mask_t mask;
1104 struct dma_chan *chan;
1105 struct dma_slave_config cfg;
1106 int ret;
1107
1108 dma_cap_zero(mask);
1109 dma_cap_set(DMA_SLAVE, mask);
1110
1111 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1112 (void *)(unsigned long)id, dev,
1113 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1114 if (!chan) {
1115 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1116 return NULL;
1117 }
1118
1119 memset(&cfg, 0, sizeof(cfg));
1120 cfg.direction = dir;
1121 if (dir == DMA_MEM_TO_DEV) {
1122 cfg.dst_addr = port_addr;
1123 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1124 } else {
1125 cfg.src_addr = port_addr;
1126 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1127 }
1128
1129 ret = dmaengine_slave_config(chan, &cfg);
1130 if (ret) {
1131 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1132 dma_release_channel(chan);
1133 return NULL;
1134 }
1135
1136 return chan;
1137 }
1138
1139 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1140 {
1141 struct platform_device *pdev = p->pdev;
1142 struct device *dev = &pdev->dev;
1143 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1144 unsigned int dma_tx_id, dma_rx_id;
1145 const struct resource *res;
1146 struct spi_master *master;
1147 struct device *tx_dev, *rx_dev;
1148
1149 if (dev->of_node) {
1150 /* In the OF case we will get the slave IDs from the DT */
1151 dma_tx_id = 0;
1152 dma_rx_id = 0;
1153 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1154 dma_tx_id = info->dma_tx_id;
1155 dma_rx_id = info->dma_rx_id;
1156 } else {
1157 /* The driver assumes no error */
1158 return 0;
1159 }
1160
1161 /* The DMA engine uses the second register set, if present */
1162 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1163 if (!res)
1164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165
1166 master = p->master;
1167 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1168 dma_tx_id,
1169 res->start + TFDR);
1170 if (!master->dma_tx)
1171 return -ENODEV;
1172
1173 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1174 dma_rx_id,
1175 res->start + RFDR);
1176 if (!master->dma_rx)
1177 goto free_tx_chan;
1178
1179 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1180 if (!p->tx_dma_page)
1181 goto free_rx_chan;
1182
1183 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1184 if (!p->rx_dma_page)
1185 goto free_tx_page;
1186
1187 tx_dev = master->dma_tx->device->dev;
1188 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1189 DMA_TO_DEVICE);
1190 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1191 goto free_rx_page;
1192
1193 rx_dev = master->dma_rx->device->dev;
1194 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1195 DMA_FROM_DEVICE);
1196 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1197 goto unmap_tx_page;
1198
1199 dev_info(dev, "DMA available");
1200 return 0;
1201
1202 unmap_tx_page:
1203 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1204 free_rx_page:
1205 free_page((unsigned long)p->rx_dma_page);
1206 free_tx_page:
1207 free_page((unsigned long)p->tx_dma_page);
1208 free_rx_chan:
1209 dma_release_channel(master->dma_rx);
1210 free_tx_chan:
1211 dma_release_channel(master->dma_tx);
1212 master->dma_tx = NULL;
1213 return -ENODEV;
1214 }
1215
1216 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1217 {
1218 struct spi_master *master = p->master;
1219
1220 if (!master->dma_tx)
1221 return;
1222
1223 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1224 PAGE_SIZE, DMA_FROM_DEVICE);
1225 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1226 PAGE_SIZE, DMA_TO_DEVICE);
1227 free_page((unsigned long)p->rx_dma_page);
1228 free_page((unsigned long)p->tx_dma_page);
1229 dma_release_channel(master->dma_rx);
1230 dma_release_channel(master->dma_tx);
1231 }
1232
1233 static int sh_msiof_spi_probe(struct platform_device *pdev)
1234 {
1235 struct resource *r;
1236 struct spi_master *master;
1237 const struct sh_msiof_chipdata *chipdata;
1238 struct sh_msiof_spi_info *info;
1239 struct sh_msiof_spi_priv *p;
1240 int i;
1241 int ret;
1242
1243 chipdata = of_device_get_match_data(&pdev->dev);
1244 if (chipdata) {
1245 info = sh_msiof_spi_parse_dt(&pdev->dev);
1246 } else {
1247 chipdata = (const void *)pdev->id_entry->driver_data;
1248 info = dev_get_platdata(&pdev->dev);
1249 }
1250
1251 if (!info) {
1252 dev_err(&pdev->dev, "failed to obtain device info\n");
1253 return -ENXIO;
1254 }
1255
1256 if (info->mode == MSIOF_SPI_SLAVE)
1257 master = spi_alloc_slave(&pdev->dev,
1258 sizeof(struct sh_msiof_spi_priv));
1259 else
1260 master = spi_alloc_master(&pdev->dev,
1261 sizeof(struct sh_msiof_spi_priv));
1262 if (master == NULL)
1263 return -ENOMEM;
1264
1265 p = spi_master_get_devdata(master);
1266
1267 platform_set_drvdata(pdev, p);
1268 p->master = master;
1269 p->info = info;
1270 p->min_div = chipdata->min_div;
1271
1272 init_completion(&p->done);
1273
1274 p->clk = devm_clk_get(&pdev->dev, NULL);
1275 if (IS_ERR(p->clk)) {
1276 dev_err(&pdev->dev, "cannot get clock\n");
1277 ret = PTR_ERR(p->clk);
1278 goto err1;
1279 }
1280
1281 i = platform_get_irq(pdev, 0);
1282 if (i < 0) {
1283 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1284 ret = -ENOENT;
1285 goto err1;
1286 }
1287
1288 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1289 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1290 if (IS_ERR(p->mapbase)) {
1291 ret = PTR_ERR(p->mapbase);
1292 goto err1;
1293 }
1294
1295 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1296 dev_name(&pdev->dev), p);
1297 if (ret) {
1298 dev_err(&pdev->dev, "unable to request irq\n");
1299 goto err1;
1300 }
1301
1302 p->pdev = pdev;
1303 pm_runtime_enable(&pdev->dev);
1304
1305 /* Platform data may override FIFO sizes */
1306 p->tx_fifo_size = chipdata->tx_fifo_size;
1307 p->rx_fifo_size = chipdata->rx_fifo_size;
1308 if (p->info->tx_fifo_override)
1309 p->tx_fifo_size = p->info->tx_fifo_override;
1310 if (p->info->rx_fifo_override)
1311 p->rx_fifo_size = p->info->rx_fifo_override;
1312
1313 /* init master code */
1314 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1315 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1316 master->flags = chipdata->master_flags;
1317 master->bus_num = pdev->id;
1318 master->dev.of_node = pdev->dev.of_node;
1319 master->num_chipselect = p->info->num_chipselect;
1320 master->setup = sh_msiof_spi_setup;
1321 master->prepare_message = sh_msiof_prepare_message;
1322 master->slave_abort = sh_msiof_slave_abort;
1323 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1324 master->auto_runtime_pm = true;
1325 master->transfer_one = sh_msiof_transfer_one;
1326
1327 ret = sh_msiof_request_dma(p);
1328 if (ret < 0)
1329 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1330
1331 ret = devm_spi_register_master(&pdev->dev, master);
1332 if (ret < 0) {
1333 dev_err(&pdev->dev, "spi_register_master error.\n");
1334 goto err2;
1335 }
1336
1337 return 0;
1338
1339 err2:
1340 sh_msiof_release_dma(p);
1341 pm_runtime_disable(&pdev->dev);
1342 err1:
1343 spi_master_put(master);
1344 return ret;
1345 }
1346
1347 static int sh_msiof_spi_remove(struct platform_device *pdev)
1348 {
1349 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1350
1351 sh_msiof_release_dma(p);
1352 pm_runtime_disable(&pdev->dev);
1353 return 0;
1354 }
1355
1356 static const struct platform_device_id spi_driver_ids[] = {
1357 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1358 {},
1359 };
1360 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1361
1362 static struct platform_driver sh_msiof_spi_drv = {
1363 .probe = sh_msiof_spi_probe,
1364 .remove = sh_msiof_spi_remove,
1365 .id_table = spi_driver_ids,
1366 .driver = {
1367 .name = "spi_sh_msiof",
1368 .of_match_table = of_match_ptr(sh_msiof_match),
1369 },
1370 };
1371 module_platform_driver(sh_msiof_spi_drv);
1372
1373 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1374 MODULE_AUTHOR("Magnus Damm");
1375 MODULE_LICENSE("GPL v2");
1376 MODULE_ALIAS("platform:spi_sh_msiof");
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