drivers/spi/spi-sirf.c

   1 /*
   2  * SPI bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22
  23 #define DRIVER_NAME "sirfsoc_spi"
  24
  25 #define SIRFSOC_SPI_CTRL                0x0000
  26 #define SIRFSOC_SPI_CMD                 0x0004
  27 #define SIRFSOC_SPI_TX_RX_EN            0x0008
  28 #define SIRFSOC_SPI_INT_EN              0x000C
  29 #define SIRFSOC_SPI_INT_STATUS          0x0010
  30 #define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  31 #define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  32 #define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  33 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  34 #define SIRFSOC_SPI_TXFIFO_OP           0x0110
  35 #define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  36 #define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  37 #define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  38 #define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  39 #define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  40 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  41 #define SIRFSOC_SPI_RXFIFO_OP           0x0130
  42 #define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  43 #define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  44 #define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  45
  46 /* SPI CTRL register defines */
  47 #define SIRFSOC_SPI_SLV_MODE            BIT(16)
  48 #define SIRFSOC_SPI_CMD_MODE            BIT(17)
  49 #define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  50 #define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  51 #define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  52 #define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  53 #define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  54 #define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  55 #define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  56 #define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  57 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  58 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  59 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  60 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  61 #define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  62 #define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  63 #define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  64
  65 /* Interrupt Enable */
  66 #define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  67 #define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  68 #define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  69 #define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  70 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  71 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  72 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  73 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  74 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  75 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  76 #define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  77
  78 #define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  79
  80 /* Interrupt status */
  81 #define SIRFSOC_SPI_RX_DONE             BIT(0)
  82 #define SIRFSOC_SPI_TX_DONE             BIT(1)
  83 #define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  84 #define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  85 #define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  86 #define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  87 #define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  88 #define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  89 #define SIRFSOC_SPI_FRM_END             BIT(10)
  90
  91 /* TX RX enable */
  92 #define SIRFSOC_SPI_RX_EN               BIT(0)
  93 #define SIRFSOC_SPI_TX_EN               BIT(1)
  94 #define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
  95
  96 #define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
  97 #define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
  98
  99 /* FIFO OPs */
 100 #define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 101 #define SIRFSOC_SPI_FIFO_START          BIT(1)
 102
 103 /* FIFO CTRL */
 104 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 105 #define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 106 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 107
 108 /* FIFO Status */
 109 #define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 110 #define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 111 #define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 112
 113 /* 256 bytes rx/tx FIFO */
 114 #define SIRFSOC_SPI_FIFO_SIZE           256
 115 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 116
 117 #define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 118 #define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 119 #define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 120 #define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 121
 122 struct sirfsoc_spi {
 123         struct spi_bitbang bitbang;
 124         struct completion done;
 125
 126         void __iomem *base;
 127         u32 ctrl_freq;  /* SPI controller clock speed */
 128         struct clk *clk;
 129
 130         /* rx & tx bufs from the spi_transfer */
 131         const void *tx;
 132         void *rx;
 133
 134         /* place received word into rx buffer */
 135         void (*rx_word) (struct sirfsoc_spi *);
 136         /* get word from tx buffer for sending */
 137         void (*tx_word) (struct sirfsoc_spi *);
 138
 139         /* number of words left to be tranmitted/received */
 140         unsigned int left_tx_cnt;
 141         unsigned int left_rx_cnt;
 142
 143         int chipselect[0];
 144 };
 145
 146 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 147 {
 148         u32 data;
 149         u8 *rx = sspi->rx;
 150
 151         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 152
 153         if (rx) {
 154                 *rx++ = (u8) data;
 155                 sspi->rx = rx;
 156         }
 157
 158         sspi->left_rx_cnt--;
 159 }
 160
 161 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 162 {
 163         u32 data = 0;
 164         const u8 *tx = sspi->tx;
 165
 166         if (tx) {
 167                 data = *tx++;
 168                 sspi->tx = tx;
 169         }
 170
 171         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 172         sspi->left_tx_cnt--;
 173 }
 174
 175 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 176 {
 177         u32 data;
 178         u16 *rx = sspi->rx;
 179
 180         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 181
 182         if (rx) {
 183                 *rx++ = (u16) data;
 184                 sspi->rx = rx;
 185         }
 186
 187         sspi->left_rx_cnt--;
 188 }
 189
 190 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 191 {
 192         u32 data = 0;
 193         const u16 *tx = sspi->tx;
 194
 195         if (tx) {
 196                 data = *tx++;
 197                 sspi->tx = tx;
 198         }
 199
 200         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 201         sspi->left_tx_cnt--;
 202 }
 203
 204 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 205 {
 206         u32 data;
 207         u32 *rx = sspi->rx;
 208
 209         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 210
 211         if (rx) {
 212                 *rx++ = (u32) data;
 213                 sspi->rx = rx;
 214         }
 215
 216         sspi->left_rx_cnt--;
 217
 218 }
 219
 220 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 221 {
 222         u32 data = 0;
 223         const u32 *tx = sspi->tx;
 224
 225         if (tx) {
 226                 data = *tx++;
 227                 sspi->tx = tx;
 228         }
 229
 230         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 231         sspi->left_tx_cnt--;
 232 }
 233
 234 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 235 {
 236         struct sirfsoc_spi *sspi = dev_id;
 237         u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 238
 239         writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
 240
 241         /* Error Conditions */
 242         if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 243                         spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 244                 complete(&sspi->done);
 245                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 246         }
 247
 248         if (spi_stat & (SIRFSOC_SPI_FRM_END
 249                         | SIRFSOC_SPI_RXFIFO_THD_REACH))
 250                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 251                                 & SIRFSOC_SPI_FIFO_EMPTY)) &&
 252                                 sspi->left_rx_cnt)
 253                         sspi->rx_word(sspi);
 254
 255         if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
 256                         | SIRFSOC_SPI_TXFIFO_THD_REACH))
 257                 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
 258                                 & SIRFSOC_SPI_FIFO_FULL)) &&
 259                                 sspi->left_tx_cnt)
 260                         sspi->tx_word(sspi);
 261
 262         /* Received all words */
 263         if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
 264                 complete(&sspi->done);
 265                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 266         }
 267         return IRQ_HANDLED;
 268 }
 269
 270 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 271 {
 272         struct sirfsoc_spi *sspi;
 273         int timeout = t->len * 10;
 274         sspi = spi_master_get_devdata(spi->master);
 275
 276         sspi->tx = t->tx_buf;
 277         sspi->rx = t->rx_buf;
 278         sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
 279         INIT_COMPLETION(sspi->done);
 280
 281         writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 282
 283         if (t->len == 1) {
 284                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 285                         SIRFSOC_SPI_ENA_AUTO_CLR,
 286                         sspi->base + SIRFSOC_SPI_CTRL);
 287                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 288                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 289         } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
 290                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 291                                 SIRFSOC_SPI_MUL_DAT_MODE |
 292                                 SIRFSOC_SPI_ENA_AUTO_CLR,
 293                         sspi->base + SIRFSOC_SPI_CTRL);
 294                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 295                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 296         } else {
 297                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 298                         sspi->base + SIRFSOC_SPI_CTRL);
 299                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 300                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 301         }
 302
 303         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 304         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 305         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 306         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 307
 308         /* Send the first word to trigger the whole tx/rx process */
 309         sspi->tx_word(sspi);
 310
 311         writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
 312                 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
 313                 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
 314                 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
 315         writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 316
 317         if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
 318                 dev_err(&spi->dev, "transfer timeout\n");
 319
 320         /* TX, RX FIFO stop */
 321         writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 322         writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 323         writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 324         writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 325
 326         return t->len - sspi->left_rx_cnt;
 327 }
 328
 329 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 330 {
 331         struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 332
 333         if (sspi->chipselect[spi->chip_select] == 0) {
 334                 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 335                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 336                 switch (value) {
 337                 case BITBANG_CS_ACTIVE:
 338                         if (spi->mode & SPI_CS_HIGH)
 339                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 340                         else
 341                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 342                         break;
 343                 case BITBANG_CS_INACTIVE:
 344                         if (spi->mode & SPI_CS_HIGH)
 345                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 346                         else
 347                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 348                         break;
 349                 }
 350                 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 351         } else {
 352                 int gpio = sspi->chipselect[spi->chip_select];
 353                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 354         }
 355 }
 356
 357 static int
 358 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 359 {
 360         struct sirfsoc_spi *sspi;
 361         u8 bits_per_word = 0;
 362         int hz = 0;
 363         u32 regval;
 364         u32 txfifo_ctrl, rxfifo_ctrl;
 365         u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 366
 367         sspi = spi_master_get_devdata(spi->master);
 368
 369         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 370         hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 371
 372         /* Enable IO mode for RX, TX */
 373         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 374         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 375         regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 376
 377         if (regval > 0xFFFF || regval < 0) {
 378                 dev_err(&spi->dev, "Speed %d not supported\n", hz);
 379                 return -EINVAL;
 380         }
 381
 382         switch (bits_per_word) {
 383         case 8:
 384                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 385                 sspi->rx_word = spi_sirfsoc_rx_word_u8;
 386                 sspi->tx_word = spi_sirfsoc_tx_word_u8;
 387                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 388                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 389                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 390                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 391                 break;
 392         case 12:
 393         case 16:
 394                 regval |= (bits_per_word ==  12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 395                         SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 396                 sspi->rx_word = spi_sirfsoc_rx_word_u16;
 397                 sspi->tx_word = spi_sirfsoc_tx_word_u16;
 398                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 399                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 400                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 401                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 402                 break;
 403         case 32:
 404                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 405                 sspi->rx_word = spi_sirfsoc_rx_word_u32;
 406                 sspi->tx_word = spi_sirfsoc_tx_word_u32;
 407                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 408                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 409                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 410                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 411                 break;
 412         default:
 413                 BUG();
 414         }
 415
 416         if (!(spi->mode & SPI_CS_HIGH))
 417                 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 418         if (!(spi->mode & SPI_LSB_FIRST))
 419                 regval |= SIRFSOC_SPI_TRAN_MSB;
 420         if (spi->mode & SPI_CPOL)
 421                 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 422
 423         /*
 424          * Data should be driven at least 1/2 cycle before the fetch edge to make
 425          * sure that data gets stable at the fetch edge.
 426          */
 427         if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 428             (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 429                 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 430         else
 431                 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 432
 433         writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 434                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 435                         SIRFSOC_SPI_FIFO_HC(2),
 436                 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 437         writel(SIRFSOC_SPI_FIFO_SC(2) |
 438                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 439                         SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 440                 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 441         writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 442         writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 443
 444         writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 445         return 0;
 446 }
 447
 448 static int spi_sirfsoc_setup(struct spi_device *spi)
 449 {
 450         struct sirfsoc_spi *sspi;
 451
 452         if (!spi->max_speed_hz)
 453                 return -EINVAL;
 454
 455         sspi = spi_master_get_devdata(spi->master);
 456
 457         if (!spi->bits_per_word)
 458                 spi->bits_per_word = 8;
 459
 460         return spi_sirfsoc_setup_transfer(spi, NULL);
 461 }
 462
 463 static int spi_sirfsoc_probe(struct platform_device *pdev)
 464 {
 465         struct sirfsoc_spi *sspi;
 466         struct spi_master *master;
 467         struct resource *mem_res;
 468         int num_cs, cs_gpio, irq;
 469         int i;
 470         int ret;
 471
 472         ret = of_property_read_u32(pdev->dev.of_node,
 473                         "sirf,spi-num-chipselects", &num_cs);
 474         if (ret < 0) {
 475                 dev_err(&pdev->dev, "Unable to get chip select number\n");
 476                 goto err_cs;
 477         }
 478
 479         master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
 480         if (!master) {
 481                 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 482                 return -ENOMEM;
 483         }
 484         platform_set_drvdata(pdev, master);
 485         sspi = spi_master_get_devdata(master);
 486
 487         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 488         if (!mem_res) {
 489                 dev_err(&pdev->dev, "Unable to get IO resource\n");
 490                 ret = -ENODEV;
 491                 goto free_master;
 492         }
 493         master->num_chipselect = num_cs;
 494
 495         for (i = 0; i < master->num_chipselect; i++) {
 496                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 497                 if (cs_gpio < 0) {
 498                         dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 499                         ret = -ENODEV;
 500                         goto free_master;
 501                 }
 502
 503                 sspi->chipselect[i] = cs_gpio;
 504                 if (cs_gpio == 0)
 505                         continue; /* use cs from spi controller */
 506
 507                 ret = gpio_request(cs_gpio, DRIVER_NAME);
 508                 if (ret) {
 509                         while (i > 0) {
 510                                 i--;
 511                                 if (sspi->chipselect[i] > 0)
 512                                         gpio_free(sspi->chipselect[i]);
 513                         }
 514                         dev_err(&pdev->dev, "fail to request cs gpios\n");
 515                         goto free_master;
 516                 }
 517         }
 518
 519         sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
 520         if (IS_ERR(sspi->base)) {
 521                 ret = PTR_ERR(sspi->base);
 522                 goto free_master;
 523         }
 524
 525         irq = platform_get_irq(pdev, 0);
 526         if (irq < 0) {
 527                 ret = -ENXIO;
 528                 goto free_master;
 529         }
 530         ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 531                                 DRIVER_NAME, sspi);
 532         if (ret)
 533                 goto free_master;
 534
 535         sspi->bitbang.master = spi_master_get(master);
 536         sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 537         sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 538         sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 539         sspi->bitbang.master->setup = spi_sirfsoc_setup;
 540         master->bus_num = pdev->id;
 541         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
 542                                         SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
 543         sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 544
 545         sspi->clk = clk_get(&pdev->dev, NULL);
 546         if (IS_ERR(sspi->clk)) {
 547                 ret = -EINVAL;
 548                 goto free_master;
 549         }
 550         clk_prepare_enable(sspi->clk);
 551         sspi->ctrl_freq = clk_get_rate(sspi->clk);
 552
 553         init_completion(&sspi->done);
 554
 555         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 556         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 557         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 558         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 559         /* We are not using dummy delay between command and data */
 560         writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 561
 562         ret = spi_bitbang_start(&sspi->bitbang);
 563         if (ret)
 564                 goto free_clk;
 565
 566         dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 567
 568         return 0;
 569
 570 free_clk:
 571         clk_disable_unprepare(sspi->clk);
 572         clk_put(sspi->clk);
 573 free_master:
 574         spi_master_put(master);
 575 err_cs:
 576         return ret;
 577 }
 578
 579 static int  spi_sirfsoc_remove(struct platform_device *pdev)
 580 {
 581         struct spi_master *master;
 582         struct sirfsoc_spi *sspi;
 583         int i;
 584
 585         master = platform_get_drvdata(pdev);
 586         sspi = spi_master_get_devdata(master);
 587
 588         spi_bitbang_stop(&sspi->bitbang);
 589         for (i = 0; i < master->num_chipselect; i++) {
 590                 if (sspi->chipselect[i] > 0)
 591                         gpio_free(sspi->chipselect[i]);
 592         }
 593         clk_disable_unprepare(sspi->clk);
 594         clk_put(sspi->clk);
 595         spi_master_put(master);
 596         return 0;
 597 }
 598
 599 #ifdef CONFIG_PM
 600 static int spi_sirfsoc_suspend(struct device *dev)
 601 {
 602         struct platform_device *pdev = to_platform_device(dev);
 603         struct spi_master *master = platform_get_drvdata(pdev);
 604         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 605
 606         clk_disable(sspi->clk);
 607         return 0;
 608 }
 609
 610 static int spi_sirfsoc_resume(struct device *dev)
 611 {
 612         struct platform_device *pdev = to_platform_device(dev);
 613         struct spi_master *master = platform_get_drvdata(pdev);
 614         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 615
 616         clk_enable(sspi->clk);
 617         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 618         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 619         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 620         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 621
 622         return 0;
 623 }
 624
 625 static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
 626         .suspend = spi_sirfsoc_suspend,
 627         .resume = spi_sirfsoc_resume,
 628 };
 629 #endif
 630
 631 static const struct of_device_id spi_sirfsoc_of_match[] = {
 632         { .compatible = "sirf,prima2-spi", },
 633         { .compatible = "sirf,marco-spi", },
 634         {}
 635 };
 636 MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
 637
 638 static struct platform_driver spi_sirfsoc_driver = {
 639         .driver = {
 640                 .name = DRIVER_NAME,
 641                 .owner = THIS_MODULE,
 642 #ifdef CONFIG_PM
 643                 .pm     = &spi_sirfsoc_pm_ops,
 644 #endif
 645                 .of_match_table = spi_sirfsoc_of_match,
 646         },
 647         .probe = spi_sirfsoc_probe,
 648         .remove = spi_sirfsoc_remove,
 649 };
 650 module_platform_driver(spi_sirfsoc_driver);
 651
 652 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 653 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 654                 "Barry Song <Baohua.Song@csr.com>");
 655 MODULE_LICENSE("GPL v2");