2 * Copyright (C) 2017 Spreadtrum Communications Inc.
4 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/delay.h>
8 #include <linux/hwspinlock.h>
9 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/reboot.h>
17 #include <linux/spi/spi.h>
18 #include <linux/sizes.h>
20 /* Registers definitions for ADI controller */
21 #define REG_ADI_CTRL0 0x4
22 #define REG_ADI_CHN_PRIL 0x8
23 #define REG_ADI_CHN_PRIH 0xc
24 #define REG_ADI_INT_EN 0x10
25 #define REG_ADI_INT_RAW 0x14
26 #define REG_ADI_INT_MASK 0x18
27 #define REG_ADI_INT_CLR 0x1c
28 #define REG_ADI_GSSI_CFG0 0x20
29 #define REG_ADI_GSSI_CFG1 0x24
30 #define REG_ADI_RD_CMD 0x28
31 #define REG_ADI_RD_DATA 0x2c
32 #define REG_ADI_ARM_FIFO_STS 0x30
33 #define REG_ADI_STS 0x34
34 #define REG_ADI_EVT_FIFO_STS 0x38
35 #define REG_ADI_ARM_CMD_STS 0x3c
36 #define REG_ADI_CHN_EN 0x40
37 #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
38 #define REG_ADI_CHN_EN1 0x20c
40 /* Bits definitions for register REG_ADI_GSSI_CFG0 */
41 #define BIT_CLK_ALL_ON BIT(30)
43 /* Bits definitions for register REG_ADI_RD_DATA */
44 #define BIT_RD_CMD_BUSY BIT(31)
45 #define RD_ADDR_SHIFT 16
46 #define RD_VALUE_MASK GENMASK(15, 0)
47 #define RD_ADDR_MASK GENMASK(30, 16)
49 /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
50 #define BIT_FIFO_FULL BIT(11)
51 #define BIT_FIFO_EMPTY BIT(10)
54 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
55 * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
56 * later versions. Since bit[1:0] are zero, so the spec describe them as
57 * 10/12/15bit address mode.
58 * The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the
59 * high two bits is slave_id.
60 * The slave devices address offset is 0x8000 for 10/12bit address mode,
61 * and 0x20000 for 15bit mode.
63 #define ADI_10BIT_SLAVE_ADDR_SIZE SZ_4K
64 #define ADI_10BIT_SLAVE_OFFSET 0x8000
65 #define ADI_12BIT_SLAVE_ADDR_SIZE SZ_16K
66 #define ADI_12BIT_SLAVE_OFFSET 0x8000
67 #define ADI_15BIT_SLAVE_ADDR_SIZE SZ_128K
68 #define ADI_15BIT_SLAVE_OFFSET 0x20000
70 /* Timeout (ms) for the trylock of hardware spinlocks */
71 #define ADI_HWSPINLOCK_TIMEOUT 5000
73 * ADI controller has 50 channels including 2 software channels
74 * and 48 hardware channels.
76 #define ADI_HW_CHNS 50
78 #define ADI_FIFO_DRAIN_TIMEOUT 1000
79 #define ADI_READ_TIMEOUT 2000
82 * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to:
83 * REG_ADI_RD_CMD bit[14:0] for r2p0
84 * REG_ADI_RD_CMD bit[16:2] for r3p0
86 #define RDBACK_ADDR_MASK_R2 GENMASK(14, 0)
87 #define RDBACK_ADDR_MASK_R3 GENMASK(16, 2)
88 #define RDBACK_ADDR_SHIFT_R3 2
90 /* Registers definitions for PMIC watchdog controller */
91 #define REG_WDG_LOAD_LOW 0x0
92 #define REG_WDG_LOAD_HIGH 0x4
93 #define REG_WDG_CTRL 0x8
94 #define REG_WDG_LOCK 0x20
96 /* Bits definitions for register REG_WDG_CTRL */
97 #define BIT_WDG_RUN BIT(1)
98 #define BIT_WDG_NEW BIT(2)
99 #define BIT_WDG_RST BIT(3)
101 /* Bits definitions for register REG_MODULE_EN */
102 #define BIT_WDG_EN BIT(2)
104 /* Registers definitions for PMIC */
105 #define PMIC_RST_STATUS 0xee8
106 #define PMIC_MODULE_EN 0xc08
107 #define PMIC_CLK_EN 0xc18
108 #define PMIC_WDG_BASE 0x80
110 /* Definition of PMIC reset status register */
111 #define HWRST_STATUS_SECURITY 0x02
112 #define HWRST_STATUS_RECOVERY 0x20
113 #define HWRST_STATUS_NORMAL 0x40
114 #define HWRST_STATUS_ALARM 0x50
115 #define HWRST_STATUS_SLEEP 0x60
116 #define HWRST_STATUS_FASTBOOT 0x30
117 #define HWRST_STATUS_SPECIAL 0x70
118 #define HWRST_STATUS_PANIC 0x80
119 #define HWRST_STATUS_CFTREBOOT 0x90
120 #define HWRST_STATUS_AUTODLOADER 0xa0
121 #define HWRST_STATUS_IQMODE 0xb0
122 #define HWRST_STATUS_SPRDISK 0xc0
123 #define HWRST_STATUS_FACTORYTEST 0xe0
124 #define HWRST_STATUS_WATCHDOG 0xf0
126 /* Use default timeout 50 ms that converts to watchdog values */
127 #define WDG_LOAD_VAL ((50 * 32768) / 1000)
128 #define WDG_LOAD_MASK GENMASK(15, 0)
129 #define WDG_UNLOCK_KEY 0xe551
131 struct sprd_adi_wdg
{
138 struct sprd_adi_data
{
141 int (*read_check
)(u32 val
, u32 reg
);
142 int (*restart
)(struct notifier_block
*this,
143 unsigned long mode
, void *cmd
);
144 void (*wdg_rst
)(void *p
);
148 struct spi_controller
*ctlr
;
151 struct hwspinlock
*hwlock
;
152 unsigned long slave_vbase
;
153 unsigned long slave_pbase
;
154 struct notifier_block restart_handler
;
155 const struct sprd_adi_data
*data
;
158 static int sprd_adi_check_addr(struct sprd_adi
*sadi
, u32 reg
)
160 if (reg
>= sadi
->data
->slave_addr_size
) {
162 "slave address offset is incorrect, reg = 0x%x\n",
170 static int sprd_adi_drain_fifo(struct sprd_adi
*sadi
)
172 u32 timeout
= ADI_FIFO_DRAIN_TIMEOUT
;
176 sts
= readl_relaxed(sadi
->base
+ REG_ADI_ARM_FIFO_STS
);
177 if (sts
& BIT_FIFO_EMPTY
)
184 dev_err(sadi
->dev
, "drain write fifo timeout\n");
191 static int sprd_adi_fifo_is_full(struct sprd_adi
*sadi
)
193 return readl_relaxed(sadi
->base
+ REG_ADI_ARM_FIFO_STS
) & BIT_FIFO_FULL
;
196 static int sprd_adi_read_check(u32 val
, u32 addr
)
200 rd_addr
= (val
& RD_ADDR_MASK
) >> RD_ADDR_SHIFT
;
202 if (rd_addr
!= addr
) {
203 pr_err("ADI read error, addr = 0x%x, val = 0x%x\n", addr
, val
);
210 static int sprd_adi_read_check_r2(u32 val
, u32 reg
)
212 return sprd_adi_read_check(val
, reg
& RDBACK_ADDR_MASK_R2
);
215 static int sprd_adi_read_check_r3(u32 val
, u32 reg
)
217 return sprd_adi_read_check(val
, (reg
& RDBACK_ADDR_MASK_R3
) >> RDBACK_ADDR_SHIFT_R3
);
220 static int sprd_adi_read(struct sprd_adi
*sadi
, u32 reg
, u32
*read_val
)
222 int read_timeout
= ADI_READ_TIMEOUT
;
228 ret
= hwspin_lock_timeout_irqsave(sadi
->hwlock
,
229 ADI_HWSPINLOCK_TIMEOUT
,
232 dev_err(sadi
->dev
, "get the hw lock failed\n");
237 ret
= sprd_adi_check_addr(sadi
, reg
);
242 * Set the slave address offset need to read into RD_CMD register,
243 * then ADI controller will start to transfer automatically.
245 writel_relaxed(reg
, sadi
->base
+ REG_ADI_RD_CMD
);
248 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
249 * simultaneously when writing read command to register, and the
250 * BIT_RD_CMD_BUSY will be cleared after the read operation is
254 val
= readl_relaxed(sadi
->base
+ REG_ADI_RD_DATA
);
255 if (!(val
& BIT_RD_CMD_BUSY
))
259 } while (--read_timeout
);
261 if (read_timeout
== 0) {
262 dev_err(sadi
->dev
, "ADI read timeout\n");
268 * The return value before adi r5p0 includes data and read register
269 * address, from bit 0to bit 15 are data, and from bit 16 to bit 30
270 * are read register address. Then we can check the returned register
271 * address to validate data.
273 if (sadi
->data
->read_check
) {
274 ret
= sadi
->data
->read_check(val
, reg
);
279 *read_val
= val
& RD_VALUE_MASK
;
283 hwspin_unlock_irqrestore(sadi
->hwlock
, &flags
);
287 static int sprd_adi_write(struct sprd_adi
*sadi
, u32 reg
, u32 val
)
289 u32 timeout
= ADI_FIFO_DRAIN_TIMEOUT
;
294 ret
= hwspin_lock_timeout_irqsave(sadi
->hwlock
,
295 ADI_HWSPINLOCK_TIMEOUT
,
298 dev_err(sadi
->dev
, "get the hw lock failed\n");
303 ret
= sprd_adi_check_addr(sadi
, reg
);
307 ret
= sprd_adi_drain_fifo(sadi
);
312 * we should wait for write fifo is empty before writing data to PMIC
316 if (!sprd_adi_fifo_is_full(sadi
)) {
317 /* we need virtual register address to write. */
318 writel_relaxed(val
, (void __iomem
*)(sadi
->slave_vbase
+ reg
));
326 dev_err(sadi
->dev
, "write fifo is full\n");
332 hwspin_unlock_irqrestore(sadi
->hwlock
, &flags
);
336 static int sprd_adi_transfer_one(struct spi_controller
*ctlr
,
337 struct spi_device
*spi_dev
,
338 struct spi_transfer
*t
)
340 struct sprd_adi
*sadi
= spi_controller_get_devdata(ctlr
);
345 reg
= *(u32
*)t
->rx_buf
;
346 ret
= sprd_adi_read(sadi
, reg
, &val
);
347 *(u32
*)t
->rx_buf
= val
;
348 } else if (t
->tx_buf
) {
349 u32
*p
= (u32
*)t
->tx_buf
;
352 ret
= sprd_adi_write(sadi
, reg
, val
);
354 dev_err(sadi
->dev
, "no buffer for transfer\n");
361 static void sprd_adi_set_wdt_rst_mode(void *p
)
363 #if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
365 struct sprd_adi
*sadi
= (struct sprd_adi
*)p
;
367 /* Init watchdog reset mode */
368 sprd_adi_read(sadi
, PMIC_RST_STATUS
, &val
);
369 val
|= HWRST_STATUS_WATCHDOG
;
370 sprd_adi_write(sadi
, PMIC_RST_STATUS
, val
);
374 static int sprd_adi_restart(struct notifier_block
*this, unsigned long mode
,
375 void *cmd
, struct sprd_adi_wdg
*wdg
)
377 struct sprd_adi
*sadi
= container_of(this, struct sprd_adi
,
379 u32 val
, reboot_mode
= 0;
382 reboot_mode
= HWRST_STATUS_NORMAL
;
383 else if (!strncmp(cmd
, "recovery", 8))
384 reboot_mode
= HWRST_STATUS_RECOVERY
;
385 else if (!strncmp(cmd
, "alarm", 5))
386 reboot_mode
= HWRST_STATUS_ALARM
;
387 else if (!strncmp(cmd
, "fastsleep", 9))
388 reboot_mode
= HWRST_STATUS_SLEEP
;
389 else if (!strncmp(cmd
, "bootloader", 10))
390 reboot_mode
= HWRST_STATUS_FASTBOOT
;
391 else if (!strncmp(cmd
, "panic", 5))
392 reboot_mode
= HWRST_STATUS_PANIC
;
393 else if (!strncmp(cmd
, "special", 7))
394 reboot_mode
= HWRST_STATUS_SPECIAL
;
395 else if (!strncmp(cmd
, "cftreboot", 9))
396 reboot_mode
= HWRST_STATUS_CFTREBOOT
;
397 else if (!strncmp(cmd
, "autodloader", 11))
398 reboot_mode
= HWRST_STATUS_AUTODLOADER
;
399 else if (!strncmp(cmd
, "iqmode", 6))
400 reboot_mode
= HWRST_STATUS_IQMODE
;
401 else if (!strncmp(cmd
, "sprdisk", 7))
402 reboot_mode
= HWRST_STATUS_SPRDISK
;
403 else if (!strncmp(cmd
, "tospanic", 8))
404 reboot_mode
= HWRST_STATUS_SECURITY
;
405 else if (!strncmp(cmd
, "factorytest", 11))
406 reboot_mode
= HWRST_STATUS_FACTORYTEST
;
408 reboot_mode
= HWRST_STATUS_NORMAL
;
410 /* Record the reboot mode */
411 sprd_adi_read(sadi
, wdg
->rst_sts
, &val
);
412 val
&= ~HWRST_STATUS_WATCHDOG
;
414 sprd_adi_write(sadi
, wdg
->rst_sts
, val
);
416 /* Enable the interface clock of the watchdog */
417 sprd_adi_read(sadi
, wdg
->wdg_en
, &val
);
419 sprd_adi_write(sadi
, wdg
->wdg_en
, val
);
421 /* Enable the work clock of the watchdog */
422 sprd_adi_read(sadi
, wdg
->wdg_clk
, &val
);
424 sprd_adi_write(sadi
, wdg
->wdg_clk
, val
);
426 /* Unlock the watchdog */
427 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_LOCK
, WDG_UNLOCK_KEY
);
429 sprd_adi_read(sadi
, wdg
->base
+ REG_WDG_CTRL
, &val
);
431 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_CTRL
, val
);
433 /* Load the watchdog timeout value, 50ms is always enough. */
434 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_LOAD_HIGH
, 0);
435 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_LOAD_LOW
,
436 WDG_LOAD_VAL
& WDG_LOAD_MASK
);
438 /* Start the watchdog to reset system */
439 sprd_adi_read(sadi
, wdg
->base
+ REG_WDG_CTRL
, &val
);
440 val
|= BIT_WDG_RUN
| BIT_WDG_RST
;
441 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_CTRL
, val
);
443 /* Lock the watchdog */
444 sprd_adi_write(sadi
, wdg
->base
+ REG_WDG_LOCK
, ~WDG_UNLOCK_KEY
);
448 dev_emerg(sadi
->dev
, "Unable to restart system\n");
452 static int sprd_adi_restart_sc9860(struct notifier_block
*this,
453 unsigned long mode
, void *cmd
)
455 struct sprd_adi_wdg wdg
= {
456 .base
= PMIC_WDG_BASE
,
457 .rst_sts
= PMIC_RST_STATUS
,
458 .wdg_en
= PMIC_MODULE_EN
,
459 .wdg_clk
= PMIC_CLK_EN
,
462 return sprd_adi_restart(this, mode
, cmd
, &wdg
);
465 static void sprd_adi_hw_init(struct sprd_adi
*sadi
)
467 struct device_node
*np
= sadi
->dev
->of_node
;
468 int i
, size
, chn_cnt
;
472 /* Set all channels as default priority */
473 writel_relaxed(0, sadi
->base
+ REG_ADI_CHN_PRIL
);
474 writel_relaxed(0, sadi
->base
+ REG_ADI_CHN_PRIH
);
476 /* Set clock auto gate mode */
477 tmp
= readl_relaxed(sadi
->base
+ REG_ADI_GSSI_CFG0
);
478 tmp
&= ~BIT_CLK_ALL_ON
;
479 writel_relaxed(tmp
, sadi
->base
+ REG_ADI_GSSI_CFG0
);
481 /* Set hardware channels setting */
482 list
= of_get_property(np
, "sprd,hw-channels", &size
);
483 if (!list
|| !size
) {
484 dev_info(sadi
->dev
, "no hw channels setting in node\n");
489 for (i
= 0; i
< chn_cnt
; i
++) {
491 u32 chn_id
= be32_to_cpu(*list
++);
492 u32 chn_config
= be32_to_cpu(*list
++);
494 /* Channel 0 and 1 are software channels */
498 writel_relaxed(chn_config
, sadi
->base
+
499 REG_ADI_CHN_ADDR(chn_id
));
502 value
= readl_relaxed(sadi
->base
+ REG_ADI_CHN_EN
);
503 value
|= BIT(chn_id
);
504 writel_relaxed(value
, sadi
->base
+ REG_ADI_CHN_EN
);
505 } else if (chn_id
< ADI_HW_CHNS
) {
506 value
= readl_relaxed(sadi
->base
+ REG_ADI_CHN_EN1
);
507 value
|= BIT(chn_id
- 32);
508 writel_relaxed(value
, sadi
->base
+ REG_ADI_CHN_EN1
);
513 static int sprd_adi_probe(struct platform_device
*pdev
)
515 struct device_node
*np
= pdev
->dev
.of_node
;
516 const struct sprd_adi_data
*data
;
517 struct spi_controller
*ctlr
;
518 struct sprd_adi
*sadi
;
519 struct resource
*res
;
524 dev_err(&pdev
->dev
, "can not find the adi bus node\n");
528 data
= of_device_get_match_data(&pdev
->dev
);
530 dev_err(&pdev
->dev
, "no matching driver data found\n");
534 pdev
->id
= of_alias_get_id(np
, "spi");
535 num_chipselect
= of_get_child_count(np
);
537 ctlr
= spi_alloc_master(&pdev
->dev
, sizeof(struct sprd_adi
));
541 dev_set_drvdata(&pdev
->dev
, ctlr
);
542 sadi
= spi_controller_get_devdata(ctlr
);
544 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
545 sadi
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
546 if (IS_ERR(sadi
->base
)) {
547 ret
= PTR_ERR(sadi
->base
);
551 sadi
->slave_vbase
= (unsigned long)sadi
->base
+
553 sadi
->slave_pbase
= res
->start
+ data
->slave_offset
;
555 sadi
->dev
= &pdev
->dev
;
557 ret
= of_hwspin_lock_get_id(np
, 0);
558 if (ret
> 0 || (IS_ENABLED(CONFIG_HWSPINLOCK
) && ret
== 0)) {
560 devm_hwspin_lock_request_specific(&pdev
->dev
, ret
);
568 dev_info(&pdev
->dev
, "no hardware spinlock supplied\n");
571 dev_err_probe(&pdev
->dev
, ret
, "failed to find hwlock id\n");
576 sprd_adi_hw_init(sadi
);
578 if (sadi
->data
->wdg_rst
)
579 sadi
->data
->wdg_rst(sadi
);
581 ctlr
->dev
.of_node
= pdev
->dev
.of_node
;
582 ctlr
->bus_num
= pdev
->id
;
583 ctlr
->num_chipselect
= num_chipselect
;
584 ctlr
->flags
= SPI_MASTER_HALF_DUPLEX
;
585 ctlr
->bits_per_word_mask
= 0;
586 ctlr
->transfer_one
= sprd_adi_transfer_one
;
588 ret
= devm_spi_register_controller(&pdev
->dev
, ctlr
);
590 dev_err(&pdev
->dev
, "failed to register SPI controller\n");
594 if (sadi
->data
->restart
) {
595 sadi
->restart_handler
.notifier_call
= sadi
->data
->restart
;
596 sadi
->restart_handler
.priority
= 128;
597 ret
= register_restart_handler(&sadi
->restart_handler
);
599 dev_err(&pdev
->dev
, "can not register restart handler\n");
607 spi_controller_put(ctlr
);
611 static int sprd_adi_remove(struct platform_device
*pdev
)
613 struct spi_controller
*ctlr
= dev_get_drvdata(&pdev
->dev
);
614 struct sprd_adi
*sadi
= spi_controller_get_devdata(ctlr
);
616 unregister_restart_handler(&sadi
->restart_handler
);
620 static struct sprd_adi_data sc9860_data
= {
621 .slave_offset
= ADI_10BIT_SLAVE_OFFSET
,
622 .slave_addr_size
= ADI_10BIT_SLAVE_ADDR_SIZE
,
623 .read_check
= sprd_adi_read_check_r2
,
624 .restart
= sprd_adi_restart_sc9860
,
625 .wdg_rst
= sprd_adi_set_wdt_rst_mode
,
628 static struct sprd_adi_data sc9863_data
= {
629 .slave_offset
= ADI_12BIT_SLAVE_OFFSET
,
630 .slave_addr_size
= ADI_12BIT_SLAVE_ADDR_SIZE
,
631 .read_check
= sprd_adi_read_check_r3
,
634 static struct sprd_adi_data ums512_data
= {
635 .slave_offset
= ADI_15BIT_SLAVE_OFFSET
,
636 .slave_addr_size
= ADI_15BIT_SLAVE_ADDR_SIZE
,
637 .read_check
= sprd_adi_read_check_r3
,
640 static const struct of_device_id sprd_adi_of_match
[] = {
642 .compatible
= "sprd,sc9860-adi",
643 .data
= &sc9860_data
,
646 .compatible
= "sprd,sc9863-adi",
647 .data
= &sc9863_data
,
650 .compatible
= "sprd,ums512-adi",
651 .data
= &ums512_data
,
655 MODULE_DEVICE_TABLE(of
, sprd_adi_of_match
);
657 static struct platform_driver sprd_adi_driver
= {
660 .of_match_table
= sprd_adi_of_match
,
662 .probe
= sprd_adi_probe
,
663 .remove
= sprd_adi_remove
,
665 module_platform_driver(sprd_adi_driver
);
667 MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
668 MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
669 MODULE_LICENSE("GPL v2");