drivers/spi/spi-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2018 Spreadtrum Communications Inc.
   3
   4 #include <linux/clk.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/spi/spi.h>
  15
  16 #define SPRD_SPI_TXD                    0x0
  17 #define SPRD_SPI_CLKD                   0x4
  18 #define SPRD_SPI_CTL0                   0x8
  19 #define SPRD_SPI_CTL1                   0xc
  20 #define SPRD_SPI_CTL2                   0x10
  21 #define SPRD_SPI_CTL3                   0x14
  22 #define SPRD_SPI_CTL4                   0x18
  23 #define SPRD_SPI_CTL5                   0x1c
  24 #define SPRD_SPI_INT_EN                 0x20
  25 #define SPRD_SPI_INT_CLR                0x24
  26 #define SPRD_SPI_INT_RAW_STS            0x28
  27 #define SPRD_SPI_INT_MASK_STS           0x2c
  28 #define SPRD_SPI_STS1                   0x30
  29 #define SPRD_SPI_STS2                   0x34
  30 #define SPRD_SPI_DSP_WAIT               0x38
  31 #define SPRD_SPI_STS3                   0x3c
  32 #define SPRD_SPI_CTL6                   0x40
  33 #define SPRD_SPI_STS4                   0x44
  34 #define SPRD_SPI_FIFO_RST               0x48
  35 #define SPRD_SPI_CTL7                   0x4c
  36 #define SPRD_SPI_STS5                   0x50
  37 #define SPRD_SPI_CTL8                   0x54
  38 #define SPRD_SPI_CTL9                   0x58
  39 #define SPRD_SPI_CTL10                  0x5c
  40 #define SPRD_SPI_CTL11                  0x60
  41 #define SPRD_SPI_CTL12                  0x64
  42 #define SPRD_SPI_STS6                   0x68
  43 #define SPRD_SPI_STS7                   0x6c
  44 #define SPRD_SPI_STS8                   0x70
  45 #define SPRD_SPI_STS9                   0x74
  46
  47 /* Bits & mask definition for register CTL0 */
  48 #define SPRD_SPI_SCK_REV                BIT(13)
  49 #define SPRD_SPI_NG_TX                  BIT(1)
  50 #define SPRD_SPI_NG_RX                  BIT(0)
  51 #define SPRD_SPI_CHNL_LEN_MASK          GENMASK(4, 0)
  52 #define SPRD_SPI_CSN_MASK               GENMASK(11, 8)
  53 #define SPRD_SPI_CS0_VALID              BIT(8)
  54
  55 /* Bits & mask definition for register SPI_INT_EN */
  56 #define SPRD_SPI_TX_END_INT_EN          BIT(8)
  57 #define SPRD_SPI_RX_END_INT_EN          BIT(9)
  58
  59 /* Bits & mask definition for register SPI_INT_RAW_STS */
  60 #define SPRD_SPI_TX_END_RAW             BIT(8)
  61 #define SPRD_SPI_RX_END_RAW             BIT(9)
  62
  63 /* Bits & mask definition for register SPI_INT_CLR */
  64 #define SPRD_SPI_TX_END_CLR             BIT(8)
  65 #define SPRD_SPI_RX_END_CLR             BIT(9)
  66
  67 /* Bits & mask definition for register INT_MASK_STS */
  68 #define SPRD_SPI_MASK_RX_END            BIT(9)
  69 #define SPRD_SPI_MASK_TX_END            BIT(8)
  70
  71 /* Bits & mask definition for register STS2 */
  72 #define SPRD_SPI_TX_BUSY                BIT(8)
  73
  74 /* Bits & mask definition for register CTL1 */
  75 #define SPRD_SPI_RX_MODE                BIT(12)
  76 #define SPRD_SPI_TX_MODE                BIT(13)
  77 #define SPRD_SPI_RTX_MD_MASK            GENMASK(13, 12)
  78
  79 /* Bits & mask definition for register CTL2 */
  80 #define SPRD_SPI_DMA_EN                 BIT(6)
  81
  82 /* Bits & mask definition for register CTL4 */
  83 #define SPRD_SPI_START_RX               BIT(9)
  84 #define SPRD_SPI_ONLY_RECV_MASK         GENMASK(8, 0)
  85
  86 /* Bits & mask definition for register SPI_INT_CLR */
  87 #define SPRD_SPI_RX_END_INT_CLR         BIT(9)
  88 #define SPRD_SPI_TX_END_INT_CLR         BIT(8)
  89
  90 /* Bits & mask definition for register SPI_INT_RAW */
  91 #define SPRD_SPI_RX_END_IRQ             BIT(9)
  92 #define SPRD_SPI_TX_END_IRQ             BIT(8)
  93
  94 /* Bits & mask definition for register CTL12 */
  95 #define SPRD_SPI_SW_RX_REQ              BIT(0)
  96 #define SPRD_SPI_SW_TX_REQ              BIT(1)
  97
  98 /* Bits & mask definition for register CTL7 */
  99 #define SPRD_SPI_DATA_LINE2_EN          BIT(15)
 100 #define SPRD_SPI_MODE_MASK              GENMASK(5, 3)
 101 #define SPRD_SPI_MODE_OFFSET            3
 102 #define SPRD_SPI_3WIRE_MODE             4
 103 #define SPRD_SPI_4WIRE_MODE             0
 104
 105 /* Bits & mask definition for register CTL8 */
 106 #define SPRD_SPI_TX_MAX_LEN_MASK        GENMASK(19, 0)
 107 #define SPRD_SPI_TX_LEN_H_MASK          GENMASK(3, 0)
 108 #define SPRD_SPI_TX_LEN_H_OFFSET        16
 109
 110 /* Bits & mask definition for register CTL9 */
 111 #define SPRD_SPI_TX_LEN_L_MASK          GENMASK(15, 0)
 112
 113 /* Bits & mask definition for register CTL10 */
 114 #define SPRD_SPI_RX_MAX_LEN_MASK        GENMASK(19, 0)
 115 #define SPRD_SPI_RX_LEN_H_MASK          GENMASK(3, 0)
 116 #define SPRD_SPI_RX_LEN_H_OFFSET        16
 117
 118 /* Bits & mask definition for register CTL11 */
 119 #define SPRD_SPI_RX_LEN_L_MASK          GENMASK(15, 0)
 120
 121 /* Default & maximum word delay cycles */
 122 #define SPRD_SPI_MIN_DELAY_CYCLE        14
 123 #define SPRD_SPI_MAX_DELAY_CYCLE        130
 124
 125 #define SPRD_SPI_FIFO_SIZE              32
 126 #define SPRD_SPI_CHIP_CS_NUM            0x4
 127 #define SPRD_SPI_CHNL_LEN               2
 128 #define SPRD_SPI_DEFAULT_SOURCE         26000000
 129 #define SPRD_SPI_MAX_SPEED_HZ           48000000
 130 #define SPRD_SPI_AUTOSUSPEND_DELAY      100
 131
 132 struct sprd_spi {
 133         void __iomem *base;
 134         struct device *dev;
 135         struct clk *clk;
 136         u32 src_clk;
 137         u32 hw_mode;
 138         u32 trans_len;
 139         u32 trans_mode;
 140         u32 word_delay;
 141         u32 hw_speed_hz;
 142         u32 len;
 143         int status;
 144         const void *tx_buf;
 145         void *rx_buf;
 146         int (*read_bufs)(struct sprd_spi *ss, u32 len);
 147         int (*write_bufs)(struct sprd_spi *ss, u32 len);
 148 };
 149
 150 static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
 151                                          struct spi_transfer *t)
 152 {
 153         /*
 154          * The time spent on transmission of the full FIFO data is the maximum
 155          * SPI transmission time.
 156          */
 157         u32 size = t->bits_per_word * SPRD_SPI_FIFO_SIZE;
 158         u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz);
 159         u32 total_time_us = size * bit_time_us;
 160         /*
 161          * There is an interval between data and the data in our SPI hardware,
 162          * so the total transmission time need add the interval time.
 163          */
 164         u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay;
 165         u32 interval_time_us = DIV_ROUND_UP(interval_cycle * USEC_PER_SEC,
 166                                             ss->src_clk);
 167
 168         return total_time_us + interval_time_us;
 169 }
 170
 171 static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t)
 172 {
 173         u32 val, us;
 174         int ret;
 175
 176         us = sprd_spi_transfer_max_timeout(ss, t);
 177         ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
 178                                          val & SPRD_SPI_TX_END_IRQ, 0, us);
 179         if (ret) {
 180                 dev_err(ss->dev, "SPI error, spi send timeout!\n");
 181                 return ret;
 182         }
 183
 184         ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
 185                                          !(val & SPRD_SPI_TX_BUSY), 0, us);
 186         if (ret) {
 187                 dev_err(ss->dev, "SPI error, spi busy timeout!\n");
 188                 return ret;
 189         }
 190
 191         writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
 192
 193         return 0;
 194 }
 195
 196 static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t)
 197 {
 198         u32 val, us;
 199         int ret;
 200
 201         us = sprd_spi_transfer_max_timeout(ss, t);
 202         ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
 203                                          val & SPRD_SPI_RX_END_IRQ, 0, us);
 204         if (ret) {
 205                 dev_err(ss->dev, "SPI error, spi rx timeout!\n");
 206                 return ret;
 207         }
 208
 209         writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
 210
 211         return 0;
 212 }
 213
 214 static void sprd_spi_tx_req(struct sprd_spi *ss)
 215 {
 216         writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
 217 }
 218
 219 static void sprd_spi_rx_req(struct sprd_spi *ss)
 220 {
 221         writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
 222 }
 223
 224 static void sprd_spi_enter_idle(struct sprd_spi *ss)
 225 {
 226         u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
 227
 228         val &= ~SPRD_SPI_RTX_MD_MASK;
 229         writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
 230 }
 231
 232 static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits)
 233 {
 234         u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
 235
 236         /* Set the valid bits for every transaction */
 237         val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN);
 238         val |= bits << SPRD_SPI_CHNL_LEN;
 239         writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
 240 }
 241
 242 static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length)
 243 {
 244         u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
 245
 246         length &= SPRD_SPI_TX_MAX_LEN_MASK;
 247         val &= ~SPRD_SPI_TX_LEN_H_MASK;
 248         val |= length >> SPRD_SPI_TX_LEN_H_OFFSET;
 249         writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
 250
 251         val = length & SPRD_SPI_TX_LEN_L_MASK;
 252         writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
 253 }
 254
 255 static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length)
 256 {
 257         u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
 258
 259         length &= SPRD_SPI_RX_MAX_LEN_MASK;
 260         val &= ~SPRD_SPI_RX_LEN_H_MASK;
 261         val |= length >> SPRD_SPI_RX_LEN_H_OFFSET;
 262         writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
 263
 264         val = length & SPRD_SPI_RX_LEN_L_MASK;
 265         writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
 266 }
 267
 268 static void sprd_spi_chipselect(struct spi_device *sdev, bool cs)
 269 {
 270         struct spi_controller *sctlr = sdev->controller;
 271         struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
 272         u32 val;
 273
 274         val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
 275         /*  The SPI controller will pull down CS pin if cs is 0 */
 276         if (!cs) {
 277                 val &= ~SPRD_SPI_CS0_VALID;
 278                 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
 279         } else {
 280                 val |= SPRD_SPI_CSN_MASK;
 281                 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
 282         }
 283 }
 284
 285 static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len)
 286 {
 287         u32 val;
 288
 289         /* Clear the start receive bit and reset receive data number */
 290         val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
 291         val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK);
 292         writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
 293
 294         /* Set the receive data length */
 295         val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
 296         val |= len & SPRD_SPI_ONLY_RECV_MASK;
 297         writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
 298
 299         /* Trigger to receive data */
 300         val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
 301         val |= SPRD_SPI_START_RX;
 302         writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
 303
 304         return len;
 305 }
 306
 307 static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len)
 308 {
 309         u8 *tx_p = (u8 *)ss->tx_buf;
 310         int i;
 311
 312         for (i = 0; i < len; i++)
 313                 writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
 314
 315         ss->tx_buf += i;
 316         return i;
 317 }
 318
 319 static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len)
 320 {
 321         u16 *tx_p = (u16 *)ss->tx_buf;
 322         int i;
 323
 324         for (i = 0; i < len; i++)
 325                 writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
 326
 327         ss->tx_buf += i << 1;
 328         return i << 1;
 329 }
 330
 331 static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len)
 332 {
 333         u32 *tx_p = (u32 *)ss->tx_buf;
 334         int i;
 335
 336         for (i = 0; i < len; i++)
 337                 writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
 338
 339         ss->tx_buf += i << 2;
 340         return i << 2;
 341 }
 342
 343 static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len)
 344 {
 345         u8 *rx_p = (u8 *)ss->rx_buf;
 346         int i;
 347
 348         for (i = 0; i < len; i++)
 349                 rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
 350
 351         ss->rx_buf += i;
 352         return i;
 353 }
 354
 355 static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len)
 356 {
 357         u16 *rx_p = (u16 *)ss->rx_buf;
 358         int i;
 359
 360         for (i = 0; i < len; i++)
 361                 rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
 362
 363         ss->rx_buf += i << 1;
 364         return i << 1;
 365 }
 366
 367 static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len)
 368 {
 369         u32 *rx_p = (u32 *)ss->rx_buf;
 370         int i;
 371
 372         for (i = 0; i < len; i++)
 373                 rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD);
 374
 375         ss->rx_buf += i << 2;
 376         return i << 2;
 377 }
 378
 379 static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t)
 380 {
 381         struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
 382         u32 trans_len = ss->trans_len, len;
 383         int ret, write_size = 0;
 384
 385         while (trans_len) {
 386                 len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE :
 387                         trans_len;
 388                 if (ss->trans_mode & SPRD_SPI_TX_MODE) {
 389                         sprd_spi_set_tx_length(ss, len);
 390                         write_size += ss->write_bufs(ss, len);
 391
 392                         /*
 393                          * For our 3 wires mode or dual TX line mode, we need
 394                          * to request the controller to transfer.
 395                          */
 396                         if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
 397                                 sprd_spi_tx_req(ss);
 398
 399                         ret = sprd_spi_wait_for_tx_end(ss, t);
 400                 } else {
 401                         sprd_spi_set_rx_length(ss, len);
 402
 403                         /*
 404                          * For our 3 wires mode or dual TX line mode, we need
 405                          * to request the controller to read.
 406                          */
 407                         if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
 408                                 sprd_spi_rx_req(ss);
 409                         else
 410                                 write_size += ss->write_bufs(ss, len);
 411
 412                         ret = sprd_spi_wait_for_rx_end(ss, t);
 413                 }
 414
 415                 if (ret)
 416                         goto complete;
 417
 418                 if (ss->trans_mode & SPRD_SPI_RX_MODE)
 419                         ss->read_bufs(ss, len);
 420
 421                 trans_len -= len;
 422         }
 423
 424         ret = write_size;
 425
 426 complete:
 427         sprd_spi_enter_idle(ss);
 428
 429         return ret;
 430 }
 431
 432 static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz)
 433 {
 434         /*
 435          * From SPI datasheet, the prescale calculation formula:
 436          * prescale = SPI source clock / (2 * SPI_freq) - 1;
 437          */
 438         u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1;
 439
 440         /* Save the real hardware speed */
 441         ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1);
 442         writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
 443 }
 444
 445 static void sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t)
 446 {
 447         u16 word_delay, interval;
 448         u32 val;
 449
 450         val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
 451         val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX);
 452         /* Set default chip selection, clock phase and clock polarity */
 453         val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
 454         val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
 455         writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
 456
 457         /*
 458          * Set the intervals of two SPI frames, and the inteval calculation
 459          * formula as below per datasheet:
 460          * interval time (source clock cycles) = interval * 4 + 10.
 461          */
 462         word_delay = clamp_t(u16, t->word_delay, SPRD_SPI_MIN_DELAY_CYCLE,
 463                              SPRD_SPI_MAX_DELAY_CYCLE);
 464         interval = DIV_ROUND_UP(word_delay - 10, 4);
 465         ss->word_delay = interval * 4 + 10;
 466         writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
 467
 468         /* Reset SPI fifo */
 469         writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
 470         writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
 471
 472         /* Set SPI work mode */
 473         val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
 474         val &= ~SPRD_SPI_MODE_MASK;
 475
 476         if (ss->hw_mode & SPI_3WIRE)
 477                 val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET;
 478         else
 479                 val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET;
 480
 481         if (ss->hw_mode & SPI_TX_DUAL)
 482                 val |= SPRD_SPI_DATA_LINE2_EN;
 483         else
 484                 val &= ~SPRD_SPI_DATA_LINE2_EN;
 485
 486         writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
 487 }
 488
 489 static int sprd_spi_setup_transfer(struct spi_device *sdev,
 490                                    struct spi_transfer *t)
 491 {
 492         struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
 493         u8 bits_per_word = t->bits_per_word;
 494         u32 val, mode = 0;
 495
 496         ss->len = t->len;
 497         ss->tx_buf = t->tx_buf;
 498         ss->rx_buf = t->rx_buf;
 499
 500         ss->hw_mode = sdev->mode;
 501         sprd_spi_init_hw(ss, t);
 502
 503         /* Set tansfer speed and valid bits */
 504         sprd_spi_set_speed(ss, t->speed_hz);
 505         sprd_spi_set_transfer_bits(ss, bits_per_word);
 506
 507         if (bits_per_word > 16)
 508                 bits_per_word = round_up(bits_per_word, 16);
 509         else
 510                 bits_per_word = round_up(bits_per_word, 8);
 511
 512         switch (bits_per_word) {
 513         case 8:
 514                 ss->trans_len = t->len;
 515                 ss->read_bufs = sprd_spi_read_bufs_u8;
 516                 ss->write_bufs = sprd_spi_write_bufs_u8;
 517                 break;
 518         case 16:
 519                 ss->trans_len = t->len >> 1;
 520                 ss->read_bufs = sprd_spi_read_bufs_u16;
 521                 ss->write_bufs = sprd_spi_write_bufs_u16;
 522                 break;
 523         case 32:
 524                 ss->trans_len = t->len >> 2;
 525                 ss->read_bufs = sprd_spi_read_bufs_u32;
 526                 ss->write_bufs = sprd_spi_write_bufs_u32;
 527                 break;
 528         default:
 529                 return -EINVAL;
 530         }
 531
 532         /* Set transfer read or write mode */
 533         val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
 534         val &= ~SPRD_SPI_RTX_MD_MASK;
 535         if (t->tx_buf)
 536                 mode |= SPRD_SPI_TX_MODE;
 537         if (t->rx_buf)
 538                 mode |= SPRD_SPI_RX_MODE;
 539
 540         writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
 541
 542         ss->trans_mode = mode;
 543
 544         /*
 545          * If in only receive mode, we need to trigger the SPI controller to
 546          * receive data automatically.
 547          */
 548         if (ss->trans_mode == SPRD_SPI_RX_MODE)
 549                 ss->write_bufs = sprd_spi_write_only_receive;
 550
 551         return 0;
 552 }
 553
 554 static int sprd_spi_transfer_one(struct spi_controller *sctlr,
 555                                  struct spi_device *sdev,
 556                                  struct spi_transfer *t)
 557 {
 558         int ret;
 559
 560         ret = sprd_spi_setup_transfer(sdev, t);
 561         if (ret)
 562                 goto setup_err;
 563
 564         ret = sprd_spi_txrx_bufs(sdev, t);
 565         if (ret == t->len)
 566                 ret = 0;
 567         else if (ret >= 0)
 568                 ret = -EREMOTEIO;
 569
 570 setup_err:
 571         spi_finalize_current_transfer(sctlr);
 572
 573         return ret;
 574 }
 575
 576 static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss)
 577 {
 578         struct clk *clk_spi, *clk_parent;
 579
 580         clk_spi = devm_clk_get(&pdev->dev, "spi");
 581         if (IS_ERR(clk_spi)) {
 582                 dev_warn(&pdev->dev, "can't get the spi clock\n");
 583                 clk_spi = NULL;
 584         }
 585
 586         clk_parent = devm_clk_get(&pdev->dev, "source");
 587         if (IS_ERR(clk_parent)) {
 588                 dev_warn(&pdev->dev, "can't get the source clock\n");
 589                 clk_parent = NULL;
 590         }
 591
 592         ss->clk = devm_clk_get(&pdev->dev, "enable");
 593         if (IS_ERR(ss->clk)) {
 594                 dev_err(&pdev->dev, "can't get the enable clock\n");
 595                 return PTR_ERR(ss->clk);
 596         }
 597
 598         if (!clk_set_parent(clk_spi, clk_parent))
 599                 ss->src_clk = clk_get_rate(clk_spi);
 600         else
 601                 ss->src_clk = SPRD_SPI_DEFAULT_SOURCE;
 602
 603         return 0;
 604 }
 605
 606 static int sprd_spi_probe(struct platform_device *pdev)
 607 {
 608         struct spi_controller *sctlr;
 609         struct resource *res;
 610         struct sprd_spi *ss;
 611         int ret;
 612
 613         pdev->id = of_alias_get_id(pdev->dev.of_node, "spi");
 614         sctlr = spi_alloc_master(&pdev->dev, sizeof(*ss));
 615         if (!sctlr)
 616                 return -ENOMEM;
 617
 618         ss = spi_controller_get_devdata(sctlr);
 619         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 620         ss->base = devm_ioremap_resource(&pdev->dev, res);
 621         if (IS_ERR(ss->base)) {
 622                 ret = PTR_ERR(ss->base);
 623                 goto free_controller;
 624         }
 625
 626         ss->dev = &pdev->dev;
 627         sctlr->dev.of_node = pdev->dev.of_node;
 628         sctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE | SPI_TX_DUAL;
 629         sctlr->bus_num = pdev->id;
 630         sctlr->set_cs = sprd_spi_chipselect;
 631         sctlr->transfer_one = sprd_spi_transfer_one;
 632         sctlr->auto_runtime_pm = true;
 633         sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1,
 634                                     SPRD_SPI_MAX_SPEED_HZ);
 635
 636         platform_set_drvdata(pdev, sctlr);
 637         ret = sprd_spi_clk_init(pdev, ss);
 638         if (ret)
 639                 goto free_controller;
 640
 641         ret = clk_prepare_enable(ss->clk);
 642         if (ret)
 643                 goto free_controller;
 644
 645         ret = pm_runtime_set_active(&pdev->dev);
 646         if (ret < 0)
 647                 goto disable_clk;
 648
 649         pm_runtime_set_autosuspend_delay(&pdev->dev,
 650                                          SPRD_SPI_AUTOSUSPEND_DELAY);
 651         pm_runtime_use_autosuspend(&pdev->dev);
 652         pm_runtime_enable(&pdev->dev);
 653         ret = pm_runtime_get_sync(&pdev->dev);
 654         if (ret < 0) {
 655                 dev_err(&pdev->dev, "failed to resume SPI controller\n");
 656                 goto err_rpm_put;
 657         }
 658
 659         ret = devm_spi_register_controller(&pdev->dev, sctlr);
 660         if (ret)
 661                 goto err_rpm_put;
 662
 663         pm_runtime_mark_last_busy(&pdev->dev);
 664         pm_runtime_put_autosuspend(&pdev->dev);
 665
 666         return 0;
 667
 668 err_rpm_put:
 669         pm_runtime_put_noidle(&pdev->dev);
 670         pm_runtime_disable(&pdev->dev);
 671 disable_clk:
 672         clk_disable_unprepare(ss->clk);
 673 free_controller:
 674         spi_controller_put(sctlr);
 675
 676         return ret;
 677 }
 678
 679 static int __exit sprd_spi_remove(struct platform_device *pdev)
 680 {
 681         struct spi_controller *sctlr = platform_get_drvdata(pdev);
 682         struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
 683         int ret;
 684
 685         ret = pm_runtime_get_sync(ss->dev);
 686         if (ret < 0) {
 687                 dev_err(ss->dev, "failed to resume SPI controller\n");
 688                 return ret;
 689         }
 690
 691         clk_disable_unprepare(ss->clk);
 692         pm_runtime_put_noidle(&pdev->dev);
 693         pm_runtime_disable(&pdev->dev);
 694
 695         return 0;
 696 }
 697
 698 static int __maybe_unused sprd_spi_runtime_suspend(struct device *dev)
 699 {
 700         struct spi_controller *sctlr = dev_get_drvdata(dev);
 701         struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
 702
 703         clk_disable_unprepare(ss->clk);
 704
 705         return 0;
 706 }
 707
 708 static int __maybe_unused sprd_spi_runtime_resume(struct device *dev)
 709 {
 710         struct spi_controller *sctlr = dev_get_drvdata(dev);
 711         struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
 712         int ret;
 713
 714         ret = clk_prepare_enable(ss->clk);
 715         if (ret)
 716                 return ret;
 717
 718         return 0;
 719 }
 720
 721 static const struct dev_pm_ops sprd_spi_pm_ops = {
 722         SET_RUNTIME_PM_OPS(sprd_spi_runtime_suspend,
 723                            sprd_spi_runtime_resume, NULL)
 724 };
 725
 726 static const struct of_device_id sprd_spi_of_match[] = {
 727         { .compatible = "sprd,sc9860-spi", },
 728         { /* sentinel */ }
 729 };
 730
 731 static struct platform_driver sprd_spi_driver = {
 732         .driver = {
 733                 .name = "sprd-spi",
 734                 .of_match_table = sprd_spi_of_match,
 735                 .pm = &sprd_spi_pm_ops,
 736         },
 737         .probe = sprd_spi_probe,
 738         .remove  = sprd_spi_remove,
 739 };
 740
 741 module_platform_driver(sprd_spi_driver);
 742
 743 MODULE_DESCRIPTION("Spreadtrum SPI Controller driver");
 744 MODULE_AUTHOR("Lanqing Liu <lanqing.liu@spreadtrum.com>");
 745 MODULE_LICENSE("GPL v2");