2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
25 #include <linux/spi/spi.h>
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_FBS BIT(12)
46 #define SUN6I_TFR_CTL_XCH BIT(31)
48 #define SUN6I_INT_CTL_REG 0x10
49 #define SUN6I_INT_CTL_RF_OVF BIT(8)
50 #define SUN6I_INT_CTL_TC BIT(12)
52 #define SUN6I_INT_STA_REG 0x14
54 #define SUN6I_FIFO_CTL_REG 0x18
55 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
56 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
58 #define SUN6I_FIFO_STA_REG 0x1c
59 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
60 #define SUN6I_FIFO_STA_RF_CNT_BITS 0
61 #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
62 #define SUN6I_FIFO_STA_TF_CNT_BITS 16
64 #define SUN6I_CLK_CTL_REG 0x24
65 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
66 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
67 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
68 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
69 #define SUN6I_CLK_CTL_DRS BIT(12)
71 #define SUN6I_BURST_CNT_REG 0x30
72 #define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
74 #define SUN6I_XMIT_CNT_REG 0x34
75 #define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
77 #define SUN6I_BURST_CTL_CNT_REG 0x38
78 #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
80 #define SUN6I_TXDATA_REG 0x200
81 #define SUN6I_RXDATA_REG 0x300
84 struct spi_master
*master
;
85 void __iomem
*base_addr
;
88 struct reset_control
*rstc
;
90 struct completion done
;
95 unsigned long fifo_depth
;
98 static inline u32
sun6i_spi_read(struct sun6i_spi
*sspi
, u32 reg
)
100 return readl(sspi
->base_addr
+ reg
);
103 static inline void sun6i_spi_write(struct sun6i_spi
*sspi
, u32 reg
, u32 value
)
105 writel(value
, sspi
->base_addr
+ reg
);
108 static inline void sun6i_spi_drain_fifo(struct sun6i_spi
*sspi
, int len
)
113 /* See how much data is available */
114 reg
= sun6i_spi_read(sspi
, SUN6I_FIFO_STA_REG
);
115 reg
&= SUN6I_FIFO_STA_RF_CNT_MASK
;
116 cnt
= reg
>> SUN6I_FIFO_STA_RF_CNT_BITS
;
122 byte
= readb(sspi
->base_addr
+ SUN6I_RXDATA_REG
);
124 *sspi
->rx_buf
++ = byte
;
128 static inline void sun6i_spi_fill_fifo(struct sun6i_spi
*sspi
, int len
)
136 byte
= sspi
->tx_buf
? *sspi
->tx_buf
++ : 0;
137 writeb(byte
, sspi
->base_addr
+ SUN6I_TXDATA_REG
);
142 static void sun6i_spi_set_cs(struct spi_device
*spi
, bool enable
)
144 struct sun6i_spi
*sspi
= spi_master_get_devdata(spi
->master
);
147 reg
= sun6i_spi_read(sspi
, SUN6I_TFR_CTL_REG
);
148 reg
&= ~SUN6I_TFR_CTL_CS_MASK
;
149 reg
|= SUN6I_TFR_CTL_CS(spi
->chip_select
);
152 reg
|= SUN6I_TFR_CTL_CS_LEVEL
;
154 reg
&= ~SUN6I_TFR_CTL_CS_LEVEL
;
156 sun6i_spi_write(sspi
, SUN6I_TFR_CTL_REG
, reg
);
159 static size_t sun6i_spi_max_transfer_size(struct spi_device
*spi
)
161 struct sun6i_spi
*sspi
= spi_master_get_devdata(spi
->master
);
163 return sspi
->fifo_depth
- 1;
166 static int sun6i_spi_transfer_one(struct spi_master
*master
,
167 struct spi_device
*spi
,
168 struct spi_transfer
*tfr
)
170 struct sun6i_spi
*sspi
= spi_master_get_devdata(master
);
171 unsigned int mclk_rate
, div
, timeout
;
172 unsigned int start
, end
, tx_time
;
173 unsigned int tx_len
= 0;
177 /* We don't support transfer larger than the FIFO */
178 if (tfr
->len
> sspi
->fifo_depth
)
181 reinit_completion(&sspi
->done
);
182 sspi
->tx_buf
= tfr
->tx_buf
;
183 sspi
->rx_buf
= tfr
->rx_buf
;
184 sspi
->len
= tfr
->len
;
186 /* Clear pending interrupts */
187 sun6i_spi_write(sspi
, SUN6I_INT_STA_REG
, ~0);
190 sun6i_spi_write(sspi
, SUN6I_FIFO_CTL_REG
,
191 SUN6I_FIFO_CTL_RF_RST
| SUN6I_FIFO_CTL_TF_RST
);
194 * Setup the transfer control register: Chip Select,
197 reg
= sun6i_spi_read(sspi
, SUN6I_TFR_CTL_REG
);
199 if (spi
->mode
& SPI_CPOL
)
200 reg
|= SUN6I_TFR_CTL_CPOL
;
202 reg
&= ~SUN6I_TFR_CTL_CPOL
;
204 if (spi
->mode
& SPI_CPHA
)
205 reg
|= SUN6I_TFR_CTL_CPHA
;
207 reg
&= ~SUN6I_TFR_CTL_CPHA
;
209 if (spi
->mode
& SPI_LSB_FIRST
)
210 reg
|= SUN6I_TFR_CTL_FBS
;
212 reg
&= ~SUN6I_TFR_CTL_FBS
;
215 * If it's a TX only transfer, we don't want to fill the RX
216 * FIFO with bogus data
219 reg
&= ~SUN6I_TFR_CTL_DHB
;
221 reg
|= SUN6I_TFR_CTL_DHB
;
223 /* We want to control the chip select manually */
224 reg
|= SUN6I_TFR_CTL_CS_MANUAL
;
226 sun6i_spi_write(sspi
, SUN6I_TFR_CTL_REG
, reg
);
228 /* Ensure that we have a parent clock fast enough */
229 mclk_rate
= clk_get_rate(sspi
->mclk
);
230 if (mclk_rate
< (2 * tfr
->speed_hz
)) {
231 clk_set_rate(sspi
->mclk
, 2 * tfr
->speed_hz
);
232 mclk_rate
= clk_get_rate(sspi
->mclk
);
236 * Setup clock divider.
238 * We have two choices there. Either we can use the clock
239 * divide rate 1, which is calculated thanks to this formula:
240 * SPI_CLK = MOD_CLK / (2 ^ cdr)
241 * Or we can use CDR2, which is calculated with the formula:
242 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
243 * Wether we use the former or the latter is set through the
246 * First try CDR2, and if we can't reach the expected
247 * frequency, fall back to CDR1.
249 div
= mclk_rate
/ (2 * tfr
->speed_hz
);
250 if (div
<= (SUN6I_CLK_CTL_CDR2_MASK
+ 1)) {
254 reg
= SUN6I_CLK_CTL_CDR2(div
) | SUN6I_CLK_CTL_DRS
;
256 div
= ilog2(mclk_rate
) - ilog2(tfr
->speed_hz
);
257 reg
= SUN6I_CLK_CTL_CDR1(div
);
260 sun6i_spi_write(sspi
, SUN6I_CLK_CTL_REG
, reg
);
262 /* Setup the transfer now... */
266 /* Setup the counters */
267 sun6i_spi_write(sspi
, SUN6I_BURST_CNT_REG
, SUN6I_BURST_CNT(tfr
->len
));
268 sun6i_spi_write(sspi
, SUN6I_XMIT_CNT_REG
, SUN6I_XMIT_CNT(tx_len
));
269 sun6i_spi_write(sspi
, SUN6I_BURST_CTL_CNT_REG
,
270 SUN6I_BURST_CTL_CNT_STC(tx_len
));
272 /* Fill the TX FIFO */
273 sun6i_spi_fill_fifo(sspi
, sspi
->fifo_depth
);
275 /* Enable the interrupts */
276 sun6i_spi_write(sspi
, SUN6I_INT_CTL_REG
, SUN6I_INT_CTL_TC
);
278 /* Start the transfer */
279 reg
= sun6i_spi_read(sspi
, SUN6I_TFR_CTL_REG
);
280 sun6i_spi_write(sspi
, SUN6I_TFR_CTL_REG
, reg
| SUN6I_TFR_CTL_XCH
);
282 tx_time
= max(tfr
->len
* 8 * 2 / (tfr
->speed_hz
/ 1000), 100U);
284 timeout
= wait_for_completion_timeout(&sspi
->done
,
285 msecs_to_jiffies(tx_time
));
288 dev_warn(&master
->dev
,
289 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
290 dev_name(&spi
->dev
), tfr
->len
, tfr
->speed_hz
,
291 jiffies_to_msecs(end
- start
), tx_time
);
296 sun6i_spi_drain_fifo(sspi
, sspi
->fifo_depth
);
299 sun6i_spi_write(sspi
, SUN6I_INT_CTL_REG
, 0);
304 static irqreturn_t
sun6i_spi_handler(int irq
, void *dev_id
)
306 struct sun6i_spi
*sspi
= dev_id
;
307 u32 status
= sun6i_spi_read(sspi
, SUN6I_INT_STA_REG
);
309 /* Transfer complete */
310 if (status
& SUN6I_INT_CTL_TC
) {
311 sun6i_spi_write(sspi
, SUN6I_INT_STA_REG
, SUN6I_INT_CTL_TC
);
312 complete(&sspi
->done
);
319 static int sun6i_spi_runtime_resume(struct device
*dev
)
321 struct spi_master
*master
= dev_get_drvdata(dev
);
322 struct sun6i_spi
*sspi
= spi_master_get_devdata(master
);
325 ret
= clk_prepare_enable(sspi
->hclk
);
327 dev_err(dev
, "Couldn't enable AHB clock\n");
331 ret
= clk_prepare_enable(sspi
->mclk
);
333 dev_err(dev
, "Couldn't enable module clock\n");
337 ret
= reset_control_deassert(sspi
->rstc
);
339 dev_err(dev
, "Couldn't deassert the device from reset\n");
343 sun6i_spi_write(sspi
, SUN6I_GBL_CTL_REG
,
344 SUN6I_GBL_CTL_BUS_ENABLE
| SUN6I_GBL_CTL_MASTER
| SUN6I_GBL_CTL_TP
);
349 clk_disable_unprepare(sspi
->mclk
);
351 clk_disable_unprepare(sspi
->hclk
);
356 static int sun6i_spi_runtime_suspend(struct device
*dev
)
358 struct spi_master
*master
= dev_get_drvdata(dev
);
359 struct sun6i_spi
*sspi
= spi_master_get_devdata(master
);
361 reset_control_assert(sspi
->rstc
);
362 clk_disable_unprepare(sspi
->mclk
);
363 clk_disable_unprepare(sspi
->hclk
);
368 static int sun6i_spi_probe(struct platform_device
*pdev
)
370 struct spi_master
*master
;
371 struct sun6i_spi
*sspi
;
372 struct resource
*res
;
375 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct sun6i_spi
));
377 dev_err(&pdev
->dev
, "Unable to allocate SPI Master\n");
381 platform_set_drvdata(pdev
, master
);
382 sspi
= spi_master_get_devdata(master
);
384 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
385 sspi
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
386 if (IS_ERR(sspi
->base_addr
)) {
387 ret
= PTR_ERR(sspi
->base_addr
);
388 goto err_free_master
;
391 irq
= platform_get_irq(pdev
, 0);
393 dev_err(&pdev
->dev
, "No spi IRQ specified\n");
395 goto err_free_master
;
398 ret
= devm_request_irq(&pdev
->dev
, irq
, sun6i_spi_handler
,
399 0, "sun6i-spi", sspi
);
401 dev_err(&pdev
->dev
, "Cannot request IRQ\n");
402 goto err_free_master
;
405 sspi
->master
= master
;
406 sspi
->fifo_depth
= (unsigned long)of_device_get_match_data(&pdev
->dev
);
408 master
->max_speed_hz
= 100 * 1000 * 1000;
409 master
->min_speed_hz
= 3 * 1000;
410 master
->set_cs
= sun6i_spi_set_cs
;
411 master
->transfer_one
= sun6i_spi_transfer_one
;
412 master
->num_chipselect
= 4;
413 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LSB_FIRST
;
414 master
->bits_per_word_mask
= SPI_BPW_MASK(8);
415 master
->dev
.of_node
= pdev
->dev
.of_node
;
416 master
->auto_runtime_pm
= true;
417 master
->max_transfer_size
= sun6i_spi_max_transfer_size
;
419 sspi
->hclk
= devm_clk_get(&pdev
->dev
, "ahb");
420 if (IS_ERR(sspi
->hclk
)) {
421 dev_err(&pdev
->dev
, "Unable to acquire AHB clock\n");
422 ret
= PTR_ERR(sspi
->hclk
);
423 goto err_free_master
;
426 sspi
->mclk
= devm_clk_get(&pdev
->dev
, "mod");
427 if (IS_ERR(sspi
->mclk
)) {
428 dev_err(&pdev
->dev
, "Unable to acquire module clock\n");
429 ret
= PTR_ERR(sspi
->mclk
);
430 goto err_free_master
;
433 init_completion(&sspi
->done
);
435 sspi
->rstc
= devm_reset_control_get(&pdev
->dev
, NULL
);
436 if (IS_ERR(sspi
->rstc
)) {
437 dev_err(&pdev
->dev
, "Couldn't get reset controller\n");
438 ret
= PTR_ERR(sspi
->rstc
);
439 goto err_free_master
;
443 * This wake-up/shutdown pattern is to be able to have the
444 * device woken up, even if runtime_pm is disabled
446 ret
= sun6i_spi_runtime_resume(&pdev
->dev
);
448 dev_err(&pdev
->dev
, "Couldn't resume the device\n");
449 goto err_free_master
;
452 pm_runtime_set_active(&pdev
->dev
);
453 pm_runtime_enable(&pdev
->dev
);
454 pm_runtime_idle(&pdev
->dev
);
456 ret
= devm_spi_register_master(&pdev
->dev
, master
);
458 dev_err(&pdev
->dev
, "cannot register SPI master\n");
465 pm_runtime_disable(&pdev
->dev
);
466 sun6i_spi_runtime_suspend(&pdev
->dev
);
468 spi_master_put(master
);
472 static int sun6i_spi_remove(struct platform_device
*pdev
)
474 pm_runtime_disable(&pdev
->dev
);
479 static const struct of_device_id sun6i_spi_match
[] = {
480 { .compatible
= "allwinner,sun6i-a31-spi", .data
= (void *)SUN6I_FIFO_DEPTH
},
481 { .compatible
= "allwinner,sun8i-h3-spi", .data
= (void *)SUN8I_FIFO_DEPTH
},
484 MODULE_DEVICE_TABLE(of
, sun6i_spi_match
);
486 static const struct dev_pm_ops sun6i_spi_pm_ops
= {
487 .runtime_resume
= sun6i_spi_runtime_resume
,
488 .runtime_suspend
= sun6i_spi_runtime_suspend
,
491 static struct platform_driver sun6i_spi_driver
= {
492 .probe
= sun6i_spi_probe
,
493 .remove
= sun6i_spi_remove
,
496 .of_match_table
= sun6i_spi_match
,
497 .pm
= &sun6i_spi_pm_ops
,
500 module_platform_driver(sun6i_spi_driver
);
502 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
503 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
504 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
505 MODULE_LICENSE("GPL");