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[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-tegra114.c
1 /*
2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
37
38 #define SPI_COMMAND1 0x000
39 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SPI_PACKED (1 << 5)
41 #define SPI_TX_EN (1 << 11)
42 #define SPI_RX_EN (1 << 12)
43 #define SPI_BOTH_EN_BYTE (1 << 13)
44 #define SPI_BOTH_EN_BIT (1 << 14)
45 #define SPI_LSBYTE_FE (1 << 15)
46 #define SPI_LSBIT_FE (1 << 16)
47 #define SPI_BIDIROE (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52 #define SPI_IDLE_SDA_MASK (3 << 18)
53 #define SPI_CS_SW_VAL (1 << 20)
54 #define SPI_CS_SW_HW (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
56 /* n from 0 to 3 */
57 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
59
60 #define SPI_CS_SEL_0 (0 << 26)
61 #define SPI_CS_SEL_1 (1 << 26)
62 #define SPI_CS_SEL_2 (2 << 26)
63 #define SPI_CS_SEL_3 (3 << 26)
64 #define SPI_CS_SEL_MASK (3 << 26)
65 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0 (0 << 28)
67 #define SPI_CONTROL_MODE_1 (1 << 28)
68 #define SPI_CONTROL_MODE_2 (2 << 28)
69 #define SPI_CONTROL_MODE_3 (3 << 28)
70 #define SPI_CONTROL_MODE_MASK (3 << 28)
71 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72 #define SPI_M_S (1 << 30)
73 #define SPI_PIO (1 << 31)
74
75 #define SPI_COMMAND2 0x004
76 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
78
79 #define SPI_CS_TIMING1 0x008
80 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85 #define SPI_CS_TIMING2 0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
100
101 #define SPI_TRANS_STATUS 0x010
102 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104 #define SPI_RDY (1 << 30)
105
106 #define SPI_FIFO_STATUS 0x014
107 #define SPI_RX_FIFO_EMPTY (1 << 0)
108 #define SPI_RX_FIFO_FULL (1 << 1)
109 #define SPI_TX_FIFO_EMPTY (1 << 2)
110 #define SPI_TX_FIFO_FULL (1 << 3)
111 #define SPI_RX_FIFO_UNF (1 << 4)
112 #define SPI_RX_FIFO_OVF (1 << 5)
113 #define SPI_TX_FIFO_UNF (1 << 6)
114 #define SPI_TX_FIFO_OVF (1 << 7)
115 #define SPI_ERR (1 << 8)
116 #define SPI_TX_FIFO_FLUSH (1 << 14)
117 #define SPI_RX_FIFO_FLUSH (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END (1 << 30)
121 #define SPI_CS_INACTIVE (1 << 31)
122
123 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127 #define SPI_TX_DATA 0x018
128 #define SPI_RX_DATA 0x01C
129
130 #define SPI_DMA_CTL 0x020
131 #define SPI_TX_TRIG_1 (0 << 15)
132 #define SPI_TX_TRIG_4 (1 << 15)
133 #define SPI_TX_TRIG_8 (2 << 15)
134 #define SPI_TX_TRIG_16 (3 << 15)
135 #define SPI_TX_TRIG_MASK (3 << 15)
136 #define SPI_RX_TRIG_1 (0 << 19)
137 #define SPI_RX_TRIG_4 (1 << 19)
138 #define SPI_RX_TRIG_8 (2 << 19)
139 #define SPI_RX_TRIG_16 (3 << 19)
140 #define SPI_RX_TRIG_MASK (3 << 19)
141 #define SPI_IE_TX (1 << 28)
142 #define SPI_IE_RX (1 << 29)
143 #define SPI_CONT (1 << 30)
144 #define SPI_DMA (1 << 31)
145 #define SPI_DMA_EN SPI_DMA
146
147 #define SPI_DMA_BLK 0x024
148 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
149
150 #define SPI_TX_FIFO 0x108
151 #define SPI_RX_FIFO 0x188
152 #define MAX_CHIP_SELECT 4
153 #define SPI_FIFO_DEPTH 64
154 #define DATA_DIR_TX (1 << 0)
155 #define DATA_DIR_RX (1 << 1)
156
157 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES 16
162 #define SPI_DEFAULT_SPEED 25000000
163
164 struct tegra_spi_data {
165 struct device *dev;
166 struct spi_master *master;
167 spinlock_t lock;
168
169 struct clk *clk;
170 struct reset_control *rst;
171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
174 u32 cur_speed;
175
176 struct spi_device *cur_spi;
177 struct spi_device *cs_control;
178 unsigned cur_pos;
179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
183
184 unsigned cur_rx_pos;
185 unsigned cur_tx_pos;
186
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
190
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
193
194 u32 tx_status;
195 u32 rx_status;
196 u32 status_reg;
197 bool is_packed;
198
199 u32 command1_reg;
200 u32 dma_control_reg;
201 u32 def_command1_reg;
202
203 struct completion xfer_completion;
204 struct spi_transfer *curr_xfer;
205 struct dma_chan *rx_dma_chan;
206 u32 *rx_dma_buf;
207 dma_addr_t rx_dma_phys;
208 struct dma_async_tx_descriptor *rx_dma_desc;
209
210 struct dma_chan *tx_dma_chan;
211 u32 *tx_dma_buf;
212 dma_addr_t tx_dma_phys;
213 struct dma_async_tx_descriptor *tx_dma_desc;
214 };
215
216 static int tegra_spi_runtime_suspend(struct device *dev);
217 static int tegra_spi_runtime_resume(struct device *dev);
218
219 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
220 unsigned long reg)
221 {
222 return readl(tspi->base + reg);
223 }
224
225 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
226 u32 val, unsigned long reg)
227 {
228 writel(val, tspi->base + reg);
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != SPI_TX_FIFO)
232 readl(tspi->base + SPI_COMMAND1);
233 }
234
235 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
236 {
237 u32 val;
238
239 /* Write 1 to clear status register */
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
242
243 /* Clear fifo status error if any */
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
245 if (val & SPI_ERR)
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
247 SPI_FIFO_STATUS);
248 }
249
250 static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device *spi, struct tegra_spi_data *tspi,
252 struct spi_transfer *t)
253 {
254 unsigned remain_len = t->len - tspi->cur_pos;
255 unsigned max_word;
256 unsigned bits_per_word = t->bits_per_word;
257 unsigned max_len;
258 unsigned total_fifo_words;
259
260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
261
262 if ((bits_per_word == 8 || bits_per_word == 16 ||
263 bits_per_word == 32) && t->len > 3) {
264 tspi->is_packed = 1;
265 tspi->words_per_32bit = 32/bits_per_word;
266 } else {
267 tspi->is_packed = 0;
268 tspi->words_per_32bit = 1;
269 }
270
271 if (tspi->is_packed) {
272 max_len = min(remain_len, tspi->max_buf_size);
273 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
274 total_fifo_words = (max_len + 3) / 4;
275 } else {
276 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
277 max_word = min(max_word, tspi->max_buf_size/4);
278 tspi->curr_dma_words = max_word;
279 total_fifo_words = max_word;
280 }
281 return total_fifo_words;
282 }
283
284 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
285 struct tegra_spi_data *tspi, struct spi_transfer *t)
286 {
287 unsigned nbytes;
288 unsigned tx_empty_count;
289 u32 fifo_status;
290 unsigned max_n_32bit;
291 unsigned i, count;
292 unsigned int written_words;
293 unsigned fifo_words_left;
294 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
295
296 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
297 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
298
299 if (tspi->is_packed) {
300 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
301 written_words = min(fifo_words_left, tspi->curr_dma_words);
302 nbytes = written_words * tspi->bytes_per_word;
303 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
304 for (count = 0; count < max_n_32bit; count++) {
305 u32 x = 0;
306
307 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
308 x |= (u32)(*tx_buf++) << (i * 8);
309 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
310 }
311
312 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
313 } else {
314 unsigned int write_bytes;
315 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
316 written_words = max_n_32bit;
317 nbytes = written_words * tspi->bytes_per_word;
318 if (nbytes > t->len - tspi->cur_pos)
319 nbytes = t->len - tspi->cur_pos;
320 write_bytes = nbytes;
321 for (count = 0; count < max_n_32bit; count++) {
322 u32 x = 0;
323
324 for (i = 0; nbytes && (i < tspi->bytes_per_word);
325 i++, nbytes--)
326 x |= (u32)(*tx_buf++) << (i * 8);
327 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
328 }
329
330 tspi->cur_tx_pos += write_bytes;
331 }
332
333 return written_words;
334 }
335
336 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
337 struct tegra_spi_data *tspi, struct spi_transfer *t)
338 {
339 unsigned rx_full_count;
340 u32 fifo_status;
341 unsigned i, count;
342 unsigned int read_words = 0;
343 unsigned len;
344 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
345
346 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
347 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
348 if (tspi->is_packed) {
349 len = tspi->curr_dma_words * tspi->bytes_per_word;
350 for (count = 0; count < rx_full_count; count++) {
351 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
352
353 for (i = 0; len && (i < 4); i++, len--)
354 *rx_buf++ = (x >> i*8) & 0xFF;
355 }
356 read_words += tspi->curr_dma_words;
357 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
358 } else {
359 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
360 u8 bytes_per_word = tspi->bytes_per_word;
361 unsigned int read_bytes;
362
363 len = rx_full_count * bytes_per_word;
364 if (len > t->len - tspi->cur_pos)
365 len = t->len - tspi->cur_pos;
366 read_bytes = len;
367 for (count = 0; count < rx_full_count; count++) {
368 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
369
370 for (i = 0; len && (i < bytes_per_word); i++, len--)
371 *rx_buf++ = (x >> (i*8)) & 0xFF;
372 }
373 read_words += rx_full_count;
374 tspi->cur_rx_pos += read_bytes;
375 }
376
377 return read_words;
378 }
379
380 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
381 struct tegra_spi_data *tspi, struct spi_transfer *t)
382 {
383 /* Make the dma buffer to read by cpu */
384 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
385 tspi->dma_buf_size, DMA_TO_DEVICE);
386
387 if (tspi->is_packed) {
388 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
389
390 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
391 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
392 } else {
393 unsigned int i;
394 unsigned int count;
395 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
396 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
397 unsigned int write_bytes;
398
399 if (consume > t->len - tspi->cur_pos)
400 consume = t->len - tspi->cur_pos;
401 write_bytes = consume;
402 for (count = 0; count < tspi->curr_dma_words; count++) {
403 u32 x = 0;
404
405 for (i = 0; consume && (i < tspi->bytes_per_word);
406 i++, consume--)
407 x |= (u32)(*tx_buf++) << (i * 8);
408 tspi->tx_dma_buf[count] = x;
409 }
410
411 tspi->cur_tx_pos += write_bytes;
412 }
413
414 /* Make the dma buffer to read by dma */
415 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
416 tspi->dma_buf_size, DMA_TO_DEVICE);
417 }
418
419 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
420 struct tegra_spi_data *tspi, struct spi_transfer *t)
421 {
422 /* Make the dma buffer to read by cpu */
423 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
424 tspi->dma_buf_size, DMA_FROM_DEVICE);
425
426 if (tspi->is_packed) {
427 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
428
429 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
430 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
431 } else {
432 unsigned int i;
433 unsigned int count;
434 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
435 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
436 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
437 unsigned int read_bytes;
438
439 if (consume > t->len - tspi->cur_pos)
440 consume = t->len - tspi->cur_pos;
441 read_bytes = consume;
442 for (count = 0; count < tspi->curr_dma_words; count++) {
443 u32 x = tspi->rx_dma_buf[count] & rx_mask;
444
445 for (i = 0; consume && (i < tspi->bytes_per_word);
446 i++, consume--)
447 *rx_buf++ = (x >> (i*8)) & 0xFF;
448 }
449
450 tspi->cur_rx_pos += read_bytes;
451 }
452
453 /* Make the dma buffer to read by dma */
454 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
455 tspi->dma_buf_size, DMA_FROM_DEVICE);
456 }
457
458 static void tegra_spi_dma_complete(void *args)
459 {
460 struct completion *dma_complete = args;
461
462 complete(dma_complete);
463 }
464
465 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
466 {
467 reinit_completion(&tspi->tx_dma_complete);
468 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
469 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
470 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
471 if (!tspi->tx_dma_desc) {
472 dev_err(tspi->dev, "Not able to get desc for Tx\n");
473 return -EIO;
474 }
475
476 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
477 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
478
479 dmaengine_submit(tspi->tx_dma_desc);
480 dma_async_issue_pending(tspi->tx_dma_chan);
481 return 0;
482 }
483
484 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
485 {
486 reinit_completion(&tspi->rx_dma_complete);
487 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
488 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
489 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
490 if (!tspi->rx_dma_desc) {
491 dev_err(tspi->dev, "Not able to get desc for Rx\n");
492 return -EIO;
493 }
494
495 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
496 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
497
498 dmaengine_submit(tspi->rx_dma_desc);
499 dma_async_issue_pending(tspi->rx_dma_chan);
500 return 0;
501 }
502
503 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
504 {
505 unsigned long timeout = jiffies + HZ;
506 u32 status;
507
508 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
509 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
510 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
511 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
512 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
513 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
514 if (time_after(jiffies, timeout)) {
515 dev_err(tspi->dev,
516 "timeout waiting for fifo flush\n");
517 return -EIO;
518 }
519
520 udelay(1);
521 }
522 }
523
524 return 0;
525 }
526
527 static int tegra_spi_start_dma_based_transfer(
528 struct tegra_spi_data *tspi, struct spi_transfer *t)
529 {
530 u32 val;
531 unsigned int len;
532 int ret = 0;
533 u8 dma_burst;
534 struct dma_slave_config dma_sconfig = {0};
535
536 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
537 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
538
539 if (tspi->is_packed)
540 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
541 4) * 4;
542 else
543 len = tspi->curr_dma_words * 4;
544
545 /* Set attention level based on length of transfer */
546 if (len & 0xF) {
547 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
548 dma_burst = 1;
549 } else if (((len) >> 4) & 0x1) {
550 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
551 dma_burst = 4;
552 } else {
553 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
554 dma_burst = 8;
555 }
556
557 if (tspi->cur_direction & DATA_DIR_TX)
558 val |= SPI_IE_TX;
559
560 if (tspi->cur_direction & DATA_DIR_RX)
561 val |= SPI_IE_RX;
562
563 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
564 tspi->dma_control_reg = val;
565
566 dma_sconfig.device_fc = true;
567 if (tspi->cur_direction & DATA_DIR_TX) {
568 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
569 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
570 dma_sconfig.dst_maxburst = dma_burst;
571 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
572 if (ret < 0) {
573 dev_err(tspi->dev,
574 "DMA slave config failed: %d\n", ret);
575 return ret;
576 }
577
578 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
579 ret = tegra_spi_start_tx_dma(tspi, len);
580 if (ret < 0) {
581 dev_err(tspi->dev,
582 "Starting tx dma failed, err %d\n", ret);
583 return ret;
584 }
585 }
586
587 if (tspi->cur_direction & DATA_DIR_RX) {
588 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
589 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
590 dma_sconfig.src_maxburst = dma_burst;
591 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
592 if (ret < 0) {
593 dev_err(tspi->dev,
594 "DMA slave config failed: %d\n", ret);
595 return ret;
596 }
597
598 /* Make the dma buffer to read by dma */
599 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
600 tspi->dma_buf_size, DMA_FROM_DEVICE);
601
602 ret = tegra_spi_start_rx_dma(tspi, len);
603 if (ret < 0) {
604 dev_err(tspi->dev,
605 "Starting rx dma failed, err %d\n", ret);
606 if (tspi->cur_direction & DATA_DIR_TX)
607 dmaengine_terminate_all(tspi->tx_dma_chan);
608 return ret;
609 }
610 }
611 tspi->is_curr_dma_xfer = true;
612 tspi->dma_control_reg = val;
613
614 val |= SPI_DMA_EN;
615 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
616 return ret;
617 }
618
619 static int tegra_spi_start_cpu_based_transfer(
620 struct tegra_spi_data *tspi, struct spi_transfer *t)
621 {
622 u32 val;
623 unsigned cur_words;
624
625 if (tspi->cur_direction & DATA_DIR_TX)
626 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
627 else
628 cur_words = tspi->curr_dma_words;
629
630 val = SPI_DMA_BLK_SET(cur_words - 1);
631 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
632
633 val = 0;
634 if (tspi->cur_direction & DATA_DIR_TX)
635 val |= SPI_IE_TX;
636
637 if (tspi->cur_direction & DATA_DIR_RX)
638 val |= SPI_IE_RX;
639
640 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
641 tspi->dma_control_reg = val;
642
643 tspi->is_curr_dma_xfer = false;
644
645 val |= SPI_DMA_EN;
646 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
647 return 0;
648 }
649
650 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
651 bool dma_to_memory)
652 {
653 struct dma_chan *dma_chan;
654 u32 *dma_buf;
655 dma_addr_t dma_phys;
656 int ret;
657
658 dma_chan = dma_request_slave_channel_reason(tspi->dev,
659 dma_to_memory ? "rx" : "tx");
660 if (IS_ERR(dma_chan)) {
661 ret = PTR_ERR(dma_chan);
662 if (ret != -EPROBE_DEFER)
663 dev_err(tspi->dev,
664 "Dma channel is not available: %d\n", ret);
665 return ret;
666 }
667
668 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
669 &dma_phys, GFP_KERNEL);
670 if (!dma_buf) {
671 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
672 dma_release_channel(dma_chan);
673 return -ENOMEM;
674 }
675
676 if (dma_to_memory) {
677 tspi->rx_dma_chan = dma_chan;
678 tspi->rx_dma_buf = dma_buf;
679 tspi->rx_dma_phys = dma_phys;
680 } else {
681 tspi->tx_dma_chan = dma_chan;
682 tspi->tx_dma_buf = dma_buf;
683 tspi->tx_dma_phys = dma_phys;
684 }
685 return 0;
686 }
687
688 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
689 bool dma_to_memory)
690 {
691 u32 *dma_buf;
692 dma_addr_t dma_phys;
693 struct dma_chan *dma_chan;
694
695 if (dma_to_memory) {
696 dma_buf = tspi->rx_dma_buf;
697 dma_chan = tspi->rx_dma_chan;
698 dma_phys = tspi->rx_dma_phys;
699 tspi->rx_dma_chan = NULL;
700 tspi->rx_dma_buf = NULL;
701 } else {
702 dma_buf = tspi->tx_dma_buf;
703 dma_chan = tspi->tx_dma_chan;
704 dma_phys = tspi->tx_dma_phys;
705 tspi->tx_dma_buf = NULL;
706 tspi->tx_dma_chan = NULL;
707 }
708 if (!dma_chan)
709 return;
710
711 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
712 dma_release_channel(dma_chan);
713 }
714
715 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
716 struct spi_transfer *t, bool is_first_of_msg)
717 {
718 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
719 u32 speed = t->speed_hz;
720 u8 bits_per_word = t->bits_per_word;
721 u32 command1;
722 int req_mode;
723
724 if (speed != tspi->cur_speed) {
725 clk_set_rate(tspi->clk, speed);
726 tspi->cur_speed = speed;
727 }
728
729 tspi->cur_spi = spi;
730 tspi->cur_pos = 0;
731 tspi->cur_rx_pos = 0;
732 tspi->cur_tx_pos = 0;
733 tspi->curr_xfer = t;
734
735 if (is_first_of_msg) {
736 tegra_spi_clear_status(tspi);
737
738 command1 = tspi->def_command1_reg;
739 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
740
741 command1 &= ~SPI_CONTROL_MODE_MASK;
742 req_mode = spi->mode & 0x3;
743 if (req_mode == SPI_MODE_0)
744 command1 |= SPI_CONTROL_MODE_0;
745 else if (req_mode == SPI_MODE_1)
746 command1 |= SPI_CONTROL_MODE_1;
747 else if (req_mode == SPI_MODE_2)
748 command1 |= SPI_CONTROL_MODE_2;
749 else if (req_mode == SPI_MODE_3)
750 command1 |= SPI_CONTROL_MODE_3;
751
752 if (spi->mode & SPI_LSB_FIRST)
753 command1 |= SPI_LSBIT_FE;
754 else
755 command1 &= ~SPI_LSBIT_FE;
756
757 if (tspi->cs_control) {
758 if (tspi->cs_control != spi)
759 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
760 tspi->cs_control = NULL;
761 } else
762 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
763
764 command1 |= SPI_CS_SW_HW;
765 if (spi->mode & SPI_CS_HIGH)
766 command1 |= SPI_CS_SW_VAL;
767 else
768 command1 &= ~SPI_CS_SW_VAL;
769
770 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
771 } else {
772 command1 = tspi->command1_reg;
773 command1 &= ~SPI_BIT_LENGTH(~0);
774 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
775 }
776
777 return command1;
778 }
779
780 static int tegra_spi_start_transfer_one(struct spi_device *spi,
781 struct spi_transfer *t, u32 command1)
782 {
783 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
784 unsigned total_fifo_words;
785 int ret;
786
787 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
788
789 if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
790 command1 |= SPI_BOTH_EN_BIT;
791 else
792 command1 &= ~SPI_BOTH_EN_BIT;
793
794 if (tspi->is_packed)
795 command1 |= SPI_PACKED;
796 else
797 command1 &= ~SPI_PACKED;
798
799 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
800 tspi->cur_direction = 0;
801 if (t->rx_buf) {
802 command1 |= SPI_RX_EN;
803 tspi->cur_direction |= DATA_DIR_RX;
804 }
805 if (t->tx_buf) {
806 command1 |= SPI_TX_EN;
807 tspi->cur_direction |= DATA_DIR_TX;
808 }
809 command1 |= SPI_CS_SEL(spi->chip_select);
810 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
811 tspi->command1_reg = command1;
812
813 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
814 tspi->def_command1_reg, (unsigned)command1);
815
816 ret = tegra_spi_flush_fifos(tspi);
817 if (ret < 0)
818 return ret;
819 if (total_fifo_words > SPI_FIFO_DEPTH)
820 ret = tegra_spi_start_dma_based_transfer(tspi, t);
821 else
822 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
823 return ret;
824 }
825
826 static int tegra_spi_setup(struct spi_device *spi)
827 {
828 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
829 u32 val;
830 unsigned long flags;
831 int ret;
832
833 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
834 spi->bits_per_word,
835 spi->mode & SPI_CPOL ? "" : "~",
836 spi->mode & SPI_CPHA ? "" : "~",
837 spi->max_speed_hz);
838
839 ret = pm_runtime_get_sync(tspi->dev);
840 if (ret < 0) {
841 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
842 return ret;
843 }
844
845 spin_lock_irqsave(&tspi->lock, flags);
846 val = tspi->def_command1_reg;
847 if (spi->mode & SPI_CS_HIGH)
848 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
849 else
850 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
851 tspi->def_command1_reg = val;
852 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
853 spin_unlock_irqrestore(&tspi->lock, flags);
854
855 pm_runtime_put(tspi->dev);
856 return 0;
857 }
858
859 static void tegra_spi_transfer_delay(int delay)
860 {
861 if (!delay)
862 return;
863
864 if (delay >= 1000)
865 mdelay(delay / 1000);
866
867 udelay(delay % 1000);
868 }
869
870 static void tegra_spi_transfer_end(struct spi_device *spi)
871 {
872 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
873 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
874
875 if (cs_val)
876 tspi->command1_reg |= SPI_CS_SW_VAL;
877 else
878 tspi->command1_reg &= ~SPI_CS_SW_VAL;
879 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
880 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
881 }
882
883 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
884 {
885 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
886 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
887 tegra_spi_readl(tspi, SPI_COMMAND1),
888 tegra_spi_readl(tspi, SPI_COMMAND2));
889 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
890 tegra_spi_readl(tspi, SPI_DMA_CTL),
891 tegra_spi_readl(tspi, SPI_DMA_BLK));
892 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
893 tegra_spi_readl(tspi, SPI_TRANS_STATUS),
894 tegra_spi_readl(tspi, SPI_FIFO_STATUS));
895 }
896
897 static int tegra_spi_transfer_one_message(struct spi_master *master,
898 struct spi_message *msg)
899 {
900 bool is_first_msg = true;
901 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
902 struct spi_transfer *xfer;
903 struct spi_device *spi = msg->spi;
904 int ret;
905 bool skip = false;
906
907 msg->status = 0;
908 msg->actual_length = 0;
909
910 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
911 u32 cmd1;
912
913 reinit_completion(&tspi->xfer_completion);
914
915 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
916
917 if (!xfer->len) {
918 ret = 0;
919 skip = true;
920 goto complete_xfer;
921 }
922
923 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
924 if (ret < 0) {
925 dev_err(tspi->dev,
926 "spi can not start transfer, err %d\n", ret);
927 goto complete_xfer;
928 }
929
930 is_first_msg = false;
931 ret = wait_for_completion_timeout(&tspi->xfer_completion,
932 SPI_DMA_TIMEOUT);
933 if (WARN_ON(ret == 0)) {
934 dev_err(tspi->dev,
935 "spi transfer timeout, err %d\n", ret);
936 if (tspi->is_curr_dma_xfer &&
937 (tspi->cur_direction & DATA_DIR_TX))
938 dmaengine_terminate_all(tspi->tx_dma_chan);
939 if (tspi->is_curr_dma_xfer &&
940 (tspi->cur_direction & DATA_DIR_RX))
941 dmaengine_terminate_all(tspi->rx_dma_chan);
942 ret = -EIO;
943 tegra_spi_dump_regs(tspi);
944 tegra_spi_flush_fifos(tspi);
945 reset_control_assert(tspi->rst);
946 udelay(2);
947 reset_control_deassert(tspi->rst);
948 goto complete_xfer;
949 }
950
951 if (tspi->tx_status || tspi->rx_status) {
952 dev_err(tspi->dev, "Error in Transfer\n");
953 ret = -EIO;
954 tegra_spi_dump_regs(tspi);
955 goto complete_xfer;
956 }
957 msg->actual_length += xfer->len;
958
959 complete_xfer:
960 if (ret < 0 || skip) {
961 tegra_spi_transfer_end(spi);
962 tegra_spi_transfer_delay(xfer->delay_usecs);
963 goto exit;
964 } else if (list_is_last(&xfer->transfer_list,
965 &msg->transfers)) {
966 if (xfer->cs_change)
967 tspi->cs_control = spi;
968 else {
969 tegra_spi_transfer_end(spi);
970 tegra_spi_transfer_delay(xfer->delay_usecs);
971 }
972 } else if (xfer->cs_change) {
973 tegra_spi_transfer_end(spi);
974 tegra_spi_transfer_delay(xfer->delay_usecs);
975 }
976
977 }
978 ret = 0;
979 exit:
980 msg->status = ret;
981 spi_finalize_current_message(master);
982 return ret;
983 }
984
985 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
986 {
987 struct spi_transfer *t = tspi->curr_xfer;
988 unsigned long flags;
989
990 spin_lock_irqsave(&tspi->lock, flags);
991 if (tspi->tx_status || tspi->rx_status) {
992 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
993 tspi->status_reg);
994 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
995 tspi->command1_reg, tspi->dma_control_reg);
996 tegra_spi_dump_regs(tspi);
997 tegra_spi_flush_fifos(tspi);
998 complete(&tspi->xfer_completion);
999 spin_unlock_irqrestore(&tspi->lock, flags);
1000 reset_control_assert(tspi->rst);
1001 udelay(2);
1002 reset_control_deassert(tspi->rst);
1003 return IRQ_HANDLED;
1004 }
1005
1006 if (tspi->cur_direction & DATA_DIR_RX)
1007 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1008
1009 if (tspi->cur_direction & DATA_DIR_TX)
1010 tspi->cur_pos = tspi->cur_tx_pos;
1011 else
1012 tspi->cur_pos = tspi->cur_rx_pos;
1013
1014 if (tspi->cur_pos == t->len) {
1015 complete(&tspi->xfer_completion);
1016 goto exit;
1017 }
1018
1019 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1020 tegra_spi_start_cpu_based_transfer(tspi, t);
1021 exit:
1022 spin_unlock_irqrestore(&tspi->lock, flags);
1023 return IRQ_HANDLED;
1024 }
1025
1026 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1027 {
1028 struct spi_transfer *t = tspi->curr_xfer;
1029 long wait_status;
1030 int err = 0;
1031 unsigned total_fifo_words;
1032 unsigned long flags;
1033
1034 /* Abort dmas if any error */
1035 if (tspi->cur_direction & DATA_DIR_TX) {
1036 if (tspi->tx_status) {
1037 dmaengine_terminate_all(tspi->tx_dma_chan);
1038 err += 1;
1039 } else {
1040 wait_status = wait_for_completion_interruptible_timeout(
1041 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1042 if (wait_status <= 0) {
1043 dmaengine_terminate_all(tspi->tx_dma_chan);
1044 dev_err(tspi->dev, "TxDma Xfer failed\n");
1045 err += 1;
1046 }
1047 }
1048 }
1049
1050 if (tspi->cur_direction & DATA_DIR_RX) {
1051 if (tspi->rx_status) {
1052 dmaengine_terminate_all(tspi->rx_dma_chan);
1053 err += 2;
1054 } else {
1055 wait_status = wait_for_completion_interruptible_timeout(
1056 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1057 if (wait_status <= 0) {
1058 dmaengine_terminate_all(tspi->rx_dma_chan);
1059 dev_err(tspi->dev, "RxDma Xfer failed\n");
1060 err += 2;
1061 }
1062 }
1063 }
1064
1065 spin_lock_irqsave(&tspi->lock, flags);
1066 if (err) {
1067 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1068 tspi->status_reg);
1069 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1070 tspi->command1_reg, tspi->dma_control_reg);
1071 tegra_spi_dump_regs(tspi);
1072 tegra_spi_flush_fifos(tspi);
1073 complete(&tspi->xfer_completion);
1074 spin_unlock_irqrestore(&tspi->lock, flags);
1075 reset_control_assert(tspi->rst);
1076 udelay(2);
1077 reset_control_deassert(tspi->rst);
1078 return IRQ_HANDLED;
1079 }
1080
1081 if (tspi->cur_direction & DATA_DIR_RX)
1082 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1083
1084 if (tspi->cur_direction & DATA_DIR_TX)
1085 tspi->cur_pos = tspi->cur_tx_pos;
1086 else
1087 tspi->cur_pos = tspi->cur_rx_pos;
1088
1089 if (tspi->cur_pos == t->len) {
1090 complete(&tspi->xfer_completion);
1091 goto exit;
1092 }
1093
1094 /* Continue transfer in current message */
1095 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1096 tspi, t);
1097 if (total_fifo_words > SPI_FIFO_DEPTH)
1098 err = tegra_spi_start_dma_based_transfer(tspi, t);
1099 else
1100 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1101
1102 exit:
1103 spin_unlock_irqrestore(&tspi->lock, flags);
1104 return IRQ_HANDLED;
1105 }
1106
1107 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1108 {
1109 struct tegra_spi_data *tspi = context_data;
1110
1111 if (!tspi->is_curr_dma_xfer)
1112 return handle_cpu_based_xfer(tspi);
1113 return handle_dma_based_xfer(tspi);
1114 }
1115
1116 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1117 {
1118 struct tegra_spi_data *tspi = context_data;
1119
1120 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1121 if (tspi->cur_direction & DATA_DIR_TX)
1122 tspi->tx_status = tspi->status_reg &
1123 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1124
1125 if (tspi->cur_direction & DATA_DIR_RX)
1126 tspi->rx_status = tspi->status_reg &
1127 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1128 tegra_spi_clear_status(tspi);
1129
1130 return IRQ_WAKE_THREAD;
1131 }
1132
1133 static const struct of_device_id tegra_spi_of_match[] = {
1134 { .compatible = "nvidia,tegra114-spi", },
1135 {}
1136 };
1137 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1138
1139 static int tegra_spi_probe(struct platform_device *pdev)
1140 {
1141 struct spi_master *master;
1142 struct tegra_spi_data *tspi;
1143 struct resource *r;
1144 int ret, spi_irq;
1145 int bus_num;
1146
1147 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1148 if (!master) {
1149 dev_err(&pdev->dev, "master allocation failed\n");
1150 return -ENOMEM;
1151 }
1152 platform_set_drvdata(pdev, master);
1153 tspi = spi_master_get_devdata(master);
1154
1155 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1156 &master->max_speed_hz))
1157 master->max_speed_hz = 25000000; /* 25MHz */
1158
1159 /* the spi->mode bits understood by this driver: */
1160 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1161 SPI_TX_DUAL | SPI_RX_DUAL;
1162 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1163 master->setup = tegra_spi_setup;
1164 master->transfer_one_message = tegra_spi_transfer_one_message;
1165 master->num_chipselect = MAX_CHIP_SELECT;
1166 master->auto_runtime_pm = true;
1167 bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1168 if (bus_num >= 0)
1169 master->bus_num = bus_num;
1170
1171 tspi->master = master;
1172 tspi->dev = &pdev->dev;
1173 spin_lock_init(&tspi->lock);
1174
1175 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1176 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1177 if (IS_ERR(tspi->base)) {
1178 ret = PTR_ERR(tspi->base);
1179 goto exit_free_master;
1180 }
1181 tspi->phys = r->start;
1182
1183 spi_irq = platform_get_irq(pdev, 0);
1184 tspi->irq = spi_irq;
1185
1186 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1187 if (IS_ERR(tspi->clk)) {
1188 dev_err(&pdev->dev, "can not get clock\n");
1189 ret = PTR_ERR(tspi->clk);
1190 goto exit_free_master;
1191 }
1192
1193 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1194 if (IS_ERR(tspi->rst)) {
1195 dev_err(&pdev->dev, "can not get reset\n");
1196 ret = PTR_ERR(tspi->rst);
1197 goto exit_free_master;
1198 }
1199
1200 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1201 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1202
1203 ret = tegra_spi_init_dma_param(tspi, true);
1204 if (ret < 0)
1205 goto exit_free_master;
1206 ret = tegra_spi_init_dma_param(tspi, false);
1207 if (ret < 0)
1208 goto exit_rx_dma_free;
1209 tspi->max_buf_size = tspi->dma_buf_size;
1210 init_completion(&tspi->tx_dma_complete);
1211 init_completion(&tspi->rx_dma_complete);
1212
1213 init_completion(&tspi->xfer_completion);
1214
1215 pm_runtime_enable(&pdev->dev);
1216 if (!pm_runtime_enabled(&pdev->dev)) {
1217 ret = tegra_spi_runtime_resume(&pdev->dev);
1218 if (ret)
1219 goto exit_pm_disable;
1220 }
1221
1222 ret = pm_runtime_get_sync(&pdev->dev);
1223 if (ret < 0) {
1224 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1225 goto exit_pm_disable;
1226 }
1227
1228 reset_control_assert(tspi->rst);
1229 udelay(2);
1230 reset_control_deassert(tspi->rst);
1231 tspi->def_command1_reg = SPI_M_S;
1232 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1233 pm_runtime_put(&pdev->dev);
1234 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1235 tegra_spi_isr_thread, IRQF_ONESHOT,
1236 dev_name(&pdev->dev), tspi);
1237 if (ret < 0) {
1238 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1239 tspi->irq);
1240 goto exit_pm_disable;
1241 }
1242
1243 master->dev.of_node = pdev->dev.of_node;
1244 ret = devm_spi_register_master(&pdev->dev, master);
1245 if (ret < 0) {
1246 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1247 goto exit_free_irq;
1248 }
1249 return ret;
1250
1251 exit_free_irq:
1252 free_irq(spi_irq, tspi);
1253 exit_pm_disable:
1254 pm_runtime_disable(&pdev->dev);
1255 if (!pm_runtime_status_suspended(&pdev->dev))
1256 tegra_spi_runtime_suspend(&pdev->dev);
1257 tegra_spi_deinit_dma_param(tspi, false);
1258 exit_rx_dma_free:
1259 tegra_spi_deinit_dma_param(tspi, true);
1260 exit_free_master:
1261 spi_master_put(master);
1262 return ret;
1263 }
1264
1265 static int tegra_spi_remove(struct platform_device *pdev)
1266 {
1267 struct spi_master *master = platform_get_drvdata(pdev);
1268 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1269
1270 free_irq(tspi->irq, tspi);
1271
1272 if (tspi->tx_dma_chan)
1273 tegra_spi_deinit_dma_param(tspi, false);
1274
1275 if (tspi->rx_dma_chan)
1276 tegra_spi_deinit_dma_param(tspi, true);
1277
1278 pm_runtime_disable(&pdev->dev);
1279 if (!pm_runtime_status_suspended(&pdev->dev))
1280 tegra_spi_runtime_suspend(&pdev->dev);
1281
1282 return 0;
1283 }
1284
1285 #ifdef CONFIG_PM_SLEEP
1286 static int tegra_spi_suspend(struct device *dev)
1287 {
1288 struct spi_master *master = dev_get_drvdata(dev);
1289
1290 return spi_master_suspend(master);
1291 }
1292
1293 static int tegra_spi_resume(struct device *dev)
1294 {
1295 struct spi_master *master = dev_get_drvdata(dev);
1296 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1297 int ret;
1298
1299 ret = pm_runtime_get_sync(dev);
1300 if (ret < 0) {
1301 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1302 return ret;
1303 }
1304 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1305 pm_runtime_put(dev);
1306
1307 return spi_master_resume(master);
1308 }
1309 #endif
1310
1311 static int tegra_spi_runtime_suspend(struct device *dev)
1312 {
1313 struct spi_master *master = dev_get_drvdata(dev);
1314 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1315
1316 /* Flush all write which are in PPSB queue by reading back */
1317 tegra_spi_readl(tspi, SPI_COMMAND1);
1318
1319 clk_disable_unprepare(tspi->clk);
1320 return 0;
1321 }
1322
1323 static int tegra_spi_runtime_resume(struct device *dev)
1324 {
1325 struct spi_master *master = dev_get_drvdata(dev);
1326 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1327 int ret;
1328
1329 ret = clk_prepare_enable(tspi->clk);
1330 if (ret < 0) {
1331 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1332 return ret;
1333 }
1334 return 0;
1335 }
1336
1337 static const struct dev_pm_ops tegra_spi_pm_ops = {
1338 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1339 tegra_spi_runtime_resume, NULL)
1340 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1341 };
1342 static struct platform_driver tegra_spi_driver = {
1343 .driver = {
1344 .name = "spi-tegra114",
1345 .pm = &tegra_spi_pm_ops,
1346 .of_match_table = tegra_spi_of_match,
1347 },
1348 .probe = tegra_spi_probe,
1349 .remove = tegra_spi_remove,
1350 };
1351 module_platform_driver(tegra_spi_driver);
1352
1353 MODULE_ALIAS("platform:spi-tegra114");
1354 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1355 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1356 MODULE_LICENSE("GPL v2");
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