2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
38 #define SPI_COMMAND1 0x000
39 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SPI_PACKED (1 << 5)
41 #define SPI_TX_EN (1 << 11)
42 #define SPI_RX_EN (1 << 12)
43 #define SPI_BOTH_EN_BYTE (1 << 13)
44 #define SPI_BOTH_EN_BIT (1 << 14)
45 #define SPI_LSBYTE_FE (1 << 15)
46 #define SPI_LSBIT_FE (1 << 16)
47 #define SPI_BIDIROE (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52 #define SPI_IDLE_SDA_MASK (3 << 18)
53 #define SPI_CS_SW_VAL (1 << 20)
54 #define SPI_CS_SW_HW (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
57 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
60 #define SPI_CS_SEL_0 (0 << 26)
61 #define SPI_CS_SEL_1 (1 << 26)
62 #define SPI_CS_SEL_2 (2 << 26)
63 #define SPI_CS_SEL_3 (3 << 26)
64 #define SPI_CS_SEL_MASK (3 << 26)
65 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0 (0 << 28)
67 #define SPI_CONTROL_MODE_1 (1 << 28)
68 #define SPI_CONTROL_MODE_2 (2 << 28)
69 #define SPI_CONTROL_MODE_3 (3 << 28)
70 #define SPI_CONTROL_MODE_MASK (3 << 28)
71 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72 #define SPI_M_S (1 << 30)
73 #define SPI_PIO (1 << 31)
75 #define SPI_COMMAND2 0x004
76 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
79 #define SPI_CS_TIMING1 0x008
80 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
85 #define SPI_CS_TIMING2 0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
101 #define SPI_TRANS_STATUS 0x010
102 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104 #define SPI_RDY (1 << 30)
106 #define SPI_FIFO_STATUS 0x014
107 #define SPI_RX_FIFO_EMPTY (1 << 0)
108 #define SPI_RX_FIFO_FULL (1 << 1)
109 #define SPI_TX_FIFO_EMPTY (1 << 2)
110 #define SPI_TX_FIFO_FULL (1 << 3)
111 #define SPI_RX_FIFO_UNF (1 << 4)
112 #define SPI_RX_FIFO_OVF (1 << 5)
113 #define SPI_TX_FIFO_UNF (1 << 6)
114 #define SPI_TX_FIFO_OVF (1 << 7)
115 #define SPI_ERR (1 << 8)
116 #define SPI_TX_FIFO_FLUSH (1 << 14)
117 #define SPI_RX_FIFO_FLUSH (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END (1 << 30)
121 #define SPI_CS_INACTIVE (1 << 31)
123 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
127 #define SPI_TX_DATA 0x018
128 #define SPI_RX_DATA 0x01C
130 #define SPI_DMA_CTL 0x020
131 #define SPI_TX_TRIG_1 (0 << 15)
132 #define SPI_TX_TRIG_4 (1 << 15)
133 #define SPI_TX_TRIG_8 (2 << 15)
134 #define SPI_TX_TRIG_16 (3 << 15)
135 #define SPI_TX_TRIG_MASK (3 << 15)
136 #define SPI_RX_TRIG_1 (0 << 19)
137 #define SPI_RX_TRIG_4 (1 << 19)
138 #define SPI_RX_TRIG_8 (2 << 19)
139 #define SPI_RX_TRIG_16 (3 << 19)
140 #define SPI_RX_TRIG_MASK (3 << 19)
141 #define SPI_IE_TX (1 << 28)
142 #define SPI_IE_RX (1 << 29)
143 #define SPI_CONT (1 << 30)
144 #define SPI_DMA (1 << 31)
145 #define SPI_DMA_EN SPI_DMA
147 #define SPI_DMA_BLK 0x024
148 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
150 #define SPI_TX_FIFO 0x108
151 #define SPI_RX_FIFO 0x188
152 #define MAX_CHIP_SELECT 4
153 #define SPI_FIFO_DEPTH 64
154 #define DATA_DIR_TX (1 << 0)
155 #define DATA_DIR_RX (1 << 1)
157 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES 16
162 #define SPI_DEFAULT_SPEED 25000000
164 struct tegra_spi_data
{
166 struct spi_master
*master
;
170 struct reset_control
*rst
;
176 struct spi_device
*cur_spi
;
177 struct spi_device
*cs_control
;
179 unsigned words_per_32bit
;
180 unsigned bytes_per_word
;
181 unsigned curr_dma_words
;
182 unsigned cur_direction
;
187 unsigned dma_buf_size
;
188 unsigned max_buf_size
;
189 bool is_curr_dma_xfer
;
191 struct completion rx_dma_complete
;
192 struct completion tx_dma_complete
;
201 u32 def_command1_reg
;
203 struct completion xfer_completion
;
204 struct spi_transfer
*curr_xfer
;
205 struct dma_chan
*rx_dma_chan
;
207 dma_addr_t rx_dma_phys
;
208 struct dma_async_tx_descriptor
*rx_dma_desc
;
210 struct dma_chan
*tx_dma_chan
;
212 dma_addr_t tx_dma_phys
;
213 struct dma_async_tx_descriptor
*tx_dma_desc
;
216 static int tegra_spi_runtime_suspend(struct device
*dev
);
217 static int tegra_spi_runtime_resume(struct device
*dev
);
219 static inline u32
tegra_spi_readl(struct tegra_spi_data
*tspi
,
222 return readl(tspi
->base
+ reg
);
225 static inline void tegra_spi_writel(struct tegra_spi_data
*tspi
,
226 u32 val
, unsigned long reg
)
228 writel(val
, tspi
->base
+ reg
);
230 /* Read back register to make sure that register writes completed */
231 if (reg
!= SPI_TX_FIFO
)
232 readl(tspi
->base
+ SPI_COMMAND1
);
235 static void tegra_spi_clear_status(struct tegra_spi_data
*tspi
)
239 /* Write 1 to clear status register */
240 val
= tegra_spi_readl(tspi
, SPI_TRANS_STATUS
);
241 tegra_spi_writel(tspi
, val
, SPI_TRANS_STATUS
);
243 /* Clear fifo status error if any */
244 val
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
246 tegra_spi_writel(tspi
, SPI_ERR
| SPI_FIFO_ERROR
,
250 static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device
*spi
, struct tegra_spi_data
*tspi
,
252 struct spi_transfer
*t
)
254 unsigned remain_len
= t
->len
- tspi
->cur_pos
;
256 unsigned bits_per_word
= t
->bits_per_word
;
258 unsigned total_fifo_words
;
260 tspi
->bytes_per_word
= DIV_ROUND_UP(bits_per_word
, 8);
262 if (bits_per_word
== 8 || bits_per_word
== 16 || bits_per_word
== 32) {
264 tspi
->words_per_32bit
= 32/bits_per_word
;
267 tspi
->words_per_32bit
= 1;
270 if (tspi
->is_packed
) {
271 max_len
= min(remain_len
, tspi
->max_buf_size
);
272 tspi
->curr_dma_words
= max_len
/tspi
->bytes_per_word
;
273 total_fifo_words
= (max_len
+ 3) / 4;
275 max_word
= (remain_len
- 1) / tspi
->bytes_per_word
+ 1;
276 max_word
= min(max_word
, tspi
->max_buf_size
/4);
277 tspi
->curr_dma_words
= max_word
;
278 total_fifo_words
= max_word
;
280 return total_fifo_words
;
283 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
287 unsigned tx_empty_count
;
289 unsigned max_n_32bit
;
291 unsigned int written_words
;
292 unsigned fifo_words_left
;
293 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
295 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
296 tx_empty_count
= SPI_TX_FIFO_EMPTY_COUNT(fifo_status
);
298 if (tspi
->is_packed
) {
299 fifo_words_left
= tx_empty_count
* tspi
->words_per_32bit
;
300 written_words
= min(fifo_words_left
, tspi
->curr_dma_words
);
301 nbytes
= written_words
* tspi
->bytes_per_word
;
302 max_n_32bit
= DIV_ROUND_UP(nbytes
, 4);
303 for (count
= 0; count
< max_n_32bit
; count
++) {
306 for (i
= 0; (i
< 4) && nbytes
; i
++, nbytes
--)
307 x
|= (u32
)(*tx_buf
++) << (i
* 8);
308 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
311 tspi
->cur_tx_pos
+= written_words
* tspi
->bytes_per_word
;
313 unsigned int write_bytes
;
314 max_n_32bit
= min(tspi
->curr_dma_words
, tx_empty_count
);
315 written_words
= max_n_32bit
;
316 nbytes
= written_words
* tspi
->bytes_per_word
;
317 if (nbytes
> t
->len
- tspi
->cur_pos
)
318 nbytes
= t
->len
- tspi
->cur_pos
;
319 write_bytes
= nbytes
;
320 for (count
= 0; count
< max_n_32bit
; count
++) {
323 for (i
= 0; nbytes
&& (i
< tspi
->bytes_per_word
);
325 x
|= (u32
)(*tx_buf
++) << (i
* 8);
326 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
329 tspi
->cur_tx_pos
+= write_bytes
;
332 return written_words
;
335 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
336 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
338 unsigned rx_full_count
;
341 unsigned int read_words
= 0;
343 u8
*rx_buf
= (u8
*)t
->rx_buf
+ tspi
->cur_rx_pos
;
345 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
346 rx_full_count
= SPI_RX_FIFO_FULL_COUNT(fifo_status
);
347 if (tspi
->is_packed
) {
348 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
349 for (count
= 0; count
< rx_full_count
; count
++) {
350 u32 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
);
352 for (i
= 0; len
&& (i
< 4); i
++, len
--)
353 *rx_buf
++ = (x
>> i
*8) & 0xFF;
355 read_words
+= tspi
->curr_dma_words
;
356 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
358 u32 rx_mask
= ((u32
)1 << t
->bits_per_word
) - 1;
359 u8 bytes_per_word
= tspi
->bytes_per_word
;
360 unsigned int read_bytes
;
362 len
= rx_full_count
* bytes_per_word
;
363 if (len
> t
->len
- tspi
->cur_pos
)
364 len
= t
->len
- tspi
->cur_pos
;
366 for (count
= 0; count
< rx_full_count
; count
++) {
367 u32 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
) & rx_mask
;
369 for (i
= 0; len
&& (i
< bytes_per_word
); i
++, len
--)
370 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
372 read_words
+= rx_full_count
;
373 tspi
->cur_rx_pos
+= read_bytes
;
379 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
380 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
382 /* Make the dma buffer to read by cpu */
383 dma_sync_single_for_cpu(tspi
->dev
, tspi
->tx_dma_phys
,
384 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
386 if (tspi
->is_packed
) {
387 unsigned len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
389 memcpy(tspi
->tx_dma_buf
, t
->tx_buf
+ tspi
->cur_pos
, len
);
390 tspi
->cur_tx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
394 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
395 unsigned consume
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
396 unsigned int write_bytes
;
398 if (consume
> t
->len
- tspi
->cur_pos
)
399 consume
= t
->len
- tspi
->cur_pos
;
400 write_bytes
= consume
;
401 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
404 for (i
= 0; consume
&& (i
< tspi
->bytes_per_word
);
406 x
|= (u32
)(*tx_buf
++) << (i
* 8);
407 tspi
->tx_dma_buf
[count
] = x
;
410 tspi
->cur_tx_pos
+= write_bytes
;
413 /* Make the dma buffer to read by dma */
414 dma_sync_single_for_device(tspi
->dev
, tspi
->tx_dma_phys
,
415 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
418 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
419 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
421 /* Make the dma buffer to read by cpu */
422 dma_sync_single_for_cpu(tspi
->dev
, tspi
->rx_dma_phys
,
423 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
425 if (tspi
->is_packed
) {
426 unsigned len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
428 memcpy(t
->rx_buf
+ tspi
->cur_rx_pos
, tspi
->rx_dma_buf
, len
);
429 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
433 unsigned char *rx_buf
= t
->rx_buf
+ tspi
->cur_rx_pos
;
434 u32 rx_mask
= ((u32
)1 << t
->bits_per_word
) - 1;
435 unsigned consume
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
436 unsigned int read_bytes
;
438 if (consume
> t
->len
- tspi
->cur_pos
)
439 consume
= t
->len
- tspi
->cur_pos
;
440 read_bytes
= consume
;
441 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
442 u32 x
= tspi
->rx_dma_buf
[count
] & rx_mask
;
444 for (i
= 0; consume
&& (i
< tspi
->bytes_per_word
);
446 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
449 tspi
->cur_rx_pos
+= read_bytes
;
452 /* Make the dma buffer to read by dma */
453 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
454 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
457 static void tegra_spi_dma_complete(void *args
)
459 struct completion
*dma_complete
= args
;
461 complete(dma_complete
);
464 static int tegra_spi_start_tx_dma(struct tegra_spi_data
*tspi
, int len
)
466 reinit_completion(&tspi
->tx_dma_complete
);
467 tspi
->tx_dma_desc
= dmaengine_prep_slave_single(tspi
->tx_dma_chan
,
468 tspi
->tx_dma_phys
, len
, DMA_MEM_TO_DEV
,
469 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
470 if (!tspi
->tx_dma_desc
) {
471 dev_err(tspi
->dev
, "Not able to get desc for Tx\n");
475 tspi
->tx_dma_desc
->callback
= tegra_spi_dma_complete
;
476 tspi
->tx_dma_desc
->callback_param
= &tspi
->tx_dma_complete
;
478 dmaengine_submit(tspi
->tx_dma_desc
);
479 dma_async_issue_pending(tspi
->tx_dma_chan
);
483 static int tegra_spi_start_rx_dma(struct tegra_spi_data
*tspi
, int len
)
485 reinit_completion(&tspi
->rx_dma_complete
);
486 tspi
->rx_dma_desc
= dmaengine_prep_slave_single(tspi
->rx_dma_chan
,
487 tspi
->rx_dma_phys
, len
, DMA_DEV_TO_MEM
,
488 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
489 if (!tspi
->rx_dma_desc
) {
490 dev_err(tspi
->dev
, "Not able to get desc for Rx\n");
494 tspi
->rx_dma_desc
->callback
= tegra_spi_dma_complete
;
495 tspi
->rx_dma_desc
->callback_param
= &tspi
->rx_dma_complete
;
497 dmaengine_submit(tspi
->rx_dma_desc
);
498 dma_async_issue_pending(tspi
->rx_dma_chan
);
502 static int tegra_spi_flush_fifos(struct tegra_spi_data
*tspi
)
504 unsigned long timeout
= jiffies
+ HZ
;
507 status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
508 if ((status
& SPI_FIFO_EMPTY
) != SPI_FIFO_EMPTY
) {
509 status
|= SPI_RX_FIFO_FLUSH
| SPI_TX_FIFO_FLUSH
;
510 tegra_spi_writel(tspi
, status
, SPI_FIFO_STATUS
);
511 while ((status
& SPI_FIFO_EMPTY
) != SPI_FIFO_EMPTY
) {
512 status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
513 if (time_after(jiffies
, timeout
)) {
515 "timeout waiting for fifo flush\n");
526 static int tegra_spi_start_dma_based_transfer(
527 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
533 struct dma_slave_config dma_sconfig
= {0};
535 val
= SPI_DMA_BLK_SET(tspi
->curr_dma_words
- 1);
536 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
539 len
= DIV_ROUND_UP(tspi
->curr_dma_words
* tspi
->bytes_per_word
,
542 len
= tspi
->curr_dma_words
* 4;
544 /* Set attention level based on length of transfer */
546 val
|= SPI_TX_TRIG_1
| SPI_RX_TRIG_1
;
548 } else if (((len
) >> 4) & 0x1) {
549 val
|= SPI_TX_TRIG_4
| SPI_RX_TRIG_4
;
552 val
|= SPI_TX_TRIG_8
| SPI_RX_TRIG_8
;
556 if (tspi
->cur_direction
& DATA_DIR_TX
)
559 if (tspi
->cur_direction
& DATA_DIR_RX
)
562 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
563 tspi
->dma_control_reg
= val
;
565 dma_sconfig
.device_fc
= true;
566 if (tspi
->cur_direction
& DATA_DIR_TX
) {
567 dma_sconfig
.dst_addr
= tspi
->phys
+ SPI_TX_FIFO
;
568 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
569 dma_sconfig
.dst_maxburst
= dma_burst
;
570 ret
= dmaengine_slave_config(tspi
->tx_dma_chan
, &dma_sconfig
);
573 "DMA slave config failed: %d\n", ret
);
577 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi
, t
);
578 ret
= tegra_spi_start_tx_dma(tspi
, len
);
581 "Starting tx dma failed, err %d\n", ret
);
586 if (tspi
->cur_direction
& DATA_DIR_RX
) {
587 dma_sconfig
.src_addr
= tspi
->phys
+ SPI_RX_FIFO
;
588 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
589 dma_sconfig
.src_maxburst
= dma_burst
;
590 ret
= dmaengine_slave_config(tspi
->rx_dma_chan
, &dma_sconfig
);
593 "DMA slave config failed: %d\n", ret
);
597 /* Make the dma buffer to read by dma */
598 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
599 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
601 ret
= tegra_spi_start_rx_dma(tspi
, len
);
604 "Starting rx dma failed, err %d\n", ret
);
605 if (tspi
->cur_direction
& DATA_DIR_TX
)
606 dmaengine_terminate_all(tspi
->tx_dma_chan
);
610 tspi
->is_curr_dma_xfer
= true;
611 tspi
->dma_control_reg
= val
;
614 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
618 static int tegra_spi_start_cpu_based_transfer(
619 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
624 if (tspi
->cur_direction
& DATA_DIR_TX
)
625 cur_words
= tegra_spi_fill_tx_fifo_from_client_txbuf(tspi
, t
);
627 cur_words
= tspi
->curr_dma_words
;
629 val
= SPI_DMA_BLK_SET(cur_words
- 1);
630 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
633 if (tspi
->cur_direction
& DATA_DIR_TX
)
636 if (tspi
->cur_direction
& DATA_DIR_RX
)
639 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
640 tspi
->dma_control_reg
= val
;
642 tspi
->is_curr_dma_xfer
= false;
645 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
649 static int tegra_spi_init_dma_param(struct tegra_spi_data
*tspi
,
652 struct dma_chan
*dma_chan
;
657 dma_chan
= dma_request_slave_channel_reason(tspi
->dev
,
658 dma_to_memory
? "rx" : "tx");
659 if (IS_ERR(dma_chan
)) {
660 ret
= PTR_ERR(dma_chan
);
661 if (ret
!= -EPROBE_DEFER
)
663 "Dma channel is not available: %d\n", ret
);
667 dma_buf
= dma_alloc_coherent(tspi
->dev
, tspi
->dma_buf_size
,
668 &dma_phys
, GFP_KERNEL
);
670 dev_err(tspi
->dev
, " Not able to allocate the dma buffer\n");
671 dma_release_channel(dma_chan
);
676 tspi
->rx_dma_chan
= dma_chan
;
677 tspi
->rx_dma_buf
= dma_buf
;
678 tspi
->rx_dma_phys
= dma_phys
;
680 tspi
->tx_dma_chan
= dma_chan
;
681 tspi
->tx_dma_buf
= dma_buf
;
682 tspi
->tx_dma_phys
= dma_phys
;
687 static void tegra_spi_deinit_dma_param(struct tegra_spi_data
*tspi
,
692 struct dma_chan
*dma_chan
;
695 dma_buf
= tspi
->rx_dma_buf
;
696 dma_chan
= tspi
->rx_dma_chan
;
697 dma_phys
= tspi
->rx_dma_phys
;
698 tspi
->rx_dma_chan
= NULL
;
699 tspi
->rx_dma_buf
= NULL
;
701 dma_buf
= tspi
->tx_dma_buf
;
702 dma_chan
= tspi
->tx_dma_chan
;
703 dma_phys
= tspi
->tx_dma_phys
;
704 tspi
->tx_dma_buf
= NULL
;
705 tspi
->tx_dma_chan
= NULL
;
710 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
711 dma_release_channel(dma_chan
);
714 static u32
tegra_spi_setup_transfer_one(struct spi_device
*spi
,
715 struct spi_transfer
*t
, bool is_first_of_msg
)
717 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
718 u32 speed
= t
->speed_hz
;
719 u8 bits_per_word
= t
->bits_per_word
;
723 if (speed
!= tspi
->cur_speed
) {
724 clk_set_rate(tspi
->clk
, speed
);
725 tspi
->cur_speed
= speed
;
730 tspi
->cur_rx_pos
= 0;
731 tspi
->cur_tx_pos
= 0;
734 if (is_first_of_msg
) {
735 tegra_spi_clear_status(tspi
);
737 command1
= tspi
->def_command1_reg
;
738 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
740 command1
&= ~SPI_CONTROL_MODE_MASK
;
741 req_mode
= spi
->mode
& 0x3;
742 if (req_mode
== SPI_MODE_0
)
743 command1
|= SPI_CONTROL_MODE_0
;
744 else if (req_mode
== SPI_MODE_1
)
745 command1
|= SPI_CONTROL_MODE_1
;
746 else if (req_mode
== SPI_MODE_2
)
747 command1
|= SPI_CONTROL_MODE_2
;
748 else if (req_mode
== SPI_MODE_3
)
749 command1
|= SPI_CONTROL_MODE_3
;
751 if (spi
->mode
& SPI_LSB_FIRST
)
752 command1
|= SPI_LSBIT_FE
;
754 command1
&= ~SPI_LSBIT_FE
;
756 if (tspi
->cs_control
) {
757 if (tspi
->cs_control
!= spi
)
758 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
759 tspi
->cs_control
= NULL
;
761 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
763 command1
|= SPI_CS_SW_HW
;
764 if (spi
->mode
& SPI_CS_HIGH
)
765 command1
|= SPI_CS_SW_VAL
;
767 command1
&= ~SPI_CS_SW_VAL
;
769 tegra_spi_writel(tspi
, 0, SPI_COMMAND2
);
771 command1
= tspi
->command1_reg
;
772 command1
&= ~SPI_BIT_LENGTH(~0);
773 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
779 static int tegra_spi_start_transfer_one(struct spi_device
*spi
,
780 struct spi_transfer
*t
, u32 command1
)
782 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
783 unsigned total_fifo_words
;
786 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(spi
, tspi
, t
);
789 command1
|= SPI_PACKED
;
791 command1
&= ~SPI_PACKED
;
793 command1
&= ~(SPI_CS_SEL_MASK
| SPI_TX_EN
| SPI_RX_EN
);
794 tspi
->cur_direction
= 0;
796 command1
|= SPI_RX_EN
;
797 tspi
->cur_direction
|= DATA_DIR_RX
;
800 command1
|= SPI_TX_EN
;
801 tspi
->cur_direction
|= DATA_DIR_TX
;
803 command1
|= SPI_CS_SEL(spi
->chip_select
);
804 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
805 tspi
->command1_reg
= command1
;
807 dev_dbg(tspi
->dev
, "The def 0x%x and written 0x%x\n",
808 tspi
->def_command1_reg
, (unsigned)command1
);
810 ret
= tegra_spi_flush_fifos(tspi
);
813 if (total_fifo_words
> SPI_FIFO_DEPTH
)
814 ret
= tegra_spi_start_dma_based_transfer(tspi
, t
);
816 ret
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
820 static int tegra_spi_setup(struct spi_device
*spi
)
822 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
827 dev_dbg(&spi
->dev
, "setup %d bpw, %scpol, %scpha, %dHz\n",
829 spi
->mode
& SPI_CPOL
? "" : "~",
830 spi
->mode
& SPI_CPHA
? "" : "~",
833 ret
= pm_runtime_get_sync(tspi
->dev
);
835 dev_err(tspi
->dev
, "pm runtime failed, e = %d\n", ret
);
839 spin_lock_irqsave(&tspi
->lock
, flags
);
840 val
= tspi
->def_command1_reg
;
841 if (spi
->mode
& SPI_CS_HIGH
)
842 val
&= ~SPI_CS_POL_INACTIVE(spi
->chip_select
);
844 val
|= SPI_CS_POL_INACTIVE(spi
->chip_select
);
845 tspi
->def_command1_reg
= val
;
846 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
847 spin_unlock_irqrestore(&tspi
->lock
, flags
);
849 pm_runtime_put(tspi
->dev
);
853 static void tegra_spi_transfer_delay(int delay
)
859 mdelay(delay
/ 1000);
861 udelay(delay
% 1000);
864 static void tegra_spi_transfer_end(struct spi_device
*spi
)
866 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
867 int cs_val
= (spi
->mode
& SPI_CS_HIGH
) ? 0 : 1;
870 tspi
->command1_reg
|= SPI_CS_SW_VAL
;
872 tspi
->command1_reg
&= ~SPI_CS_SW_VAL
;
873 tegra_spi_writel(tspi
, tspi
->command1_reg
, SPI_COMMAND1
);
874 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
877 static int tegra_spi_transfer_one_message(struct spi_master
*master
,
878 struct spi_message
*msg
)
880 bool is_first_msg
= true;
881 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
882 struct spi_transfer
*xfer
;
883 struct spi_device
*spi
= msg
->spi
;
888 msg
->actual_length
= 0;
890 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
893 reinit_completion(&tspi
->xfer_completion
);
895 cmd1
= tegra_spi_setup_transfer_one(spi
, xfer
, is_first_msg
);
903 ret
= tegra_spi_start_transfer_one(spi
, xfer
, cmd1
);
906 "spi can not start transfer, err %d\n", ret
);
910 is_first_msg
= false;
911 ret
= wait_for_completion_timeout(&tspi
->xfer_completion
,
913 if (WARN_ON(ret
== 0)) {
915 "spi transfer timeout, err %d\n", ret
);
916 if (tspi
->is_curr_dma_xfer
&&
917 (tspi
->cur_direction
& DATA_DIR_TX
))
918 dmaengine_terminate_all(tspi
->tx_dma_chan
);
919 if (tspi
->is_curr_dma_xfer
&&
920 (tspi
->cur_direction
& DATA_DIR_RX
))
921 dmaengine_terminate_all(tspi
->rx_dma_chan
);
923 tegra_spi_flush_fifos(tspi
);
924 reset_control_assert(tspi
->rst
);
926 reset_control_deassert(tspi
->rst
);
930 if (tspi
->tx_status
|| tspi
->rx_status
) {
931 dev_err(tspi
->dev
, "Error in Transfer\n");
935 msg
->actual_length
+= xfer
->len
;
938 if (ret
< 0 || skip
) {
939 tegra_spi_transfer_end(spi
);
940 tegra_spi_transfer_delay(xfer
->delay_usecs
);
942 } else if (list_is_last(&xfer
->transfer_list
,
945 tspi
->cs_control
= spi
;
947 tegra_spi_transfer_end(spi
);
948 tegra_spi_transfer_delay(xfer
->delay_usecs
);
950 } else if (xfer
->cs_change
) {
951 tegra_spi_transfer_end(spi
);
952 tegra_spi_transfer_delay(xfer
->delay_usecs
);
959 spi_finalize_current_message(master
);
963 static irqreturn_t
handle_cpu_based_xfer(struct tegra_spi_data
*tspi
)
965 struct spi_transfer
*t
= tspi
->curr_xfer
;
968 spin_lock_irqsave(&tspi
->lock
, flags
);
969 if (tspi
->tx_status
|| tspi
->rx_status
) {
970 dev_err(tspi
->dev
, "CpuXfer ERROR bit set 0x%x\n",
972 dev_err(tspi
->dev
, "CpuXfer 0x%08x:0x%08x\n",
973 tspi
->command1_reg
, tspi
->dma_control_reg
);
974 tegra_spi_flush_fifos(tspi
);
975 complete(&tspi
->xfer_completion
);
976 spin_unlock_irqrestore(&tspi
->lock
, flags
);
977 reset_control_assert(tspi
->rst
);
979 reset_control_deassert(tspi
->rst
);
983 if (tspi
->cur_direction
& DATA_DIR_RX
)
984 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi
, t
);
986 if (tspi
->cur_direction
& DATA_DIR_TX
)
987 tspi
->cur_pos
= tspi
->cur_tx_pos
;
989 tspi
->cur_pos
= tspi
->cur_rx_pos
;
991 if (tspi
->cur_pos
== t
->len
) {
992 complete(&tspi
->xfer_completion
);
996 tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
, tspi
, t
);
997 tegra_spi_start_cpu_based_transfer(tspi
, t
);
999 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1003 static irqreturn_t
handle_dma_based_xfer(struct tegra_spi_data
*tspi
)
1005 struct spi_transfer
*t
= tspi
->curr_xfer
;
1008 unsigned total_fifo_words
;
1009 unsigned long flags
;
1011 /* Abort dmas if any error */
1012 if (tspi
->cur_direction
& DATA_DIR_TX
) {
1013 if (tspi
->tx_status
) {
1014 dmaengine_terminate_all(tspi
->tx_dma_chan
);
1017 wait_status
= wait_for_completion_interruptible_timeout(
1018 &tspi
->tx_dma_complete
, SPI_DMA_TIMEOUT
);
1019 if (wait_status
<= 0) {
1020 dmaengine_terminate_all(tspi
->tx_dma_chan
);
1021 dev_err(tspi
->dev
, "TxDma Xfer failed\n");
1027 if (tspi
->cur_direction
& DATA_DIR_RX
) {
1028 if (tspi
->rx_status
) {
1029 dmaengine_terminate_all(tspi
->rx_dma_chan
);
1032 wait_status
= wait_for_completion_interruptible_timeout(
1033 &tspi
->rx_dma_complete
, SPI_DMA_TIMEOUT
);
1034 if (wait_status
<= 0) {
1035 dmaengine_terminate_all(tspi
->rx_dma_chan
);
1036 dev_err(tspi
->dev
, "RxDma Xfer failed\n");
1042 spin_lock_irqsave(&tspi
->lock
, flags
);
1044 dev_err(tspi
->dev
, "DmaXfer: ERROR bit set 0x%x\n",
1046 dev_err(tspi
->dev
, "DmaXfer 0x%08x:0x%08x\n",
1047 tspi
->command1_reg
, tspi
->dma_control_reg
);
1048 tegra_spi_flush_fifos(tspi
);
1049 complete(&tspi
->xfer_completion
);
1050 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1051 reset_control_assert(tspi
->rst
);
1053 reset_control_deassert(tspi
->rst
);
1057 if (tspi
->cur_direction
& DATA_DIR_RX
)
1058 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi
, t
);
1060 if (tspi
->cur_direction
& DATA_DIR_TX
)
1061 tspi
->cur_pos
= tspi
->cur_tx_pos
;
1063 tspi
->cur_pos
= tspi
->cur_rx_pos
;
1065 if (tspi
->cur_pos
== t
->len
) {
1066 complete(&tspi
->xfer_completion
);
1070 /* Continue transfer in current message */
1071 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
,
1073 if (total_fifo_words
> SPI_FIFO_DEPTH
)
1074 err
= tegra_spi_start_dma_based_transfer(tspi
, t
);
1076 err
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
1079 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1083 static irqreturn_t
tegra_spi_isr_thread(int irq
, void *context_data
)
1085 struct tegra_spi_data
*tspi
= context_data
;
1087 if (!tspi
->is_curr_dma_xfer
)
1088 return handle_cpu_based_xfer(tspi
);
1089 return handle_dma_based_xfer(tspi
);
1092 static irqreturn_t
tegra_spi_isr(int irq
, void *context_data
)
1094 struct tegra_spi_data
*tspi
= context_data
;
1096 tspi
->status_reg
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
1097 if (tspi
->cur_direction
& DATA_DIR_TX
)
1098 tspi
->tx_status
= tspi
->status_reg
&
1099 (SPI_TX_FIFO_UNF
| SPI_TX_FIFO_OVF
);
1101 if (tspi
->cur_direction
& DATA_DIR_RX
)
1102 tspi
->rx_status
= tspi
->status_reg
&
1103 (SPI_RX_FIFO_OVF
| SPI_RX_FIFO_UNF
);
1104 tegra_spi_clear_status(tspi
);
1106 return IRQ_WAKE_THREAD
;
1109 static const struct of_device_id tegra_spi_of_match
[] = {
1110 { .compatible
= "nvidia,tegra114-spi", },
1113 MODULE_DEVICE_TABLE(of
, tegra_spi_of_match
);
1115 static int tegra_spi_probe(struct platform_device
*pdev
)
1117 struct spi_master
*master
;
1118 struct tegra_spi_data
*tspi
;
1122 master
= spi_alloc_master(&pdev
->dev
, sizeof(*tspi
));
1124 dev_err(&pdev
->dev
, "master allocation failed\n");
1127 platform_set_drvdata(pdev
, master
);
1128 tspi
= spi_master_get_devdata(master
);
1130 if (of_property_read_u32(pdev
->dev
.of_node
, "spi-max-frequency",
1131 &master
->max_speed_hz
))
1132 master
->max_speed_hz
= 25000000; /* 25MHz */
1134 /* the spi->mode bits understood by this driver: */
1135 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LSB_FIRST
;
1136 master
->setup
= tegra_spi_setup
;
1137 master
->transfer_one_message
= tegra_spi_transfer_one_message
;
1138 master
->num_chipselect
= MAX_CHIP_SELECT
;
1139 master
->auto_runtime_pm
= true;
1141 tspi
->master
= master
;
1142 tspi
->dev
= &pdev
->dev
;
1143 spin_lock_init(&tspi
->lock
);
1145 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1146 tspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1147 if (IS_ERR(tspi
->base
)) {
1148 ret
= PTR_ERR(tspi
->base
);
1149 goto exit_free_master
;
1151 tspi
->phys
= r
->start
;
1153 spi_irq
= platform_get_irq(pdev
, 0);
1154 tspi
->irq
= spi_irq
;
1156 tspi
->clk
= devm_clk_get(&pdev
->dev
, "spi");
1157 if (IS_ERR(tspi
->clk
)) {
1158 dev_err(&pdev
->dev
, "can not get clock\n");
1159 ret
= PTR_ERR(tspi
->clk
);
1160 goto exit_free_master
;
1163 tspi
->rst
= devm_reset_control_get_exclusive(&pdev
->dev
, "spi");
1164 if (IS_ERR(tspi
->rst
)) {
1165 dev_err(&pdev
->dev
, "can not get reset\n");
1166 ret
= PTR_ERR(tspi
->rst
);
1167 goto exit_free_master
;
1170 tspi
->max_buf_size
= SPI_FIFO_DEPTH
<< 2;
1171 tspi
->dma_buf_size
= DEFAULT_SPI_DMA_BUF_LEN
;
1173 ret
= tegra_spi_init_dma_param(tspi
, true);
1175 goto exit_free_master
;
1176 ret
= tegra_spi_init_dma_param(tspi
, false);
1178 goto exit_rx_dma_free
;
1179 tspi
->max_buf_size
= tspi
->dma_buf_size
;
1180 init_completion(&tspi
->tx_dma_complete
);
1181 init_completion(&tspi
->rx_dma_complete
);
1183 init_completion(&tspi
->xfer_completion
);
1185 pm_runtime_enable(&pdev
->dev
);
1186 if (!pm_runtime_enabled(&pdev
->dev
)) {
1187 ret
= tegra_spi_runtime_resume(&pdev
->dev
);
1189 goto exit_pm_disable
;
1192 ret
= pm_runtime_get_sync(&pdev
->dev
);
1194 dev_err(&pdev
->dev
, "pm runtime get failed, e = %d\n", ret
);
1195 goto exit_pm_disable
;
1198 reset_control_assert(tspi
->rst
);
1200 reset_control_deassert(tspi
->rst
);
1201 tspi
->def_command1_reg
= SPI_M_S
;
1202 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
1203 pm_runtime_put(&pdev
->dev
);
1204 ret
= request_threaded_irq(tspi
->irq
, tegra_spi_isr
,
1205 tegra_spi_isr_thread
, IRQF_ONESHOT
,
1206 dev_name(&pdev
->dev
), tspi
);
1208 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
1210 goto exit_pm_disable
;
1213 master
->dev
.of_node
= pdev
->dev
.of_node
;
1214 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1216 dev_err(&pdev
->dev
, "can not register to master err %d\n", ret
);
1222 free_irq(spi_irq
, tspi
);
1224 pm_runtime_disable(&pdev
->dev
);
1225 if (!pm_runtime_status_suspended(&pdev
->dev
))
1226 tegra_spi_runtime_suspend(&pdev
->dev
);
1227 tegra_spi_deinit_dma_param(tspi
, false);
1229 tegra_spi_deinit_dma_param(tspi
, true);
1231 spi_master_put(master
);
1235 static int tegra_spi_remove(struct platform_device
*pdev
)
1237 struct spi_master
*master
= platform_get_drvdata(pdev
);
1238 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1240 free_irq(tspi
->irq
, tspi
);
1242 if (tspi
->tx_dma_chan
)
1243 tegra_spi_deinit_dma_param(tspi
, false);
1245 if (tspi
->rx_dma_chan
)
1246 tegra_spi_deinit_dma_param(tspi
, true);
1248 pm_runtime_disable(&pdev
->dev
);
1249 if (!pm_runtime_status_suspended(&pdev
->dev
))
1250 tegra_spi_runtime_suspend(&pdev
->dev
);
1255 #ifdef CONFIG_PM_SLEEP
1256 static int tegra_spi_suspend(struct device
*dev
)
1258 struct spi_master
*master
= dev_get_drvdata(dev
);
1260 return spi_master_suspend(master
);
1263 static int tegra_spi_resume(struct device
*dev
)
1265 struct spi_master
*master
= dev_get_drvdata(dev
);
1266 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1269 ret
= pm_runtime_get_sync(dev
);
1271 dev_err(dev
, "pm runtime failed, e = %d\n", ret
);
1274 tegra_spi_writel(tspi
, tspi
->command1_reg
, SPI_COMMAND1
);
1275 pm_runtime_put(dev
);
1277 return spi_master_resume(master
);
1281 static int tegra_spi_runtime_suspend(struct device
*dev
)
1283 struct spi_master
*master
= dev_get_drvdata(dev
);
1284 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1286 /* Flush all write which are in PPSB queue by reading back */
1287 tegra_spi_readl(tspi
, SPI_COMMAND1
);
1289 clk_disable_unprepare(tspi
->clk
);
1293 static int tegra_spi_runtime_resume(struct device
*dev
)
1295 struct spi_master
*master
= dev_get_drvdata(dev
);
1296 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1299 ret
= clk_prepare_enable(tspi
->clk
);
1301 dev_err(tspi
->dev
, "clk_prepare failed: %d\n", ret
);
1307 static const struct dev_pm_ops tegra_spi_pm_ops
= {
1308 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend
,
1309 tegra_spi_runtime_resume
, NULL
)
1310 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend
, tegra_spi_resume
)
1312 static struct platform_driver tegra_spi_driver
= {
1314 .name
= "spi-tegra114",
1315 .pm
= &tegra_spi_pm_ops
,
1316 .of_match_table
= tegra_spi_of_match
,
1318 .probe
= tegra_spi_probe
,
1319 .remove
= tegra_spi_remove
,
1321 module_platform_driver(tegra_spi_driver
);
1323 MODULE_ALIAS("platform:spi-tegra114");
1324 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1325 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1326 MODULE_LICENSE("GPL v2");