2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
38 #define SPI_COMMAND1 0x000
39 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SPI_PACKED (1 << 5)
41 #define SPI_TX_EN (1 << 11)
42 #define SPI_RX_EN (1 << 12)
43 #define SPI_BOTH_EN_BYTE (1 << 13)
44 #define SPI_BOTH_EN_BIT (1 << 14)
45 #define SPI_LSBYTE_FE (1 << 15)
46 #define SPI_LSBIT_FE (1 << 16)
47 #define SPI_BIDIROE (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52 #define SPI_IDLE_SDA_MASK (3 << 18)
53 #define SPI_CS_SW_VAL (1 << 20)
54 #define SPI_CS_SW_HW (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
57 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
60 #define SPI_CS_SEL_0 (0 << 26)
61 #define SPI_CS_SEL_1 (1 << 26)
62 #define SPI_CS_SEL_2 (2 << 26)
63 #define SPI_CS_SEL_3 (3 << 26)
64 #define SPI_CS_SEL_MASK (3 << 26)
65 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0 (0 << 28)
67 #define SPI_CONTROL_MODE_1 (1 << 28)
68 #define SPI_CONTROL_MODE_2 (2 << 28)
69 #define SPI_CONTROL_MODE_3 (3 << 28)
70 #define SPI_CONTROL_MODE_MASK (3 << 28)
71 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72 #define SPI_M_S (1 << 30)
73 #define SPI_PIO (1 << 31)
75 #define SPI_COMMAND2 0x004
76 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
79 #define SPI_CS_TIMING1 0x008
80 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
85 #define SPI_CS_TIMING2 0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
101 #define SPI_TRANS_STATUS 0x010
102 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104 #define SPI_RDY (1 << 30)
106 #define SPI_FIFO_STATUS 0x014
107 #define SPI_RX_FIFO_EMPTY (1 << 0)
108 #define SPI_RX_FIFO_FULL (1 << 1)
109 #define SPI_TX_FIFO_EMPTY (1 << 2)
110 #define SPI_TX_FIFO_FULL (1 << 3)
111 #define SPI_RX_FIFO_UNF (1 << 4)
112 #define SPI_RX_FIFO_OVF (1 << 5)
113 #define SPI_TX_FIFO_UNF (1 << 6)
114 #define SPI_TX_FIFO_OVF (1 << 7)
115 #define SPI_ERR (1 << 8)
116 #define SPI_TX_FIFO_FLUSH (1 << 14)
117 #define SPI_RX_FIFO_FLUSH (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END (1 << 30)
121 #define SPI_CS_INACTIVE (1 << 31)
123 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
127 #define SPI_TX_DATA 0x018
128 #define SPI_RX_DATA 0x01C
130 #define SPI_DMA_CTL 0x020
131 #define SPI_TX_TRIG_1 (0 << 15)
132 #define SPI_TX_TRIG_4 (1 << 15)
133 #define SPI_TX_TRIG_8 (2 << 15)
134 #define SPI_TX_TRIG_16 (3 << 15)
135 #define SPI_TX_TRIG_MASK (3 << 15)
136 #define SPI_RX_TRIG_1 (0 << 19)
137 #define SPI_RX_TRIG_4 (1 << 19)
138 #define SPI_RX_TRIG_8 (2 << 19)
139 #define SPI_RX_TRIG_16 (3 << 19)
140 #define SPI_RX_TRIG_MASK (3 << 19)
141 #define SPI_IE_TX (1 << 28)
142 #define SPI_IE_RX (1 << 29)
143 #define SPI_CONT (1 << 30)
144 #define SPI_DMA (1 << 31)
145 #define SPI_DMA_EN SPI_DMA
147 #define SPI_DMA_BLK 0x024
148 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
150 #define SPI_TX_FIFO 0x108
151 #define SPI_RX_FIFO 0x188
152 #define MAX_CHIP_SELECT 4
153 #define SPI_FIFO_DEPTH 64
154 #define DATA_DIR_TX (1 << 0)
155 #define DATA_DIR_RX (1 << 1)
157 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES 16
162 #define SPI_DEFAULT_SPEED 25000000
164 struct tegra_spi_data
{
166 struct spi_master
*master
;
170 struct reset_control
*rst
;
176 struct spi_device
*cur_spi
;
177 struct spi_device
*cs_control
;
179 unsigned words_per_32bit
;
180 unsigned bytes_per_word
;
181 unsigned curr_dma_words
;
182 unsigned cur_direction
;
187 unsigned dma_buf_size
;
188 unsigned max_buf_size
;
189 bool is_curr_dma_xfer
;
191 struct completion rx_dma_complete
;
192 struct completion tx_dma_complete
;
201 u32 def_command1_reg
;
203 struct completion xfer_completion
;
204 struct spi_transfer
*curr_xfer
;
205 struct dma_chan
*rx_dma_chan
;
207 dma_addr_t rx_dma_phys
;
208 struct dma_async_tx_descriptor
*rx_dma_desc
;
210 struct dma_chan
*tx_dma_chan
;
212 dma_addr_t tx_dma_phys
;
213 struct dma_async_tx_descriptor
*tx_dma_desc
;
216 static int tegra_spi_runtime_suspend(struct device
*dev
);
217 static int tegra_spi_runtime_resume(struct device
*dev
);
219 static inline u32
tegra_spi_readl(struct tegra_spi_data
*tspi
,
222 return readl(tspi
->base
+ reg
);
225 static inline void tegra_spi_writel(struct tegra_spi_data
*tspi
,
226 u32 val
, unsigned long reg
)
228 writel(val
, tspi
->base
+ reg
);
230 /* Read back register to make sure that register writes completed */
231 if (reg
!= SPI_TX_FIFO
)
232 readl(tspi
->base
+ SPI_COMMAND1
);
235 static void tegra_spi_clear_status(struct tegra_spi_data
*tspi
)
239 /* Write 1 to clear status register */
240 val
= tegra_spi_readl(tspi
, SPI_TRANS_STATUS
);
241 tegra_spi_writel(tspi
, val
, SPI_TRANS_STATUS
);
243 /* Clear fifo status error if any */
244 val
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
246 tegra_spi_writel(tspi
, SPI_ERR
| SPI_FIFO_ERROR
,
250 static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device
*spi
, struct tegra_spi_data
*tspi
,
252 struct spi_transfer
*t
)
254 unsigned remain_len
= t
->len
- tspi
->cur_pos
;
256 unsigned bits_per_word
= t
->bits_per_word
;
258 unsigned total_fifo_words
;
260 tspi
->bytes_per_word
= DIV_ROUND_UP(bits_per_word
, 8);
262 if (bits_per_word
== 8 || bits_per_word
== 16) {
264 tspi
->words_per_32bit
= 32/bits_per_word
;
267 tspi
->words_per_32bit
= 1;
270 if (tspi
->is_packed
) {
271 max_len
= min(remain_len
, tspi
->max_buf_size
);
272 tspi
->curr_dma_words
= max_len
/tspi
->bytes_per_word
;
273 total_fifo_words
= (max_len
+ 3) / 4;
275 max_word
= (remain_len
- 1) / tspi
->bytes_per_word
+ 1;
276 max_word
= min(max_word
, tspi
->max_buf_size
/4);
277 tspi
->curr_dma_words
= max_word
;
278 total_fifo_words
= max_word
;
280 return total_fifo_words
;
283 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
287 unsigned tx_empty_count
;
289 unsigned max_n_32bit
;
291 unsigned int written_words
;
292 unsigned fifo_words_left
;
293 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
295 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
296 tx_empty_count
= SPI_TX_FIFO_EMPTY_COUNT(fifo_status
);
298 if (tspi
->is_packed
) {
299 fifo_words_left
= tx_empty_count
* tspi
->words_per_32bit
;
300 written_words
= min(fifo_words_left
, tspi
->curr_dma_words
);
301 nbytes
= written_words
* tspi
->bytes_per_word
;
302 max_n_32bit
= DIV_ROUND_UP(nbytes
, 4);
303 for (count
= 0; count
< max_n_32bit
; count
++) {
306 for (i
= 0; (i
< 4) && nbytes
; i
++, nbytes
--)
307 x
|= (u32
)(*tx_buf
++) << (i
* 8);
308 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
311 max_n_32bit
= min(tspi
->curr_dma_words
, tx_empty_count
);
312 written_words
= max_n_32bit
;
313 nbytes
= written_words
* tspi
->bytes_per_word
;
314 for (count
= 0; count
< max_n_32bit
; count
++) {
317 for (i
= 0; nbytes
&& (i
< tspi
->bytes_per_word
);
319 x
|= (u32
)(*tx_buf
++) << (i
* 8);
320 tegra_spi_writel(tspi
, x
, SPI_TX_FIFO
);
323 tspi
->cur_tx_pos
+= written_words
* tspi
->bytes_per_word
;
324 return written_words
;
327 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
328 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
330 unsigned rx_full_count
;
333 unsigned int read_words
= 0;
335 u8
*rx_buf
= (u8
*)t
->rx_buf
+ tspi
->cur_rx_pos
;
337 fifo_status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
338 rx_full_count
= SPI_RX_FIFO_FULL_COUNT(fifo_status
);
339 if (tspi
->is_packed
) {
340 len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
341 for (count
= 0; count
< rx_full_count
; count
++) {
342 u32 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
);
344 for (i
= 0; len
&& (i
< 4); i
++, len
--)
345 *rx_buf
++ = (x
>> i
*8) & 0xFF;
347 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
348 read_words
+= tspi
->curr_dma_words
;
350 u32 rx_mask
= ((u32
)1 << t
->bits_per_word
) - 1;
352 for (count
= 0; count
< rx_full_count
; count
++) {
353 u32 x
= tegra_spi_readl(tspi
, SPI_RX_FIFO
) & rx_mask
;
355 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
356 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
358 tspi
->cur_rx_pos
+= rx_full_count
* tspi
->bytes_per_word
;
359 read_words
+= rx_full_count
;
364 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
365 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
367 /* Make the dma buffer to read by cpu */
368 dma_sync_single_for_cpu(tspi
->dev
, tspi
->tx_dma_phys
,
369 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
371 if (tspi
->is_packed
) {
372 unsigned len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
374 memcpy(tspi
->tx_dma_buf
, t
->tx_buf
+ tspi
->cur_pos
, len
);
378 u8
*tx_buf
= (u8
*)t
->tx_buf
+ tspi
->cur_tx_pos
;
379 unsigned consume
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
381 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
384 for (i
= 0; consume
&& (i
< tspi
->bytes_per_word
);
386 x
|= (u32
)(*tx_buf
++) << (i
* 8);
387 tspi
->tx_dma_buf
[count
] = x
;
390 tspi
->cur_tx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
392 /* Make the dma buffer to read by dma */
393 dma_sync_single_for_device(tspi
->dev
, tspi
->tx_dma_phys
,
394 tspi
->dma_buf_size
, DMA_TO_DEVICE
);
397 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
398 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
400 /* Make the dma buffer to read by cpu */
401 dma_sync_single_for_cpu(tspi
->dev
, tspi
->rx_dma_phys
,
402 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
404 if (tspi
->is_packed
) {
405 unsigned len
= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
407 memcpy(t
->rx_buf
+ tspi
->cur_rx_pos
, tspi
->rx_dma_buf
, len
);
411 unsigned char *rx_buf
= t
->rx_buf
+ tspi
->cur_rx_pos
;
412 u32 rx_mask
= ((u32
)1 << t
->bits_per_word
) - 1;
414 for (count
= 0; count
< tspi
->curr_dma_words
; count
++) {
415 u32 x
= tspi
->rx_dma_buf
[count
] & rx_mask
;
417 for (i
= 0; (i
< tspi
->bytes_per_word
); i
++)
418 *rx_buf
++ = (x
>> (i
*8)) & 0xFF;
421 tspi
->cur_rx_pos
+= tspi
->curr_dma_words
* tspi
->bytes_per_word
;
423 /* Make the dma buffer to read by dma */
424 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
425 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
428 static void tegra_spi_dma_complete(void *args
)
430 struct completion
*dma_complete
= args
;
432 complete(dma_complete
);
435 static int tegra_spi_start_tx_dma(struct tegra_spi_data
*tspi
, int len
)
437 reinit_completion(&tspi
->tx_dma_complete
);
438 tspi
->tx_dma_desc
= dmaengine_prep_slave_single(tspi
->tx_dma_chan
,
439 tspi
->tx_dma_phys
, len
, DMA_MEM_TO_DEV
,
440 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
441 if (!tspi
->tx_dma_desc
) {
442 dev_err(tspi
->dev
, "Not able to get desc for Tx\n");
446 tspi
->tx_dma_desc
->callback
= tegra_spi_dma_complete
;
447 tspi
->tx_dma_desc
->callback_param
= &tspi
->tx_dma_complete
;
449 dmaengine_submit(tspi
->tx_dma_desc
);
450 dma_async_issue_pending(tspi
->tx_dma_chan
);
454 static int tegra_spi_start_rx_dma(struct tegra_spi_data
*tspi
, int len
)
456 reinit_completion(&tspi
->rx_dma_complete
);
457 tspi
->rx_dma_desc
= dmaengine_prep_slave_single(tspi
->rx_dma_chan
,
458 tspi
->rx_dma_phys
, len
, DMA_DEV_TO_MEM
,
459 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
460 if (!tspi
->rx_dma_desc
) {
461 dev_err(tspi
->dev
, "Not able to get desc for Rx\n");
465 tspi
->rx_dma_desc
->callback
= tegra_spi_dma_complete
;
466 tspi
->rx_dma_desc
->callback_param
= &tspi
->rx_dma_complete
;
468 dmaengine_submit(tspi
->rx_dma_desc
);
469 dma_async_issue_pending(tspi
->rx_dma_chan
);
473 static int tegra_spi_start_dma_based_transfer(
474 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
481 /* Make sure that Rx and Tx fifo are empty */
482 status
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
483 if ((status
& SPI_FIFO_EMPTY
) != SPI_FIFO_EMPTY
) {
484 dev_err(tspi
->dev
, "Rx/Tx fifo are not empty status 0x%08x\n",
489 val
= SPI_DMA_BLK_SET(tspi
->curr_dma_words
- 1);
490 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
493 len
= DIV_ROUND_UP(tspi
->curr_dma_words
* tspi
->bytes_per_word
,
496 len
= tspi
->curr_dma_words
* 4;
498 /* Set attention level based on length of transfer */
500 val
|= SPI_TX_TRIG_1
| SPI_RX_TRIG_1
;
501 else if (((len
) >> 4) & 0x1)
502 val
|= SPI_TX_TRIG_4
| SPI_RX_TRIG_4
;
504 val
|= SPI_TX_TRIG_8
| SPI_RX_TRIG_8
;
506 if (tspi
->cur_direction
& DATA_DIR_TX
)
509 if (tspi
->cur_direction
& DATA_DIR_RX
)
512 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
513 tspi
->dma_control_reg
= val
;
515 if (tspi
->cur_direction
& DATA_DIR_TX
) {
516 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi
, t
);
517 ret
= tegra_spi_start_tx_dma(tspi
, len
);
520 "Starting tx dma failed, err %d\n", ret
);
525 if (tspi
->cur_direction
& DATA_DIR_RX
) {
526 /* Make the dma buffer to read by dma */
527 dma_sync_single_for_device(tspi
->dev
, tspi
->rx_dma_phys
,
528 tspi
->dma_buf_size
, DMA_FROM_DEVICE
);
530 ret
= tegra_spi_start_rx_dma(tspi
, len
);
533 "Starting rx dma failed, err %d\n", ret
);
534 if (tspi
->cur_direction
& DATA_DIR_TX
)
535 dmaengine_terminate_all(tspi
->tx_dma_chan
);
539 tspi
->is_curr_dma_xfer
= true;
540 tspi
->dma_control_reg
= val
;
543 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
547 static int tegra_spi_start_cpu_based_transfer(
548 struct tegra_spi_data
*tspi
, struct spi_transfer
*t
)
553 if (tspi
->cur_direction
& DATA_DIR_TX
)
554 cur_words
= tegra_spi_fill_tx_fifo_from_client_txbuf(tspi
, t
);
556 cur_words
= tspi
->curr_dma_words
;
558 val
= SPI_DMA_BLK_SET(cur_words
- 1);
559 tegra_spi_writel(tspi
, val
, SPI_DMA_BLK
);
562 if (tspi
->cur_direction
& DATA_DIR_TX
)
565 if (tspi
->cur_direction
& DATA_DIR_RX
)
568 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
569 tspi
->dma_control_reg
= val
;
571 tspi
->is_curr_dma_xfer
= false;
574 tegra_spi_writel(tspi
, val
, SPI_DMA_CTL
);
578 static int tegra_spi_init_dma_param(struct tegra_spi_data
*tspi
,
581 struct dma_chan
*dma_chan
;
585 struct dma_slave_config dma_sconfig
;
587 dma_chan
= dma_request_slave_channel_reason(tspi
->dev
,
588 dma_to_memory
? "rx" : "tx");
589 if (IS_ERR(dma_chan
)) {
590 ret
= PTR_ERR(dma_chan
);
591 if (ret
!= -EPROBE_DEFER
)
593 "Dma channel is not available: %d\n", ret
);
597 dma_buf
= dma_alloc_coherent(tspi
->dev
, tspi
->dma_buf_size
,
598 &dma_phys
, GFP_KERNEL
);
600 dev_err(tspi
->dev
, " Not able to allocate the dma buffer\n");
601 dma_release_channel(dma_chan
);
606 dma_sconfig
.src_addr
= tspi
->phys
+ SPI_RX_FIFO
;
607 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
608 dma_sconfig
.src_maxburst
= 0;
610 dma_sconfig
.dst_addr
= tspi
->phys
+ SPI_TX_FIFO
;
611 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
612 dma_sconfig
.dst_maxburst
= 0;
615 ret
= dmaengine_slave_config(dma_chan
, &dma_sconfig
);
619 tspi
->rx_dma_chan
= dma_chan
;
620 tspi
->rx_dma_buf
= dma_buf
;
621 tspi
->rx_dma_phys
= dma_phys
;
623 tspi
->tx_dma_chan
= dma_chan
;
624 tspi
->tx_dma_buf
= dma_buf
;
625 tspi
->tx_dma_phys
= dma_phys
;
630 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
631 dma_release_channel(dma_chan
);
635 static void tegra_spi_deinit_dma_param(struct tegra_spi_data
*tspi
,
640 struct dma_chan
*dma_chan
;
643 dma_buf
= tspi
->rx_dma_buf
;
644 dma_chan
= tspi
->rx_dma_chan
;
645 dma_phys
= tspi
->rx_dma_phys
;
646 tspi
->rx_dma_chan
= NULL
;
647 tspi
->rx_dma_buf
= NULL
;
649 dma_buf
= tspi
->tx_dma_buf
;
650 dma_chan
= tspi
->tx_dma_chan
;
651 dma_phys
= tspi
->tx_dma_phys
;
652 tspi
->tx_dma_buf
= NULL
;
653 tspi
->tx_dma_chan
= NULL
;
658 dma_free_coherent(tspi
->dev
, tspi
->dma_buf_size
, dma_buf
, dma_phys
);
659 dma_release_channel(dma_chan
);
662 static u32
tegra_spi_setup_transfer_one(struct spi_device
*spi
,
663 struct spi_transfer
*t
, bool is_first_of_msg
)
665 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
666 u32 speed
= t
->speed_hz
;
667 u8 bits_per_word
= t
->bits_per_word
;
671 if (speed
!= tspi
->cur_speed
) {
672 clk_set_rate(tspi
->clk
, speed
);
673 tspi
->cur_speed
= speed
;
678 tspi
->cur_rx_pos
= 0;
679 tspi
->cur_tx_pos
= 0;
682 if (is_first_of_msg
) {
683 tegra_spi_clear_status(tspi
);
685 command1
= tspi
->def_command1_reg
;
686 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
688 command1
&= ~SPI_CONTROL_MODE_MASK
;
689 req_mode
= spi
->mode
& 0x3;
690 if (req_mode
== SPI_MODE_0
)
691 command1
|= SPI_CONTROL_MODE_0
;
692 else if (req_mode
== SPI_MODE_1
)
693 command1
|= SPI_CONTROL_MODE_1
;
694 else if (req_mode
== SPI_MODE_2
)
695 command1
|= SPI_CONTROL_MODE_2
;
696 else if (req_mode
== SPI_MODE_3
)
697 command1
|= SPI_CONTROL_MODE_3
;
699 if (tspi
->cs_control
) {
700 if (tspi
->cs_control
!= spi
)
701 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
702 tspi
->cs_control
= NULL
;
704 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
706 command1
|= SPI_CS_SW_HW
;
707 if (spi
->mode
& SPI_CS_HIGH
)
708 command1
|= SPI_CS_SW_VAL
;
710 command1
&= ~SPI_CS_SW_VAL
;
712 tegra_spi_writel(tspi
, 0, SPI_COMMAND2
);
714 command1
= tspi
->command1_reg
;
715 command1
&= ~SPI_BIT_LENGTH(~0);
716 command1
|= SPI_BIT_LENGTH(bits_per_word
- 1);
722 static int tegra_spi_start_transfer_one(struct spi_device
*spi
,
723 struct spi_transfer
*t
, u32 command1
)
725 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
726 unsigned total_fifo_words
;
729 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(spi
, tspi
, t
);
732 command1
|= SPI_PACKED
;
734 command1
&= ~SPI_PACKED
;
736 command1
&= ~(SPI_CS_SEL_MASK
| SPI_TX_EN
| SPI_RX_EN
);
737 tspi
->cur_direction
= 0;
739 command1
|= SPI_RX_EN
;
740 tspi
->cur_direction
|= DATA_DIR_RX
;
743 command1
|= SPI_TX_EN
;
744 tspi
->cur_direction
|= DATA_DIR_TX
;
746 command1
|= SPI_CS_SEL(spi
->chip_select
);
747 tegra_spi_writel(tspi
, command1
, SPI_COMMAND1
);
748 tspi
->command1_reg
= command1
;
750 dev_dbg(tspi
->dev
, "The def 0x%x and written 0x%x\n",
751 tspi
->def_command1_reg
, (unsigned)command1
);
753 if (total_fifo_words
> SPI_FIFO_DEPTH
)
754 ret
= tegra_spi_start_dma_based_transfer(tspi
, t
);
756 ret
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
760 static int tegra_spi_setup(struct spi_device
*spi
)
762 struct tegra_spi_data
*tspi
= spi_master_get_devdata(spi
->master
);
767 dev_dbg(&spi
->dev
, "setup %d bpw, %scpol, %scpha, %dHz\n",
769 spi
->mode
& SPI_CPOL
? "" : "~",
770 spi
->mode
& SPI_CPHA
? "" : "~",
773 ret
= pm_runtime_get_sync(tspi
->dev
);
775 dev_err(tspi
->dev
, "pm runtime failed, e = %d\n", ret
);
779 spin_lock_irqsave(&tspi
->lock
, flags
);
780 val
= tspi
->def_command1_reg
;
781 if (spi
->mode
& SPI_CS_HIGH
)
782 val
&= ~SPI_CS_POL_INACTIVE(spi
->chip_select
);
784 val
|= SPI_CS_POL_INACTIVE(spi
->chip_select
);
785 tspi
->def_command1_reg
= val
;
786 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
787 spin_unlock_irqrestore(&tspi
->lock
, flags
);
789 pm_runtime_put(tspi
->dev
);
793 static void tegra_spi_transfer_delay(int delay
)
799 mdelay(delay
/ 1000);
801 udelay(delay
% 1000);
804 static int tegra_spi_transfer_one_message(struct spi_master
*master
,
805 struct spi_message
*msg
)
807 bool is_first_msg
= true;
808 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
809 struct spi_transfer
*xfer
;
810 struct spi_device
*spi
= msg
->spi
;
815 msg
->actual_length
= 0;
817 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
820 reinit_completion(&tspi
->xfer_completion
);
822 cmd1
= tegra_spi_setup_transfer_one(spi
, xfer
, is_first_msg
);
830 ret
= tegra_spi_start_transfer_one(spi
, xfer
, cmd1
);
833 "spi can not start transfer, err %d\n", ret
);
837 is_first_msg
= false;
838 ret
= wait_for_completion_timeout(&tspi
->xfer_completion
,
840 if (WARN_ON(ret
== 0)) {
842 "spi transfer timeout, err %d\n", ret
);
847 if (tspi
->tx_status
|| tspi
->rx_status
) {
848 dev_err(tspi
->dev
, "Error in Transfer\n");
852 msg
->actual_length
+= xfer
->len
;
855 if (ret
< 0 || skip
) {
856 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
858 tegra_spi_transfer_delay(xfer
->delay_usecs
);
860 } else if (list_is_last(&xfer
->transfer_list
,
863 tspi
->cs_control
= spi
;
865 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
867 tegra_spi_transfer_delay(xfer
->delay_usecs
);
869 } else if (xfer
->cs_change
) {
870 tegra_spi_writel(tspi
, tspi
->def_command1_reg
,
872 tegra_spi_transfer_delay(xfer
->delay_usecs
);
879 spi_finalize_current_message(master
);
883 static irqreturn_t
handle_cpu_based_xfer(struct tegra_spi_data
*tspi
)
885 struct spi_transfer
*t
= tspi
->curr_xfer
;
888 spin_lock_irqsave(&tspi
->lock
, flags
);
889 if (tspi
->tx_status
|| tspi
->rx_status
) {
890 dev_err(tspi
->dev
, "CpuXfer ERROR bit set 0x%x\n",
892 dev_err(tspi
->dev
, "CpuXfer 0x%08x:0x%08x\n",
893 tspi
->command1_reg
, tspi
->dma_control_reg
);
894 reset_control_assert(tspi
->rst
);
896 reset_control_deassert(tspi
->rst
);
897 complete(&tspi
->xfer_completion
);
901 if (tspi
->cur_direction
& DATA_DIR_RX
)
902 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi
, t
);
904 if (tspi
->cur_direction
& DATA_DIR_TX
)
905 tspi
->cur_pos
= tspi
->cur_tx_pos
;
907 tspi
->cur_pos
= tspi
->cur_rx_pos
;
909 if (tspi
->cur_pos
== t
->len
) {
910 complete(&tspi
->xfer_completion
);
914 tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
, tspi
, t
);
915 tegra_spi_start_cpu_based_transfer(tspi
, t
);
917 spin_unlock_irqrestore(&tspi
->lock
, flags
);
921 static irqreturn_t
handle_dma_based_xfer(struct tegra_spi_data
*tspi
)
923 struct spi_transfer
*t
= tspi
->curr_xfer
;
926 unsigned total_fifo_words
;
929 /* Abort dmas if any error */
930 if (tspi
->cur_direction
& DATA_DIR_TX
) {
931 if (tspi
->tx_status
) {
932 dmaengine_terminate_all(tspi
->tx_dma_chan
);
935 wait_status
= wait_for_completion_interruptible_timeout(
936 &tspi
->tx_dma_complete
, SPI_DMA_TIMEOUT
);
937 if (wait_status
<= 0) {
938 dmaengine_terminate_all(tspi
->tx_dma_chan
);
939 dev_err(tspi
->dev
, "TxDma Xfer failed\n");
945 if (tspi
->cur_direction
& DATA_DIR_RX
) {
946 if (tspi
->rx_status
) {
947 dmaengine_terminate_all(tspi
->rx_dma_chan
);
950 wait_status
= wait_for_completion_interruptible_timeout(
951 &tspi
->rx_dma_complete
, SPI_DMA_TIMEOUT
);
952 if (wait_status
<= 0) {
953 dmaengine_terminate_all(tspi
->rx_dma_chan
);
954 dev_err(tspi
->dev
, "RxDma Xfer failed\n");
960 spin_lock_irqsave(&tspi
->lock
, flags
);
962 dev_err(tspi
->dev
, "DmaXfer: ERROR bit set 0x%x\n",
964 dev_err(tspi
->dev
, "DmaXfer 0x%08x:0x%08x\n",
965 tspi
->command1_reg
, tspi
->dma_control_reg
);
966 reset_control_assert(tspi
->rst
);
968 reset_control_deassert(tspi
->rst
);
969 complete(&tspi
->xfer_completion
);
970 spin_unlock_irqrestore(&tspi
->lock
, flags
);
974 if (tspi
->cur_direction
& DATA_DIR_RX
)
975 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi
, t
);
977 if (tspi
->cur_direction
& DATA_DIR_TX
)
978 tspi
->cur_pos
= tspi
->cur_tx_pos
;
980 tspi
->cur_pos
= tspi
->cur_rx_pos
;
982 if (tspi
->cur_pos
== t
->len
) {
983 complete(&tspi
->xfer_completion
);
987 /* Continue transfer in current message */
988 total_fifo_words
= tegra_spi_calculate_curr_xfer_param(tspi
->cur_spi
,
990 if (total_fifo_words
> SPI_FIFO_DEPTH
)
991 err
= tegra_spi_start_dma_based_transfer(tspi
, t
);
993 err
= tegra_spi_start_cpu_based_transfer(tspi
, t
);
996 spin_unlock_irqrestore(&tspi
->lock
, flags
);
1000 static irqreturn_t
tegra_spi_isr_thread(int irq
, void *context_data
)
1002 struct tegra_spi_data
*tspi
= context_data
;
1004 if (!tspi
->is_curr_dma_xfer
)
1005 return handle_cpu_based_xfer(tspi
);
1006 return handle_dma_based_xfer(tspi
);
1009 static irqreturn_t
tegra_spi_isr(int irq
, void *context_data
)
1011 struct tegra_spi_data
*tspi
= context_data
;
1013 tspi
->status_reg
= tegra_spi_readl(tspi
, SPI_FIFO_STATUS
);
1014 if (tspi
->cur_direction
& DATA_DIR_TX
)
1015 tspi
->tx_status
= tspi
->status_reg
&
1016 (SPI_TX_FIFO_UNF
| SPI_TX_FIFO_OVF
);
1018 if (tspi
->cur_direction
& DATA_DIR_RX
)
1019 tspi
->rx_status
= tspi
->status_reg
&
1020 (SPI_RX_FIFO_OVF
| SPI_RX_FIFO_UNF
);
1021 tegra_spi_clear_status(tspi
);
1023 return IRQ_WAKE_THREAD
;
1026 static const struct of_device_id tegra_spi_of_match
[] = {
1027 { .compatible
= "nvidia,tegra114-spi", },
1030 MODULE_DEVICE_TABLE(of
, tegra_spi_of_match
);
1032 static int tegra_spi_probe(struct platform_device
*pdev
)
1034 struct spi_master
*master
;
1035 struct tegra_spi_data
*tspi
;
1039 master
= spi_alloc_master(&pdev
->dev
, sizeof(*tspi
));
1041 dev_err(&pdev
->dev
, "master allocation failed\n");
1044 platform_set_drvdata(pdev
, master
);
1045 tspi
= spi_master_get_devdata(master
);
1047 if (of_property_read_u32(pdev
->dev
.of_node
, "spi-max-frequency",
1048 &master
->max_speed_hz
))
1049 master
->max_speed_hz
= 25000000; /* 25MHz */
1051 /* the spi->mode bits understood by this driver: */
1052 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1053 master
->setup
= tegra_spi_setup
;
1054 master
->transfer_one_message
= tegra_spi_transfer_one_message
;
1055 master
->num_chipselect
= MAX_CHIP_SELECT
;
1056 master
->auto_runtime_pm
= true;
1058 tspi
->master
= master
;
1059 tspi
->dev
= &pdev
->dev
;
1060 spin_lock_init(&tspi
->lock
);
1062 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1063 tspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1064 if (IS_ERR(tspi
->base
)) {
1065 ret
= PTR_ERR(tspi
->base
);
1066 goto exit_free_master
;
1068 tspi
->phys
= r
->start
;
1070 spi_irq
= platform_get_irq(pdev
, 0);
1071 tspi
->irq
= spi_irq
;
1073 tspi
->clk
= devm_clk_get(&pdev
->dev
, "spi");
1074 if (IS_ERR(tspi
->clk
)) {
1075 dev_err(&pdev
->dev
, "can not get clock\n");
1076 ret
= PTR_ERR(tspi
->clk
);
1077 goto exit_free_master
;
1080 tspi
->rst
= devm_reset_control_get_exclusive(&pdev
->dev
, "spi");
1081 if (IS_ERR(tspi
->rst
)) {
1082 dev_err(&pdev
->dev
, "can not get reset\n");
1083 ret
= PTR_ERR(tspi
->rst
);
1084 goto exit_free_master
;
1087 tspi
->max_buf_size
= SPI_FIFO_DEPTH
<< 2;
1088 tspi
->dma_buf_size
= DEFAULT_SPI_DMA_BUF_LEN
;
1090 ret
= tegra_spi_init_dma_param(tspi
, true);
1092 goto exit_free_master
;
1093 ret
= tegra_spi_init_dma_param(tspi
, false);
1095 goto exit_rx_dma_free
;
1096 tspi
->max_buf_size
= tspi
->dma_buf_size
;
1097 init_completion(&tspi
->tx_dma_complete
);
1098 init_completion(&tspi
->rx_dma_complete
);
1100 init_completion(&tspi
->xfer_completion
);
1102 pm_runtime_enable(&pdev
->dev
);
1103 if (!pm_runtime_enabled(&pdev
->dev
)) {
1104 ret
= tegra_spi_runtime_resume(&pdev
->dev
);
1106 goto exit_pm_disable
;
1109 ret
= pm_runtime_get_sync(&pdev
->dev
);
1111 dev_err(&pdev
->dev
, "pm runtime get failed, e = %d\n", ret
);
1112 goto exit_pm_disable
;
1115 reset_control_assert(tspi
->rst
);
1117 reset_control_deassert(tspi
->rst
);
1118 tspi
->def_command1_reg
= SPI_M_S
;
1119 tegra_spi_writel(tspi
, tspi
->def_command1_reg
, SPI_COMMAND1
);
1120 pm_runtime_put(&pdev
->dev
);
1121 ret
= request_threaded_irq(tspi
->irq
, tegra_spi_isr
,
1122 tegra_spi_isr_thread
, IRQF_ONESHOT
,
1123 dev_name(&pdev
->dev
), tspi
);
1125 dev_err(&pdev
->dev
, "Failed to register ISR for IRQ %d\n",
1127 goto exit_pm_disable
;
1130 master
->dev
.of_node
= pdev
->dev
.of_node
;
1131 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1133 dev_err(&pdev
->dev
, "can not register to master err %d\n", ret
);
1139 free_irq(spi_irq
, tspi
);
1141 pm_runtime_disable(&pdev
->dev
);
1142 if (!pm_runtime_status_suspended(&pdev
->dev
))
1143 tegra_spi_runtime_suspend(&pdev
->dev
);
1144 tegra_spi_deinit_dma_param(tspi
, false);
1146 tegra_spi_deinit_dma_param(tspi
, true);
1148 spi_master_put(master
);
1152 static int tegra_spi_remove(struct platform_device
*pdev
)
1154 struct spi_master
*master
= platform_get_drvdata(pdev
);
1155 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1157 free_irq(tspi
->irq
, tspi
);
1159 if (tspi
->tx_dma_chan
)
1160 tegra_spi_deinit_dma_param(tspi
, false);
1162 if (tspi
->rx_dma_chan
)
1163 tegra_spi_deinit_dma_param(tspi
, true);
1165 pm_runtime_disable(&pdev
->dev
);
1166 if (!pm_runtime_status_suspended(&pdev
->dev
))
1167 tegra_spi_runtime_suspend(&pdev
->dev
);
1172 #ifdef CONFIG_PM_SLEEP
1173 static int tegra_spi_suspend(struct device
*dev
)
1175 struct spi_master
*master
= dev_get_drvdata(dev
);
1177 return spi_master_suspend(master
);
1180 static int tegra_spi_resume(struct device
*dev
)
1182 struct spi_master
*master
= dev_get_drvdata(dev
);
1183 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1186 ret
= pm_runtime_get_sync(dev
);
1188 dev_err(dev
, "pm runtime failed, e = %d\n", ret
);
1191 tegra_spi_writel(tspi
, tspi
->command1_reg
, SPI_COMMAND1
);
1192 pm_runtime_put(dev
);
1194 return spi_master_resume(master
);
1198 static int tegra_spi_runtime_suspend(struct device
*dev
)
1200 struct spi_master
*master
= dev_get_drvdata(dev
);
1201 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1203 /* Flush all write which are in PPSB queue by reading back */
1204 tegra_spi_readl(tspi
, SPI_COMMAND1
);
1206 clk_disable_unprepare(tspi
->clk
);
1210 static int tegra_spi_runtime_resume(struct device
*dev
)
1212 struct spi_master
*master
= dev_get_drvdata(dev
);
1213 struct tegra_spi_data
*tspi
= spi_master_get_devdata(master
);
1216 ret
= clk_prepare_enable(tspi
->clk
);
1218 dev_err(tspi
->dev
, "clk_prepare failed: %d\n", ret
);
1224 static const struct dev_pm_ops tegra_spi_pm_ops
= {
1225 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend
,
1226 tegra_spi_runtime_resume
, NULL
)
1227 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend
, tegra_spi_resume
)
1229 static struct platform_driver tegra_spi_driver
= {
1231 .name
= "spi-tegra114",
1232 .pm
= &tegra_spi_pm_ops
,
1233 .of_match_table
= tegra_spi_of_match
,
1235 .probe
= tegra_spi_probe
,
1236 .remove
= tegra_spi_remove
,
1238 module_platform_driver(tegra_spi_driver
);
1240 MODULE_ALIAS("platform:spi-tegra114");
1241 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1242 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1243 MODULE_LICENSE("GPL v2");