drivers/spi/spi-uniphier.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // spi-uniphier.c - Socionext UniPhier SPI controller driver
   3 // Copyright 2012      Panasonic Corporation
   4 // Copyright 2016-2018 Socionext Inc.
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitfield.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15
  16 #include <asm/unaligned.h>
  17
  18 #define SSI_TIMEOUT_MS          2000
  19 #define SSI_MAX_CLK_DIVIDER     254
  20 #define SSI_MIN_CLK_DIVIDER     4
  21
  22 struct uniphier_spi_priv {
  23         void __iomem *base;
  24         struct clk *clk;
  25         struct spi_master *master;
  26         struct completion xfer_done;
  27
  28         int error;
  29         unsigned int tx_bytes;
  30         unsigned int rx_bytes;
  31         const u8 *tx_buf;
  32         u8 *rx_buf;
  33
  34         bool is_save_param;
  35         u8 bits_per_word;
  36         u16 mode;
  37         u32 speed_hz;
  38 };
  39
  40 #define SSI_CTL                 0x00
  41 #define   SSI_CTL_EN            BIT(0)
  42
  43 #define SSI_CKS                 0x04
  44 #define   SSI_CKS_CKRAT_MASK    GENMASK(7, 0)
  45 #define   SSI_CKS_CKPHS         BIT(14)
  46 #define   SSI_CKS_CKINIT        BIT(13)
  47 #define   SSI_CKS_CKDLY         BIT(12)
  48
  49 #define SSI_TXWDS               0x08
  50 #define   SSI_TXWDS_WDLEN_MASK  GENMASK(13, 8)
  51 #define   SSI_TXWDS_TDTF_MASK   GENMASK(7, 6)
  52 #define   SSI_TXWDS_DTLEN_MASK  GENMASK(5, 0)
  53
  54 #define SSI_RXWDS               0x0c
  55 #define   SSI_RXWDS_DTLEN_MASK  GENMASK(5, 0)
  56
  57 #define SSI_FPS                 0x10
  58 #define   SSI_FPS_FSPOL         BIT(15)
  59 #define   SSI_FPS_FSTRT         BIT(14)
  60
  61 #define SSI_SR                  0x14
  62 #define   SSI_SR_RNE            BIT(0)
  63
  64 #define SSI_IE                  0x18
  65 #define   SSI_IE_RCIE           BIT(3)
  66 #define   SSI_IE_RORIE          BIT(0)
  67
  68 #define SSI_IS                  0x1c
  69 #define   SSI_IS_RXRS           BIT(9)
  70 #define   SSI_IS_RCID           BIT(3)
  71 #define   SSI_IS_RORID          BIT(0)
  72
  73 #define SSI_IC                  0x1c
  74 #define   SSI_IC_TCIC           BIT(4)
  75 #define   SSI_IC_RCIC           BIT(3)
  76 #define   SSI_IC_RORIC          BIT(0)
  77
  78 #define SSI_FC                  0x20
  79 #define   SSI_FC_TXFFL          BIT(12)
  80 #define   SSI_FC_TXFTH_MASK     GENMASK(11, 8)
  81 #define   SSI_FC_RXFFL          BIT(4)
  82 #define   SSI_FC_RXFTH_MASK     GENMASK(3, 0)
  83
  84 #define SSI_TXDR                0x24
  85 #define SSI_RXDR                0x24
  86
  87 #define SSI_FIFO_DEPTH          8U
  88
  89 static inline unsigned int bytes_per_word(unsigned int bits)
  90 {
  91         return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
  92 }
  93
  94 static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask)
  95 {
  96         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
  97         u32 val;
  98
  99         val = readl(priv->base + SSI_IE);
 100         val |= mask;
 101         writel(val, priv->base + SSI_IE);
 102 }
 103
 104 static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask)
 105 {
 106         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 107         u32 val;
 108
 109         val = readl(priv->base + SSI_IE);
 110         val &= ~mask;
 111         writel(val, priv->base + SSI_IE);
 112 }
 113
 114 static void uniphier_spi_set_mode(struct spi_device *spi)
 115 {
 116         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 117         u32 val1, val2;
 118
 119         /*
 120          * clock setting
 121          * CKPHS    capture timing. 0:rising edge, 1:falling edge
 122          * CKINIT   clock initial level. 0:low, 1:high
 123          * CKDLY    clock delay. 0:no delay, 1:delay depending on FSTRT
 124          *          (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
 125          *
 126          * frame setting
 127          * FSPOL    frame signal porarity. 0: low, 1: high
 128          * FSTRT    start frame timing
 129          *          0: rising edge of clock, 1: falling edge of clock
 130          */
 131         switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 132         case SPI_MODE_0:
 133                 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
 134                 val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
 135                 val2 = 0;
 136                 break;
 137         case SPI_MODE_1:
 138                 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
 139                 val1 = 0;
 140                 val2 = SSI_FPS_FSTRT;
 141                 break;
 142         case SPI_MODE_2:
 143                 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
 144                 val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
 145                 val2 = SSI_FPS_FSTRT;
 146                 break;
 147         case SPI_MODE_3:
 148                 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
 149                 val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
 150                 val2 = 0;
 151                 break;
 152         }
 153
 154         if (!(spi->mode & SPI_CS_HIGH))
 155                 val2 |= SSI_FPS_FSPOL;
 156
 157         writel(val1, priv->base + SSI_CKS);
 158         writel(val2, priv->base + SSI_FPS);
 159
 160         val1 = 0;
 161         if (spi->mode & SPI_LSB_FIRST)
 162                 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
 163         writel(val1, priv->base + SSI_TXWDS);
 164         writel(val1, priv->base + SSI_RXWDS);
 165 }
 166
 167 static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
 168 {
 169         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 170         u32 val;
 171
 172         val = readl(priv->base + SSI_TXWDS);
 173         val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
 174         val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
 175         val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
 176         writel(val, priv->base + SSI_TXWDS);
 177
 178         val = readl(priv->base + SSI_RXWDS);
 179         val &= ~SSI_RXWDS_DTLEN_MASK;
 180         val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
 181         writel(val, priv->base + SSI_RXWDS);
 182 }
 183
 184 static void uniphier_spi_set_baudrate(struct spi_device *spi,
 185                                       unsigned int speed)
 186 {
 187         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 188         u32 val, ckdiv;
 189
 190         /*
 191          * the supported rates are even numbers from 4 to 254. (4,6,8...254)
 192          * round up as we look for equal or less speed
 193          */
 194         ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
 195         ckdiv = round_up(ckdiv, 2);
 196
 197         val = readl(priv->base + SSI_CKS);
 198         val &= ~SSI_CKS_CKRAT_MASK;
 199         val |= ckdiv & SSI_CKS_CKRAT_MASK;
 200         writel(val, priv->base + SSI_CKS);
 201 }
 202
 203 static void uniphier_spi_setup_transfer(struct spi_device *spi,
 204                                        struct spi_transfer *t)
 205 {
 206         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 207         u32 val;
 208
 209         priv->error = 0;
 210         priv->tx_buf = t->tx_buf;
 211         priv->rx_buf = t->rx_buf;
 212         priv->tx_bytes = priv->rx_bytes = t->len;
 213
 214         if (!priv->is_save_param || priv->mode != spi->mode) {
 215                 uniphier_spi_set_mode(spi);
 216                 priv->mode = spi->mode;
 217                 priv->is_save_param = false;
 218         }
 219
 220         if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
 221                 uniphier_spi_set_transfer_size(spi, t->bits_per_word);
 222                 priv->bits_per_word = t->bits_per_word;
 223         }
 224
 225         if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
 226                 uniphier_spi_set_baudrate(spi, t->speed_hz);
 227                 priv->speed_hz = t->speed_hz;
 228         }
 229
 230         if (!priv->is_save_param)
 231                 priv->is_save_param = true;
 232
 233         /* reset FIFOs */
 234         val = SSI_FC_TXFFL | SSI_FC_RXFFL;
 235         writel(val, priv->base + SSI_FC);
 236 }
 237
 238 static void uniphier_spi_send(struct uniphier_spi_priv *priv)
 239 {
 240         int wsize;
 241         u32 val = 0;
 242
 243         wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
 244         priv->tx_bytes -= wsize;
 245
 246         if (priv->tx_buf) {
 247                 switch (wsize) {
 248                 case 1:
 249                         val = *priv->tx_buf;
 250                         break;
 251                 case 2:
 252                         val = get_unaligned_le16(priv->tx_buf);
 253                         break;
 254                 case 4:
 255                         val = get_unaligned_le32(priv->tx_buf);
 256                         break;
 257                 }
 258
 259                 priv->tx_buf += wsize;
 260         }
 261
 262         writel(val, priv->base + SSI_TXDR);
 263 }
 264
 265 static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
 266 {
 267         int rsize;
 268         u32 val;
 269
 270         rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
 271         priv->rx_bytes -= rsize;
 272
 273         val = readl(priv->base + SSI_RXDR);
 274
 275         if (priv->rx_buf) {
 276                 switch (rsize) {
 277                 case 1:
 278                         *priv->rx_buf = val;
 279                         break;
 280                 case 2:
 281                         put_unaligned_le16(val, priv->rx_buf);
 282                         break;
 283                 case 4:
 284                         put_unaligned_le32(val, priv->rx_buf);
 285                         break;
 286                 }
 287
 288                 priv->rx_buf += rsize;
 289         }
 290 }
 291
 292 static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
 293 {
 294         unsigned int tx_count;
 295         u32 val;
 296
 297         tx_count = DIV_ROUND_UP(priv->tx_bytes,
 298                                 bytes_per_word(priv->bits_per_word));
 299         tx_count = min(tx_count, SSI_FIFO_DEPTH);
 300
 301         /* set fifo threshold */
 302         val = readl(priv->base + SSI_FC);
 303         val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
 304         val |= FIELD_PREP(SSI_FC_TXFTH_MASK, tx_count);
 305         val |= FIELD_PREP(SSI_FC_RXFTH_MASK, tx_count);
 306         writel(val, priv->base + SSI_FC);
 307
 308         while (tx_count--)
 309                 uniphier_spi_send(priv);
 310 }
 311
 312 static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
 313 {
 314         struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
 315         u32 val;
 316
 317         val = readl(priv->base + SSI_FPS);
 318
 319         if (enable)
 320                 val |= SSI_FPS_FSPOL;
 321         else
 322                 val &= ~SSI_FPS_FSPOL;
 323
 324         writel(val, priv->base + SSI_FPS);
 325 }
 326
 327 static int uniphier_spi_transfer_one(struct spi_master *master,
 328                                      struct spi_device *spi,
 329                                      struct spi_transfer *t)
 330 {
 331         struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
 332         struct device *dev = master->dev.parent;
 333         unsigned long time_left;
 334
 335         /* Terminate and return success for 0 byte length transfer */
 336         if (!t->len)
 337                 return 0;
 338
 339         uniphier_spi_setup_transfer(spi, t);
 340
 341         reinit_completion(&priv->xfer_done);
 342
 343         uniphier_spi_fill_tx_fifo(priv);
 344
 345         uniphier_spi_irq_enable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
 346
 347         time_left = wait_for_completion_timeout(&priv->xfer_done,
 348                                         msecs_to_jiffies(SSI_TIMEOUT_MS));
 349
 350         uniphier_spi_irq_disable(spi, SSI_IE_RCIE | SSI_IE_RORIE);
 351
 352         if (!time_left) {
 353                 dev_err(dev, "transfer timeout.\n");
 354                 return -ETIMEDOUT;
 355         }
 356
 357         return priv->error;
 358 }
 359
 360 static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
 361 {
 362         struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
 363
 364         writel(SSI_CTL_EN, priv->base + SSI_CTL);
 365
 366         return 0;
 367 }
 368
 369 static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
 370 {
 371         struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
 372
 373         writel(0, priv->base + SSI_CTL);
 374
 375         return 0;
 376 }
 377
 378 static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
 379 {
 380         struct uniphier_spi_priv *priv = dev_id;
 381         u32 val, stat;
 382
 383         stat = readl(priv->base + SSI_IS);
 384         val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
 385         writel(val, priv->base + SSI_IC);
 386
 387         /* rx fifo overrun */
 388         if (stat & SSI_IS_RORID) {
 389                 priv->error = -EIO;
 390                 goto done;
 391         }
 392
 393         /* rx complete */
 394         if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
 395                 while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
 396                                 (priv->rx_bytes - priv->tx_bytes) > 0)
 397                         uniphier_spi_recv(priv);
 398
 399                 if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
 400                                 (priv->rx_bytes != priv->tx_bytes)) {
 401                         priv->error = -EIO;
 402                         goto done;
 403                 } else if (priv->rx_bytes == 0)
 404                         goto done;
 405
 406                 /* next tx transfer */
 407                 uniphier_spi_fill_tx_fifo(priv);
 408
 409                 return IRQ_HANDLED;
 410         }
 411
 412         return IRQ_NONE;
 413
 414 done:
 415         complete(&priv->xfer_done);
 416         return IRQ_HANDLED;
 417 }
 418
 419 static int uniphier_spi_probe(struct platform_device *pdev)
 420 {
 421         struct uniphier_spi_priv *priv;
 422         struct spi_master *master;
 423         struct resource *res;
 424         unsigned long clk_rate;
 425         int irq;
 426         int ret;
 427
 428         master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 429         if (!master)
 430                 return -ENOMEM;
 431
 432         platform_set_drvdata(pdev, master);
 433
 434         priv = spi_master_get_devdata(master);
 435         priv->master = master;
 436         priv->is_save_param = false;
 437
 438         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 439         priv->base = devm_ioremap_resource(&pdev->dev, res);
 440         if (IS_ERR(priv->base)) {
 441                 ret = PTR_ERR(priv->base);
 442                 goto out_master_put;
 443         }
 444
 445         priv->clk = devm_clk_get(&pdev->dev, NULL);
 446         if (IS_ERR(priv->clk)) {
 447                 dev_err(&pdev->dev, "failed to get clock\n");
 448                 ret = PTR_ERR(priv->clk);
 449                 goto out_master_put;
 450         }
 451
 452         ret = clk_prepare_enable(priv->clk);
 453         if (ret)
 454                 goto out_master_put;
 455
 456         irq = platform_get_irq(pdev, 0);
 457         if (irq < 0) {
 458                 dev_err(&pdev->dev, "failed to get IRQ\n");
 459                 ret = irq;
 460                 goto out_disable_clk;
 461         }
 462
 463         ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
 464                                0, "uniphier-spi", priv);
 465         if (ret) {
 466                 dev_err(&pdev->dev, "failed to request IRQ\n");
 467                 goto out_disable_clk;
 468         }
 469
 470         init_completion(&priv->xfer_done);
 471
 472         clk_rate = clk_get_rate(priv->clk);
 473
 474         master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
 475         master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
 476         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 477         master->dev.of_node = pdev->dev.of_node;
 478         master->bus_num = pdev->id;
 479         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
 480
 481         master->set_cs = uniphier_spi_set_cs;
 482         master->transfer_one = uniphier_spi_transfer_one;
 483         master->prepare_transfer_hardware
 484                                 = uniphier_spi_prepare_transfer_hardware;
 485         master->unprepare_transfer_hardware
 486                                 = uniphier_spi_unprepare_transfer_hardware;
 487         master->num_chipselect = 1;
 488
 489         ret = devm_spi_register_master(&pdev->dev, master);
 490         if (ret)
 491                 goto out_disable_clk;
 492
 493         return 0;
 494
 495 out_disable_clk:
 496         clk_disable_unprepare(priv->clk);
 497
 498 out_master_put:
 499         spi_master_put(master);
 500         return ret;
 501 }
 502
 503 static int uniphier_spi_remove(struct platform_device *pdev)
 504 {
 505         struct uniphier_spi_priv *priv = platform_get_drvdata(pdev);
 506
 507         clk_disable_unprepare(priv->clk);
 508
 509         return 0;
 510 }
 511
 512 static const struct of_device_id uniphier_spi_match[] = {
 513         { .compatible = "socionext,uniphier-scssi" },
 514         { /* sentinel */ }
 515 };
 516 MODULE_DEVICE_TABLE(of, uniphier_spi_match);
 517
 518 static struct platform_driver uniphier_spi_driver = {
 519         .probe = uniphier_spi_probe,
 520         .remove = uniphier_spi_remove,
 521         .driver = {
 522                 .name = "uniphier-spi",
 523                 .of_match_table = uniphier_spi_match,
 524         },
 525 };
 526 module_platform_driver(uniphier_spi_driver);
 527
 528 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
 529 MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
 530 MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
 531 MODULE_LICENSE("GPL v2");