2 * Xilinx SPI controller driver (master mode only)
4 * Author: MontaVista Software, Inc.
7 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/spi/xilinx_spi.h>
25 #define XILINX_SPI_NAME "xilinx_spi"
27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
30 #define XSPI_CR_OFFSET 0x60 /* Control Register */
32 #define XSPI_CR_LOOP 0x01
33 #define XSPI_CR_ENABLE 0x02
34 #define XSPI_CR_MASTER_MODE 0x04
35 #define XSPI_CR_CPOL 0x08
36 #define XSPI_CR_CPHA 0x10
37 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
38 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
39 #define XSPI_CR_TXFIFO_RESET 0x20
40 #define XSPI_CR_RXFIFO_RESET 0x40
41 #define XSPI_CR_MANUAL_SSELECT 0x80
42 #define XSPI_CR_TRANS_INHIBIT 0x100
43 #define XSPI_CR_LSB_FIRST 0x200
45 #define XSPI_SR_OFFSET 0x64 /* Status Register */
47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59 * IPIF registers are 32 bit
61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
80 /* bitbang has to be first */
81 struct spi_bitbang bitbang
;
82 struct completion done
;
83 void __iomem
*regs
; /* virt. address of the control registers */
87 u8
*rx_ptr
; /* pointer in the Tx buffer */
88 const u8
*tx_ptr
; /* pointer in the Rx buffer */
89 int remaining_bytes
; /* the number of bytes left to transfer */
91 int buffer_size
; /* buffer size in words */
92 unsigned int (*read_fn
)(void __iomem
*);
93 void (*write_fn
)(u32
, void __iomem
*);
94 void (*tx_fn
)(struct xilinx_spi
*);
95 void (*rx_fn
)(struct xilinx_spi
*);
98 static void xspi_write32(u32 val
, void __iomem
*addr
)
100 iowrite32(val
, addr
);
103 static unsigned int xspi_read32(void __iomem
*addr
)
105 return ioread32(addr
);
108 static void xspi_write32_be(u32 val
, void __iomem
*addr
)
110 iowrite32be(val
, addr
);
113 static unsigned int xspi_read32_be(void __iomem
*addr
)
115 return ioread32be(addr
);
118 static void xspi_tx8(struct xilinx_spi
*xspi
)
120 xspi
->write_fn(*xspi
->tx_ptr
, xspi
->regs
+ XSPI_TXD_OFFSET
);
124 static void xspi_tx16(struct xilinx_spi
*xspi
)
126 xspi
->write_fn(*(u16
*)(xspi
->tx_ptr
), xspi
->regs
+ XSPI_TXD_OFFSET
);
130 static void xspi_tx32(struct xilinx_spi
*xspi
)
132 xspi
->write_fn(*(u32
*)(xspi
->tx_ptr
), xspi
->regs
+ XSPI_TXD_OFFSET
);
136 static void xspi_rx8(struct xilinx_spi
*xspi
)
138 u32 data
= xspi
->read_fn(xspi
->regs
+ XSPI_RXD_OFFSET
);
140 *xspi
->rx_ptr
= data
& 0xff;
145 static void xspi_rx16(struct xilinx_spi
*xspi
)
147 u32 data
= xspi
->read_fn(xspi
->regs
+ XSPI_RXD_OFFSET
);
149 *(u16
*)(xspi
->rx_ptr
) = data
& 0xffff;
154 static void xspi_rx32(struct xilinx_spi
*xspi
)
156 u32 data
= xspi
->read_fn(xspi
->regs
+ XSPI_RXD_OFFSET
);
158 *(u32
*)(xspi
->rx_ptr
) = data
;
163 static void xspi_init_hw(struct xilinx_spi
*xspi
)
165 void __iomem
*regs_base
= xspi
->regs
;
167 /* Reset the SPI device */
168 xspi
->write_fn(XIPIF_V123B_RESET_MASK
,
169 regs_base
+ XIPIF_V123B_RESETR_OFFSET
);
170 /* Disable all the interrupts just in case */
171 xspi
->write_fn(0, regs_base
+ XIPIF_V123B_IIER_OFFSET
);
172 /* Enable the global IPIF interrupt */
173 xspi
->write_fn(XIPIF_V123B_GINTR_ENABLE
,
174 regs_base
+ XIPIF_V123B_DGIER_OFFSET
);
175 /* Deselect the slave on the SPI bus */
176 xspi
->write_fn(0xffff, regs_base
+ XSPI_SSR_OFFSET
);
177 /* Disable the transmitter, enable Manual Slave Select Assertion,
178 * put SPI controller into master mode, and enable it */
179 xspi
->write_fn(XSPI_CR_TRANS_INHIBIT
| XSPI_CR_MANUAL_SSELECT
|
180 XSPI_CR_MASTER_MODE
| XSPI_CR_ENABLE
| XSPI_CR_TXFIFO_RESET
|
181 XSPI_CR_RXFIFO_RESET
, regs_base
+ XSPI_CR_OFFSET
);
184 static void xilinx_spi_chipselect(struct spi_device
*spi
, int is_on
)
186 struct xilinx_spi
*xspi
= spi_master_get_devdata(spi
->master
);
188 if (is_on
== BITBANG_CS_INACTIVE
) {
189 /* Deselect the slave on the SPI bus */
190 xspi
->write_fn(0xffff, xspi
->regs
+ XSPI_SSR_OFFSET
);
191 } else if (is_on
== BITBANG_CS_ACTIVE
) {
192 /* Set the SPI clock phase and polarity */
193 u16 cr
= xspi
->read_fn(xspi
->regs
+ XSPI_CR_OFFSET
)
194 & ~XSPI_CR_MODE_MASK
;
195 if (spi
->mode
& SPI_CPHA
)
197 if (spi
->mode
& SPI_CPOL
)
199 if (spi
->mode
& SPI_LSB_FIRST
)
200 cr
|= XSPI_CR_LSB_FIRST
;
201 if (spi
->mode
& SPI_LOOP
)
203 xspi
->write_fn(cr
, xspi
->regs
+ XSPI_CR_OFFSET
);
205 /* We do not check spi->max_speed_hz here as the SPI clock
206 * frequency is not software programmable (the IP block design
210 /* Activate the chip select */
211 xspi
->write_fn(~(0x0001 << spi
->chip_select
),
212 xspi
->regs
+ XSPI_SSR_OFFSET
);
216 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
217 * custom txrx_bufs().
219 static int xilinx_spi_setup_transfer(struct spi_device
*spi
,
220 struct spi_transfer
*t
)
225 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi
*xspi
, int n_words
)
227 xspi
->remaining_bytes
-= n_words
* xspi
->bits_per_word
/ 8;
233 xspi
->write_fn(0, xspi
->regs
+ XSPI_TXD_OFFSET
);
237 static int xilinx_spi_txrx_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
239 struct xilinx_spi
*xspi
= spi_master_get_devdata(spi
->master
);
242 /* We get here with transmitter inhibited */
244 xspi
->tx_ptr
= t
->tx_buf
;
245 xspi
->rx_ptr
= t
->rx_buf
;
246 xspi
->remaining_bytes
= t
->len
;
247 reinit_completion(&xspi
->done
);
250 /* Enable the transmit empty interrupt, which we use to determine
251 * progress on the transmission.
253 ipif_ier
= xspi
->read_fn(xspi
->regs
+ XIPIF_V123B_IIER_OFFSET
);
254 xspi
->write_fn(ipif_ier
| XSPI_INTR_TX_EMPTY
,
255 xspi
->regs
+ XIPIF_V123B_IIER_OFFSET
);
261 n_words
= (xspi
->remaining_bytes
* 8) / xspi
->bits_per_word
;
262 n_words
= min(n_words
, xspi
->buffer_size
);
264 xilinx_spi_fill_tx_fifo(xspi
, n_words
);
266 /* Start the transfer by not inhibiting the transmitter any
269 cr
= xspi
->read_fn(xspi
->regs
+ XSPI_CR_OFFSET
) &
270 ~XSPI_CR_TRANS_INHIBIT
;
271 xspi
->write_fn(cr
, xspi
->regs
+ XSPI_CR_OFFSET
);
273 wait_for_completion(&xspi
->done
);
275 /* A transmit has just completed. Process received data and
276 * check for more data to transmit. Always inhibit the
277 * transmitter while the Isr refills the transmit register/FIFO,
278 * or make sure it is stopped if we're done.
280 cr
= xspi
->read_fn(xspi
->regs
+ XSPI_CR_OFFSET
);
281 xspi
->write_fn(cr
| XSPI_CR_TRANS_INHIBIT
,
282 xspi
->regs
+ XSPI_CR_OFFSET
);
284 /* Read out all the data from the Rx FIFO */
288 /* See if there is more data to send */
289 if (xspi
->remaining_bytes
<= 0)
293 /* Disable the transmit empty interrupt */
294 xspi
->write_fn(ipif_ier
, xspi
->regs
+ XIPIF_V123B_IIER_OFFSET
);
296 return t
->len
- xspi
->remaining_bytes
;
300 /* This driver supports single master mode only. Hence Tx FIFO Empty
301 * is the only interrupt we care about.
302 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
303 * Fault are not to happen.
305 static irqreturn_t
xilinx_spi_irq(int irq
, void *dev_id
)
307 struct xilinx_spi
*xspi
= dev_id
;
310 /* Get the IPIF interrupts, and clear them immediately */
311 ipif_isr
= xspi
->read_fn(xspi
->regs
+ XIPIF_V123B_IISR_OFFSET
);
312 xspi
->write_fn(ipif_isr
, xspi
->regs
+ XIPIF_V123B_IISR_OFFSET
);
314 if (ipif_isr
& XSPI_INTR_TX_EMPTY
) { /* Transmission completed */
315 complete(&xspi
->done
);
321 static int xilinx_spi_find_buffer_size(struct xilinx_spi
*xspi
)
327 * Before the buffer_size detection we reset the core
328 * to make sure we start with a clean state.
330 xspi
->write_fn(XIPIF_V123B_RESET_MASK
,
331 xspi
->regs
+ XIPIF_V123B_RESETR_OFFSET
);
333 /* Fill the Tx FIFO with as many words as possible */
335 xspi
->write_fn(0, xspi
->regs
+ XSPI_TXD_OFFSET
);
336 sr
= xspi
->read_fn(xspi
->regs
+ XSPI_SR_OFFSET
);
338 } while (!(sr
& XSPI_SR_TX_FULL_MASK
));
343 static const struct of_device_id xilinx_spi_of_match
[] = {
344 { .compatible
= "xlnx,xps-spi-2.00.a", },
345 { .compatible
= "xlnx,xps-spi-2.00.b", },
348 MODULE_DEVICE_TABLE(of
, xilinx_spi_of_match
);
350 static int xilinx_spi_probe(struct platform_device
*pdev
)
352 struct xilinx_spi
*xspi
;
353 struct xspi_platform_data
*pdata
;
354 struct resource
*res
;
355 int ret
, num_cs
= 0, bits_per_word
= 8;
356 struct spi_master
*master
;
360 pdata
= dev_get_platdata(&pdev
->dev
);
362 num_cs
= pdata
->num_chipselect
;
363 bits_per_word
= pdata
->bits_per_word
;
365 of_property_read_u32(pdev
->dev
.of_node
, "xlnx,num-ss-bits",
371 "Missing slave select configuration data\n");
375 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct xilinx_spi
));
379 /* the spi->mode bits understood by this driver: */
380 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
| SPI_LOOP
;
382 xspi
= spi_master_get_devdata(master
);
383 xspi
->bitbang
.master
= master
;
384 xspi
->bitbang
.chipselect
= xilinx_spi_chipselect
;
385 xspi
->bitbang
.setup_transfer
= xilinx_spi_setup_transfer
;
386 xspi
->bitbang
.txrx_bufs
= xilinx_spi_txrx_bufs
;
387 init_completion(&xspi
->done
);
389 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
390 xspi
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
391 if (IS_ERR(xspi
->regs
)) {
392 ret
= PTR_ERR(xspi
->regs
);
396 master
->bus_num
= pdev
->id
;
397 master
->num_chipselect
= num_cs
;
398 master
->dev
.of_node
= pdev
->dev
.of_node
;
401 * Detect endianess on the IP via loop bit in CR. Detection
402 * must be done before reset is sent because incorrect reset
403 * value generates error interrupt.
404 * Setup little endian helper functions first and try to use them
405 * and check if bit was correctly setup or not.
407 xspi
->read_fn
= xspi_read32
;
408 xspi
->write_fn
= xspi_write32
;
410 xspi
->write_fn(XSPI_CR_LOOP
, xspi
->regs
+ XSPI_CR_OFFSET
);
411 tmp
= xspi
->read_fn(xspi
->regs
+ XSPI_CR_OFFSET
);
413 if (tmp
!= XSPI_CR_LOOP
) {
414 xspi
->read_fn
= xspi_read32_be
;
415 xspi
->write_fn
= xspi_write32_be
;
418 master
->bits_per_word_mask
= SPI_BPW_MASK(bits_per_word
);
419 xspi
->bits_per_word
= bits_per_word
;
420 if (xspi
->bits_per_word
== 8) {
421 xspi
->tx_fn
= xspi_tx8
;
422 xspi
->rx_fn
= xspi_rx8
;
423 } else if (xspi
->bits_per_word
== 16) {
424 xspi
->tx_fn
= xspi_tx16
;
425 xspi
->rx_fn
= xspi_rx16
;
426 } else if (xspi
->bits_per_word
== 32) {
427 xspi
->tx_fn
= xspi_tx32
;
428 xspi
->rx_fn
= xspi_rx32
;
434 xspi
->buffer_size
= xilinx_spi_find_buffer_size(xspi
);
436 /* SPI controller initializations */
439 xspi
->irq
= platform_get_irq(pdev
, 0);
445 /* Register for SPI Interrupt */
446 ret
= devm_request_irq(&pdev
->dev
, xspi
->irq
, xilinx_spi_irq
, 0,
447 dev_name(&pdev
->dev
), xspi
);
451 ret
= spi_bitbang_start(&xspi
->bitbang
);
453 dev_err(&pdev
->dev
, "spi_bitbang_start FAILED\n");
457 dev_info(&pdev
->dev
, "at 0x%08llX mapped to 0x%p, irq=%d\n",
458 (unsigned long long)res
->start
, xspi
->regs
, xspi
->irq
);
461 for (i
= 0; i
< pdata
->num_devices
; i
++)
462 spi_new_device(master
, pdata
->devices
+ i
);
465 platform_set_drvdata(pdev
, master
);
469 spi_master_put(master
);
474 static int xilinx_spi_remove(struct platform_device
*pdev
)
476 struct spi_master
*master
= platform_get_drvdata(pdev
);
477 struct xilinx_spi
*xspi
= spi_master_get_devdata(master
);
478 void __iomem
*regs_base
= xspi
->regs
;
480 spi_bitbang_stop(&xspi
->bitbang
);
482 /* Disable all the interrupts just in case */
483 xspi
->write_fn(0, regs_base
+ XIPIF_V123B_IIER_OFFSET
);
484 /* Disable the global IPIF interrupt */
485 xspi
->write_fn(0, regs_base
+ XIPIF_V123B_DGIER_OFFSET
);
487 spi_master_put(xspi
->bitbang
.master
);
492 /* work with hotplug and coldplug */
493 MODULE_ALIAS("platform:" XILINX_SPI_NAME
);
495 static struct platform_driver xilinx_spi_driver
= {
496 .probe
= xilinx_spi_probe
,
497 .remove
= xilinx_spi_remove
,
499 .name
= XILINX_SPI_NAME
,
500 .of_match_table
= xilinx_spi_of_match
,
503 module_platform_driver(xilinx_spi_driver
);
505 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
506 MODULE_DESCRIPTION("Xilinx SPI driver");
507 MODULE_LICENSE("GPL");