2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
35 MODULE_AUTHOR(DRV_AUTHOR
);
36 MODULE_DESCRIPTION(DRV_DESC
);
37 MODULE_LICENSE("GPL");
39 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45 #define QUEUE_RUNNING 0
46 #define QUEUE_STOPPED 1
49 /* Driver model hookup */
50 struct platform_device
*pdev
;
52 /* SPI framework hookup */
53 struct spi_master
*master
;
55 /* Regs base of SPI controller */
56 void __iomem
*regs_base
;
58 /* Pin request list */
62 struct bfin5xx_spi_master
*master_info
;
64 /* Driver message queue */
65 struct workqueue_struct
*workqueue
;
66 struct work_struct pump_messages
;
68 struct list_head queue
;
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers
;
75 /* Current message transfer state info */
76 struct spi_message
*cur_msg
;
77 struct spi_transfer
*cur_transfer
;
78 struct chip_data
*cur_chip
;
97 void (*write
) (struct driver_data
*);
98 void (*read
) (struct driver_data
*);
99 void (*duplex
) (struct driver_data
*);
109 u8 width
; /* 0 or 1 */
111 u8 bits_per_word
; /* 8 or 16 */
112 u8 cs_change_per_word
;
113 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
114 void (*write
) (struct driver_data
*);
115 void (*read
) (struct driver_data
*);
116 void (*duplex
) (struct driver_data
*);
119 #define DEFINE_SPI_REG(reg, off) \
120 static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
125 DEFINE_SPI_REG(CTRL
, 0x00)
126 DEFINE_SPI_REG(FLAG
, 0x04)
127 DEFINE_SPI_REG(STAT
, 0x08)
128 DEFINE_SPI_REG(TDBR
, 0x0C)
129 DEFINE_SPI_REG(RDBR
, 0x10)
130 DEFINE_SPI_REG(BAUD
, 0x14)
131 DEFINE_SPI_REG(SHAW
, 0x18)
133 static void bfin_spi_enable(struct driver_data
*drv_data
)
137 cr
= read_CTRL(drv_data
);
138 write_CTRL(drv_data
, (cr
| BIT_CTL_ENABLE
));
141 static void bfin_spi_disable(struct driver_data
*drv_data
)
145 cr
= read_CTRL(drv_data
);
146 write_CTRL(drv_data
, (cr
& (~BIT_CTL_ENABLE
)));
149 /* Caculate the SPI_BAUD register value based on input HZ */
150 static u16
hz_to_spi_baud(u32 speed_hz
)
152 u_long sclk
= get_sclk();
153 u16 spi_baud
= (sclk
/ (2 * speed_hz
));
155 if ((sclk
% (2 * speed_hz
)) > 0)
158 if (spi_baud
< MIN_SPI_BAUD_VAL
)
159 spi_baud
= MIN_SPI_BAUD_VAL
;
164 static int flush(struct driver_data
*drv_data
)
166 unsigned long limit
= loops_per_jiffy
<< 1;
168 /* wait for stop and clear stat */
169 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
) && limit
--)
172 write_STAT(drv_data
, BIT_STAT_CLR
);
177 /* Chip select operation functions for cs_change flag */
178 static void cs_active(struct driver_data
*drv_data
, struct chip_data
*chip
)
180 u16 flag
= read_FLAG(drv_data
);
183 flag
&= ~(chip
->flag
<< 8);
185 write_FLAG(drv_data
, flag
);
188 static void cs_deactive(struct driver_data
*drv_data
, struct chip_data
*chip
)
190 u16 flag
= read_FLAG(drv_data
);
192 flag
|= (chip
->flag
<< 8);
194 write_FLAG(drv_data
, flag
);
196 /* Move delay here for consistency */
197 if (chip
->cs_chg_udelay
)
198 udelay(chip
->cs_chg_udelay
);
201 #define MAX_SPI_SSEL 7
203 /* stop controller and re-config current chip*/
204 static void restore_state(struct driver_data
*drv_data
)
206 struct chip_data
*chip
= drv_data
->cur_chip
;
208 /* Clear status and disable clock */
209 write_STAT(drv_data
, BIT_STAT_CLR
);
210 bfin_spi_disable(drv_data
);
211 dev_dbg(&drv_data
->pdev
->dev
, "restoring spi ctl state\n");
213 /* Load the registers */
214 write_CTRL(drv_data
, chip
->ctl_reg
);
215 write_BAUD(drv_data
, chip
->baud
);
217 bfin_spi_enable(drv_data
);
218 cs_active(drv_data
, chip
);
221 /* used to kick off transfer in rx mode */
222 static unsigned short dummy_read(struct driver_data
*drv_data
)
225 tmp
= read_RDBR(drv_data
);
229 static void null_writer(struct driver_data
*drv_data
)
231 u8 n_bytes
= drv_data
->n_bytes
;
233 while (drv_data
->tx
< drv_data
->tx_end
) {
234 write_TDBR(drv_data
, 0);
235 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
237 drv_data
->tx
+= n_bytes
;
241 static void null_reader(struct driver_data
*drv_data
)
243 u8 n_bytes
= drv_data
->n_bytes
;
244 dummy_read(drv_data
);
246 while (drv_data
->rx
< drv_data
->rx_end
) {
247 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
249 dummy_read(drv_data
);
250 drv_data
->rx
+= n_bytes
;
254 static void u8_writer(struct driver_data
*drv_data
)
256 dev_dbg(&drv_data
->pdev
->dev
,
257 "cr8-s is 0x%x\n", read_STAT(drv_data
));
259 while (drv_data
->tx
< drv_data
->tx_end
) {
260 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
261 while (read_STAT(drv_data
) & BIT_STAT_TXS
)
266 /* poll for SPI completion before return */
267 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
271 static void u8_cs_chg_writer(struct driver_data
*drv_data
)
273 struct chip_data
*chip
= drv_data
->cur_chip
;
275 while (drv_data
->tx
< drv_data
->tx_end
) {
276 cs_active(drv_data
, chip
);
278 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
279 while (read_STAT(drv_data
) & BIT_STAT_TXS
)
281 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
284 cs_deactive(drv_data
, chip
);
290 static void u8_reader(struct driver_data
*drv_data
)
292 dev_dbg(&drv_data
->pdev
->dev
,
293 "cr-8 is 0x%x\n", read_STAT(drv_data
));
295 /* poll for SPI completion before start */
296 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
299 /* clear TDBR buffer before read(else it will be shifted out) */
300 write_TDBR(drv_data
, 0xFFFF);
302 dummy_read(drv_data
);
304 while (drv_data
->rx
< drv_data
->rx_end
- 1) {
305 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
307 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
311 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
313 *(u8
*) (drv_data
->rx
) = read_SHAW(drv_data
);
317 static void u8_cs_chg_reader(struct driver_data
*drv_data
)
319 struct chip_data
*chip
= drv_data
->cur_chip
;
321 while (drv_data
->rx
< drv_data
->rx_end
) {
322 cs_active(drv_data
, chip
);
323 read_RDBR(drv_data
); /* kick off */
325 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
327 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
330 *(u8
*) (drv_data
->rx
) = read_SHAW(drv_data
);
331 cs_deactive(drv_data
, chip
);
337 static void u8_duplex(struct driver_data
*drv_data
)
339 /* in duplex mode, clk is triggered by writing of TDBR */
340 while (drv_data
->rx
< drv_data
->rx_end
) {
341 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
342 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
344 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
346 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
352 static void u8_cs_chg_duplex(struct driver_data
*drv_data
)
354 struct chip_data
*chip
= drv_data
->cur_chip
;
356 while (drv_data
->rx
< drv_data
->rx_end
) {
357 cs_active(drv_data
, chip
);
359 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
361 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
363 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
365 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
367 cs_deactive(drv_data
, chip
);
374 static void u16_writer(struct driver_data
*drv_data
)
376 dev_dbg(&drv_data
->pdev
->dev
,
377 "cr16 is 0x%x\n", read_STAT(drv_data
));
379 while (drv_data
->tx
< drv_data
->tx_end
) {
380 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
381 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
386 /* poll for SPI completion before return */
387 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
391 static void u16_cs_chg_writer(struct driver_data
*drv_data
)
393 struct chip_data
*chip
= drv_data
->cur_chip
;
395 while (drv_data
->tx
< drv_data
->tx_end
) {
396 cs_active(drv_data
, chip
);
398 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
399 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
401 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
404 cs_deactive(drv_data
, chip
);
410 static void u16_reader(struct driver_data
*drv_data
)
412 dev_dbg(&drv_data
->pdev
->dev
,
413 "cr-16 is 0x%x\n", read_STAT(drv_data
));
415 /* poll for SPI completion before start */
416 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
419 /* clear TDBR buffer before read(else it will be shifted out) */
420 write_TDBR(drv_data
, 0xFFFF);
422 dummy_read(drv_data
);
424 while (drv_data
->rx
< (drv_data
->rx_end
- 2)) {
425 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
427 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
431 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
433 *(u16
*) (drv_data
->rx
) = read_SHAW(drv_data
);
437 static void u16_cs_chg_reader(struct driver_data
*drv_data
)
439 struct chip_data
*chip
= drv_data
->cur_chip
;
441 /* poll for SPI completion before start */
442 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
445 /* clear TDBR buffer before read(else it will be shifted out) */
446 write_TDBR(drv_data
, 0xFFFF);
448 cs_active(drv_data
, chip
);
449 dummy_read(drv_data
);
451 while (drv_data
->rx
< drv_data
->rx_end
- 2) {
452 cs_deactive(drv_data
, chip
);
454 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
456 cs_active(drv_data
, chip
);
457 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
460 cs_deactive(drv_data
, chip
);
462 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
464 *(u16
*) (drv_data
->rx
) = read_SHAW(drv_data
);
468 static void u16_duplex(struct driver_data
*drv_data
)
470 /* in duplex mode, clk is triggered by writing of TDBR */
471 while (drv_data
->tx
< drv_data
->tx_end
) {
472 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
473 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
475 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
477 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
483 static void u16_cs_chg_duplex(struct driver_data
*drv_data
)
485 struct chip_data
*chip
= drv_data
->cur_chip
;
487 while (drv_data
->tx
< drv_data
->tx_end
) {
488 cs_active(drv_data
, chip
);
490 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
491 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
493 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
495 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
497 cs_deactive(drv_data
, chip
);
504 /* test if ther is more transfer to be done */
505 static void *next_transfer(struct driver_data
*drv_data
)
507 struct spi_message
*msg
= drv_data
->cur_msg
;
508 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
510 /* Move to next transfer */
511 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
512 drv_data
->cur_transfer
=
513 list_entry(trans
->transfer_list
.next
,
514 struct spi_transfer
, transfer_list
);
515 return RUNNING_STATE
;
521 * caller already set message->status;
522 * dma and pio irqs are blocked give finished message back
524 static void giveback(struct driver_data
*drv_data
)
526 struct chip_data
*chip
= drv_data
->cur_chip
;
527 struct spi_transfer
*last_transfer
;
529 struct spi_message
*msg
;
531 spin_lock_irqsave(&drv_data
->lock
, flags
);
532 msg
= drv_data
->cur_msg
;
533 drv_data
->cur_msg
= NULL
;
534 drv_data
->cur_transfer
= NULL
;
535 drv_data
->cur_chip
= NULL
;
536 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
537 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
539 last_transfer
= list_entry(msg
->transfers
.prev
,
540 struct spi_transfer
, transfer_list
);
544 /* disable chip select signal. And not stop spi in autobuffer mode */
545 if (drv_data
->tx_dma
!= 0xFFFF) {
546 cs_deactive(drv_data
, chip
);
547 bfin_spi_disable(drv_data
);
550 if (!drv_data
->cs_change
)
551 cs_deactive(drv_data
, chip
);
554 msg
->complete(msg
->context
);
557 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
559 struct driver_data
*drv_data
= dev_id
;
560 struct chip_data
*chip
= drv_data
->cur_chip
;
561 struct spi_message
*msg
= drv_data
->cur_msg
;
562 u16 spistat
= read_STAT(drv_data
);
564 dev_dbg(&drv_data
->pdev
->dev
, "in dma_irq_handler\n");
565 clear_dma_irqstat(drv_data
->dma_channel
);
567 /* Wait for DMA to complete */
568 while (get_dma_curr_irqstat(drv_data
->dma_channel
) & DMA_RUN
)
572 * wait for the last transaction shifted out. HRM states:
573 * at this point there may still be data in the SPI DMA FIFO waiting
574 * to be transmitted ... software needs to poll TXS in the SPI_STAT
575 * register until it goes low for 2 successive reads
577 if (drv_data
->tx
!= NULL
) {
578 while ((read_STAT(drv_data
) & TXS
) ||
579 (read_STAT(drv_data
) & TXS
))
583 while (!(read_STAT(drv_data
) & SPIF
))
586 if (spistat
& RBSY
) {
587 msg
->state
= ERROR_STATE
;
588 dev_err(&drv_data
->pdev
->dev
, "dma receive: fifo/buffer overflow\n");
590 msg
->actual_length
+= drv_data
->len_in_bytes
;
592 if (drv_data
->cs_change
)
593 cs_deactive(drv_data
, chip
);
595 /* Move to next transfer */
596 msg
->state
= next_transfer(drv_data
);
599 /* Schedule transfer tasklet */
600 tasklet_schedule(&drv_data
->pump_transfers
);
602 /* free the irq handler before next transfer */
603 dev_dbg(&drv_data
->pdev
->dev
,
604 "disable dma channel irq%d\n",
605 drv_data
->dma_channel
);
606 dma_disable_irq(drv_data
->dma_channel
);
611 static void pump_transfers(unsigned long data
)
613 struct driver_data
*drv_data
= (struct driver_data
*)data
;
614 struct spi_message
*message
= NULL
;
615 struct spi_transfer
*transfer
= NULL
;
616 struct spi_transfer
*previous
= NULL
;
617 struct chip_data
*chip
= NULL
;
619 u16 cr
, dma_width
, dma_config
;
620 u32 tranf_success
= 1;
623 /* Get current state information */
624 message
= drv_data
->cur_msg
;
625 transfer
= drv_data
->cur_transfer
;
626 chip
= drv_data
->cur_chip
;
629 * if msg is error or done, report it back using complete() callback
632 /* Handle for abort */
633 if (message
->state
== ERROR_STATE
) {
634 message
->status
= -EIO
;
639 /* Handle end of message */
640 if (message
->state
== DONE_STATE
) {
646 /* Delay if requested at end of transfer */
647 if (message
->state
== RUNNING_STATE
) {
648 previous
= list_entry(transfer
->transfer_list
.prev
,
649 struct spi_transfer
, transfer_list
);
650 if (previous
->delay_usecs
)
651 udelay(previous
->delay_usecs
);
654 /* Setup the transfer state based on the type of transfer */
655 if (flush(drv_data
) == 0) {
656 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
657 message
->status
= -EIO
;
662 if (transfer
->tx_buf
!= NULL
) {
663 drv_data
->tx
= (void *)transfer
->tx_buf
;
664 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
665 dev_dbg(&drv_data
->pdev
->dev
, "tx_buf is %p, tx_end is %p\n",
666 transfer
->tx_buf
, drv_data
->tx_end
);
671 if (transfer
->rx_buf
!= NULL
) {
672 full_duplex
= transfer
->tx_buf
!= NULL
;
673 drv_data
->rx
= transfer
->rx_buf
;
674 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
675 dev_dbg(&drv_data
->pdev
->dev
, "rx_buf is %p, rx_end is %p\n",
676 transfer
->rx_buf
, drv_data
->rx_end
);
681 drv_data
->rx_dma
= transfer
->rx_dma
;
682 drv_data
->tx_dma
= transfer
->tx_dma
;
683 drv_data
->len_in_bytes
= transfer
->len
;
684 drv_data
->cs_change
= transfer
->cs_change
;
686 /* Bits per word setup */
687 switch (transfer
->bits_per_word
) {
689 drv_data
->n_bytes
= 1;
690 width
= CFG_SPI_WORDSIZE8
;
691 drv_data
->read
= chip
->cs_change_per_word
?
692 u8_cs_chg_reader
: u8_reader
;
693 drv_data
->write
= chip
->cs_change_per_word
?
694 u8_cs_chg_writer
: u8_writer
;
695 drv_data
->duplex
= chip
->cs_change_per_word
?
696 u8_cs_chg_duplex
: u8_duplex
;
700 drv_data
->n_bytes
= 2;
701 width
= CFG_SPI_WORDSIZE16
;
702 drv_data
->read
= chip
->cs_change_per_word
?
703 u16_cs_chg_reader
: u16_reader
;
704 drv_data
->write
= chip
->cs_change_per_word
?
705 u16_cs_chg_writer
: u16_writer
;
706 drv_data
->duplex
= chip
->cs_change_per_word
?
707 u16_cs_chg_duplex
: u16_duplex
;
711 /* No change, the same as default setting */
712 drv_data
->n_bytes
= chip
->n_bytes
;
714 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
715 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
716 drv_data
->duplex
= chip
->duplex
? chip
->duplex
: null_writer
;
719 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
721 write_CTRL(drv_data
, cr
);
723 if (width
== CFG_SPI_WORDSIZE16
) {
724 drv_data
->len
= (transfer
->len
) >> 1;
726 drv_data
->len
= transfer
->len
;
728 dev_dbg(&drv_data
->pdev
->dev
,
729 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
730 drv_data
->write
, chip
->write
, null_writer
);
732 /* speed and width has been set on per message */
733 message
->state
= RUNNING_STATE
;
736 /* Speed setup (surely valid because already checked) */
737 if (transfer
->speed_hz
)
738 write_BAUD(drv_data
, hz_to_spi_baud(transfer
->speed_hz
));
740 write_BAUD(drv_data
, chip
->baud
);
742 write_STAT(drv_data
, BIT_STAT_CLR
);
743 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
744 cs_active(drv_data
, chip
);
746 dev_dbg(&drv_data
->pdev
->dev
,
747 "now pumping a transfer: width is %d, len is %d\n",
748 width
, transfer
->len
);
751 * Try to map dma buffer and do a dma transfer. If successful use,
752 * different way to r/w according to the enable_dma settings and if
753 * we are not doing a full duplex transfer (since the hardware does
754 * not support full duplex DMA transfers).
756 if (!full_duplex
&& drv_data
->cur_chip
->enable_dma
757 && drv_data
->len
> 6) {
759 disable_dma(drv_data
->dma_channel
);
760 clear_dma_irqstat(drv_data
->dma_channel
);
761 bfin_spi_disable(drv_data
);
763 /* config dma channel */
764 dev_dbg(&drv_data
->pdev
->dev
, "doing dma transfer\n");
765 if (width
== CFG_SPI_WORDSIZE16
) {
766 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
767 set_dma_x_modify(drv_data
->dma_channel
, 2);
768 dma_width
= WDSIZE_16
;
770 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
771 set_dma_x_modify(drv_data
->dma_channel
, 1);
772 dma_width
= WDSIZE_8
;
775 /* poll for SPI completion before start */
776 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
779 /* dirty hack for autobuffer DMA mode */
780 if (drv_data
->tx_dma
== 0xFFFF) {
781 dev_dbg(&drv_data
->pdev
->dev
,
782 "doing autobuffer DMA out.\n");
784 /* no irq in autobuffer mode */
786 (DMAFLOW_AUTO
| RESTART
| dma_width
| DI_EN
);
787 set_dma_config(drv_data
->dma_channel
, dma_config
);
788 set_dma_start_addr(drv_data
->dma_channel
,
789 (unsigned long)drv_data
->tx
);
790 enable_dma(drv_data
->dma_channel
);
792 /* start SPI transfer */
794 (cr
| CFG_SPI_DMAWRITE
| BIT_CTL_ENABLE
));
796 /* just return here, there can only be one transfer
804 /* In dma mode, rx or tx must be NULL in one transfer */
805 if (drv_data
->rx
!= NULL
) {
806 /* set transfer mode, and enable SPI */
807 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA in.\n");
809 /* invalidate caches, if needed */
810 if (bfin_addr_dcachable((unsigned long) drv_data
->rx
))
811 invalidate_dcache_range((unsigned long) drv_data
->rx
,
812 (unsigned long) (drv_data
->rx
+
813 drv_data
->len_in_bytes
));
815 /* clear tx reg soformer data is not shifted out */
816 write_TDBR(drv_data
, 0xFFFF);
818 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
821 dma_enable_irq(drv_data
->dma_channel
);
822 dma_config
= (WNR
| RESTART
| dma_width
| DI_EN
);
823 set_dma_config(drv_data
->dma_channel
, dma_config
);
824 set_dma_start_addr(drv_data
->dma_channel
,
825 (unsigned long)drv_data
->rx
);
826 enable_dma(drv_data
->dma_channel
);
828 /* start SPI transfer */
830 (cr
| CFG_SPI_DMAREAD
| BIT_CTL_ENABLE
));
832 } else if (drv_data
->tx
!= NULL
) {
833 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA out.\n");
835 /* flush caches, if needed */
836 if (bfin_addr_dcachable((unsigned long) drv_data
->tx
))
837 flush_dcache_range((unsigned long) drv_data
->tx
,
838 (unsigned long) (drv_data
->tx
+
839 drv_data
->len_in_bytes
));
842 dma_enable_irq(drv_data
->dma_channel
);
843 dma_config
= (RESTART
| dma_width
| DI_EN
);
844 set_dma_config(drv_data
->dma_channel
, dma_config
);
845 set_dma_start_addr(drv_data
->dma_channel
,
846 (unsigned long)drv_data
->tx
);
847 enable_dma(drv_data
->dma_channel
);
849 /* start SPI transfer */
851 (cr
| CFG_SPI_DMAWRITE
| BIT_CTL_ENABLE
));
854 /* IO mode write then read */
855 dev_dbg(&drv_data
->pdev
->dev
, "doing IO transfer\n");
858 /* full duplex mode */
859 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
860 (drv_data
->rx_end
- drv_data
->rx
));
861 dev_dbg(&drv_data
->pdev
->dev
,
862 "IO duplex: cr is 0x%x\n", cr
);
864 /* set SPI transfer mode */
865 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
867 drv_data
->duplex(drv_data
);
869 if (drv_data
->tx
!= drv_data
->tx_end
)
871 } else if (drv_data
->tx
!= NULL
) {
872 /* write only half duplex */
873 dev_dbg(&drv_data
->pdev
->dev
,
874 "IO write: cr is 0x%x\n", cr
);
876 /* set SPI transfer mode */
877 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
879 drv_data
->write(drv_data
);
881 if (drv_data
->tx
!= drv_data
->tx_end
)
883 } else if (drv_data
->rx
!= NULL
) {
884 /* read only half duplex */
885 dev_dbg(&drv_data
->pdev
->dev
,
886 "IO read: cr is 0x%x\n", cr
);
888 /* set SPI transfer mode */
889 write_CTRL(drv_data
, (cr
| CFG_SPI_READ
));
891 drv_data
->read(drv_data
);
892 if (drv_data
->rx
!= drv_data
->rx_end
)
896 if (!tranf_success
) {
897 dev_dbg(&drv_data
->pdev
->dev
,
898 "IO write error!\n");
899 message
->state
= ERROR_STATE
;
901 /* Update total byte transfered */
902 message
->actual_length
+= drv_data
->len_in_bytes
;
904 /* Move to next transfer of this msg */
905 message
->state
= next_transfer(drv_data
);
908 /* Schedule next transfer tasklet */
909 tasklet_schedule(&drv_data
->pump_transfers
);
914 /* pop a msg from queue and kick off real transfer */
915 static void pump_messages(struct work_struct
*work
)
917 struct driver_data
*drv_data
;
920 drv_data
= container_of(work
, struct driver_data
, pump_messages
);
922 /* Lock queue and check for queue work */
923 spin_lock_irqsave(&drv_data
->lock
, flags
);
924 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
925 /* pumper kicked off but no work to do */
927 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
931 /* Make sure we are not already running a message */
932 if (drv_data
->cur_msg
) {
933 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
937 /* Extract head of queue */
938 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
939 struct spi_message
, queue
);
941 /* Setup the SSP using the per chip configuration */
942 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
943 restore_state(drv_data
);
945 list_del_init(&drv_data
->cur_msg
->queue
);
947 /* Initial message state */
948 drv_data
->cur_msg
->state
= START_STATE
;
949 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
950 struct spi_transfer
, transfer_list
);
952 dev_dbg(&drv_data
->pdev
->dev
, "got a message to pump, "
953 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
954 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->flag
,
955 drv_data
->cur_chip
->ctl_reg
);
957 dev_dbg(&drv_data
->pdev
->dev
,
958 "the first transfer len is %d\n",
959 drv_data
->cur_transfer
->len
);
961 /* Mark as busy and launch transfers */
962 tasklet_schedule(&drv_data
->pump_transfers
);
965 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
969 * got a msg to transfer, queue it in drv_data->queue.
970 * And kick off message pumper
972 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
974 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
977 spin_lock_irqsave(&drv_data
->lock
, flags
);
979 if (drv_data
->run
== QUEUE_STOPPED
) {
980 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
984 msg
->actual_length
= 0;
985 msg
->status
= -EINPROGRESS
;
986 msg
->state
= START_STATE
;
988 dev_dbg(&spi
->dev
, "adding an msg in transfer() \n");
989 list_add_tail(&msg
->queue
, &drv_data
->queue
);
991 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
992 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
994 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
999 #define MAX_SPI_SSEL 7
1001 static u16 ssel
[3][MAX_SPI_SSEL
] = {
1002 {P_SPI0_SSEL1
, P_SPI0_SSEL2
, P_SPI0_SSEL3
,
1003 P_SPI0_SSEL4
, P_SPI0_SSEL5
,
1004 P_SPI0_SSEL6
, P_SPI0_SSEL7
},
1006 {P_SPI1_SSEL1
, P_SPI1_SSEL2
, P_SPI1_SSEL3
,
1007 P_SPI1_SSEL4
, P_SPI1_SSEL5
,
1008 P_SPI1_SSEL6
, P_SPI1_SSEL7
},
1010 {P_SPI2_SSEL1
, P_SPI2_SSEL2
, P_SPI2_SSEL3
,
1011 P_SPI2_SSEL4
, P_SPI2_SSEL5
,
1012 P_SPI2_SSEL6
, P_SPI2_SSEL7
},
1015 /* first setup for new devices */
1016 static int setup(struct spi_device
*spi
)
1018 struct bfin5xx_spi_chip
*chip_info
= NULL
;
1019 struct chip_data
*chip
;
1020 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1023 /* Abort device setup if requested features are not supported */
1024 if (spi
->mode
& ~(SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
)) {
1025 dev_err(&spi
->dev
, "requested mode not fully supported\n");
1029 /* Zero (the default) here means 8 bits */
1030 if (!spi
->bits_per_word
)
1031 spi
->bits_per_word
= 8;
1033 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16)
1036 /* Only alloc (or use chip_info) on first setup */
1037 chip
= spi_get_ctldata(spi
);
1039 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1043 chip
->enable_dma
= 0;
1044 chip_info
= spi
->controller_data
;
1047 /* chip_info isn't always needed */
1049 /* Make sure people stop trying to set fields via ctl_reg
1050 * when they should actually be using common SPI framework.
1051 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1052 * Not sure if a user actually needs/uses any of these,
1053 * but let's assume (for now) they do.
1055 if (chip_info
->ctl_reg
& (SPE
|MSTR
|CPOL
|CPHA
|LSBF
|SIZE
)) {
1056 dev_err(&spi
->dev
, "do not set bits in ctl_reg "
1057 "that the SPI framework manages\n");
1061 chip
->enable_dma
= chip_info
->enable_dma
!= 0
1062 && drv_data
->master_info
->enable_dma
;
1063 chip
->ctl_reg
= chip_info
->ctl_reg
;
1064 chip
->bits_per_word
= chip_info
->bits_per_word
;
1065 chip
->cs_change_per_word
= chip_info
->cs_change_per_word
;
1066 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
1069 /* translate common spi framework into our register */
1070 if (spi
->mode
& SPI_CPOL
)
1071 chip
->ctl_reg
|= CPOL
;
1072 if (spi
->mode
& SPI_CPHA
)
1073 chip
->ctl_reg
|= CPHA
;
1074 if (spi
->mode
& SPI_LSB_FIRST
)
1075 chip
->ctl_reg
|= LSBF
;
1076 /* we dont support running in slave mode (yet?) */
1077 chip
->ctl_reg
|= MSTR
;
1080 * if any one SPI chip is registered and wants DMA, request the
1081 * DMA channel for it
1083 if (chip
->enable_dma
&& !drv_data
->dma_requested
) {
1084 /* register dma irq handler */
1085 if (request_dma(drv_data
->dma_channel
, "BF53x_SPI_DMA") < 0) {
1087 "Unable to request BlackFin SPI DMA channel\n");
1090 if (set_dma_callback(drv_data
->dma_channel
,
1091 (void *)dma_irq_handler
, drv_data
) < 0) {
1092 dev_dbg(&spi
->dev
, "Unable to set dma callback\n");
1095 dma_disable_irq(drv_data
->dma_channel
);
1096 drv_data
->dma_requested
= 1;
1100 * Notice: for blackfin, the speed_hz is the value of register
1101 * SPI_BAUD, not the real baudrate
1103 chip
->baud
= hz_to_spi_baud(spi
->max_speed_hz
);
1104 spi_flg
= ~(1 << (spi
->chip_select
));
1105 chip
->flag
= ((u16
) spi_flg
<< 8) | (1 << (spi
->chip_select
));
1106 chip
->chip_select_num
= spi
->chip_select
;
1108 switch (chip
->bits_per_word
) {
1111 chip
->width
= CFG_SPI_WORDSIZE8
;
1112 chip
->read
= chip
->cs_change_per_word
?
1113 u8_cs_chg_reader
: u8_reader
;
1114 chip
->write
= chip
->cs_change_per_word
?
1115 u8_cs_chg_writer
: u8_writer
;
1116 chip
->duplex
= chip
->cs_change_per_word
?
1117 u8_cs_chg_duplex
: u8_duplex
;
1122 chip
->width
= CFG_SPI_WORDSIZE16
;
1123 chip
->read
= chip
->cs_change_per_word
?
1124 u16_cs_chg_reader
: u16_reader
;
1125 chip
->write
= chip
->cs_change_per_word
?
1126 u16_cs_chg_writer
: u16_writer
;
1127 chip
->duplex
= chip
->cs_change_per_word
?
1128 u16_cs_chg_duplex
: u16_duplex
;
1132 dev_err(&spi
->dev
, "%d bits_per_word is not supported\n",
1133 chip
->bits_per_word
);
1138 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d, dma is %d\n",
1139 spi
->modalias
, chip
->width
, chip
->enable_dma
);
1140 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1141 chip
->ctl_reg
, chip
->flag
);
1143 spi_set_ctldata(spi
, chip
);
1145 dev_dbg(&spi
->dev
, "chip select number is %d\n", chip
->chip_select_num
);
1146 if ((chip
->chip_select_num
> 0)
1147 && (chip
->chip_select_num
<= spi
->master
->num_chipselect
))
1148 peripheral_request(ssel
[spi
->master
->bus_num
]
1149 [chip
->chip_select_num
-1], spi
->modalias
);
1151 cs_deactive(drv_data
, chip
);
1157 * callback for spi framework.
1158 * clean driver specific data
1160 static void cleanup(struct spi_device
*spi
)
1162 struct chip_data
*chip
= spi_get_ctldata(spi
);
1164 if ((chip
->chip_select_num
> 0)
1165 && (chip
->chip_select_num
<= spi
->master
->num_chipselect
))
1166 peripheral_free(ssel
[spi
->master
->bus_num
]
1167 [chip
->chip_select_num
-1]);
1172 static inline int init_queue(struct driver_data
*drv_data
)
1174 INIT_LIST_HEAD(&drv_data
->queue
);
1175 spin_lock_init(&drv_data
->lock
);
1177 drv_data
->run
= QUEUE_STOPPED
;
1180 /* init transfer tasklet */
1181 tasklet_init(&drv_data
->pump_transfers
,
1182 pump_transfers
, (unsigned long)drv_data
);
1184 /* init messages workqueue */
1185 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1186 drv_data
->workqueue
= create_singlethread_workqueue(
1187 dev_name(drv_data
->master
->dev
.parent
));
1188 if (drv_data
->workqueue
== NULL
)
1194 static inline int start_queue(struct driver_data
*drv_data
)
1196 unsigned long flags
;
1198 spin_lock_irqsave(&drv_data
->lock
, flags
);
1200 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1201 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1205 drv_data
->run
= QUEUE_RUNNING
;
1206 drv_data
->cur_msg
= NULL
;
1207 drv_data
->cur_transfer
= NULL
;
1208 drv_data
->cur_chip
= NULL
;
1209 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1211 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1216 static inline int stop_queue(struct driver_data
*drv_data
)
1218 unsigned long flags
;
1219 unsigned limit
= 500;
1222 spin_lock_irqsave(&drv_data
->lock
, flags
);
1225 * This is a bit lame, but is optimized for the common execution path.
1226 * A wait_queue on the drv_data->busy could be used, but then the common
1227 * execution path (pump_messages) would be required to call wake_up or
1228 * friends on every SPI message. Do this instead
1230 drv_data
->run
= QUEUE_STOPPED
;
1231 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1232 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1234 spin_lock_irqsave(&drv_data
->lock
, flags
);
1237 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1240 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1245 static inline int destroy_queue(struct driver_data
*drv_data
)
1249 status
= stop_queue(drv_data
);
1253 destroy_workqueue(drv_data
->workqueue
);
1258 static int __init
bfin5xx_spi_probe(struct platform_device
*pdev
)
1260 struct device
*dev
= &pdev
->dev
;
1261 struct bfin5xx_spi_master
*platform_info
;
1262 struct spi_master
*master
;
1263 struct driver_data
*drv_data
= 0;
1264 struct resource
*res
;
1267 platform_info
= dev
->platform_data
;
1269 /* Allocate master with space for drv_data */
1270 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1272 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1276 drv_data
= spi_master_get_devdata(master
);
1277 drv_data
->master
= master
;
1278 drv_data
->master_info
= platform_info
;
1279 drv_data
->pdev
= pdev
;
1280 drv_data
->pin_req
= platform_info
->pin_req
;
1282 master
->bus_num
= pdev
->id
;
1283 master
->num_chipselect
= platform_info
->num_chipselect
;
1284 master
->cleanup
= cleanup
;
1285 master
->setup
= setup
;
1286 master
->transfer
= transfer
;
1288 /* Find and map our resources */
1289 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1291 dev_err(dev
, "Cannot get IORESOURCE_MEM\n");
1293 goto out_error_get_res
;
1296 drv_data
->regs_base
= ioremap(res
->start
, (res
->end
- res
->start
+ 1));
1297 if (drv_data
->regs_base
== NULL
) {
1298 dev_err(dev
, "Cannot map IO\n");
1300 goto out_error_ioremap
;
1303 drv_data
->dma_channel
= platform_get_irq(pdev
, 0);
1304 if (drv_data
->dma_channel
< 0) {
1305 dev_err(dev
, "No DMA channel specified\n");
1307 goto out_error_no_dma_ch
;
1310 /* Initial and start queue */
1311 status
= init_queue(drv_data
);
1313 dev_err(dev
, "problem initializing queue\n");
1314 goto out_error_queue_alloc
;
1317 status
= start_queue(drv_data
);
1319 dev_err(dev
, "problem starting queue\n");
1320 goto out_error_queue_alloc
;
1323 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
1325 dev_err(&pdev
->dev
, ": Requesting Peripherals failed\n");
1326 goto out_error_queue_alloc
;
1329 /* Register with the SPI framework */
1330 platform_set_drvdata(pdev
, drv_data
);
1331 status
= spi_register_master(master
);
1333 dev_err(dev
, "problem registering spi master\n");
1334 goto out_error_queue_alloc
;
1337 dev_info(dev
, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1338 DRV_DESC
, DRV_VERSION
, drv_data
->regs_base
,
1339 drv_data
->dma_channel
);
1342 out_error_queue_alloc
:
1343 destroy_queue(drv_data
);
1344 out_error_no_dma_ch
:
1345 iounmap((void *) drv_data
->regs_base
);
1348 spi_master_put(master
);
1353 /* stop hardware and remove the driver */
1354 static int __devexit
bfin5xx_spi_remove(struct platform_device
*pdev
)
1356 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1362 /* Remove the queue */
1363 status
= destroy_queue(drv_data
);
1367 /* Disable the SSP at the peripheral and SOC level */
1368 bfin_spi_disable(drv_data
);
1371 if (drv_data
->master_info
->enable_dma
) {
1372 if (dma_channel_active(drv_data
->dma_channel
))
1373 free_dma(drv_data
->dma_channel
);
1376 /* Disconnect from the SPI framework */
1377 spi_unregister_master(drv_data
->master
);
1379 peripheral_free_list(drv_data
->pin_req
);
1381 /* Prevent double remove */
1382 platform_set_drvdata(pdev
, NULL
);
1388 static int bfin5xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1390 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1393 status
= stop_queue(drv_data
);
1398 bfin_spi_disable(drv_data
);
1403 static int bfin5xx_spi_resume(struct platform_device
*pdev
)
1405 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1408 /* Enable the SPI interface */
1409 bfin_spi_enable(drv_data
);
1411 /* Start the queue running */
1412 status
= start_queue(drv_data
);
1414 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1421 #define bfin5xx_spi_suspend NULL
1422 #define bfin5xx_spi_resume NULL
1423 #endif /* CONFIG_PM */
1425 MODULE_ALIAS("platform:bfin-spi");
1426 static struct platform_driver bfin5xx_spi_driver
= {
1429 .owner
= THIS_MODULE
,
1431 .suspend
= bfin5xx_spi_suspend
,
1432 .resume
= bfin5xx_spi_resume
,
1433 .remove
= __devexit_p(bfin5xx_spi_remove
),
1436 static int __init
bfin5xx_spi_init(void)
1438 return platform_driver_probe(&bfin5xx_spi_driver
, bfin5xx_spi_probe
);
1440 module_init(bfin5xx_spi_init
);
1442 static void __exit
bfin5xx_spi_exit(void)
1444 platform_driver_unregister(&bfin5xx_spi_driver
);
1446 module_exit(bfin5xx_spi_exit
);