]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/spi/spi_bfin5xx.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Blackfin SPI driver: move hard coded pin_req to board file
[mirror_ubuntu-zesty-kernel.git] / drivers / spi / spi_bfin5xx.c
1 /*
2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
7 *
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
18 *
19 * Copyright 2004-2007 Analog Devices Inc.
20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
41 #include <linux/io.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
50
51 #include <asm/dma.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
54
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver"
58 #define DRV_VERSION "1.0"
59
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
63
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
65
66 #define START_STATE ((void *)0)
67 #define RUNNING_STATE ((void *)1)
68 #define DONE_STATE ((void *)2)
69 #define ERROR_STATE ((void *)-1)
70 #define QUEUE_RUNNING 0
71 #define QUEUE_STOPPED 1
72
73 struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
80 /* Regs base of SPI controller */
81 void __iomem *regs_base;
82
83 /* Pin request list */
84 u16 *pin_req;
85
86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info;
88
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
92 spinlock_t lock;
93 struct list_head queue;
94 int busy;
95 int run;
96
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
99
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
104 size_t len_in_bytes;
105 size_t len;
106 void *tx;
107 void *tx_end;
108 void *rx;
109 void *rx_end;
110
111 /* DMA stuffs */
112 int dma_channel;
113 int dma_mapped;
114 int dma_requested;
115 dma_addr_t rx_dma;
116 dma_addr_t tx_dma;
117
118 size_t rx_map_len;
119 size_t tx_map_len;
120 u8 n_bytes;
121 int cs_change;
122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
125 };
126
127 struct chip_data {
128 u16 ctl_reg;
129 u16 baud;
130 u16 flag;
131
132 u8 chip_select_num;
133 u8 n_bytes;
134 u8 width; /* 0 or 1 */
135 u8 enable_dma;
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
142 };
143
144 #define DEFINE_SPI_REG(reg, off) \
145 static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150 DEFINE_SPI_REG(CTRL, 0x00)
151 DEFINE_SPI_REG(FLAG, 0x04)
152 DEFINE_SPI_REG(STAT, 0x08)
153 DEFINE_SPI_REG(TDBR, 0x0C)
154 DEFINE_SPI_REG(RDBR, 0x10)
155 DEFINE_SPI_REG(BAUD, 0x14)
156 DEFINE_SPI_REG(SHAW, 0x18)
157
158 static void bfin_spi_enable(struct driver_data *drv_data)
159 {
160 u16 cr;
161
162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
164 }
165
166 static void bfin_spi_disable(struct driver_data *drv_data)
167 {
168 u16 cr;
169
170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
172 }
173
174 /* Caculate the SPI_BAUD register value based on input HZ */
175 static u16 hz_to_spi_baud(u32 speed_hz)
176 {
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
179
180 if ((sclk % (2 * speed_hz)) > 0)
181 spi_baud++;
182
183 return spi_baud;
184 }
185
186 static int flush(struct driver_data *drv_data)
187 {
188 unsigned long limit = loops_per_jiffy << 1;
189
190 /* wait for stop and clear stat */
191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
192 cpu_relax();
193
194 write_STAT(drv_data, BIT_STAT_CLR);
195
196 return limit;
197 }
198
199 /* Chip select operation functions for cs_change flag */
200 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
201 {
202 u16 flag = read_FLAG(drv_data);
203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
207 write_FLAG(drv_data, flag);
208 }
209
210 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
211 {
212 u16 flag = read_FLAG(drv_data);
213
214 flag |= (chip->flag << 8);
215
216 write_FLAG(drv_data, flag);
217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
221 }
222
223 #define MAX_SPI_SSEL 7
224
225 /* stop controller and re-config current chip*/
226 static int restore_state(struct driver_data *drv_data)
227 {
228 struct chip_data *chip = drv_data->cur_chip;
229 int ret = 0;
230
231 /* Clear status and disable clock */
232 write_STAT(drv_data, BIT_STAT_CLR);
233 bfin_spi_disable(drv_data);
234 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
235
236 /* Load the registers */
237 write_BAUD(drv_data, chip->baud);
238 chip->ctl_reg &= (~BIT_CTL_TIMOD);
239 chip->ctl_reg |= (chip->width << 8);
240 write_CTRL(drv_data, chip->ctl_reg);
241
242 bfin_spi_enable(drv_data);
243 cs_active(drv_data, chip);
244
245 if (ret)
246 dev_dbg(&drv_data->pdev->dev,
247 ": request chip select number %d failed\n",
248 chip->chip_select_num);
249
250 return ret;
251 }
252
253 /* used to kick off transfer in rx mode */
254 static unsigned short dummy_read(struct driver_data *drv_data)
255 {
256 unsigned short tmp;
257 tmp = read_RDBR(drv_data);
258 return tmp;
259 }
260
261 static void null_writer(struct driver_data *drv_data)
262 {
263 u8 n_bytes = drv_data->n_bytes;
264
265 while (drv_data->tx < drv_data->tx_end) {
266 write_TDBR(drv_data, 0);
267 while ((read_STAT(drv_data) & BIT_STAT_TXS))
268 cpu_relax();
269 drv_data->tx += n_bytes;
270 }
271 }
272
273 static void null_reader(struct driver_data *drv_data)
274 {
275 u8 n_bytes = drv_data->n_bytes;
276 dummy_read(drv_data);
277
278 while (drv_data->rx < drv_data->rx_end) {
279 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
280 cpu_relax();
281 dummy_read(drv_data);
282 drv_data->rx += n_bytes;
283 }
284 }
285
286 static void u8_writer(struct driver_data *drv_data)
287 {
288 dev_dbg(&drv_data->pdev->dev,
289 "cr8-s is 0x%x\n", read_STAT(drv_data));
290
291 /* poll for SPI completion before start */
292 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
293 cpu_relax();
294
295 while (drv_data->tx < drv_data->tx_end) {
296 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
297 while (read_STAT(drv_data) & BIT_STAT_TXS)
298 cpu_relax();
299 ++drv_data->tx;
300 }
301 }
302
303 static void u8_cs_chg_writer(struct driver_data *drv_data)
304 {
305 struct chip_data *chip = drv_data->cur_chip;
306
307 /* poll for SPI completion before start */
308 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
309 cpu_relax();
310
311 while (drv_data->tx < drv_data->tx_end) {
312 cs_active(drv_data, chip);
313
314 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
315 while (read_STAT(drv_data) & BIT_STAT_TXS)
316 cpu_relax();
317
318 cs_deactive(drv_data, chip);
319
320 ++drv_data->tx;
321 }
322 }
323
324 static void u8_reader(struct driver_data *drv_data)
325 {
326 dev_dbg(&drv_data->pdev->dev,
327 "cr-8 is 0x%x\n", read_STAT(drv_data));
328
329 /* poll for SPI completion before start */
330 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
331 cpu_relax();
332
333 /* clear TDBR buffer before read(else it will be shifted out) */
334 write_TDBR(drv_data, 0xFFFF);
335
336 dummy_read(drv_data);
337
338 while (drv_data->rx < drv_data->rx_end - 1) {
339 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
340 cpu_relax();
341 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
342 ++drv_data->rx;
343 }
344
345 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
346 cpu_relax();
347 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
348 ++drv_data->rx;
349 }
350
351 static void u8_cs_chg_reader(struct driver_data *drv_data)
352 {
353 struct chip_data *chip = drv_data->cur_chip;
354
355 /* poll for SPI completion before start */
356 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
357 cpu_relax();
358
359 /* clear TDBR buffer before read(else it will be shifted out) */
360 write_TDBR(drv_data, 0xFFFF);
361
362 cs_active(drv_data, chip);
363 dummy_read(drv_data);
364
365 while (drv_data->rx < drv_data->rx_end - 1) {
366 cs_deactive(drv_data, chip);
367
368 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
369 cpu_relax();
370 cs_active(drv_data, chip);
371 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
372 ++drv_data->rx;
373 }
374 cs_deactive(drv_data, chip);
375
376 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
377 cpu_relax();
378 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
379 ++drv_data->rx;
380 }
381
382 static void u8_duplex(struct driver_data *drv_data)
383 {
384 /* poll for SPI completion before start */
385 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
386 cpu_relax();
387
388 /* in duplex mode, clk is triggered by writing of TDBR */
389 while (drv_data->rx < drv_data->rx_end) {
390 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
391 while (read_STAT(drv_data) & BIT_STAT_TXS)
392 cpu_relax();
393 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
394 cpu_relax();
395 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
396 ++drv_data->rx;
397 ++drv_data->tx;
398 }
399 }
400
401 static void u8_cs_chg_duplex(struct driver_data *drv_data)
402 {
403 struct chip_data *chip = drv_data->cur_chip;
404
405 /* poll for SPI completion before start */
406 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
407 cpu_relax();
408
409 while (drv_data->rx < drv_data->rx_end) {
410 cs_active(drv_data, chip);
411
412 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
413 while (read_STAT(drv_data) & BIT_STAT_TXS)
414 cpu_relax();
415 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
416 cpu_relax();
417 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
418
419 cs_deactive(drv_data, chip);
420
421 ++drv_data->rx;
422 ++drv_data->tx;
423 }
424 }
425
426 static void u16_writer(struct driver_data *drv_data)
427 {
428 dev_dbg(&drv_data->pdev->dev,
429 "cr16 is 0x%x\n", read_STAT(drv_data));
430
431 /* poll for SPI completion before start */
432 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
433 cpu_relax();
434
435 while (drv_data->tx < drv_data->tx_end) {
436 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
437 while ((read_STAT(drv_data) & BIT_STAT_TXS))
438 cpu_relax();
439 drv_data->tx += 2;
440 }
441 }
442
443 static void u16_cs_chg_writer(struct driver_data *drv_data)
444 {
445 struct chip_data *chip = drv_data->cur_chip;
446
447 /* poll for SPI completion before start */
448 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
449 cpu_relax();
450
451 while (drv_data->tx < drv_data->tx_end) {
452 cs_active(drv_data, chip);
453
454 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
455 while ((read_STAT(drv_data) & BIT_STAT_TXS))
456 cpu_relax();
457
458 cs_deactive(drv_data, chip);
459
460 drv_data->tx += 2;
461 }
462 }
463
464 static void u16_reader(struct driver_data *drv_data)
465 {
466 dev_dbg(&drv_data->pdev->dev,
467 "cr-16 is 0x%x\n", read_STAT(drv_data));
468
469 /* poll for SPI completion before start */
470 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
471 cpu_relax();
472
473 /* clear TDBR buffer before read(else it will be shifted out) */
474 write_TDBR(drv_data, 0xFFFF);
475
476 dummy_read(drv_data);
477
478 while (drv_data->rx < (drv_data->rx_end - 2)) {
479 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
480 cpu_relax();
481 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
482 drv_data->rx += 2;
483 }
484
485 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
486 cpu_relax();
487 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
488 drv_data->rx += 2;
489 }
490
491 static void u16_cs_chg_reader(struct driver_data *drv_data)
492 {
493 struct chip_data *chip = drv_data->cur_chip;
494
495 /* poll for SPI completion before start */
496 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
497 cpu_relax();
498
499 /* clear TDBR buffer before read(else it will be shifted out) */
500 write_TDBR(drv_data, 0xFFFF);
501
502 cs_active(drv_data, chip);
503 dummy_read(drv_data);
504
505 while (drv_data->rx < drv_data->rx_end - 2) {
506 cs_deactive(drv_data, chip);
507
508 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
509 cpu_relax();
510 cs_active(drv_data, chip);
511 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
512 drv_data->rx += 2;
513 }
514 cs_deactive(drv_data, chip);
515
516 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
517 cpu_relax();
518 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
519 drv_data->rx += 2;
520 }
521
522 static void u16_duplex(struct driver_data *drv_data)
523 {
524 /* poll for SPI completion before start */
525 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
526 cpu_relax();
527
528 /* in duplex mode, clk is triggered by writing of TDBR */
529 while (drv_data->tx < drv_data->tx_end) {
530 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
531 while (read_STAT(drv_data) & BIT_STAT_TXS)
532 cpu_relax();
533 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
534 cpu_relax();
535 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
536 drv_data->rx += 2;
537 drv_data->tx += 2;
538 }
539 }
540
541 static void u16_cs_chg_duplex(struct driver_data *drv_data)
542 {
543 struct chip_data *chip = drv_data->cur_chip;
544
545 /* poll for SPI completion before start */
546 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
547 cpu_relax();
548
549 while (drv_data->tx < drv_data->tx_end) {
550 cs_active(drv_data, chip);
551
552 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
553 while (read_STAT(drv_data) & BIT_STAT_TXS)
554 cpu_relax();
555 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
556 cpu_relax();
557 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
558
559 cs_deactive(drv_data, chip);
560
561 drv_data->rx += 2;
562 drv_data->tx += 2;
563 }
564 }
565
566 /* test if ther is more transfer to be done */
567 static void *next_transfer(struct driver_data *drv_data)
568 {
569 struct spi_message *msg = drv_data->cur_msg;
570 struct spi_transfer *trans = drv_data->cur_transfer;
571
572 /* Move to next transfer */
573 if (trans->transfer_list.next != &msg->transfers) {
574 drv_data->cur_transfer =
575 list_entry(trans->transfer_list.next,
576 struct spi_transfer, transfer_list);
577 return RUNNING_STATE;
578 } else
579 return DONE_STATE;
580 }
581
582 /*
583 * caller already set message->status;
584 * dma and pio irqs are blocked give finished message back
585 */
586 static void giveback(struct driver_data *drv_data)
587 {
588 struct chip_data *chip = drv_data->cur_chip;
589 struct spi_transfer *last_transfer;
590 unsigned long flags;
591 struct spi_message *msg;
592
593 spin_lock_irqsave(&drv_data->lock, flags);
594 msg = drv_data->cur_msg;
595 drv_data->cur_msg = NULL;
596 drv_data->cur_transfer = NULL;
597 drv_data->cur_chip = NULL;
598 queue_work(drv_data->workqueue, &drv_data->pump_messages);
599 spin_unlock_irqrestore(&drv_data->lock, flags);
600
601 last_transfer = list_entry(msg->transfers.prev,
602 struct spi_transfer, transfer_list);
603
604 msg->state = NULL;
605
606 /* disable chip select signal. And not stop spi in autobuffer mode */
607 if (drv_data->tx_dma != 0xFFFF) {
608 cs_deactive(drv_data, chip);
609 bfin_spi_disable(drv_data);
610 }
611
612 if (!drv_data->cs_change)
613 cs_deactive(drv_data, chip);
614
615 if (msg->complete)
616 msg->complete(msg->context);
617 }
618
619 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
620 {
621 struct driver_data *drv_data = (struct driver_data *)dev_id;
622 struct chip_data *chip = drv_data->cur_chip;
623 struct spi_message *msg = drv_data->cur_msg;
624
625 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
626 clear_dma_irqstat(drv_data->dma_channel);
627
628 /* Wait for DMA to complete */
629 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
630 cpu_relax();
631
632 /*
633 * wait for the last transaction shifted out. HRM states:
634 * at this point there may still be data in the SPI DMA FIFO waiting
635 * to be transmitted ... software needs to poll TXS in the SPI_STAT
636 * register until it goes low for 2 successive reads
637 */
638 if (drv_data->tx != NULL) {
639 while ((read_STAT(drv_data) & TXS) ||
640 (read_STAT(drv_data) & TXS))
641 cpu_relax();
642 }
643
644 while (!(read_STAT(drv_data) & SPIF))
645 cpu_relax();
646
647 msg->actual_length += drv_data->len_in_bytes;
648
649 if (drv_data->cs_change)
650 cs_deactive(drv_data, chip);
651
652 /* Move to next transfer */
653 msg->state = next_transfer(drv_data);
654
655 /* Schedule transfer tasklet */
656 tasklet_schedule(&drv_data->pump_transfers);
657
658 /* free the irq handler before next transfer */
659 dev_dbg(&drv_data->pdev->dev,
660 "disable dma channel irq%d\n",
661 drv_data->dma_channel);
662 dma_disable_irq(drv_data->dma_channel);
663
664 return IRQ_HANDLED;
665 }
666
667 static void pump_transfers(unsigned long data)
668 {
669 struct driver_data *drv_data = (struct driver_data *)data;
670 struct spi_message *message = NULL;
671 struct spi_transfer *transfer = NULL;
672 struct spi_transfer *previous = NULL;
673 struct chip_data *chip = NULL;
674 u8 width;
675 u16 cr, dma_width, dma_config;
676 u32 tranf_success = 1;
677
678 /* Get current state information */
679 message = drv_data->cur_msg;
680 transfer = drv_data->cur_transfer;
681 chip = drv_data->cur_chip;
682 /*
683 * if msg is error or done, report it back using complete() callback
684 */
685
686 /* Handle for abort */
687 if (message->state == ERROR_STATE) {
688 message->status = -EIO;
689 giveback(drv_data);
690 return;
691 }
692
693 /* Handle end of message */
694 if (message->state == DONE_STATE) {
695 message->status = 0;
696 giveback(drv_data);
697 return;
698 }
699
700 /* Delay if requested at end of transfer */
701 if (message->state == RUNNING_STATE) {
702 previous = list_entry(transfer->transfer_list.prev,
703 struct spi_transfer, transfer_list);
704 if (previous->delay_usecs)
705 udelay(previous->delay_usecs);
706 }
707
708 /* Setup the transfer state based on the type of transfer */
709 if (flush(drv_data) == 0) {
710 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
711 message->status = -EIO;
712 giveback(drv_data);
713 return;
714 }
715
716 if (transfer->tx_buf != NULL) {
717 drv_data->tx = (void *)transfer->tx_buf;
718 drv_data->tx_end = drv_data->tx + transfer->len;
719 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
720 transfer->tx_buf, drv_data->tx_end);
721 } else {
722 drv_data->tx = NULL;
723 }
724
725 if (transfer->rx_buf != NULL) {
726 drv_data->rx = transfer->rx_buf;
727 drv_data->rx_end = drv_data->rx + transfer->len;
728 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
729 transfer->rx_buf, drv_data->rx_end);
730 } else {
731 drv_data->rx = NULL;
732 }
733
734 drv_data->rx_dma = transfer->rx_dma;
735 drv_data->tx_dma = transfer->tx_dma;
736 drv_data->len_in_bytes = transfer->len;
737 drv_data->cs_change = transfer->cs_change;
738
739 width = chip->width;
740 if (width == CFG_SPI_WORDSIZE16) {
741 drv_data->len = (transfer->len) >> 1;
742 } else {
743 drv_data->len = transfer->len;
744 }
745 drv_data->write = drv_data->tx ? chip->write : null_writer;
746 drv_data->read = drv_data->rx ? chip->read : null_reader;
747 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
748 dev_dbg(&drv_data->pdev->dev, "transfer: ",
749 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
750 drv_data->write, chip->write, null_writer);
751
752 /* speed and width has been set on per message */
753 message->state = RUNNING_STATE;
754 dma_config = 0;
755
756 write_STAT(drv_data, BIT_STAT_CLR);
757 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
758 cs_active(drv_data, chip);
759
760 dev_dbg(&drv_data->pdev->dev,
761 "now pumping a transfer: width is %d, len is %d\n",
762 width, transfer->len);
763
764 /*
765 * Try to map dma buffer and do a dma transfer if
766 * successful use different way to r/w according to
767 * drv_data->cur_chip->enable_dma
768 */
769 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
770
771 disable_dma(drv_data->dma_channel);
772 clear_dma_irqstat(drv_data->dma_channel);
773 bfin_spi_disable(drv_data);
774
775 /* config dma channel */
776 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
777 if (width == CFG_SPI_WORDSIZE16) {
778 set_dma_x_count(drv_data->dma_channel, drv_data->len);
779 set_dma_x_modify(drv_data->dma_channel, 2);
780 dma_width = WDSIZE_16;
781 } else {
782 set_dma_x_count(drv_data->dma_channel, drv_data->len);
783 set_dma_x_modify(drv_data->dma_channel, 1);
784 dma_width = WDSIZE_8;
785 }
786
787 /* poll for SPI completion before start */
788 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
789 cpu_relax();
790
791 /* dirty hack for autobuffer DMA mode */
792 if (drv_data->tx_dma == 0xFFFF) {
793 dev_dbg(&drv_data->pdev->dev,
794 "doing autobuffer DMA out.\n");
795
796 /* no irq in autobuffer mode */
797 dma_config =
798 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
799 set_dma_config(drv_data->dma_channel, dma_config);
800 set_dma_start_addr(drv_data->dma_channel,
801 (unsigned long)drv_data->tx);
802 enable_dma(drv_data->dma_channel);
803
804 /* start SPI transfer */
805 write_CTRL(drv_data,
806 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
807
808 /* just return here, there can only be one transfer
809 * in this mode
810 */
811 message->status = 0;
812 giveback(drv_data);
813 return;
814 }
815
816 /* In dma mode, rx or tx must be NULL in one transfer */
817 if (drv_data->rx != NULL) {
818 /* set transfer mode, and enable SPI */
819 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
820
821 /* clear tx reg soformer data is not shifted out */
822 write_TDBR(drv_data, 0xFFFF);
823
824 set_dma_x_count(drv_data->dma_channel, drv_data->len);
825
826 /* start dma */
827 dma_enable_irq(drv_data->dma_channel);
828 dma_config = (WNR | RESTART | dma_width | DI_EN);
829 set_dma_config(drv_data->dma_channel, dma_config);
830 set_dma_start_addr(drv_data->dma_channel,
831 (unsigned long)drv_data->rx);
832 enable_dma(drv_data->dma_channel);
833
834 /* start SPI transfer */
835 write_CTRL(drv_data,
836 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
837
838 } else if (drv_data->tx != NULL) {
839 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
840
841 /* start dma */
842 dma_enable_irq(drv_data->dma_channel);
843 dma_config = (RESTART | dma_width | DI_EN);
844 set_dma_config(drv_data->dma_channel, dma_config);
845 set_dma_start_addr(drv_data->dma_channel,
846 (unsigned long)drv_data->tx);
847 enable_dma(drv_data->dma_channel);
848
849 /* start SPI transfer */
850 write_CTRL(drv_data,
851 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
852 }
853 } else {
854 /* IO mode write then read */
855 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
856
857 if (drv_data->tx != NULL && drv_data->rx != NULL) {
858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
863
864 /* set SPI transfer mode */
865 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
866
867 drv_data->duplex(drv_data);
868
869 if (drv_data->tx != drv_data->tx_end)
870 tranf_success = 0;
871 } else if (drv_data->tx != NULL) {
872 /* write only half duplex */
873 dev_dbg(&drv_data->pdev->dev,
874 "IO write: cr is 0x%x\n", cr);
875
876 /* set SPI transfer mode */
877 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
878
879 drv_data->write(drv_data);
880
881 if (drv_data->tx != drv_data->tx_end)
882 tranf_success = 0;
883 } else if (drv_data->rx != NULL) {
884 /* read only half duplex */
885 dev_dbg(&drv_data->pdev->dev,
886 "IO read: cr is 0x%x\n", cr);
887
888 /* set SPI transfer mode */
889 write_CTRL(drv_data, (cr | CFG_SPI_READ));
890
891 drv_data->read(drv_data);
892 if (drv_data->rx != drv_data->rx_end)
893 tranf_success = 0;
894 }
895
896 if (!tranf_success) {
897 dev_dbg(&drv_data->pdev->dev,
898 "IO write error!\n");
899 message->state = ERROR_STATE;
900 } else {
901 /* Update total byte transfered */
902 message->actual_length += drv_data->len;
903
904 /* Move to next transfer of this msg */
905 message->state = next_transfer(drv_data);
906 }
907
908 /* Schedule next transfer tasklet */
909 tasklet_schedule(&drv_data->pump_transfers);
910
911 }
912 }
913
914 /* pop a msg from queue and kick off real transfer */
915 static void pump_messages(struct work_struct *work)
916 {
917 struct driver_data *drv_data;
918 unsigned long flags;
919
920 drv_data = container_of(work, struct driver_data, pump_messages);
921
922 /* Lock queue and check for queue work */
923 spin_lock_irqsave(&drv_data->lock, flags);
924 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
925 /* pumper kicked off but no work to do */
926 drv_data->busy = 0;
927 spin_unlock_irqrestore(&drv_data->lock, flags);
928 return;
929 }
930
931 /* Make sure we are not already running a message */
932 if (drv_data->cur_msg) {
933 spin_unlock_irqrestore(&drv_data->lock, flags);
934 return;
935 }
936
937 /* Extract head of queue */
938 drv_data->cur_msg = list_entry(drv_data->queue.next,
939 struct spi_message, queue);
940
941 /* Setup the SSP using the per chip configuration */
942 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
943 if (restore_state(drv_data)) {
944 spin_unlock_irqrestore(&drv_data->lock, flags);
945 return;
946 };
947
948 list_del_init(&drv_data->cur_msg->queue);
949
950 /* Initial message state */
951 drv_data->cur_msg->state = START_STATE;
952 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
953 struct spi_transfer, transfer_list);
954
955 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
956 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
957 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
958 drv_data->cur_chip->ctl_reg);
959
960 dev_dbg(&drv_data->pdev->dev,
961 "the first transfer len is %d\n",
962 drv_data->cur_transfer->len);
963
964 /* Mark as busy and launch transfers */
965 tasklet_schedule(&drv_data->pump_transfers);
966
967 drv_data->busy = 1;
968 spin_unlock_irqrestore(&drv_data->lock, flags);
969 }
970
971 /*
972 * got a msg to transfer, queue it in drv_data->queue.
973 * And kick off message pumper
974 */
975 static int transfer(struct spi_device *spi, struct spi_message *msg)
976 {
977 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
978 unsigned long flags;
979
980 spin_lock_irqsave(&drv_data->lock, flags);
981
982 if (drv_data->run == QUEUE_STOPPED) {
983 spin_unlock_irqrestore(&drv_data->lock, flags);
984 return -ESHUTDOWN;
985 }
986
987 msg->actual_length = 0;
988 msg->status = -EINPROGRESS;
989 msg->state = START_STATE;
990
991 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
992 list_add_tail(&msg->queue, &drv_data->queue);
993
994 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
995 queue_work(drv_data->workqueue, &drv_data->pump_messages);
996
997 spin_unlock_irqrestore(&drv_data->lock, flags);
998
999 return 0;
1000 }
1001
1002 #define MAX_SPI_SSEL 7
1003
1004 static u16 ssel[3][MAX_SPI_SSEL] = {
1005 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1006 P_SPI0_SSEL4, P_SPI0_SSEL5,
1007 P_SPI0_SSEL6, P_SPI0_SSEL7},
1008
1009 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1010 P_SPI1_SSEL4, P_SPI1_SSEL5,
1011 P_SPI1_SSEL6, P_SPI1_SSEL7},
1012
1013 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1014 P_SPI2_SSEL4, P_SPI2_SSEL5,
1015 P_SPI2_SSEL6, P_SPI2_SSEL7},
1016 };
1017
1018 /* first setup for new devices */
1019 static int setup(struct spi_device *spi)
1020 {
1021 struct bfin5xx_spi_chip *chip_info = NULL;
1022 struct chip_data *chip;
1023 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1024 u8 spi_flg;
1025
1026 /* Abort device setup if requested features are not supported */
1027 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1028 dev_err(&spi->dev, "requested mode not fully supported\n");
1029 return -EINVAL;
1030 }
1031
1032 /* Zero (the default) here means 8 bits */
1033 if (!spi->bits_per_word)
1034 spi->bits_per_word = 8;
1035
1036 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1037 return -EINVAL;
1038
1039 /* Only alloc (or use chip_info) on first setup */
1040 chip = spi_get_ctldata(spi);
1041 if (chip == NULL) {
1042 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1043 if (!chip)
1044 return -ENOMEM;
1045
1046 chip->enable_dma = 0;
1047 chip_info = spi->controller_data;
1048 }
1049
1050 /* chip_info isn't always needed */
1051 if (chip_info) {
1052 /* Make sure people stop trying to set fields via ctl_reg
1053 * when they should actually be using common SPI framework.
1054 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1055 * Not sure if a user actually needs/uses any of these,
1056 * but let's assume (for now) they do.
1057 */
1058 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1059 dev_err(&spi->dev, "do not set bits in ctl_reg "
1060 "that the SPI framework manages\n");
1061 return -EINVAL;
1062 }
1063
1064 chip->enable_dma = chip_info->enable_dma != 0
1065 && drv_data->master_info->enable_dma;
1066 chip->ctl_reg = chip_info->ctl_reg;
1067 chip->bits_per_word = chip_info->bits_per_word;
1068 chip->cs_change_per_word = chip_info->cs_change_per_word;
1069 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1070 }
1071
1072 /* translate common spi framework into our register */
1073 if (spi->mode & SPI_CPOL)
1074 chip->ctl_reg |= CPOL;
1075 if (spi->mode & SPI_CPHA)
1076 chip->ctl_reg |= CPHA;
1077 if (spi->mode & SPI_LSB_FIRST)
1078 chip->ctl_reg |= LSBF;
1079 /* we dont support running in slave mode (yet?) */
1080 chip->ctl_reg |= MSTR;
1081
1082 /*
1083 * if any one SPI chip is registered and wants DMA, request the
1084 * DMA channel for it
1085 */
1086 if (chip->enable_dma && !drv_data->dma_requested) {
1087 /* register dma irq handler */
1088 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1089 dev_dbg(&spi->dev,
1090 "Unable to request BlackFin SPI DMA channel\n");
1091 return -ENODEV;
1092 }
1093 if (set_dma_callback(drv_data->dma_channel,
1094 (void *)dma_irq_handler, drv_data) < 0) {
1095 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1096 return -EPERM;
1097 }
1098 dma_disable_irq(drv_data->dma_channel);
1099 drv_data->dma_requested = 1;
1100 }
1101
1102 /*
1103 * Notice: for blackfin, the speed_hz is the value of register
1104 * SPI_BAUD, not the real baudrate
1105 */
1106 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1107 spi_flg = ~(1 << (spi->chip_select));
1108 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1109 chip->chip_select_num = spi->chip_select;
1110
1111 switch (chip->bits_per_word) {
1112 case 8:
1113 chip->n_bytes = 1;
1114 chip->width = CFG_SPI_WORDSIZE8;
1115 chip->read = chip->cs_change_per_word ?
1116 u8_cs_chg_reader : u8_reader;
1117 chip->write = chip->cs_change_per_word ?
1118 u8_cs_chg_writer : u8_writer;
1119 chip->duplex = chip->cs_change_per_word ?
1120 u8_cs_chg_duplex : u8_duplex;
1121 break;
1122
1123 case 16:
1124 chip->n_bytes = 2;
1125 chip->width = CFG_SPI_WORDSIZE16;
1126 chip->read = chip->cs_change_per_word ?
1127 u16_cs_chg_reader : u16_reader;
1128 chip->write = chip->cs_change_per_word ?
1129 u16_cs_chg_writer : u16_writer;
1130 chip->duplex = chip->cs_change_per_word ?
1131 u16_cs_chg_duplex : u16_duplex;
1132 break;
1133
1134 default:
1135 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1136 chip->bits_per_word);
1137 kfree(chip);
1138 return -ENODEV;
1139 }
1140
1141 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1142 spi->modalias, chip->width, chip->enable_dma);
1143 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1144 chip->ctl_reg, chip->flag);
1145
1146 spi_set_ctldata(spi, chip);
1147
1148 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1149 if ((chip->chip_select_num > 0)
1150 && (chip->chip_select_num <= spi->master->num_chipselect))
1151 peripheral_request(ssel[spi->master->bus_num]
1152 [chip->chip_select_num-1], DRV_NAME);
1153
1154 cs_deactive(drv_data, chip);
1155
1156 return 0;
1157 }
1158
1159 /*
1160 * callback for spi framework.
1161 * clean driver specific data
1162 */
1163 static void cleanup(struct spi_device *spi)
1164 {
1165 struct chip_data *chip = spi_get_ctldata(spi);
1166
1167 if ((chip->chip_select_num > 0)
1168 && (chip->chip_select_num <= spi->master->num_chipselect))
1169 peripheral_free(ssel[spi->master->bus_num]
1170 [chip->chip_select_num-1]);
1171
1172 kfree(chip);
1173 }
1174
1175 static inline int init_queue(struct driver_data *drv_data)
1176 {
1177 INIT_LIST_HEAD(&drv_data->queue);
1178 spin_lock_init(&drv_data->lock);
1179
1180 drv_data->run = QUEUE_STOPPED;
1181 drv_data->busy = 0;
1182
1183 /* init transfer tasklet */
1184 tasklet_init(&drv_data->pump_transfers,
1185 pump_transfers, (unsigned long)drv_data);
1186
1187 /* init messages workqueue */
1188 INIT_WORK(&drv_data->pump_messages, pump_messages);
1189 drv_data->workqueue =
1190 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1191 if (drv_data->workqueue == NULL)
1192 return -EBUSY;
1193
1194 return 0;
1195 }
1196
1197 static inline int start_queue(struct driver_data *drv_data)
1198 {
1199 unsigned long flags;
1200
1201 spin_lock_irqsave(&drv_data->lock, flags);
1202
1203 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1204 spin_unlock_irqrestore(&drv_data->lock, flags);
1205 return -EBUSY;
1206 }
1207
1208 drv_data->run = QUEUE_RUNNING;
1209 drv_data->cur_msg = NULL;
1210 drv_data->cur_transfer = NULL;
1211 drv_data->cur_chip = NULL;
1212 spin_unlock_irqrestore(&drv_data->lock, flags);
1213
1214 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1215
1216 return 0;
1217 }
1218
1219 static inline int stop_queue(struct driver_data *drv_data)
1220 {
1221 unsigned long flags;
1222 unsigned limit = 500;
1223 int status = 0;
1224
1225 spin_lock_irqsave(&drv_data->lock, flags);
1226
1227 /*
1228 * This is a bit lame, but is optimized for the common execution path.
1229 * A wait_queue on the drv_data->busy could be used, but then the common
1230 * execution path (pump_messages) would be required to call wake_up or
1231 * friends on every SPI message. Do this instead
1232 */
1233 drv_data->run = QUEUE_STOPPED;
1234 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1235 spin_unlock_irqrestore(&drv_data->lock, flags);
1236 msleep(10);
1237 spin_lock_irqsave(&drv_data->lock, flags);
1238 }
1239
1240 if (!list_empty(&drv_data->queue) || drv_data->busy)
1241 status = -EBUSY;
1242
1243 spin_unlock_irqrestore(&drv_data->lock, flags);
1244
1245 return status;
1246 }
1247
1248 static inline int destroy_queue(struct driver_data *drv_data)
1249 {
1250 int status;
1251
1252 status = stop_queue(drv_data);
1253 if (status != 0)
1254 return status;
1255
1256 destroy_workqueue(drv_data->workqueue);
1257
1258 return 0;
1259 }
1260
1261 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1262 {
1263 struct device *dev = &pdev->dev;
1264 struct bfin5xx_spi_master *platform_info;
1265 struct spi_master *master;
1266 struct driver_data *drv_data = 0;
1267 struct resource *res;
1268 int status = 0;
1269
1270 platform_info = dev->platform_data;
1271
1272 /* Allocate master with space for drv_data */
1273 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1274 if (!master) {
1275 dev_err(&pdev->dev, "can not alloc spi_master\n");
1276 return -ENOMEM;
1277 }
1278
1279 drv_data = spi_master_get_devdata(master);
1280 drv_data->master = master;
1281 drv_data->master_info = platform_info;
1282 drv_data->pdev = pdev;
1283 drv_data->pin_req = platform_info->pin_req;
1284
1285 master->bus_num = pdev->id;
1286 master->num_chipselect = platform_info->num_chipselect;
1287 master->cleanup = cleanup;
1288 master->setup = setup;
1289 master->transfer = transfer;
1290
1291 /* Find and map our resources */
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 if (res == NULL) {
1294 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1295 status = -ENOENT;
1296 goto out_error_get_res;
1297 }
1298
1299 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1300 if (drv_data->regs_base == NULL) {
1301 dev_err(dev, "Cannot map IO\n");
1302 status = -ENXIO;
1303 goto out_error_ioremap;
1304 }
1305
1306 drv_data->dma_channel = platform_get_irq(pdev, 0);
1307 if (drv_data->dma_channel < 0) {
1308 dev_err(dev, "No DMA channel specified\n");
1309 status = -ENOENT;
1310 goto out_error_no_dma_ch;
1311 }
1312
1313 /* Initial and start queue */
1314 status = init_queue(drv_data);
1315 if (status != 0) {
1316 dev_err(dev, "problem initializing queue\n");
1317 goto out_error_queue_alloc;
1318 }
1319
1320 status = start_queue(drv_data);
1321 if (status != 0) {
1322 dev_err(dev, "problem starting queue\n");
1323 goto out_error_queue_alloc;
1324 }
1325
1326 /* Register with the SPI framework */
1327 platform_set_drvdata(pdev, drv_data);
1328 status = spi_register_master(master);
1329 if (status != 0) {
1330 dev_err(dev, "problem registering spi master\n");
1331 goto out_error_queue_alloc;
1332 }
1333
1334 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1335 if (status != 0) {
1336 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1337 goto out_error;
1338 }
1339
1340 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1341 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1342 drv_data->dma_channel);
1343 return status;
1344
1345 out_error_queue_alloc:
1346 destroy_queue(drv_data);
1347 out_error_no_dma_ch:
1348 iounmap((void *) drv_data->regs_base);
1349 out_error_ioremap:
1350 out_error_get_res:
1351 out_error:
1352 spi_master_put(master);
1353
1354 return status;
1355 }
1356
1357 /* stop hardware and remove the driver */
1358 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1359 {
1360 struct driver_data *drv_data = platform_get_drvdata(pdev);
1361 int status = 0;
1362
1363 if (!drv_data)
1364 return 0;
1365
1366 /* Remove the queue */
1367 status = destroy_queue(drv_data);
1368 if (status != 0)
1369 return status;
1370
1371 /* Disable the SSP at the peripheral and SOC level */
1372 bfin_spi_disable(drv_data);
1373
1374 /* Release DMA */
1375 if (drv_data->master_info->enable_dma) {
1376 if (dma_channel_active(drv_data->dma_channel))
1377 free_dma(drv_data->dma_channel);
1378 }
1379
1380 /* Disconnect from the SPI framework */
1381 spi_unregister_master(drv_data->master);
1382
1383 peripheral_free_list(drv_data->pin_req);
1384
1385 /* Prevent double remove */
1386 platform_set_drvdata(pdev, NULL);
1387
1388 return 0;
1389 }
1390
1391 #ifdef CONFIG_PM
1392 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1393 {
1394 struct driver_data *drv_data = platform_get_drvdata(pdev);
1395 int status = 0;
1396
1397 status = stop_queue(drv_data);
1398 if (status != 0)
1399 return status;
1400
1401 /* stop hardware */
1402 bfin_spi_disable(drv_data);
1403
1404 return 0;
1405 }
1406
1407 static int bfin5xx_spi_resume(struct platform_device *pdev)
1408 {
1409 struct driver_data *drv_data = platform_get_drvdata(pdev);
1410 int status = 0;
1411
1412 /* Enable the SPI interface */
1413 bfin_spi_enable(drv_data);
1414
1415 /* Start the queue running */
1416 status = start_queue(drv_data);
1417 if (status != 0) {
1418 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1419 return status;
1420 }
1421
1422 return 0;
1423 }
1424 #else
1425 #define bfin5xx_spi_suspend NULL
1426 #define bfin5xx_spi_resume NULL
1427 #endif /* CONFIG_PM */
1428
1429 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1430 static struct platform_driver bfin5xx_spi_driver = {
1431 .driver = {
1432 .name = DRV_NAME,
1433 .owner = THIS_MODULE,
1434 },
1435 .suspend = bfin5xx_spi_suspend,
1436 .resume = bfin5xx_spi_resume,
1437 .remove = __devexit_p(bfin5xx_spi_remove),
1438 };
1439
1440 static int __init bfin5xx_spi_init(void)
1441 {
1442 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1443 }
1444 module_init(bfin5xx_spi_init);
1445
1446 static void __exit bfin5xx_spi_exit(void)
1447 {
1448 platform_driver_unregister(&bfin5xx_spi_driver);
1449 }
1450 module_exit(bfin5xx_spi_exit);
ubuntu-zesty-kernel mirror