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Blackfin SPI Driver: fix bug - spi controller driver does not assert/deassert CS...
[mirror_ubuntu-kernels.git] / drivers / spi / spi_bfin5xx.c
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
29
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
34
35 MODULE_AUTHOR(DRV_AUTHOR);
36 MODULE_DESCRIPTION(DRV_DESC);
37 MODULE_LICENSE("GPL");
38
39 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
40
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45 #define QUEUE_RUNNING 0
46 #define QUEUE_STOPPED 1
47
48 struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
55 /* Regs base of SPI controller */
56 void __iomem *regs_base;
57
58 /* Pin request list */
59 u16 *pin_req;
60
61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
85
86 /* DMA stuffs */
87 int dma_channel;
88 int dma_mapped;
89 int dma_requested;
90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
92
93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
96 int cs_change;
97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100 };
101
102 struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
109 u8 width; /* 0 or 1 */
110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117 };
118
119 #define DEFINE_SPI_REG(reg, off) \
120 static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125 DEFINE_SPI_REG(CTRL, 0x00)
126 DEFINE_SPI_REG(FLAG, 0x04)
127 DEFINE_SPI_REG(STAT, 0x08)
128 DEFINE_SPI_REG(TDBR, 0x0C)
129 DEFINE_SPI_REG(RDBR, 0x10)
130 DEFINE_SPI_REG(BAUD, 0x14)
131 DEFINE_SPI_REG(SHAW, 0x18)
132
133 static void bfin_spi_enable(struct driver_data *drv_data)
134 {
135 u16 cr;
136
137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
139 }
140
141 static void bfin_spi_disable(struct driver_data *drv_data)
142 {
143 u16 cr;
144
145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
147 }
148
149 /* Caculate the SPI_BAUD register value based on input HZ */
150 static u16 hz_to_spi_baud(u32 speed_hz)
151 {
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
161 return spi_baud;
162 }
163
164 static int flush(struct driver_data *drv_data)
165 {
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
170 cpu_relax();
171
172 write_STAT(drv_data, BIT_STAT_CLR);
173
174 return limit;
175 }
176
177 /* Chip select operation functions for cs_change flag */
178 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
179 {
180 u16 flag = read_FLAG(drv_data);
181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
185 write_FLAG(drv_data, flag);
186 }
187
188 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
189 {
190 u16 flag = read_FLAG(drv_data);
191
192 flag &= ~chip->flag;
193 flag |= (chip->flag << 8);
194
195 write_FLAG(drv_data, flag);
196
197 /* Move delay here for consistency */
198 if (chip->cs_chg_udelay)
199 udelay(chip->cs_chg_udelay);
200 }
201
202 /* stop controller and re-config current chip*/
203 static void restore_state(struct driver_data *drv_data)
204 {
205 struct chip_data *chip = drv_data->cur_chip;
206
207 /* Clear status and disable clock */
208 write_STAT(drv_data, BIT_STAT_CLR);
209 bfin_spi_disable(drv_data);
210 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
211
212 /* Load the registers */
213 write_CTRL(drv_data, chip->ctl_reg);
214 write_BAUD(drv_data, chip->baud);
215
216 bfin_spi_enable(drv_data);
217 cs_active(drv_data, chip);
218 }
219
220 /* used to kick off transfer in rx mode */
221 static unsigned short dummy_read(struct driver_data *drv_data)
222 {
223 unsigned short tmp;
224 tmp = read_RDBR(drv_data);
225 return tmp;
226 }
227
228 static void null_writer(struct driver_data *drv_data)
229 {
230 u8 n_bytes = drv_data->n_bytes;
231
232 while (drv_data->tx < drv_data->tx_end) {
233 write_TDBR(drv_data, 0);
234 while ((read_STAT(drv_data) & BIT_STAT_TXS))
235 cpu_relax();
236 drv_data->tx += n_bytes;
237 }
238 }
239
240 static void null_reader(struct driver_data *drv_data)
241 {
242 u8 n_bytes = drv_data->n_bytes;
243 dummy_read(drv_data);
244
245 while (drv_data->rx < drv_data->rx_end) {
246 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
247 cpu_relax();
248 dummy_read(drv_data);
249 drv_data->rx += n_bytes;
250 }
251 }
252
253 static void u8_writer(struct driver_data *drv_data)
254 {
255 dev_dbg(&drv_data->pdev->dev,
256 "cr8-s is 0x%x\n", read_STAT(drv_data));
257
258 while (drv_data->tx < drv_data->tx_end) {
259 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
260 while (read_STAT(drv_data) & BIT_STAT_TXS)
261 cpu_relax();
262 ++drv_data->tx;
263 }
264
265 /* poll for SPI completion before return */
266 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
267 cpu_relax();
268 }
269
270 static void u8_cs_chg_writer(struct driver_data *drv_data)
271 {
272 struct chip_data *chip = drv_data->cur_chip;
273
274 while (drv_data->tx < drv_data->tx_end) {
275 cs_active(drv_data, chip);
276
277 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
278 while (read_STAT(drv_data) & BIT_STAT_TXS)
279 cpu_relax();
280 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
281 cpu_relax();
282
283 cs_deactive(drv_data, chip);
284
285 ++drv_data->tx;
286 }
287 }
288
289 static void u8_reader(struct driver_data *drv_data)
290 {
291 dev_dbg(&drv_data->pdev->dev,
292 "cr-8 is 0x%x\n", read_STAT(drv_data));
293
294 /* poll for SPI completion before start */
295 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
296 cpu_relax();
297
298 /* clear TDBR buffer before read(else it will be shifted out) */
299 write_TDBR(drv_data, 0xFFFF);
300
301 dummy_read(drv_data);
302
303 while (drv_data->rx < drv_data->rx_end - 1) {
304 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
305 cpu_relax();
306 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
307 ++drv_data->rx;
308 }
309
310 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
311 cpu_relax();
312 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
313 ++drv_data->rx;
314 }
315
316 static void u8_cs_chg_reader(struct driver_data *drv_data)
317 {
318 struct chip_data *chip = drv_data->cur_chip;
319
320 while (drv_data->rx < drv_data->rx_end) {
321 cs_active(drv_data, chip);
322 read_RDBR(drv_data); /* kick off */
323
324 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
325 cpu_relax();
326 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
327 cpu_relax();
328
329 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
330 cs_deactive(drv_data, chip);
331
332 ++drv_data->rx;
333 }
334 }
335
336 static void u8_duplex(struct driver_data *drv_data)
337 {
338 /* in duplex mode, clk is triggered by writing of TDBR */
339 while (drv_data->rx < drv_data->rx_end) {
340 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
341 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
342 cpu_relax();
343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
344 cpu_relax();
345 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
346 ++drv_data->rx;
347 ++drv_data->tx;
348 }
349 }
350
351 static void u8_cs_chg_duplex(struct driver_data *drv_data)
352 {
353 struct chip_data *chip = drv_data->cur_chip;
354
355 while (drv_data->rx < drv_data->rx_end) {
356 cs_active(drv_data, chip);
357
358 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
359
360 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
361 cpu_relax();
362 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
363 cpu_relax();
364 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
365
366 cs_deactive(drv_data, chip);
367
368 ++drv_data->rx;
369 ++drv_data->tx;
370 }
371 }
372
373 static void u16_writer(struct driver_data *drv_data)
374 {
375 dev_dbg(&drv_data->pdev->dev,
376 "cr16 is 0x%x\n", read_STAT(drv_data));
377
378 while (drv_data->tx < drv_data->tx_end) {
379 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
380 while ((read_STAT(drv_data) & BIT_STAT_TXS))
381 cpu_relax();
382 drv_data->tx += 2;
383 }
384
385 /* poll for SPI completion before return */
386 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
387 cpu_relax();
388 }
389
390 static void u16_cs_chg_writer(struct driver_data *drv_data)
391 {
392 struct chip_data *chip = drv_data->cur_chip;
393
394 while (drv_data->tx < drv_data->tx_end) {
395 cs_active(drv_data, chip);
396
397 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
398 while ((read_STAT(drv_data) & BIT_STAT_TXS))
399 cpu_relax();
400 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
401 cpu_relax();
402
403 cs_deactive(drv_data, chip);
404
405 drv_data->tx += 2;
406 }
407 }
408
409 static void u16_reader(struct driver_data *drv_data)
410 {
411 dev_dbg(&drv_data->pdev->dev,
412 "cr-16 is 0x%x\n", read_STAT(drv_data));
413
414 /* poll for SPI completion before start */
415 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
416 cpu_relax();
417
418 /* clear TDBR buffer before read(else it will be shifted out) */
419 write_TDBR(drv_data, 0xFFFF);
420
421 dummy_read(drv_data);
422
423 while (drv_data->rx < (drv_data->rx_end - 2)) {
424 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
425 cpu_relax();
426 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
427 drv_data->rx += 2;
428 }
429
430 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
431 cpu_relax();
432 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
433 drv_data->rx += 2;
434 }
435
436 static void u16_cs_chg_reader(struct driver_data *drv_data)
437 {
438 struct chip_data *chip = drv_data->cur_chip;
439
440 /* poll for SPI completion before start */
441 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
442 cpu_relax();
443
444 /* clear TDBR buffer before read(else it will be shifted out) */
445 write_TDBR(drv_data, 0xFFFF);
446
447 cs_active(drv_data, chip);
448 dummy_read(drv_data);
449
450 while (drv_data->rx < drv_data->rx_end - 2) {
451 cs_deactive(drv_data, chip);
452
453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
454 cpu_relax();
455 cs_active(drv_data, chip);
456 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
457 drv_data->rx += 2;
458 }
459 cs_deactive(drv_data, chip);
460
461 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
462 cpu_relax();
463 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
464 drv_data->rx += 2;
465 }
466
467 static void u16_duplex(struct driver_data *drv_data)
468 {
469 /* in duplex mode, clk is triggered by writing of TDBR */
470 while (drv_data->tx < drv_data->tx_end) {
471 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
472 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
473 cpu_relax();
474 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
475 cpu_relax();
476 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
477 drv_data->rx += 2;
478 drv_data->tx += 2;
479 }
480 }
481
482 static void u16_cs_chg_duplex(struct driver_data *drv_data)
483 {
484 struct chip_data *chip = drv_data->cur_chip;
485
486 while (drv_data->tx < drv_data->tx_end) {
487 cs_active(drv_data, chip);
488
489 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
490 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
491 cpu_relax();
492 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
493 cpu_relax();
494 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
495
496 cs_deactive(drv_data, chip);
497
498 drv_data->rx += 2;
499 drv_data->tx += 2;
500 }
501 }
502
503 /* test if ther is more transfer to be done */
504 static void *next_transfer(struct driver_data *drv_data)
505 {
506 struct spi_message *msg = drv_data->cur_msg;
507 struct spi_transfer *trans = drv_data->cur_transfer;
508
509 /* Move to next transfer */
510 if (trans->transfer_list.next != &msg->transfers) {
511 drv_data->cur_transfer =
512 list_entry(trans->transfer_list.next,
513 struct spi_transfer, transfer_list);
514 return RUNNING_STATE;
515 } else
516 return DONE_STATE;
517 }
518
519 /*
520 * caller already set message->status;
521 * dma and pio irqs are blocked give finished message back
522 */
523 static void giveback(struct driver_data *drv_data)
524 {
525 struct chip_data *chip = drv_data->cur_chip;
526 struct spi_transfer *last_transfer;
527 unsigned long flags;
528 struct spi_message *msg;
529
530 spin_lock_irqsave(&drv_data->lock, flags);
531 msg = drv_data->cur_msg;
532 drv_data->cur_msg = NULL;
533 drv_data->cur_transfer = NULL;
534 drv_data->cur_chip = NULL;
535 queue_work(drv_data->workqueue, &drv_data->pump_messages);
536 spin_unlock_irqrestore(&drv_data->lock, flags);
537
538 last_transfer = list_entry(msg->transfers.prev,
539 struct spi_transfer, transfer_list);
540
541 msg->state = NULL;
542
543 /* disable chip select signal. And not stop spi in autobuffer mode */
544 if (drv_data->tx_dma != 0xFFFF) {
545 cs_deactive(drv_data, chip);
546 bfin_spi_disable(drv_data);
547 }
548
549 if (!drv_data->cs_change)
550 cs_deactive(drv_data, chip);
551
552 if (msg->complete)
553 msg->complete(msg->context);
554 }
555
556 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
557 {
558 struct driver_data *drv_data = dev_id;
559 struct chip_data *chip = drv_data->cur_chip;
560 struct spi_message *msg = drv_data->cur_msg;
561 unsigned long timeout;
562 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
563 u16 spistat = read_STAT(drv_data);
564
565 dev_dbg(&drv_data->pdev->dev,
566 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
567 dmastat, spistat);
568
569 clear_dma_irqstat(drv_data->dma_channel);
570
571 /* Wait for DMA to complete */
572 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
573 cpu_relax();
574
575 /*
576 * wait for the last transaction shifted out. HRM states:
577 * at this point there may still be data in the SPI DMA FIFO waiting
578 * to be transmitted ... software needs to poll TXS in the SPI_STAT
579 * register until it goes low for 2 successive reads
580 */
581 if (drv_data->tx != NULL) {
582 while ((read_STAT(drv_data) & TXS) ||
583 (read_STAT(drv_data) & TXS))
584 cpu_relax();
585 }
586
587 dev_dbg(&drv_data->pdev->dev,
588 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
589 dmastat, read_STAT(drv_data));
590
591 timeout = jiffies + HZ;
592 while (!(read_STAT(drv_data) & SPIF))
593 if (!time_before(jiffies, timeout)) {
594 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
595 break;
596 } else
597 cpu_relax();
598
599 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
600 msg->state = ERROR_STATE;
601 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
602 } else {
603 msg->actual_length += drv_data->len_in_bytes;
604
605 if (drv_data->cs_change)
606 cs_deactive(drv_data, chip);
607
608 /* Move to next transfer */
609 msg->state = next_transfer(drv_data);
610 }
611
612 /* Schedule transfer tasklet */
613 tasklet_schedule(&drv_data->pump_transfers);
614
615 /* free the irq handler before next transfer */
616 dev_dbg(&drv_data->pdev->dev,
617 "disable dma channel irq%d\n",
618 drv_data->dma_channel);
619 dma_disable_irq(drv_data->dma_channel);
620
621 return IRQ_HANDLED;
622 }
623
624 static void pump_transfers(unsigned long data)
625 {
626 struct driver_data *drv_data = (struct driver_data *)data;
627 struct spi_message *message = NULL;
628 struct spi_transfer *transfer = NULL;
629 struct spi_transfer *previous = NULL;
630 struct chip_data *chip = NULL;
631 u8 width;
632 u16 cr, dma_width, dma_config;
633 u32 tranf_success = 1;
634 u8 full_duplex = 0;
635
636 /* Get current state information */
637 message = drv_data->cur_msg;
638 transfer = drv_data->cur_transfer;
639 chip = drv_data->cur_chip;
640
641 /*
642 * if msg is error or done, report it back using complete() callback
643 */
644
645 /* Handle for abort */
646 if (message->state == ERROR_STATE) {
647 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
648 message->status = -EIO;
649 giveback(drv_data);
650 return;
651 }
652
653 /* Handle end of message */
654 if (message->state == DONE_STATE) {
655 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
656 message->status = 0;
657 giveback(drv_data);
658 return;
659 }
660
661 /* Delay if requested at end of transfer */
662 if (message->state == RUNNING_STATE) {
663 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
664 previous = list_entry(transfer->transfer_list.prev,
665 struct spi_transfer, transfer_list);
666 if (previous->delay_usecs)
667 udelay(previous->delay_usecs);
668 }
669
670 /* Setup the transfer state based on the type of transfer */
671 if (flush(drv_data) == 0) {
672 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
673 message->status = -EIO;
674 giveback(drv_data);
675 return;
676 }
677
678 if (transfer->tx_buf != NULL) {
679 drv_data->tx = (void *)transfer->tx_buf;
680 drv_data->tx_end = drv_data->tx + transfer->len;
681 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
682 transfer->tx_buf, drv_data->tx_end);
683 } else {
684 drv_data->tx = NULL;
685 }
686
687 if (transfer->rx_buf != NULL) {
688 full_duplex = transfer->tx_buf != NULL;
689 drv_data->rx = transfer->rx_buf;
690 drv_data->rx_end = drv_data->rx + transfer->len;
691 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
692 transfer->rx_buf, drv_data->rx_end);
693 } else {
694 drv_data->rx = NULL;
695 }
696
697 drv_data->rx_dma = transfer->rx_dma;
698 drv_data->tx_dma = transfer->tx_dma;
699 drv_data->len_in_bytes = transfer->len;
700 drv_data->cs_change = transfer->cs_change;
701
702 /* Bits per word setup */
703 switch (transfer->bits_per_word) {
704 case 8:
705 drv_data->n_bytes = 1;
706 width = CFG_SPI_WORDSIZE8;
707 drv_data->read = chip->cs_change_per_word ?
708 u8_cs_chg_reader : u8_reader;
709 drv_data->write = chip->cs_change_per_word ?
710 u8_cs_chg_writer : u8_writer;
711 drv_data->duplex = chip->cs_change_per_word ?
712 u8_cs_chg_duplex : u8_duplex;
713 break;
714
715 case 16:
716 drv_data->n_bytes = 2;
717 width = CFG_SPI_WORDSIZE16;
718 drv_data->read = chip->cs_change_per_word ?
719 u16_cs_chg_reader : u16_reader;
720 drv_data->write = chip->cs_change_per_word ?
721 u16_cs_chg_writer : u16_writer;
722 drv_data->duplex = chip->cs_change_per_word ?
723 u16_cs_chg_duplex : u16_duplex;
724 break;
725
726 default:
727 /* No change, the same as default setting */
728 drv_data->n_bytes = chip->n_bytes;
729 width = chip->width;
730 drv_data->write = drv_data->tx ? chip->write : null_writer;
731 drv_data->read = drv_data->rx ? chip->read : null_reader;
732 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
733 break;
734 }
735 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
736 cr |= (width << 8);
737 write_CTRL(drv_data, cr);
738
739 if (width == CFG_SPI_WORDSIZE16) {
740 drv_data->len = (transfer->len) >> 1;
741 } else {
742 drv_data->len = transfer->len;
743 }
744 dev_dbg(&drv_data->pdev->dev,
745 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
746 drv_data->write, chip->write, null_writer);
747
748 /* speed and width has been set on per message */
749 message->state = RUNNING_STATE;
750 dma_config = 0;
751
752 /* Speed setup (surely valid because already checked) */
753 if (transfer->speed_hz)
754 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
755 else
756 write_BAUD(drv_data, chip->baud);
757
758 write_STAT(drv_data, BIT_STAT_CLR);
759 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
760 cs_active(drv_data, chip);
761
762 dev_dbg(&drv_data->pdev->dev,
763 "now pumping a transfer: width is %d, len is %d\n",
764 width, transfer->len);
765
766 /*
767 * Try to map dma buffer and do a dma transfer. If successful use,
768 * different way to r/w according to the enable_dma settings and if
769 * we are not doing a full duplex transfer (since the hardware does
770 * not support full duplex DMA transfers).
771 */
772 if (!full_duplex && drv_data->cur_chip->enable_dma
773 && drv_data->len > 6) {
774
775 unsigned long dma_start_addr, flags;
776
777 disable_dma(drv_data->dma_channel);
778 clear_dma_irqstat(drv_data->dma_channel);
779
780 /* config dma channel */
781 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
782 set_dma_x_count(drv_data->dma_channel, drv_data->len);
783 if (width == CFG_SPI_WORDSIZE16) {
784 set_dma_x_modify(drv_data->dma_channel, 2);
785 dma_width = WDSIZE_16;
786 } else {
787 set_dma_x_modify(drv_data->dma_channel, 1);
788 dma_width = WDSIZE_8;
789 }
790
791 /* poll for SPI completion before start */
792 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
793 cpu_relax();
794
795 /* dirty hack for autobuffer DMA mode */
796 if (drv_data->tx_dma == 0xFFFF) {
797 dev_dbg(&drv_data->pdev->dev,
798 "doing autobuffer DMA out.\n");
799
800 /* no irq in autobuffer mode */
801 dma_config =
802 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
803 set_dma_config(drv_data->dma_channel, dma_config);
804 set_dma_start_addr(drv_data->dma_channel,
805 (unsigned long)drv_data->tx);
806 enable_dma(drv_data->dma_channel);
807
808 /* start SPI transfer */
809 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
810
811 /* just return here, there can only be one transfer
812 * in this mode
813 */
814 message->status = 0;
815 giveback(drv_data);
816 return;
817 }
818
819 /* In dma mode, rx or tx must be NULL in one transfer */
820 dma_config = (RESTART | dma_width | DI_EN);
821 if (drv_data->rx != NULL) {
822 /* set transfer mode, and enable SPI */
823 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
824 drv_data->rx, drv_data->len_in_bytes);
825
826 /* invalidate caches, if needed */
827 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
828 invalidate_dcache_range((unsigned long) drv_data->rx,
829 (unsigned long) (drv_data->rx +
830 drv_data->len_in_bytes));
831
832 /* clear tx reg soformer data is not shifted out */
833 write_TDBR(drv_data, 0xFFFF);
834
835 dma_config |= WNR;
836 dma_start_addr = (unsigned long)drv_data->rx;
837 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
838
839 } else if (drv_data->tx != NULL) {
840 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
841
842 /* flush caches, if needed */
843 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
844 flush_dcache_range((unsigned long) drv_data->tx,
845 (unsigned long) (drv_data->tx +
846 drv_data->len_in_bytes));
847
848 dma_start_addr = (unsigned long)drv_data->tx;
849 cr |= BIT_CTL_TIMOD_DMA_TX;
850
851 } else
852 BUG();
853
854 /* oh man, here there be monsters ... and i dont mean the
855 * fluffy cute ones from pixar, i mean the kind that'll eat
856 * your data, kick your dog, and love it all. do *not* try
857 * and change these lines unless you (1) heavily test DMA
858 * with SPI flashes on a loaded system (e.g. ping floods),
859 * (2) know just how broken the DMA engine interaction with
860 * the SPI peripheral is, and (3) have someone else to blame
861 * when you screw it all up anyways.
862 */
863 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
864 set_dma_config(drv_data->dma_channel, dma_config);
865 local_irq_save(flags);
866 SSYNC();
867 write_CTRL(drv_data, cr);
868 enable_dma(drv_data->dma_channel);
869 dma_enable_irq(drv_data->dma_channel);
870 local_irq_restore(flags);
871
872 } else {
873 /* IO mode write then read */
874 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
875
876 if (full_duplex) {
877 /* full duplex mode */
878 BUG_ON((drv_data->tx_end - drv_data->tx) !=
879 (drv_data->rx_end - drv_data->rx));
880 dev_dbg(&drv_data->pdev->dev,
881 "IO duplex: cr is 0x%x\n", cr);
882
883 /* set SPI transfer mode */
884 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
885
886 drv_data->duplex(drv_data);
887
888 if (drv_data->tx != drv_data->tx_end)
889 tranf_success = 0;
890 } else if (drv_data->tx != NULL) {
891 /* write only half duplex */
892 dev_dbg(&drv_data->pdev->dev,
893 "IO write: cr is 0x%x\n", cr);
894
895 /* set SPI transfer mode */
896 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
897
898 drv_data->write(drv_data);
899
900 if (drv_data->tx != drv_data->tx_end)
901 tranf_success = 0;
902 } else if (drv_data->rx != NULL) {
903 /* read only half duplex */
904 dev_dbg(&drv_data->pdev->dev,
905 "IO read: cr is 0x%x\n", cr);
906
907 /* set SPI transfer mode */
908 write_CTRL(drv_data, (cr | CFG_SPI_READ));
909
910 drv_data->read(drv_data);
911 if (drv_data->rx != drv_data->rx_end)
912 tranf_success = 0;
913 }
914
915 if (!tranf_success) {
916 dev_dbg(&drv_data->pdev->dev,
917 "IO write error!\n");
918 message->state = ERROR_STATE;
919 } else {
920 /* Update total byte transfered */
921 message->actual_length += drv_data->len_in_bytes;
922
923 /* Move to next transfer of this msg */
924 message->state = next_transfer(drv_data);
925 }
926
927 /* Schedule next transfer tasklet */
928 tasklet_schedule(&drv_data->pump_transfers);
929
930 }
931 }
932
933 /* pop a msg from queue and kick off real transfer */
934 static void pump_messages(struct work_struct *work)
935 {
936 struct driver_data *drv_data;
937 unsigned long flags;
938
939 drv_data = container_of(work, struct driver_data, pump_messages);
940
941 /* Lock queue and check for queue work */
942 spin_lock_irqsave(&drv_data->lock, flags);
943 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
944 /* pumper kicked off but no work to do */
945 drv_data->busy = 0;
946 spin_unlock_irqrestore(&drv_data->lock, flags);
947 return;
948 }
949
950 /* Make sure we are not already running a message */
951 if (drv_data->cur_msg) {
952 spin_unlock_irqrestore(&drv_data->lock, flags);
953 return;
954 }
955
956 /* Extract head of queue */
957 drv_data->cur_msg = list_entry(drv_data->queue.next,
958 struct spi_message, queue);
959
960 /* Setup the SSP using the per chip configuration */
961 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
962 restore_state(drv_data);
963
964 list_del_init(&drv_data->cur_msg->queue);
965
966 /* Initial message state */
967 drv_data->cur_msg->state = START_STATE;
968 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
969 struct spi_transfer, transfer_list);
970
971 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
972 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
973 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
974 drv_data->cur_chip->ctl_reg);
975
976 dev_dbg(&drv_data->pdev->dev,
977 "the first transfer len is %d\n",
978 drv_data->cur_transfer->len);
979
980 /* Mark as busy and launch transfers */
981 tasklet_schedule(&drv_data->pump_transfers);
982
983 drv_data->busy = 1;
984 spin_unlock_irqrestore(&drv_data->lock, flags);
985 }
986
987 /*
988 * got a msg to transfer, queue it in drv_data->queue.
989 * And kick off message pumper
990 */
991 static int transfer(struct spi_device *spi, struct spi_message *msg)
992 {
993 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
994 unsigned long flags;
995
996 spin_lock_irqsave(&drv_data->lock, flags);
997
998 if (drv_data->run == QUEUE_STOPPED) {
999 spin_unlock_irqrestore(&drv_data->lock, flags);
1000 return -ESHUTDOWN;
1001 }
1002
1003 msg->actual_length = 0;
1004 msg->status = -EINPROGRESS;
1005 msg->state = START_STATE;
1006
1007 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
1008 list_add_tail(&msg->queue, &drv_data->queue);
1009
1010 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1011 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1012
1013 spin_unlock_irqrestore(&drv_data->lock, flags);
1014
1015 return 0;
1016 }
1017
1018 #define MAX_SPI_SSEL 7
1019
1020 static u16 ssel[][MAX_SPI_SSEL] = {
1021 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1022 P_SPI0_SSEL4, P_SPI0_SSEL5,
1023 P_SPI0_SSEL6, P_SPI0_SSEL7},
1024
1025 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1026 P_SPI1_SSEL4, P_SPI1_SSEL5,
1027 P_SPI1_SSEL6, P_SPI1_SSEL7},
1028
1029 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1030 P_SPI2_SSEL4, P_SPI2_SSEL5,
1031 P_SPI2_SSEL6, P_SPI2_SSEL7},
1032 };
1033
1034 /* first setup for new devices */
1035 static int setup(struct spi_device *spi)
1036 {
1037 struct bfin5xx_spi_chip *chip_info = NULL;
1038 struct chip_data *chip;
1039 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1040
1041 /* Abort device setup if requested features are not supported */
1042 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1043 dev_err(&spi->dev, "requested mode not fully supported\n");
1044 return -EINVAL;
1045 }
1046
1047 /* Zero (the default) here means 8 bits */
1048 if (!spi->bits_per_word)
1049 spi->bits_per_word = 8;
1050
1051 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1052 return -EINVAL;
1053
1054 /* Only alloc (or use chip_info) on first setup */
1055 chip = spi_get_ctldata(spi);
1056 if (chip == NULL) {
1057 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1058 if (!chip)
1059 return -ENOMEM;
1060
1061 chip->enable_dma = 0;
1062 chip_info = spi->controller_data;
1063 }
1064
1065 /* chip_info isn't always needed */
1066 if (chip_info) {
1067 /* Make sure people stop trying to set fields via ctl_reg
1068 * when they should actually be using common SPI framework.
1069 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1070 * Not sure if a user actually needs/uses any of these,
1071 * but let's assume (for now) they do.
1072 */
1073 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1074 dev_err(&spi->dev, "do not set bits in ctl_reg "
1075 "that the SPI framework manages\n");
1076 return -EINVAL;
1077 }
1078
1079 chip->enable_dma = chip_info->enable_dma != 0
1080 && drv_data->master_info->enable_dma;
1081 chip->ctl_reg = chip_info->ctl_reg;
1082 chip->bits_per_word = chip_info->bits_per_word;
1083 chip->cs_change_per_word = chip_info->cs_change_per_word;
1084 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1085 }
1086
1087 /* translate common spi framework into our register */
1088 if (spi->mode & SPI_CPOL)
1089 chip->ctl_reg |= CPOL;
1090 if (spi->mode & SPI_CPHA)
1091 chip->ctl_reg |= CPHA;
1092 if (spi->mode & SPI_LSB_FIRST)
1093 chip->ctl_reg |= LSBF;
1094 /* we dont support running in slave mode (yet?) */
1095 chip->ctl_reg |= MSTR;
1096
1097 /*
1098 * if any one SPI chip is registered and wants DMA, request the
1099 * DMA channel for it
1100 */
1101 if (chip->enable_dma && !drv_data->dma_requested) {
1102 /* register dma irq handler */
1103 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1104 dev_dbg(&spi->dev,
1105 "Unable to request BlackFin SPI DMA channel\n");
1106 return -ENODEV;
1107 }
1108 if (set_dma_callback(drv_data->dma_channel,
1109 dma_irq_handler, drv_data) < 0) {
1110 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1111 return -EPERM;
1112 }
1113 dma_disable_irq(drv_data->dma_channel);
1114 drv_data->dma_requested = 1;
1115 }
1116
1117 /*
1118 * Notice: for blackfin, the speed_hz is the value of register
1119 * SPI_BAUD, not the real baudrate
1120 */
1121 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1122 chip->flag = 1 << (spi->chip_select);
1123 chip->chip_select_num = spi->chip_select;
1124
1125 switch (chip->bits_per_word) {
1126 case 8:
1127 chip->n_bytes = 1;
1128 chip->width = CFG_SPI_WORDSIZE8;
1129 chip->read = chip->cs_change_per_word ?
1130 u8_cs_chg_reader : u8_reader;
1131 chip->write = chip->cs_change_per_word ?
1132 u8_cs_chg_writer : u8_writer;
1133 chip->duplex = chip->cs_change_per_word ?
1134 u8_cs_chg_duplex : u8_duplex;
1135 break;
1136
1137 case 16:
1138 chip->n_bytes = 2;
1139 chip->width = CFG_SPI_WORDSIZE16;
1140 chip->read = chip->cs_change_per_word ?
1141 u16_cs_chg_reader : u16_reader;
1142 chip->write = chip->cs_change_per_word ?
1143 u16_cs_chg_writer : u16_writer;
1144 chip->duplex = chip->cs_change_per_word ?
1145 u16_cs_chg_duplex : u16_duplex;
1146 break;
1147
1148 default:
1149 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1150 chip->bits_per_word);
1151 kfree(chip);
1152 return -ENODEV;
1153 }
1154
1155 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1156 spi->modalias, chip->width, chip->enable_dma);
1157 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1158 chip->ctl_reg, chip->flag);
1159
1160 spi_set_ctldata(spi, chip);
1161
1162 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1163 if ((chip->chip_select_num > 0)
1164 && (chip->chip_select_num <= spi->master->num_chipselect))
1165 peripheral_request(ssel[spi->master->bus_num]
1166 [chip->chip_select_num-1], spi->modalias);
1167
1168 cs_deactive(drv_data, chip);
1169
1170 return 0;
1171 }
1172
1173 /*
1174 * callback for spi framework.
1175 * clean driver specific data
1176 */
1177 static void cleanup(struct spi_device *spi)
1178 {
1179 struct chip_data *chip = spi_get_ctldata(spi);
1180
1181 if ((chip->chip_select_num > 0)
1182 && (chip->chip_select_num <= spi->master->num_chipselect))
1183 peripheral_free(ssel[spi->master->bus_num]
1184 [chip->chip_select_num-1]);
1185
1186 kfree(chip);
1187 }
1188
1189 static inline int init_queue(struct driver_data *drv_data)
1190 {
1191 INIT_LIST_HEAD(&drv_data->queue);
1192 spin_lock_init(&drv_data->lock);
1193
1194 drv_data->run = QUEUE_STOPPED;
1195 drv_data->busy = 0;
1196
1197 /* init transfer tasklet */
1198 tasklet_init(&drv_data->pump_transfers,
1199 pump_transfers, (unsigned long)drv_data);
1200
1201 /* init messages workqueue */
1202 INIT_WORK(&drv_data->pump_messages, pump_messages);
1203 drv_data->workqueue = create_singlethread_workqueue(
1204 dev_name(drv_data->master->dev.parent));
1205 if (drv_data->workqueue == NULL)
1206 return -EBUSY;
1207
1208 return 0;
1209 }
1210
1211 static inline int start_queue(struct driver_data *drv_data)
1212 {
1213 unsigned long flags;
1214
1215 spin_lock_irqsave(&drv_data->lock, flags);
1216
1217 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1218 spin_unlock_irqrestore(&drv_data->lock, flags);
1219 return -EBUSY;
1220 }
1221
1222 drv_data->run = QUEUE_RUNNING;
1223 drv_data->cur_msg = NULL;
1224 drv_data->cur_transfer = NULL;
1225 drv_data->cur_chip = NULL;
1226 spin_unlock_irqrestore(&drv_data->lock, flags);
1227
1228 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1229
1230 return 0;
1231 }
1232
1233 static inline int stop_queue(struct driver_data *drv_data)
1234 {
1235 unsigned long flags;
1236 unsigned limit = 500;
1237 int status = 0;
1238
1239 spin_lock_irqsave(&drv_data->lock, flags);
1240
1241 /*
1242 * This is a bit lame, but is optimized for the common execution path.
1243 * A wait_queue on the drv_data->busy could be used, but then the common
1244 * execution path (pump_messages) would be required to call wake_up or
1245 * friends on every SPI message. Do this instead
1246 */
1247 drv_data->run = QUEUE_STOPPED;
1248 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1249 spin_unlock_irqrestore(&drv_data->lock, flags);
1250 msleep(10);
1251 spin_lock_irqsave(&drv_data->lock, flags);
1252 }
1253
1254 if (!list_empty(&drv_data->queue) || drv_data->busy)
1255 status = -EBUSY;
1256
1257 spin_unlock_irqrestore(&drv_data->lock, flags);
1258
1259 return status;
1260 }
1261
1262 static inline int destroy_queue(struct driver_data *drv_data)
1263 {
1264 int status;
1265
1266 status = stop_queue(drv_data);
1267 if (status != 0)
1268 return status;
1269
1270 destroy_workqueue(drv_data->workqueue);
1271
1272 return 0;
1273 }
1274
1275 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1276 {
1277 struct device *dev = &pdev->dev;
1278 struct bfin5xx_spi_master *platform_info;
1279 struct spi_master *master;
1280 struct driver_data *drv_data = 0;
1281 struct resource *res;
1282 int status = 0;
1283
1284 platform_info = dev->platform_data;
1285
1286 /* Allocate master with space for drv_data */
1287 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1288 if (!master) {
1289 dev_err(&pdev->dev, "can not alloc spi_master\n");
1290 return -ENOMEM;
1291 }
1292
1293 drv_data = spi_master_get_devdata(master);
1294 drv_data->master = master;
1295 drv_data->master_info = platform_info;
1296 drv_data->pdev = pdev;
1297 drv_data->pin_req = platform_info->pin_req;
1298
1299 master->bus_num = pdev->id;
1300 master->num_chipselect = platform_info->num_chipselect;
1301 master->cleanup = cleanup;
1302 master->setup = setup;
1303 master->transfer = transfer;
1304
1305 /* Find and map our resources */
1306 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1307 if (res == NULL) {
1308 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1309 status = -ENOENT;
1310 goto out_error_get_res;
1311 }
1312
1313 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1314 if (drv_data->regs_base == NULL) {
1315 dev_err(dev, "Cannot map IO\n");
1316 status = -ENXIO;
1317 goto out_error_ioremap;
1318 }
1319
1320 drv_data->dma_channel = platform_get_irq(pdev, 0);
1321 if (drv_data->dma_channel < 0) {
1322 dev_err(dev, "No DMA channel specified\n");
1323 status = -ENOENT;
1324 goto out_error_no_dma_ch;
1325 }
1326
1327 /* Initial and start queue */
1328 status = init_queue(drv_data);
1329 if (status != 0) {
1330 dev_err(dev, "problem initializing queue\n");
1331 goto out_error_queue_alloc;
1332 }
1333
1334 status = start_queue(drv_data);
1335 if (status != 0) {
1336 dev_err(dev, "problem starting queue\n");
1337 goto out_error_queue_alloc;
1338 }
1339
1340 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1341 if (status != 0) {
1342 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1343 goto out_error_queue_alloc;
1344 }
1345
1346 /* Register with the SPI framework */
1347 platform_set_drvdata(pdev, drv_data);
1348 status = spi_register_master(master);
1349 if (status != 0) {
1350 dev_err(dev, "problem registering spi master\n");
1351 goto out_error_queue_alloc;
1352 }
1353
1354 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1355 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1356 drv_data->dma_channel);
1357 return status;
1358
1359 out_error_queue_alloc:
1360 destroy_queue(drv_data);
1361 out_error_no_dma_ch:
1362 iounmap((void *) drv_data->regs_base);
1363 out_error_ioremap:
1364 out_error_get_res:
1365 spi_master_put(master);
1366
1367 return status;
1368 }
1369
1370 /* stop hardware and remove the driver */
1371 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1372 {
1373 struct driver_data *drv_data = platform_get_drvdata(pdev);
1374 int status = 0;
1375
1376 if (!drv_data)
1377 return 0;
1378
1379 /* Remove the queue */
1380 status = destroy_queue(drv_data);
1381 if (status != 0)
1382 return status;
1383
1384 /* Disable the SSP at the peripheral and SOC level */
1385 bfin_spi_disable(drv_data);
1386
1387 /* Release DMA */
1388 if (drv_data->master_info->enable_dma) {
1389 if (dma_channel_active(drv_data->dma_channel))
1390 free_dma(drv_data->dma_channel);
1391 }
1392
1393 /* Disconnect from the SPI framework */
1394 spi_unregister_master(drv_data->master);
1395
1396 peripheral_free_list(drv_data->pin_req);
1397
1398 /* Prevent double remove */
1399 platform_set_drvdata(pdev, NULL);
1400
1401 return 0;
1402 }
1403
1404 #ifdef CONFIG_PM
1405 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1406 {
1407 struct driver_data *drv_data = platform_get_drvdata(pdev);
1408 int status = 0;
1409
1410 status = stop_queue(drv_data);
1411 if (status != 0)
1412 return status;
1413
1414 /* stop hardware */
1415 bfin_spi_disable(drv_data);
1416
1417 return 0;
1418 }
1419
1420 static int bfin5xx_spi_resume(struct platform_device *pdev)
1421 {
1422 struct driver_data *drv_data = platform_get_drvdata(pdev);
1423 int status = 0;
1424
1425 /* Enable the SPI interface */
1426 bfin_spi_enable(drv_data);
1427
1428 /* Start the queue running */
1429 status = start_queue(drv_data);
1430 if (status != 0) {
1431 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1432 return status;
1433 }
1434
1435 return 0;
1436 }
1437 #else
1438 #define bfin5xx_spi_suspend NULL
1439 #define bfin5xx_spi_resume NULL
1440 #endif /* CONFIG_PM */
1441
1442 MODULE_ALIAS("platform:bfin-spi");
1443 static struct platform_driver bfin5xx_spi_driver = {
1444 .driver = {
1445 .name = DRV_NAME,
1446 .owner = THIS_MODULE,
1447 },
1448 .suspend = bfin5xx_spi_suspend,
1449 .resume = bfin5xx_spi_resume,
1450 .remove = __devexit_p(bfin5xx_spi_remove),
1451 };
1452
1453 static int __init bfin5xx_spi_init(void)
1454 {
1455 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1456 }
1457 module_init(bfin5xx_spi_init);
1458
1459 static void __exit bfin5xx_spi_exit(void)
1460 {
1461 platform_driver_unregister(&bfin5xx_spi_driver);
1462 }
1463 module_exit(bfin5xx_spi_exit);
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