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[mirror_ubuntu-kernels.git] / drivers / spmi / spmi-pmic-arb.c
1 /*
2 * Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13 #include <linux/bitmap.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spmi.h>
27
28 /* PMIC Arbiter configuration registers */
29 #define PMIC_ARB_VERSION 0x0000
30 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
31 #define PMIC_ARB_VERSION_V3_MIN 0x30000000
32 #define PMIC_ARB_VERSION_V5_MIN 0x50000000
33 #define PMIC_ARB_INT_EN 0x0004
34
35 /* PMIC Arbiter channel registers offsets */
36 #define PMIC_ARB_CMD 0x00
37 #define PMIC_ARB_CONFIG 0x04
38 #define PMIC_ARB_STATUS 0x08
39 #define PMIC_ARB_WDATA0 0x10
40 #define PMIC_ARB_WDATA1 0x14
41 #define PMIC_ARB_RDATA0 0x18
42 #define PMIC_ARB_RDATA1 0x1C
43
44 /* Mapping Table */
45 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
46 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
47 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
48 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
49 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
50 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
51
52 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
53 #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */
54 #define PMIC_ARB_APID_VALID BIT(15)
55 #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
56 #define INVALID_EE 0xFF
57
58 /* Ownership Table */
59 #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
60 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
61
62 /* Channel Status fields */
63 enum pmic_arb_chnl_status {
64 PMIC_ARB_STATUS_DONE = BIT(0),
65 PMIC_ARB_STATUS_FAILURE = BIT(1),
66 PMIC_ARB_STATUS_DENIED = BIT(2),
67 PMIC_ARB_STATUS_DROPPED = BIT(3),
68 };
69
70 /* Command register fields */
71 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
72
73 /* Command Opcodes */
74 enum pmic_arb_cmd_op_code {
75 PMIC_ARB_OP_EXT_WRITEL = 0,
76 PMIC_ARB_OP_EXT_READL = 1,
77 PMIC_ARB_OP_EXT_WRITE = 2,
78 PMIC_ARB_OP_RESET = 3,
79 PMIC_ARB_OP_SLEEP = 4,
80 PMIC_ARB_OP_SHUTDOWN = 5,
81 PMIC_ARB_OP_WAKEUP = 6,
82 PMIC_ARB_OP_AUTHENTICATE = 7,
83 PMIC_ARB_OP_MSTR_READ = 8,
84 PMIC_ARB_OP_MSTR_WRITE = 9,
85 PMIC_ARB_OP_EXT_READ = 13,
86 PMIC_ARB_OP_WRITE = 14,
87 PMIC_ARB_OP_READ = 15,
88 PMIC_ARB_OP_ZERO_WRITE = 16,
89 };
90
91 /*
92 * PMIC arbiter version 5 uses different register offsets for read/write vs
93 * observer channels.
94 */
95 enum pmic_arb_channel {
96 PMIC_ARB_CHANNEL_RW,
97 PMIC_ARB_CHANNEL_OBS,
98 };
99
100 /* Maximum number of support PMIC peripherals */
101 #define PMIC_ARB_MAX_PERIPHS 512
102 #define PMIC_ARB_TIMEOUT_US 100
103 #define PMIC_ARB_MAX_TRANS_BYTES (8)
104
105 #define PMIC_ARB_APID_MASK 0xFF
106 #define PMIC_ARB_PPID_MASK 0xFFF
107
108 /* interrupt enable bit */
109 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
110
111 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
112 ((((slave_id) & 0xF) << 28) | \
113 (((periph_id) & 0xFF) << 20) | \
114 (((irq_id) & 0x7) << 16) | \
115 (((apid) & 0x1FF) << 0))
116
117 #define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
118 #define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
119 #define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
120 #define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x1FF)
121
122 struct pmic_arb_ver_ops;
123
124 struct apid_data {
125 u16 ppid;
126 u8 write_ee;
127 u8 irq_ee;
128 };
129
130 /**
131 * spmi_pmic_arb - SPMI PMIC Arbiter object
132 *
133 * @rd_base: on v1 "core", on v2 "observer" register base off DT.
134 * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
135 * @intr: address of the SPMI interrupt control registers.
136 * @cnfg: address of the PMIC Arbiter configuration registers.
137 * @lock: lock to synchronize accesses.
138 * @channel: execution environment channel to use for accesses.
139 * @irq: PMIC ARB interrupt.
140 * @ee: the current Execution Environment
141 * @min_apid: minimum APID (used for bounding IRQ search)
142 * @max_apid: maximum APID
143 * @mapping_table: in-memory copy of PPID -> APID mapping table.
144 * @domain: irq domain object for PMIC IRQ domain
145 * @spmic: SPMI controller object
146 * @ver_ops: version dependent operations.
147 * @ppid_to_apid in-memory copy of PPID -> APID mapping table.
148 */
149 struct spmi_pmic_arb {
150 void __iomem *rd_base;
151 void __iomem *wr_base;
152 void __iomem *intr;
153 void __iomem *cnfg;
154 void __iomem *core;
155 resource_size_t core_size;
156 raw_spinlock_t lock;
157 u8 channel;
158 int irq;
159 u8 ee;
160 u16 min_apid;
161 u16 max_apid;
162 u32 *mapping_table;
163 DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
164 struct irq_domain *domain;
165 struct spmi_controller *spmic;
166 const struct pmic_arb_ver_ops *ver_ops;
167 u16 *ppid_to_apid;
168 u16 last_apid;
169 struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS];
170 };
171
172 /**
173 * pmic_arb_ver: version dependent functionality.
174 *
175 * @ver_str: version string.
176 * @ppid_to_apid: finds the apid for a given ppid.
177 * @non_data_cmd: on v1 issues an spmi non-data command.
178 * on v2 no HW support, returns -EOPNOTSUPP.
179 * @offset: on v1 offset of per-ee channel.
180 * on v2 offset of per-ee and per-ppid channel.
181 * @fmt_cmd: formats a GENI/SPMI command.
182 * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
183 * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
184 * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
185 * on v2 address of SPMI_PIC_ACC_ENABLEn.
186 * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
187 * on v2 address of SPMI_PIC_IRQ_STATUSn.
188 * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
189 * on v2 address of SPMI_PIC_IRQ_CLEARn.
190 * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn
191 */
192 struct pmic_arb_ver_ops {
193 const char *ver_str;
194 int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
195 /* spmi commands (read_cmd, write_cmd, cmd) functionality */
196 int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
197 enum pmic_arb_channel ch_type);
198 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
199 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
200 /* Interrupts controller functionality (offset of PIC registers) */
201 void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
202 u16 n);
203 void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
204 void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
205 void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
206 u32 (*apid_map_offset)(u16 n);
207 };
208
209 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
210 u32 offset, u32 val)
211 {
212 writel_relaxed(val, pmic_arb->wr_base + offset);
213 }
214
215 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
216 u32 offset, u32 val)
217 {
218 writel_relaxed(val, pmic_arb->rd_base + offset);
219 }
220
221 /**
222 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
223 * @bc: byte count -1. range: 0..3
224 * @reg: register's address
225 * @buf: output parameter, length must be bc + 1
226 */
227 static void
228 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
229 {
230 u32 data = __raw_readl(pmic_arb->rd_base + reg);
231
232 memcpy(buf, &data, (bc & 3) + 1);
233 }
234
235 /**
236 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
237 * @bc: byte-count -1. range: 0..3.
238 * @reg: register's address.
239 * @buf: buffer to write. length must be bc + 1.
240 */
241 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
242 u32 reg, u8 bc)
243 {
244 u32 data = 0;
245
246 memcpy(&data, buf, (bc & 3) + 1);
247 __raw_writel(data, pmic_arb->wr_base + reg);
248 }
249
250 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
251 void __iomem *base, u8 sid, u16 addr,
252 enum pmic_arb_channel ch_type)
253 {
254 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
255 u32 status = 0;
256 u32 timeout = PMIC_ARB_TIMEOUT_US;
257 u32 offset;
258 int rc;
259
260 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
261 if (rc < 0)
262 return rc;
263
264 offset = rc;
265 offset += PMIC_ARB_STATUS;
266
267 while (timeout--) {
268 status = readl_relaxed(base + offset);
269
270 if (status & PMIC_ARB_STATUS_DONE) {
271 if (status & PMIC_ARB_STATUS_DENIED) {
272 dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
273 __func__, status);
274 return -EPERM;
275 }
276
277 if (status & PMIC_ARB_STATUS_FAILURE) {
278 dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
279 __func__, status);
280 return -EIO;
281 }
282
283 if (status & PMIC_ARB_STATUS_DROPPED) {
284 dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
285 __func__, status);
286 return -EIO;
287 }
288
289 return 0;
290 }
291 udelay(1);
292 }
293
294 dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
295 __func__, status);
296 return -ETIMEDOUT;
297 }
298
299 static int
300 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
301 {
302 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
303 unsigned long flags;
304 u32 cmd;
305 int rc;
306 u32 offset;
307
308 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
309 if (rc < 0)
310 return rc;
311
312 offset = rc;
313 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
314
315 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
316 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
317 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
318 PMIC_ARB_CHANNEL_RW);
319 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
320
321 return rc;
322 }
323
324 static int
325 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
326 {
327 return -EOPNOTSUPP;
328 }
329
330 /* Non-data command */
331 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
332 {
333 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
334
335 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
336
337 /* Check for valid non-data command */
338 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
339 return -EINVAL;
340
341 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
342 }
343
344 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
345 u16 addr, u8 *buf, size_t len)
346 {
347 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
348 unsigned long flags;
349 u8 bc = len - 1;
350 u32 cmd;
351 int rc;
352 u32 offset;
353
354 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
355 PMIC_ARB_CHANNEL_OBS);
356 if (rc < 0)
357 return rc;
358
359 offset = rc;
360 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
361 dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
362 PMIC_ARB_MAX_TRANS_BYTES, len);
363 return -EINVAL;
364 }
365
366 /* Check the opcode */
367 if (opc >= 0x60 && opc <= 0x7F)
368 opc = PMIC_ARB_OP_READ;
369 else if (opc >= 0x20 && opc <= 0x2F)
370 opc = PMIC_ARB_OP_EXT_READ;
371 else if (opc >= 0x38 && opc <= 0x3F)
372 opc = PMIC_ARB_OP_EXT_READL;
373 else
374 return -EINVAL;
375
376 cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
377
378 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
379 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
380 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
381 PMIC_ARB_CHANNEL_OBS);
382 if (rc)
383 goto done;
384
385 pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
386 min_t(u8, bc, 3));
387
388 if (bc > 3)
389 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
390 bc - 4);
391
392 done:
393 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
394 return rc;
395 }
396
397 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
398 u16 addr, const u8 *buf, size_t len)
399 {
400 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
401 unsigned long flags;
402 u8 bc = len - 1;
403 u32 cmd;
404 int rc;
405 u32 offset;
406
407 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
408 PMIC_ARB_CHANNEL_RW);
409 if (rc < 0)
410 return rc;
411
412 offset = rc;
413 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
414 dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
415 PMIC_ARB_MAX_TRANS_BYTES, len);
416 return -EINVAL;
417 }
418
419 /* Check the opcode */
420 if (opc >= 0x40 && opc <= 0x5F)
421 opc = PMIC_ARB_OP_WRITE;
422 else if (opc <= 0x0F)
423 opc = PMIC_ARB_OP_EXT_WRITE;
424 else if (opc >= 0x30 && opc <= 0x37)
425 opc = PMIC_ARB_OP_EXT_WRITEL;
426 else if (opc >= 0x80)
427 opc = PMIC_ARB_OP_ZERO_WRITE;
428 else
429 return -EINVAL;
430
431 cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
432
433 /* Write data to FIFOs */
434 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
435 pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
436 min_t(u8, bc, 3));
437 if (bc > 3)
438 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
439 bc - 4);
440
441 /* Start the transaction */
442 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
443 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
444 PMIC_ARB_CHANNEL_RW);
445 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
446
447 return rc;
448 }
449
450 enum qpnpint_regs {
451 QPNPINT_REG_RT_STS = 0x10,
452 QPNPINT_REG_SET_TYPE = 0x11,
453 QPNPINT_REG_POLARITY_HIGH = 0x12,
454 QPNPINT_REG_POLARITY_LOW = 0x13,
455 QPNPINT_REG_LATCHED_CLR = 0x14,
456 QPNPINT_REG_EN_SET = 0x15,
457 QPNPINT_REG_EN_CLR = 0x16,
458 QPNPINT_REG_LATCHED_STS = 0x18,
459 };
460
461 struct spmi_pmic_arb_qpnpint_type {
462 u8 type; /* 1 -> edge */
463 u8 polarity_high;
464 u8 polarity_low;
465 } __packed;
466
467 /* Simplified accessor functions for irqchip callbacks */
468 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
469 size_t len)
470 {
471 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
472 u8 sid = hwirq_to_sid(d->hwirq);
473 u8 per = hwirq_to_per(d->hwirq);
474
475 if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
476 (per << 8) + reg, buf, len))
477 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
478 d->irq);
479 }
480
481 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
482 {
483 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
484 u8 sid = hwirq_to_sid(d->hwirq);
485 u8 per = hwirq_to_per(d->hwirq);
486
487 if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
488 (per << 8) + reg, buf, len))
489 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
490 d->irq);
491 }
492
493 static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
494 {
495 u16 ppid = pmic_arb->apid_data[apid].ppid;
496 u8 sid = ppid >> 8;
497 u8 per = ppid & 0xFF;
498 u8 irq_mask = BIT(id);
499
500 writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
501
502 if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
503 (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
504 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
505 irq_mask, ppid);
506
507 if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
508 (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
509 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
510 irq_mask, ppid);
511 }
512
513 static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
514 {
515 unsigned int irq;
516 u32 status;
517 int id;
518 u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
519 u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
520
521 status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
522 while (status) {
523 id = ffs(status) - 1;
524 status &= ~BIT(id);
525 irq = irq_find_mapping(pmic_arb->domain,
526 spec_to_hwirq(sid, per, id, apid));
527 if (irq == 0) {
528 cleanup_irq(pmic_arb, apid, id);
529 continue;
530 }
531 generic_handle_irq(irq);
532 }
533 }
534
535 static void pmic_arb_chained_irq(struct irq_desc *desc)
536 {
537 struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
538 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
539 struct irq_chip *chip = irq_desc_get_chip(desc);
540 int first = pmic_arb->min_apid >> 5;
541 int last = pmic_arb->max_apid >> 5;
542 u8 ee = pmic_arb->ee;
543 u32 status, enable;
544 int i, id, apid;
545
546 chained_irq_enter(chip, desc);
547
548 for (i = first; i <= last; ++i) {
549 status = readl_relaxed(
550 ver_ops->owner_acc_status(pmic_arb, ee, i));
551 while (status) {
552 id = ffs(status) - 1;
553 status &= ~BIT(id);
554 apid = id + i * 32;
555 enable = readl_relaxed(
556 ver_ops->acc_enable(pmic_arb, apid));
557 if (enable & SPMI_PIC_ACC_ENABLE_BIT)
558 periph_interrupt(pmic_arb, apid);
559 }
560 }
561
562 chained_irq_exit(chip, desc);
563 }
564
565 static void qpnpint_irq_ack(struct irq_data *d)
566 {
567 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
568 u8 irq = hwirq_to_irq(d->hwirq);
569 u16 apid = hwirq_to_apid(d->hwirq);
570 u8 data;
571
572 writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
573
574 data = BIT(irq);
575 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
576 }
577
578 static void qpnpint_irq_mask(struct irq_data *d)
579 {
580 u8 irq = hwirq_to_irq(d->hwirq);
581 u8 data = BIT(irq);
582
583 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
584 }
585
586 static void qpnpint_irq_unmask(struct irq_data *d)
587 {
588 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
589 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
590 u8 irq = hwirq_to_irq(d->hwirq);
591 u16 apid = hwirq_to_apid(d->hwirq);
592 u8 buf[2];
593
594 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
595 ver_ops->acc_enable(pmic_arb, apid));
596
597 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
598 if (!(buf[0] & BIT(irq))) {
599 /*
600 * Since the interrupt is currently disabled, write to both the
601 * LATCHED_CLR and EN_SET registers so that a spurious interrupt
602 * cannot be triggered when the interrupt is enabled
603 */
604 buf[0] = BIT(irq);
605 buf[1] = BIT(irq);
606 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
607 }
608 }
609
610 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
611 {
612 struct spmi_pmic_arb_qpnpint_type type;
613 irq_flow_handler_t flow_handler;
614 u8 irq = hwirq_to_irq(d->hwirq);
615
616 qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
617
618 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
619 type.type |= BIT(irq);
620 if (flow_type & IRQF_TRIGGER_RISING)
621 type.polarity_high |= BIT(irq);
622 if (flow_type & IRQF_TRIGGER_FALLING)
623 type.polarity_low |= BIT(irq);
624
625 flow_handler = handle_edge_irq;
626 } else {
627 if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
628 (flow_type & (IRQF_TRIGGER_LOW)))
629 return -EINVAL;
630
631 type.type &= ~BIT(irq); /* level trig */
632 if (flow_type & IRQF_TRIGGER_HIGH)
633 type.polarity_high |= BIT(irq);
634 else
635 type.polarity_low |= BIT(irq);
636
637 flow_handler = handle_level_irq;
638 }
639
640 qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
641 irq_set_handler_locked(d, flow_handler);
642
643 return 0;
644 }
645
646 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
647 {
648 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
649
650 return irq_set_irq_wake(pmic_arb->irq, on);
651 }
652
653 static int qpnpint_get_irqchip_state(struct irq_data *d,
654 enum irqchip_irq_state which,
655 bool *state)
656 {
657 u8 irq = hwirq_to_irq(d->hwirq);
658 u8 status = 0;
659
660 if (which != IRQCHIP_STATE_LINE_LEVEL)
661 return -EINVAL;
662
663 qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
664 *state = !!(status & BIT(irq));
665
666 return 0;
667 }
668
669 static int qpnpint_irq_domain_activate(struct irq_domain *domain,
670 struct irq_data *d, bool reserve)
671 {
672 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
673 u16 periph = hwirq_to_per(d->hwirq);
674 u16 apid = hwirq_to_apid(d->hwirq);
675 u16 sid = hwirq_to_sid(d->hwirq);
676 u16 irq = hwirq_to_irq(d->hwirq);
677
678 if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
679 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
680 sid, periph, irq, pmic_arb->ee,
681 pmic_arb->apid_data[apid].irq_ee);
682 return -ENODEV;
683 }
684
685 return 0;
686 }
687
688 static struct irq_chip pmic_arb_irqchip = {
689 .name = "pmic_arb",
690 .irq_ack = qpnpint_irq_ack,
691 .irq_mask = qpnpint_irq_mask,
692 .irq_unmask = qpnpint_irq_unmask,
693 .irq_set_type = qpnpint_irq_set_type,
694 .irq_set_wake = qpnpint_irq_set_wake,
695 .irq_get_irqchip_state = qpnpint_get_irqchip_state,
696 .flags = IRQCHIP_MASK_ON_SUSPEND,
697 };
698
699 static int qpnpint_irq_domain_translate(struct irq_domain *d,
700 struct irq_fwspec *fwspec,
701 unsigned long *out_hwirq,
702 unsigned int *out_type)
703 {
704 struct spmi_pmic_arb *pmic_arb = d->host_data;
705 u32 *intspec = fwspec->param;
706 u16 apid, ppid;
707 int rc;
708
709 dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
710 intspec[0], intspec[1], intspec[2]);
711
712 if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
713 return -EINVAL;
714 if (fwspec->param_count != 4)
715 return -EINVAL;
716 if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
717 return -EINVAL;
718
719 ppid = intspec[0] << 8 | intspec[1];
720 rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
721 if (rc < 0) {
722 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
723 intspec[0], intspec[1], intspec[2], rc);
724 return rc;
725 }
726
727 apid = rc;
728 /* Keep track of {max,min}_apid for bounding search during interrupt */
729 if (apid > pmic_arb->max_apid)
730 pmic_arb->max_apid = apid;
731 if (apid < pmic_arb->min_apid)
732 pmic_arb->min_apid = apid;
733
734 *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
735 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
736
737 dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
738
739 return 0;
740 }
741
742
743 static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
744 struct irq_domain *domain, unsigned int virq,
745 irq_hw_number_t hwirq, unsigned int type)
746 {
747 irq_flow_handler_t handler;
748
749 dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
750 virq, hwirq, type);
751
752 if (type & IRQ_TYPE_EDGE_BOTH)
753 handler = handle_edge_irq;
754 else
755 handler = handle_level_irq;
756
757 irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
758 handler, NULL, NULL);
759 }
760
761 static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
762 unsigned int virq, unsigned int nr_irqs,
763 void *data)
764 {
765 struct spmi_pmic_arb *pmic_arb = domain->host_data;
766 struct irq_fwspec *fwspec = data;
767 irq_hw_number_t hwirq;
768 unsigned int type;
769 int ret, i;
770
771 ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
772 if (ret)
773 return ret;
774
775 for (i = 0; i < nr_irqs; i++)
776 qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
777 type);
778
779 return 0;
780 }
781
782 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
783 {
784 u32 *mapping_table = pmic_arb->mapping_table;
785 int index = 0, i;
786 u16 apid_valid;
787 u16 apid;
788 u32 data;
789
790 apid_valid = pmic_arb->ppid_to_apid[ppid];
791 if (apid_valid & PMIC_ARB_APID_VALID) {
792 apid = apid_valid & ~PMIC_ARB_APID_VALID;
793 return apid;
794 }
795
796 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
797 if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
798 mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
799 SPMI_MAPPING_TABLE_REG(index));
800
801 data = mapping_table[index];
802
803 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
804 if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
805 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
806 } else {
807 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
808 pmic_arb->ppid_to_apid[ppid]
809 = apid | PMIC_ARB_APID_VALID;
810 pmic_arb->apid_data[apid].ppid = ppid;
811 return apid;
812 }
813 } else {
814 if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
815 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
816 } else {
817 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
818 pmic_arb->ppid_to_apid[ppid]
819 = apid | PMIC_ARB_APID_VALID;
820 pmic_arb->apid_data[apid].ppid = ppid;
821 return apid;
822 }
823 }
824 }
825
826 return -ENODEV;
827 }
828
829 /* v1 offset per ee */
830 static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
831 enum pmic_arb_channel ch_type)
832 {
833 return 0x800 + 0x80 * pmic_arb->channel;
834 }
835
836 static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
837 {
838 struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
839 u32 regval, offset;
840 u16 id, apid;
841
842 for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
843 offset = pmic_arb->ver_ops->apid_map_offset(apid);
844 if (offset >= pmic_arb->core_size)
845 break;
846
847 regval = readl_relaxed(pmic_arb->cnfg +
848 SPMI_OWNERSHIP_TABLE_REG(apid));
849 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
850 apidd->write_ee = apidd->irq_ee;
851
852 regval = readl_relaxed(pmic_arb->core + offset);
853 if (!regval)
854 continue;
855
856 id = (regval >> 8) & PMIC_ARB_PPID_MASK;
857 pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
858 apidd->ppid = id;
859 if (id == ppid) {
860 apid |= PMIC_ARB_APID_VALID;
861 break;
862 }
863 }
864 pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
865
866 return apid;
867 }
868
869 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
870 {
871 u16 apid_valid;
872
873 apid_valid = pmic_arb->ppid_to_apid[ppid];
874 if (!(apid_valid & PMIC_ARB_APID_VALID))
875 apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
876 if (!(apid_valid & PMIC_ARB_APID_VALID))
877 return -ENODEV;
878
879 return apid_valid & ~PMIC_ARB_APID_VALID;
880 }
881
882 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
883 {
884 struct apid_data *apidd = pmic_arb->apid_data;
885 struct apid_data *prev_apidd;
886 u16 i, apid, ppid;
887 bool valid, is_irq_ee;
888 u32 regval, offset;
889
890 /*
891 * In order to allow multiple EEs to write to a single PPID in arbiter
892 * version 5, there is more than one APID mapped to each PPID.
893 * The owner field for each of these mappings specifies the EE which is
894 * allowed to write to the APID. The owner of the last (highest) APID
895 * for a given PPID will receive interrupts from the PPID.
896 */
897 for (i = 0; ; i++, apidd++) {
898 offset = pmic_arb->ver_ops->apid_map_offset(i);
899 if (offset >= pmic_arb->core_size)
900 break;
901
902 regval = readl_relaxed(pmic_arb->core + offset);
903 if (!regval)
904 continue;
905 ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
906 is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
907
908 regval = readl_relaxed(pmic_arb->cnfg +
909 SPMI_OWNERSHIP_TABLE_REG(i));
910 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
911
912 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
913
914 valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
915 apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
916 prev_apidd = &pmic_arb->apid_data[apid];
917
918 if (valid && is_irq_ee &&
919 prev_apidd->write_ee == pmic_arb->ee) {
920 /*
921 * Duplicate PPID mapping after the one for this EE;
922 * override the irq owner
923 */
924 prev_apidd->irq_ee = apidd->irq_ee;
925 } else if (!valid || is_irq_ee) {
926 /* First PPID mapping or duplicate for another EE */
927 pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
928 }
929
930 apidd->ppid = ppid;
931 pmic_arb->last_apid = i;
932 }
933
934 /* Dump the mapping table for debug purposes. */
935 dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
936 for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
937 apid = pmic_arb->ppid_to_apid[ppid];
938 if (apid & PMIC_ARB_APID_VALID) {
939 apid &= ~PMIC_ARB_APID_VALID;
940 apidd = &pmic_arb->apid_data[apid];
941 dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
942 ppid, apid, apidd->write_ee, apidd->irq_ee);
943 }
944 }
945
946 return 0;
947 }
948
949 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
950 {
951 if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
952 return -ENODEV;
953
954 return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
955 }
956
957 /* v2 offset per ppid and per ee */
958 static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
959 enum pmic_arb_channel ch_type)
960 {
961 u16 apid;
962 u16 ppid;
963 int rc;
964
965 ppid = sid << 8 | ((addr >> 8) & 0xFF);
966 rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
967 if (rc < 0)
968 return rc;
969
970 apid = rc;
971 return 0x1000 * pmic_arb->ee + 0x8000 * apid;
972 }
973
974 /*
975 * v5 offset per ee and per apid for observer channels and per apid for
976 * read/write channels.
977 */
978 static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
979 enum pmic_arb_channel ch_type)
980 {
981 u16 apid;
982 int rc;
983 u32 offset = 0;
984 u16 ppid = (sid << 8) | (addr >> 8);
985
986 rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
987 if (rc < 0)
988 return rc;
989
990 apid = rc;
991 switch (ch_type) {
992 case PMIC_ARB_CHANNEL_OBS:
993 offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
994 break;
995 case PMIC_ARB_CHANNEL_RW:
996 offset = 0x10000 * apid;
997 break;
998 }
999
1000 return offset;
1001 }
1002
1003 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
1004 {
1005 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
1006 }
1007
1008 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
1009 {
1010 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
1011 }
1012
1013 static void __iomem *
1014 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1015 {
1016 return pmic_arb->intr + 0x20 * m + 0x4 * n;
1017 }
1018
1019 static void __iomem *
1020 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1021 {
1022 return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1023 }
1024
1025 static void __iomem *
1026 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1027 {
1028 return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1029 }
1030
1031 static void __iomem *
1032 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1033 {
1034 return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1035 }
1036
1037 static void __iomem *
1038 pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1039 {
1040 return pmic_arb->intr + 0x200 + 0x4 * n;
1041 }
1042
1043 static void __iomem *
1044 pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1045 {
1046 return pmic_arb->intr + 0x1000 * n;
1047 }
1048
1049 static void __iomem *
1050 pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1051 {
1052 return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1053 }
1054
1055 static void __iomem *
1056 pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1057 {
1058 return pmic_arb->intr + 0x600 + 0x4 * n;
1059 }
1060
1061 static void __iomem *
1062 pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1063 {
1064 return pmic_arb->intr + 0x4 + 0x1000 * n;
1065 }
1066
1067 static void __iomem *
1068 pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1069 {
1070 return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1071 }
1072
1073 static void __iomem *
1074 pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1075 {
1076 return pmic_arb->intr + 0xA00 + 0x4 * n;
1077 }
1078
1079 static void __iomem *
1080 pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1081 {
1082 return pmic_arb->intr + 0x8 + 0x1000 * n;
1083 }
1084
1085 static void __iomem *
1086 pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1087 {
1088 return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1089 }
1090
1091 static u32 pmic_arb_apid_map_offset_v2(u16 n)
1092 {
1093 return 0x800 + 0x4 * n;
1094 }
1095
1096 static u32 pmic_arb_apid_map_offset_v5(u16 n)
1097 {
1098 return 0x900 + 0x4 * n;
1099 }
1100
1101 static const struct pmic_arb_ver_ops pmic_arb_v1 = {
1102 .ver_str = "v1",
1103 .ppid_to_apid = pmic_arb_ppid_to_apid_v1,
1104 .non_data_cmd = pmic_arb_non_data_cmd_v1,
1105 .offset = pmic_arb_offset_v1,
1106 .fmt_cmd = pmic_arb_fmt_cmd_v1,
1107 .owner_acc_status = pmic_arb_owner_acc_status_v1,
1108 .acc_enable = pmic_arb_acc_enable_v1,
1109 .irq_status = pmic_arb_irq_status_v1,
1110 .irq_clear = pmic_arb_irq_clear_v1,
1111 .apid_map_offset = pmic_arb_apid_map_offset_v2,
1112 };
1113
1114 static const struct pmic_arb_ver_ops pmic_arb_v2 = {
1115 .ver_str = "v2",
1116 .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
1117 .non_data_cmd = pmic_arb_non_data_cmd_v2,
1118 .offset = pmic_arb_offset_v2,
1119 .fmt_cmd = pmic_arb_fmt_cmd_v2,
1120 .owner_acc_status = pmic_arb_owner_acc_status_v2,
1121 .acc_enable = pmic_arb_acc_enable_v2,
1122 .irq_status = pmic_arb_irq_status_v2,
1123 .irq_clear = pmic_arb_irq_clear_v2,
1124 .apid_map_offset = pmic_arb_apid_map_offset_v2,
1125 };
1126
1127 static const struct pmic_arb_ver_ops pmic_arb_v3 = {
1128 .ver_str = "v3",
1129 .ppid_to_apid = pmic_arb_ppid_to_apid_v2,
1130 .non_data_cmd = pmic_arb_non_data_cmd_v2,
1131 .offset = pmic_arb_offset_v2,
1132 .fmt_cmd = pmic_arb_fmt_cmd_v2,
1133 .owner_acc_status = pmic_arb_owner_acc_status_v3,
1134 .acc_enable = pmic_arb_acc_enable_v2,
1135 .irq_status = pmic_arb_irq_status_v2,
1136 .irq_clear = pmic_arb_irq_clear_v2,
1137 .apid_map_offset = pmic_arb_apid_map_offset_v2,
1138 };
1139
1140 static const struct pmic_arb_ver_ops pmic_arb_v5 = {
1141 .ver_str = "v5",
1142 .ppid_to_apid = pmic_arb_ppid_to_apid_v5,
1143 .non_data_cmd = pmic_arb_non_data_cmd_v2,
1144 .offset = pmic_arb_offset_v5,
1145 .fmt_cmd = pmic_arb_fmt_cmd_v2,
1146 .owner_acc_status = pmic_arb_owner_acc_status_v5,
1147 .acc_enable = pmic_arb_acc_enable_v5,
1148 .irq_status = pmic_arb_irq_status_v5,
1149 .irq_clear = pmic_arb_irq_clear_v5,
1150 .apid_map_offset = pmic_arb_apid_map_offset_v5,
1151 };
1152
1153 static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
1154 .activate = qpnpint_irq_domain_activate,
1155 .alloc = qpnpint_irq_domain_alloc,
1156 .free = irq_domain_free_irqs_common,
1157 .translate = qpnpint_irq_domain_translate,
1158 };
1159
1160 static int spmi_pmic_arb_probe(struct platform_device *pdev)
1161 {
1162 struct spmi_pmic_arb *pmic_arb;
1163 struct spmi_controller *ctrl;
1164 struct resource *res;
1165 void __iomem *core;
1166 u32 *mapping_table;
1167 u32 channel, ee, hw_ver;
1168 int err;
1169
1170 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1171 if (!ctrl)
1172 return -ENOMEM;
1173
1174 pmic_arb = spmi_controller_get_drvdata(ctrl);
1175 pmic_arb->spmic = ctrl;
1176
1177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
1178 core = devm_ioremap_resource(&ctrl->dev, res);
1179 if (IS_ERR(core)) {
1180 err = PTR_ERR(core);
1181 goto err_put_ctrl;
1182 }
1183
1184 pmic_arb->core_size = resource_size(res);
1185
1186 pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1187 sizeof(*pmic_arb->ppid_to_apid),
1188 GFP_KERNEL);
1189 if (!pmic_arb->ppid_to_apid) {
1190 err = -ENOMEM;
1191 goto err_put_ctrl;
1192 }
1193
1194 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
1195
1196 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
1197 pmic_arb->ver_ops = &pmic_arb_v1;
1198 pmic_arb->wr_base = core;
1199 pmic_arb->rd_base = core;
1200 } else {
1201 pmic_arb->core = core;
1202
1203 if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
1204 pmic_arb->ver_ops = &pmic_arb_v2;
1205 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
1206 pmic_arb->ver_ops = &pmic_arb_v3;
1207 else
1208 pmic_arb->ver_ops = &pmic_arb_v5;
1209
1210 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1211 "obsrvr");
1212 pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
1213 if (IS_ERR(pmic_arb->rd_base)) {
1214 err = PTR_ERR(pmic_arb->rd_base);
1215 goto err_put_ctrl;
1216 }
1217
1218 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1219 "chnls");
1220 pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
1221 if (IS_ERR(pmic_arb->wr_base)) {
1222 err = PTR_ERR(pmic_arb->wr_base);
1223 goto err_put_ctrl;
1224 }
1225 }
1226
1227 dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
1228 pmic_arb->ver_ops->ver_str, hw_ver);
1229
1230 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
1231 pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1232 if (IS_ERR(pmic_arb->intr)) {
1233 err = PTR_ERR(pmic_arb->intr);
1234 goto err_put_ctrl;
1235 }
1236
1237 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
1238 pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1239 if (IS_ERR(pmic_arb->cnfg)) {
1240 err = PTR_ERR(pmic_arb->cnfg);
1241 goto err_put_ctrl;
1242 }
1243
1244 pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1245 if (pmic_arb->irq < 0) {
1246 err = pmic_arb->irq;
1247 goto err_put_ctrl;
1248 }
1249
1250 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
1251 if (err) {
1252 dev_err(&pdev->dev, "channel unspecified.\n");
1253 goto err_put_ctrl;
1254 }
1255
1256 if (channel > 5) {
1257 dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
1258 channel);
1259 err = -EINVAL;
1260 goto err_put_ctrl;
1261 }
1262
1263 pmic_arb->channel = channel;
1264
1265 err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
1266 if (err) {
1267 dev_err(&pdev->dev, "EE unspecified.\n");
1268 goto err_put_ctrl;
1269 }
1270
1271 if (ee > 5) {
1272 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
1273 err = -EINVAL;
1274 goto err_put_ctrl;
1275 }
1276
1277 pmic_arb->ee = ee;
1278 mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
1279 sizeof(*mapping_table), GFP_KERNEL);
1280 if (!mapping_table) {
1281 err = -ENOMEM;
1282 goto err_put_ctrl;
1283 }
1284
1285 pmic_arb->mapping_table = mapping_table;
1286 /* Initialize max_apid/min_apid to the opposite bounds, during
1287 * the irq domain translation, we are sure to update these */
1288 pmic_arb->max_apid = 0;
1289 pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
1290
1291 platform_set_drvdata(pdev, ctrl);
1292 raw_spin_lock_init(&pmic_arb->lock);
1293
1294 ctrl->cmd = pmic_arb_cmd;
1295 ctrl->read_cmd = pmic_arb_read_cmd;
1296 ctrl->write_cmd = pmic_arb_write_cmd;
1297
1298 if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
1299 err = pmic_arb_read_apid_map_v5(pmic_arb);
1300 if (err) {
1301 dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
1302 err);
1303 goto err_put_ctrl;
1304 }
1305 }
1306
1307 dev_dbg(&pdev->dev, "adding irq domain\n");
1308 pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1309 &pmic_arb_irq_domain_ops, pmic_arb);
1310 if (!pmic_arb->domain) {
1311 dev_err(&pdev->dev, "unable to create irq_domain\n");
1312 err = -ENOMEM;
1313 goto err_put_ctrl;
1314 }
1315
1316 irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1317 pmic_arb);
1318 err = spmi_controller_add(ctrl);
1319 if (err)
1320 goto err_domain_remove;
1321
1322 return 0;
1323
1324 err_domain_remove:
1325 irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1326 irq_domain_remove(pmic_arb->domain);
1327 err_put_ctrl:
1328 spmi_controller_put(ctrl);
1329 return err;
1330 }
1331
1332 static int spmi_pmic_arb_remove(struct platform_device *pdev)
1333 {
1334 struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1335 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1336 spmi_controller_remove(ctrl);
1337 irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1338 irq_domain_remove(pmic_arb->domain);
1339 spmi_controller_put(ctrl);
1340 return 0;
1341 }
1342
1343 static const struct of_device_id spmi_pmic_arb_match_table[] = {
1344 { .compatible = "qcom,spmi-pmic-arb", },
1345 {},
1346 };
1347 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1348
1349 static struct platform_driver spmi_pmic_arb_driver = {
1350 .probe = spmi_pmic_arb_probe,
1351 .remove = spmi_pmic_arb_remove,
1352 .driver = {
1353 .name = "spmi_pmic_arb",
1354 .of_match_table = spmi_pmic_arb_match_table,
1355 },
1356 };
1357 module_platform_driver(spmi_pmic_arb_driver);
1358
1359 MODULE_LICENSE("GPL v2");
1360 MODULE_ALIAS("platform:spmi_pmic_arb");
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