2 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irq.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spmi.h>
27 /* PMIC Arbiter configuration registers */
28 #define PMIC_ARB_VERSION 0x0000
29 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
30 #define PMIC_ARB_INT_EN 0x0004
32 /* PMIC Arbiter channel registers offsets */
33 #define PMIC_ARB_CMD 0x00
34 #define PMIC_ARB_CONFIG 0x04
35 #define PMIC_ARB_STATUS 0x08
36 #define PMIC_ARB_WDATA0 0x10
37 #define PMIC_ARB_WDATA1 0x14
38 #define PMIC_ARB_RDATA0 0x18
39 #define PMIC_ARB_RDATA1 0x1C
40 #define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N))
43 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
44 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
45 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
46 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
47 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
48 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
50 #define SPMI_MAPPING_TABLE_LEN 255
51 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
52 #define PPID_TO_CHAN_TABLE_SZ BIT(12) /* PPID is 12bit chan is 1byte*/
55 #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
56 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
58 /* Channel Status fields */
59 enum pmic_arb_chnl_status
{
60 PMIC_ARB_STATUS_DONE
= (1 << 0),
61 PMIC_ARB_STATUS_FAILURE
= (1 << 1),
62 PMIC_ARB_STATUS_DENIED
= (1 << 2),
63 PMIC_ARB_STATUS_DROPPED
= (1 << 3),
66 /* Command register fields */
67 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
70 enum pmic_arb_cmd_op_code
{
71 PMIC_ARB_OP_EXT_WRITEL
= 0,
72 PMIC_ARB_OP_EXT_READL
= 1,
73 PMIC_ARB_OP_EXT_WRITE
= 2,
74 PMIC_ARB_OP_RESET
= 3,
75 PMIC_ARB_OP_SLEEP
= 4,
76 PMIC_ARB_OP_SHUTDOWN
= 5,
77 PMIC_ARB_OP_WAKEUP
= 6,
78 PMIC_ARB_OP_AUTHENTICATE
= 7,
79 PMIC_ARB_OP_MSTR_READ
= 8,
80 PMIC_ARB_OP_MSTR_WRITE
= 9,
81 PMIC_ARB_OP_EXT_READ
= 13,
82 PMIC_ARB_OP_WRITE
= 14,
83 PMIC_ARB_OP_READ
= 15,
84 PMIC_ARB_OP_ZERO_WRITE
= 16,
87 /* Maximum number of support PMIC peripherals */
88 #define PMIC_ARB_MAX_PERIPHS 256
89 #define PMIC_ARB_MAX_CHNL 128
90 #define PMIC_ARB_PERIPH_ID_VALID (1 << 15)
91 #define PMIC_ARB_TIMEOUT_US 100
92 #define PMIC_ARB_MAX_TRANS_BYTES (8)
94 #define PMIC_ARB_APID_MASK 0xFF
95 #define PMIC_ARB_PPID_MASK 0xFFF
97 /* interrupt enable bit */
98 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
100 struct pmic_arb_ver_ops
;
103 * spmi_pmic_arb_dev - SPMI PMIC Arbiter object
105 * @rd_base: on v1 "core", on v2 "observer" register base off DT.
106 * @wr_base: on v1 "core", on v2 "chnls" register base off DT.
107 * @intr: address of the SPMI interrupt control registers.
108 * @cnfg: address of the PMIC Arbiter configuration registers.
109 * @lock: lock to synchronize accesses.
110 * @channel: execution environment channel to use for accesses.
111 * @irq: PMIC ARB interrupt.
112 * @ee: the current Execution Environment
113 * @min_apid: minimum APID (used for bounding IRQ search)
114 * @max_apid: maximum APID
115 * @mapping_table: in-memory copy of PPID -> APID mapping table.
116 * @domain: irq domain object for PMIC IRQ domain
117 * @spmic: SPMI controller object
118 * @apid_to_ppid: in-memory copy of APID -> PPID mapping table.
119 * @ver_ops: version dependent operations.
120 * @ppid_to_chan in-memory copy of PPID -> channel (APID) mapping table.
123 struct spmi_pmic_arb_dev
{
124 void __iomem
*rd_base
;
125 void __iomem
*wr_base
;
134 u32 mapping_table
[SPMI_MAPPING_TABLE_LEN
];
135 struct irq_domain
*domain
;
136 struct spmi_controller
*spmic
;
137 u16 apid_to_ppid
[256];
138 const struct pmic_arb_ver_ops
*ver_ops
;
143 * pmic_arb_ver: version dependent functionality.
145 * @non_data_cmd: on v1 issues an spmi non-data command.
146 * on v2 no HW support, returns -EOPNOTSUPP.
147 * @offset: on v1 offset of per-ee channel.
148 * on v2 offset of per-ee and per-ppid channel.
149 * @fmt_cmd: formats a GENI/SPMI command.
150 * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
151 * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn.
152 * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
153 * on v2 offset of SPMI_PIC_ACC_ENABLEn.
154 * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
155 * on v2 offset of SPMI_PIC_IRQ_STATUSn.
156 * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
157 * on v2 offset of SPMI_PIC_IRQ_CLEARn.
159 struct pmic_arb_ver_ops
{
160 /* spmi commands (read_cmd, write_cmd, cmd) functionality */
161 u32 (*offset
)(struct spmi_pmic_arb_dev
*dev
, u8 sid
, u16 addr
);
162 u32 (*fmt_cmd
)(u8 opc
, u8 sid
, u16 addr
, u8 bc
);
163 int (*non_data_cmd
)(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
);
164 /* Interrupts controller functionality (offset of PIC registers) */
165 u32 (*owner_acc_status
)(u8 m
, u8 n
);
166 u32 (*acc_enable
)(u8 n
);
167 u32 (*irq_status
)(u8 n
);
168 u32 (*irq_clear
)(u8 n
);
171 static inline u32
pmic_arb_base_read(struct spmi_pmic_arb_dev
*dev
, u32 offset
)
173 return readl_relaxed(dev
->rd_base
+ offset
);
176 static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev
*dev
,
179 writel_relaxed(val
, dev
->wr_base
+ offset
);
182 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev
*dev
,
185 writel_relaxed(val
, dev
->rd_base
+ offset
);
189 * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
190 * @bc: byte count -1. range: 0..3
191 * @reg: register's address
192 * @buf: output parameter, length must be bc + 1
194 static void pa_read_data(struct spmi_pmic_arb_dev
*dev
, u8
*buf
, u32 reg
, u8 bc
)
196 u32 data
= pmic_arb_base_read(dev
, reg
);
197 memcpy(buf
, &data
, (bc
& 3) + 1);
201 * pa_write_data: write 1..4 bytes from buf to pmic-arb's register
202 * @bc: byte-count -1. range: 0..3.
203 * @reg: register's address.
204 * @buf: buffer to write. length must be bc + 1.
207 pa_write_data(struct spmi_pmic_arb_dev
*dev
, const u8
*buf
, u32 reg
, u8 bc
)
210 memcpy(&data
, buf
, (bc
& 3) + 1);
211 pmic_arb_base_write(dev
, reg
, data
);
214 static int pmic_arb_wait_for_done(struct spmi_controller
*ctrl
,
215 void __iomem
*base
, u8 sid
, u16 addr
)
217 struct spmi_pmic_arb_dev
*dev
= spmi_controller_get_drvdata(ctrl
);
219 u32 timeout
= PMIC_ARB_TIMEOUT_US
;
220 u32 offset
= dev
->ver_ops
->offset(dev
, sid
, addr
) + PMIC_ARB_STATUS
;
223 status
= readl_relaxed(base
+ offset
);
225 if (status
& PMIC_ARB_STATUS_DONE
) {
226 if (status
& PMIC_ARB_STATUS_DENIED
) {
228 "%s: transaction denied (0x%x)\n",
233 if (status
& PMIC_ARB_STATUS_FAILURE
) {
235 "%s: transaction failed (0x%x)\n",
240 if (status
& PMIC_ARB_STATUS_DROPPED
) {
242 "%s: transaction dropped (0x%x)\n",
253 "%s: timeout, status 0x%x\n",
259 pmic_arb_non_data_cmd_v1(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
)
261 struct spmi_pmic_arb_dev
*pmic_arb
= spmi_controller_get_drvdata(ctrl
);
265 u32 offset
= pmic_arb
->ver_ops
->offset(pmic_arb
, sid
, 0);
267 cmd
= ((opc
| 0x40) << 27) | ((sid
& 0xf) << 20);
269 raw_spin_lock_irqsave(&pmic_arb
->lock
, flags
);
270 pmic_arb_base_write(pmic_arb
, offset
+ PMIC_ARB_CMD
, cmd
);
271 rc
= pmic_arb_wait_for_done(ctrl
, pmic_arb
->wr_base
, sid
, 0);
272 raw_spin_unlock_irqrestore(&pmic_arb
->lock
, flags
);
278 pmic_arb_non_data_cmd_v2(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
)
283 /* Non-data command */
284 static int pmic_arb_cmd(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
)
286 struct spmi_pmic_arb_dev
*pmic_arb
= spmi_controller_get_drvdata(ctrl
);
288 dev_dbg(&ctrl
->dev
, "cmd op:0x%x sid:%d\n", opc
, sid
);
290 /* Check for valid non-data command */
291 if (opc
< SPMI_CMD_RESET
|| opc
> SPMI_CMD_WAKEUP
)
294 return pmic_arb
->ver_ops
->non_data_cmd(ctrl
, opc
, sid
);
297 static int pmic_arb_read_cmd(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
,
298 u16 addr
, u8
*buf
, size_t len
)
300 struct spmi_pmic_arb_dev
*pmic_arb
= spmi_controller_get_drvdata(ctrl
);
305 u32 offset
= pmic_arb
->ver_ops
->offset(pmic_arb
, sid
, addr
);
307 if (bc
>= PMIC_ARB_MAX_TRANS_BYTES
) {
309 "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
310 PMIC_ARB_MAX_TRANS_BYTES
, len
);
314 /* Check the opcode */
315 if (opc
>= 0x60 && opc
<= 0x7F)
316 opc
= PMIC_ARB_OP_READ
;
317 else if (opc
>= 0x20 && opc
<= 0x2F)
318 opc
= PMIC_ARB_OP_EXT_READ
;
319 else if (opc
>= 0x38 && opc
<= 0x3F)
320 opc
= PMIC_ARB_OP_EXT_READL
;
324 cmd
= pmic_arb
->ver_ops
->fmt_cmd(opc
, sid
, addr
, bc
);
326 raw_spin_lock_irqsave(&pmic_arb
->lock
, flags
);
327 pmic_arb_set_rd_cmd(pmic_arb
, offset
+ PMIC_ARB_CMD
, cmd
);
328 rc
= pmic_arb_wait_for_done(ctrl
, pmic_arb
->rd_base
, sid
, addr
);
332 pa_read_data(pmic_arb
, buf
, offset
+ PMIC_ARB_RDATA0
,
336 pa_read_data(pmic_arb
, buf
+ 4,
337 offset
+ PMIC_ARB_RDATA1
, bc
- 4);
340 raw_spin_unlock_irqrestore(&pmic_arb
->lock
, flags
);
344 static int pmic_arb_write_cmd(struct spmi_controller
*ctrl
, u8 opc
, u8 sid
,
345 u16 addr
, const u8
*buf
, size_t len
)
347 struct spmi_pmic_arb_dev
*pmic_arb
= spmi_controller_get_drvdata(ctrl
);
352 u32 offset
= pmic_arb
->ver_ops
->offset(pmic_arb
, sid
, addr
);
354 if (bc
>= PMIC_ARB_MAX_TRANS_BYTES
) {
356 "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
357 PMIC_ARB_MAX_TRANS_BYTES
, len
);
361 /* Check the opcode */
362 if (opc
>= 0x40 && opc
<= 0x5F)
363 opc
= PMIC_ARB_OP_WRITE
;
364 else if (opc
>= 0x00 && opc
<= 0x0F)
365 opc
= PMIC_ARB_OP_EXT_WRITE
;
366 else if (opc
>= 0x30 && opc
<= 0x37)
367 opc
= PMIC_ARB_OP_EXT_WRITEL
;
368 else if (opc
>= 0x80 && opc
<= 0xFF)
369 opc
= PMIC_ARB_OP_ZERO_WRITE
;
373 cmd
= pmic_arb
->ver_ops
->fmt_cmd(opc
, sid
, addr
, bc
);
375 /* Write data to FIFOs */
376 raw_spin_lock_irqsave(&pmic_arb
->lock
, flags
);
377 pa_write_data(pmic_arb
, buf
, offset
+ PMIC_ARB_WDATA0
,
380 pa_write_data(pmic_arb
, buf
+ 4,
381 offset
+ PMIC_ARB_WDATA1
, bc
- 4);
383 /* Start the transaction */
384 pmic_arb_base_write(pmic_arb
, offset
+ PMIC_ARB_CMD
, cmd
);
385 rc
= pmic_arb_wait_for_done(ctrl
, pmic_arb
->wr_base
, sid
, addr
);
386 raw_spin_unlock_irqrestore(&pmic_arb
->lock
, flags
);
392 QPNPINT_REG_RT_STS
= 0x10,
393 QPNPINT_REG_SET_TYPE
= 0x11,
394 QPNPINT_REG_POLARITY_HIGH
= 0x12,
395 QPNPINT_REG_POLARITY_LOW
= 0x13,
396 QPNPINT_REG_LATCHED_CLR
= 0x14,
397 QPNPINT_REG_EN_SET
= 0x15,
398 QPNPINT_REG_EN_CLR
= 0x16,
399 QPNPINT_REG_LATCHED_STS
= 0x18,
402 struct spmi_pmic_arb_qpnpint_type
{
403 u8 type
; /* 1 -> edge */
408 /* Simplified accessor functions for irqchip callbacks */
409 static void qpnpint_spmi_write(struct irq_data
*d
, u8 reg
, void *buf
,
412 struct spmi_pmic_arb_dev
*pa
= irq_data_get_irq_chip_data(d
);
413 u8 sid
= d
->hwirq
>> 24;
414 u8 per
= d
->hwirq
>> 16;
416 if (pmic_arb_write_cmd(pa
->spmic
, SPMI_CMD_EXT_WRITEL
, sid
,
417 (per
<< 8) + reg
, buf
, len
))
418 dev_err_ratelimited(&pa
->spmic
->dev
,
419 "failed irqchip transaction on %x\n",
423 static void qpnpint_spmi_read(struct irq_data
*d
, u8 reg
, void *buf
, size_t len
)
425 struct spmi_pmic_arb_dev
*pa
= irq_data_get_irq_chip_data(d
);
426 u8 sid
= d
->hwirq
>> 24;
427 u8 per
= d
->hwirq
>> 16;
429 if (pmic_arb_read_cmd(pa
->spmic
, SPMI_CMD_EXT_READL
, sid
,
430 (per
<< 8) + reg
, buf
, len
))
431 dev_err_ratelimited(&pa
->spmic
->dev
,
432 "failed irqchip transaction on %x\n",
436 static void periph_interrupt(struct spmi_pmic_arb_dev
*pa
, u8 apid
)
442 status
= readl_relaxed(pa
->intr
+ pa
->ver_ops
->irq_status(apid
));
444 id
= ffs(status
) - 1;
445 status
&= ~(1 << id
);
446 irq
= irq_find_mapping(pa
->domain
,
447 pa
->apid_to_ppid
[apid
] << 16
450 generic_handle_irq(irq
);
454 static void pmic_arb_chained_irq(struct irq_desc
*desc
)
456 struct spmi_pmic_arb_dev
*pa
= irq_desc_get_handler_data(desc
);
457 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
458 void __iomem
*intr
= pa
->intr
;
459 int first
= pa
->min_apid
>> 5;
460 int last
= pa
->max_apid
>> 5;
464 chained_irq_enter(chip
, desc
);
466 for (i
= first
; i
<= last
; ++i
) {
467 status
= readl_relaxed(intr
+
468 pa
->ver_ops
->owner_acc_status(pa
->ee
, i
));
470 id
= ffs(status
) - 1;
471 status
&= ~(1 << id
);
472 periph_interrupt(pa
, id
+ i
* 32);
476 chained_irq_exit(chip
, desc
);
479 static void qpnpint_irq_ack(struct irq_data
*d
)
481 struct spmi_pmic_arb_dev
*pa
= irq_data_get_irq_chip_data(d
);
482 u8 irq
= d
->hwirq
>> 8;
487 raw_spin_lock_irqsave(&pa
->lock
, flags
);
488 writel_relaxed(1 << irq
, pa
->intr
+ pa
->ver_ops
->irq_clear(apid
));
489 raw_spin_unlock_irqrestore(&pa
->lock
, flags
);
492 qpnpint_spmi_write(d
, QPNPINT_REG_LATCHED_CLR
, &data
, 1);
495 static void qpnpint_irq_mask(struct irq_data
*d
)
497 struct spmi_pmic_arb_dev
*pa
= irq_data_get_irq_chip_data(d
);
498 u8 irq
= d
->hwirq
>> 8;
504 raw_spin_lock_irqsave(&pa
->lock
, flags
);
505 status
= readl_relaxed(pa
->intr
+ pa
->ver_ops
->acc_enable(apid
));
506 if (status
& SPMI_PIC_ACC_ENABLE_BIT
) {
507 status
= status
& ~SPMI_PIC_ACC_ENABLE_BIT
;
508 writel_relaxed(status
, pa
->intr
+
509 pa
->ver_ops
->acc_enable(apid
));
511 raw_spin_unlock_irqrestore(&pa
->lock
, flags
);
514 qpnpint_spmi_write(d
, QPNPINT_REG_EN_CLR
, &data
, 1);
517 static void qpnpint_irq_unmask(struct irq_data
*d
)
519 struct spmi_pmic_arb_dev
*pa
= irq_data_get_irq_chip_data(d
);
520 u8 irq
= d
->hwirq
>> 8;
526 raw_spin_lock_irqsave(&pa
->lock
, flags
);
527 status
= readl_relaxed(pa
->intr
+ pa
->ver_ops
->acc_enable(apid
));
528 if (!(status
& SPMI_PIC_ACC_ENABLE_BIT
)) {
529 writel_relaxed(status
| SPMI_PIC_ACC_ENABLE_BIT
,
530 pa
->intr
+ pa
->ver_ops
->acc_enable(apid
));
532 raw_spin_unlock_irqrestore(&pa
->lock
, flags
);
535 qpnpint_spmi_write(d
, QPNPINT_REG_EN_SET
, &data
, 1);
538 static void qpnpint_irq_enable(struct irq_data
*d
)
540 u8 irq
= d
->hwirq
>> 8;
543 qpnpint_irq_unmask(d
);
546 qpnpint_spmi_write(d
, QPNPINT_REG_LATCHED_CLR
, &data
, 1);
549 static int qpnpint_irq_set_type(struct irq_data
*d
, unsigned int flow_type
)
551 struct spmi_pmic_arb_qpnpint_type type
;
552 u8 irq
= d
->hwirq
>> 8;
554 qpnpint_spmi_read(d
, QPNPINT_REG_SET_TYPE
, &type
, sizeof(type
));
556 if (flow_type
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
)) {
557 type
.type
|= 1 << irq
;
558 if (flow_type
& IRQF_TRIGGER_RISING
)
559 type
.polarity_high
|= 1 << irq
;
560 if (flow_type
& IRQF_TRIGGER_FALLING
)
561 type
.polarity_low
|= 1 << irq
;
563 if ((flow_type
& (IRQF_TRIGGER_HIGH
)) &&
564 (flow_type
& (IRQF_TRIGGER_LOW
)))
567 type
.type
&= ~(1 << irq
); /* level trig */
568 if (flow_type
& IRQF_TRIGGER_HIGH
)
569 type
.polarity_high
|= 1 << irq
;
571 type
.polarity_low
|= 1 << irq
;
574 qpnpint_spmi_write(d
, QPNPINT_REG_SET_TYPE
, &type
, sizeof(type
));
578 static int qpnpint_get_irqchip_state(struct irq_data
*d
,
579 enum irqchip_irq_state which
,
582 u8 irq
= d
->hwirq
>> 8;
585 if (which
!= IRQCHIP_STATE_LINE_LEVEL
)
588 qpnpint_spmi_read(d
, QPNPINT_REG_RT_STS
, &status
, 1);
589 *state
= !!(status
& BIT(irq
));
594 static struct irq_chip pmic_arb_irqchip
= {
596 .irq_enable
= qpnpint_irq_enable
,
597 .irq_ack
= qpnpint_irq_ack
,
598 .irq_mask
= qpnpint_irq_mask
,
599 .irq_unmask
= qpnpint_irq_unmask
,
600 .irq_set_type
= qpnpint_irq_set_type
,
601 .irq_get_irqchip_state
= qpnpint_get_irqchip_state
,
602 .flags
= IRQCHIP_MASK_ON_SUSPEND
603 | IRQCHIP_SKIP_SET_WAKE
,
606 struct spmi_pmic_arb_irq_spec
{
612 static int search_mapping_table(struct spmi_pmic_arb_dev
*pa
,
613 struct spmi_pmic_arb_irq_spec
*spec
,
616 u16 ppid
= spec
->slave
<< 8 | spec
->per
;
617 u32
*mapping_table
= pa
->mapping_table
;
621 for (i
= 0; i
< SPMI_MAPPING_TABLE_TREE_DEPTH
; ++i
) {
622 data
= mapping_table
[index
];
624 if (ppid
& (1 << SPMI_MAPPING_BIT_INDEX(data
))) {
625 if (SPMI_MAPPING_BIT_IS_1_FLAG(data
)) {
626 index
= SPMI_MAPPING_BIT_IS_1_RESULT(data
);
628 *apid
= SPMI_MAPPING_BIT_IS_1_RESULT(data
);
632 if (SPMI_MAPPING_BIT_IS_0_FLAG(data
)) {
633 index
= SPMI_MAPPING_BIT_IS_0_RESULT(data
);
635 *apid
= SPMI_MAPPING_BIT_IS_0_RESULT(data
);
644 static int qpnpint_irq_domain_dt_translate(struct irq_domain
*d
,
645 struct device_node
*controller
,
647 unsigned int intsize
,
648 unsigned long *out_hwirq
,
649 unsigned int *out_type
)
651 struct spmi_pmic_arb_dev
*pa
= d
->host_data
;
652 struct spmi_pmic_arb_irq_spec spec
;
656 dev_dbg(&pa
->spmic
->dev
,
657 "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
658 intspec
[0], intspec
[1], intspec
[2]);
660 if (irq_domain_get_of_node(d
) != controller
)
664 if (intspec
[0] > 0xF || intspec
[1] > 0xFF || intspec
[2] > 0x7)
667 spec
.slave
= intspec
[0];
668 spec
.per
= intspec
[1];
669 spec
.irq
= intspec
[2];
671 err
= search_mapping_table(pa
, &spec
, &apid
);
675 pa
->apid_to_ppid
[apid
] = spec
.slave
<< 8 | spec
.per
;
677 /* Keep track of {max,min}_apid for bounding search during interrupt */
678 if (apid
> pa
->max_apid
)
680 if (apid
< pa
->min_apid
)
683 *out_hwirq
= spec
.slave
<< 24
687 *out_type
= intspec
[3] & IRQ_TYPE_SENSE_MASK
;
689 dev_dbg(&pa
->spmic
->dev
, "out_hwirq = %lu\n", *out_hwirq
);
694 static int qpnpint_irq_domain_map(struct irq_domain
*d
,
696 irq_hw_number_t hwirq
)
698 struct spmi_pmic_arb_dev
*pa
= d
->host_data
;
700 dev_dbg(&pa
->spmic
->dev
, "virq = %u, hwirq = %lu\n", virq
, hwirq
);
702 irq_set_chip_and_handler(virq
, &pmic_arb_irqchip
, handle_level_irq
);
703 irq_set_chip_data(virq
, d
->host_data
);
704 irq_set_noprobe(virq
);
708 /* v1 offset per ee */
709 static u32
pmic_arb_offset_v1(struct spmi_pmic_arb_dev
*pa
, u8 sid
, u16 addr
)
711 return 0x800 + 0x80 * pa
->channel
;
714 /* v2 offset per ppid (chan) and per ee */
715 static u32
pmic_arb_offset_v2(struct spmi_pmic_arb_dev
*pa
, u8 sid
, u16 addr
)
717 u16 ppid
= (sid
<< 8) | (addr
>> 8);
718 u8 chan
= pa
->ppid_to_chan
[ppid
];
720 return 0x1000 * pa
->ee
+ 0x8000 * chan
;
723 static u32
pmic_arb_fmt_cmd_v1(u8 opc
, u8 sid
, u16 addr
, u8 bc
)
725 return (opc
<< 27) | ((sid
& 0xf) << 20) | (addr
<< 4) | (bc
& 0x7);
728 static u32
pmic_arb_fmt_cmd_v2(u8 opc
, u8 sid
, u16 addr
, u8 bc
)
730 return (opc
<< 27) | ((addr
& 0xff) << 4) | (bc
& 0x7);
733 static u32
pmic_arb_owner_acc_status_v1(u8 m
, u8 n
)
735 return 0x20 * m
+ 0x4 * n
;
738 static u32
pmic_arb_owner_acc_status_v2(u8 m
, u8 n
)
740 return 0x100000 + 0x1000 * m
+ 0x4 * n
;
743 static u32
pmic_arb_acc_enable_v1(u8 n
)
745 return 0x200 + 0x4 * n
;
748 static u32
pmic_arb_acc_enable_v2(u8 n
)
753 static u32
pmic_arb_irq_status_v1(u8 n
)
755 return 0x600 + 0x4 * n
;
758 static u32
pmic_arb_irq_status_v2(u8 n
)
760 return 0x4 + 0x1000 * n
;
763 static u32
pmic_arb_irq_clear_v1(u8 n
)
765 return 0xA00 + 0x4 * n
;
768 static u32
pmic_arb_irq_clear_v2(u8 n
)
770 return 0x8 + 0x1000 * n
;
773 static const struct pmic_arb_ver_ops pmic_arb_v1
= {
774 .non_data_cmd
= pmic_arb_non_data_cmd_v1
,
775 .offset
= pmic_arb_offset_v1
,
776 .fmt_cmd
= pmic_arb_fmt_cmd_v1
,
777 .owner_acc_status
= pmic_arb_owner_acc_status_v1
,
778 .acc_enable
= pmic_arb_acc_enable_v1
,
779 .irq_status
= pmic_arb_irq_status_v1
,
780 .irq_clear
= pmic_arb_irq_clear_v1
,
783 static const struct pmic_arb_ver_ops pmic_arb_v2
= {
784 .non_data_cmd
= pmic_arb_non_data_cmd_v2
,
785 .offset
= pmic_arb_offset_v2
,
786 .fmt_cmd
= pmic_arb_fmt_cmd_v2
,
787 .owner_acc_status
= pmic_arb_owner_acc_status_v2
,
788 .acc_enable
= pmic_arb_acc_enable_v2
,
789 .irq_status
= pmic_arb_irq_status_v2
,
790 .irq_clear
= pmic_arb_irq_clear_v2
,
793 static const struct irq_domain_ops pmic_arb_irq_domain_ops
= {
794 .map
= qpnpint_irq_domain_map
,
795 .xlate
= qpnpint_irq_domain_dt_translate
,
798 static int spmi_pmic_arb_probe(struct platform_device
*pdev
)
800 struct spmi_pmic_arb_dev
*pa
;
801 struct spmi_controller
*ctrl
;
802 struct resource
*res
;
804 u32 channel
, ee
, hw_ver
;
808 ctrl
= spmi_controller_alloc(&pdev
->dev
, sizeof(*pa
));
812 pa
= spmi_controller_get_drvdata(ctrl
);
815 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "core");
816 core
= devm_ioremap_resource(&ctrl
->dev
, res
);
822 hw_ver
= readl_relaxed(core
+ PMIC_ARB_VERSION
);
823 is_v1
= (hw_ver
< PMIC_ARB_VERSION_V2_MIN
);
825 dev_info(&ctrl
->dev
, "PMIC Arb Version-%d (0x%x)\n", (is_v1
? 1 : 2),
829 pa
->ver_ops
= &pmic_arb_v1
;
837 pa
->ver_ops
= &pmic_arb_v2
;
839 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
841 pa
->rd_base
= devm_ioremap_resource(&ctrl
->dev
, res
);
842 if (IS_ERR(pa
->rd_base
)) {
843 err
= PTR_ERR(pa
->rd_base
);
847 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
849 pa
->wr_base
= devm_ioremap_resource(&ctrl
->dev
, res
);
850 if (IS_ERR(pa
->wr_base
)) {
851 err
= PTR_ERR(pa
->wr_base
);
855 pa
->ppid_to_chan
= devm_kzalloc(&ctrl
->dev
,
856 PPID_TO_CHAN_TABLE_SZ
, GFP_KERNEL
);
857 if (!pa
->ppid_to_chan
) {
862 * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
863 * ppid_to_chan is an in-memory invert of that table.
865 for (chan
= 0; chan
< PMIC_ARB_MAX_CHNL
; ++chan
) {
866 regval
= readl_relaxed(core
+ PMIC_ARB_REG_CHNL(chan
));
870 ppid
= (regval
>> 8) & 0xFFF;
871 pa
->ppid_to_chan
[ppid
] = chan
;
875 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "intr");
876 pa
->intr
= devm_ioremap_resource(&ctrl
->dev
, res
);
877 if (IS_ERR(pa
->intr
)) {
878 err
= PTR_ERR(pa
->intr
);
882 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "cnfg");
883 pa
->cnfg
= devm_ioremap_resource(&ctrl
->dev
, res
);
884 if (IS_ERR(pa
->cnfg
)) {
885 err
= PTR_ERR(pa
->cnfg
);
889 pa
->irq
= platform_get_irq_byname(pdev
, "periph_irq");
895 err
= of_property_read_u32(pdev
->dev
.of_node
, "qcom,channel", &channel
);
897 dev_err(&pdev
->dev
, "channel unspecified.\n");
902 dev_err(&pdev
->dev
, "invalid channel (%u) specified.\n",
907 pa
->channel
= channel
;
909 err
= of_property_read_u32(pdev
->dev
.of_node
, "qcom,ee", &ee
);
911 dev_err(&pdev
->dev
, "EE unspecified.\n");
916 dev_err(&pdev
->dev
, "invalid EE (%u) specified\n", ee
);
923 for (i
= 0; i
< ARRAY_SIZE(pa
->mapping_table
); ++i
)
924 pa
->mapping_table
[i
] = readl_relaxed(
925 pa
->cnfg
+ SPMI_MAPPING_TABLE_REG(i
));
927 /* Initialize max_apid/min_apid to the opposite bounds, during
928 * the irq domain translation, we are sure to update these */
930 pa
->min_apid
= PMIC_ARB_MAX_PERIPHS
- 1;
932 platform_set_drvdata(pdev
, ctrl
);
933 raw_spin_lock_init(&pa
->lock
);
935 ctrl
->cmd
= pmic_arb_cmd
;
936 ctrl
->read_cmd
= pmic_arb_read_cmd
;
937 ctrl
->write_cmd
= pmic_arb_write_cmd
;
939 dev_dbg(&pdev
->dev
, "adding irq domain\n");
940 pa
->domain
= irq_domain_add_tree(pdev
->dev
.of_node
,
941 &pmic_arb_irq_domain_ops
, pa
);
943 dev_err(&pdev
->dev
, "unable to create irq_domain\n");
948 irq_set_chained_handler_and_data(pa
->irq
, pmic_arb_chained_irq
, pa
);
950 err
= spmi_controller_add(ctrl
);
952 goto err_domain_remove
;
957 irq_set_chained_handler_and_data(pa
->irq
, NULL
, NULL
);
958 irq_domain_remove(pa
->domain
);
960 spmi_controller_put(ctrl
);
964 static int spmi_pmic_arb_remove(struct platform_device
*pdev
)
966 struct spmi_controller
*ctrl
= platform_get_drvdata(pdev
);
967 struct spmi_pmic_arb_dev
*pa
= spmi_controller_get_drvdata(ctrl
);
968 spmi_controller_remove(ctrl
);
969 irq_set_chained_handler_and_data(pa
->irq
, NULL
, NULL
);
970 irq_domain_remove(pa
->domain
);
971 spmi_controller_put(ctrl
);
975 static const struct of_device_id spmi_pmic_arb_match_table
[] = {
976 { .compatible
= "qcom,spmi-pmic-arb", },
979 MODULE_DEVICE_TABLE(of
, spmi_pmic_arb_match_table
);
981 static struct platform_driver spmi_pmic_arb_driver
= {
982 .probe
= spmi_pmic_arb_probe
,
983 .remove
= spmi_pmic_arb_remove
,
985 .name
= "spmi_pmic_arb",
986 .of_match_table
= spmi_pmic_arb_match_table
,
989 module_platform_driver(spmi_pmic_arb_driver
);
991 MODULE_LICENSE("GPL v2");
992 MODULE_ALIAS("platform:spmi_pmic_arb");