drivers/staging/agnx/agnx.h

   1 #ifndef AGNX_H_
   2 #define AGNX_H_
   3
   4 #include "xmit.h"
   5
   6 #define PFX                             KBUILD_MODNAME ": "
   7
   8 static inline u32 agnx_read32(void __iomem *mem_region, u32 offset)
   9 {
  10         return ioread32(mem_region + offset);
  11 }
  12
  13 static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val)
  14 {
  15         iowrite32(val, mem_region + offset);
  16 }
  17
  18 /* static const struct ieee80211_rate agnx_rates_80211b[] = { */
  19 /*      { .rate = 10, */
  20 /*        .val = 0xa, */
  21 /*        .flags = IEEE80211_RATE_CCK }, */
  22 /*      { .rate = 20, */
  23 /*        .val = 0x14, */
  24 /*        .hw_value = -0x14, */
  25 /*        .flags = IEEE80211_RATE_CCK_2 }, */
  26 /*      { .rate = 55, */
  27 /*        .val = 0x37, */
  28 /*        .val2 = -0x37, */
  29 /*        .flags = IEEE80211_RATE_CCK_2 }, */
  30 /*      { .rate = 110, */
  31 /*        .val = 0x6e, */
  32 /*        .val2 = -0x6e, */
  33 /*        .flags = IEEE80211_RATE_CCK_2 } */
  34 /* }; */
  35
  36
  37 static const struct ieee80211_rate agnx_rates_80211g[] = {
  38 /*      { .bitrate = 10, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
  39 /*      { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
  40 /*      { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
  41 /*      { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
  42         { .bitrate = 10, .hw_value = 1, },
  43         { .bitrate = 20, .hw_value = 2, },
  44         { .bitrate = 55, .hw_value = 3, },
  45         { .bitrate = 110, .hw_value = 4,},
  46
  47         { .bitrate = 60, .hw_value = 0xB, },
  48         { .bitrate = 90, .hw_value = 0xF, },
  49         { .bitrate = 120, .hw_value = 0xA },
  50         { .bitrate = 180, .hw_value = 0xE, },
  51 //      { .bitrate = 240, .hw_value = 0xd, },
  52         { .bitrate = 360, .hw_value = 0xD, },
  53         { .bitrate = 480, .hw_value = 0x8, },
  54         { .bitrate = 540, .hw_value = 0xC, },
  55 };
  56
  57 static const struct ieee80211_channel agnx_channels[] = {
  58         { .center_freq = 2412, .hw_value = 1, },
  59         { .center_freq = 2417, .hw_value = 2, },
  60         { .center_freq = 2422, .hw_value = 3, },
  61         { .center_freq = 2427, .hw_value = 4, },
  62         { .center_freq = 2432, .hw_value = 5, },
  63         { .center_freq = 2437, .hw_value = 6, },
  64         { .center_freq = 2442, .hw_value = 7, },
  65         { .center_freq = 2447, .hw_value = 8, },
  66         { .center_freq = 2452, .hw_value = 9, },
  67         { .center_freq = 2457, .hw_value = 10, },
  68         { .center_freq = 2462, .hw_value = 11, },
  69         { .center_freq = 2467, .hw_value = 12, },
  70         { .center_freq = 2472, .hw_value = 13, },
  71         { .center_freq = 2484, .hw_value = 14, },
  72 };
  73
  74 #define NUM_DRIVE_MODES 2
  75 /* Agnx operate mode */
  76 enum {
  77         AGNX_MODE_80211A,
  78         AGNX_MODE_80211A_OOB,
  79         AGNX_MODE_80211A_MIMO,
  80         AGNX_MODE_80211B_SHORT,
  81         AGNX_MODE_80211B_LONG,
  82         AGNX_MODE_80211G,
  83         AGNX_MODE_80211G_OOB,
  84         AGNX_MODE_80211G_MIMO,
  85 };
  86
  87 enum {
  88         AGNX_UNINIT,
  89         AGNX_START,
  90         AGNX_STOP,
  91 };
  92
  93 struct agnx_priv {
  94         struct pci_dev *pdev;
  95         struct ieee80211_hw *hw;
  96
  97         spinlock_t lock;
  98         struct mutex mutex;
  99         unsigned int init_status;
 100
 101         void __iomem *ctl;      /* pointer to base ram address */
 102         void __iomem *data;     /* pointer to mem region #2 */
 103
 104         struct agnx_ring rx;
 105         struct agnx_ring txm;
 106         struct agnx_ring txd;
 107
 108         /* Need volatile? */
 109         u32 irq_status;
 110
 111         struct delayed_work periodic_work; /* Periodic tasks like recalibrate*/
 112         struct ieee80211_low_level_stats stats;
 113
 114 //        unsigned int phymode;
 115         int mode;
 116         int channel;
 117         u8 bssid[ETH_ALEN];
 118
 119         u8 mac_addr[ETH_ALEN];
 120         u8 revid;
 121
 122         struct ieee80211_supported_band band;
 123 };
 124
 125
 126 #define AGNX_CHAINS_MAX 6
 127 #define AGNX_PERIODIC_DELAY 60000 /* unit: ms */
 128 #define LOCAL_STAID     0       /* the station entry for the card itself */
 129 #define BSSID_STAID     1       /* the station entry for the bsssid AP */
 130 #define spi_delay()     udelay(40)
 131 #define eeprom_delay()  udelay(40)
 132 #define routing_table_delay()   udelay(50)
 133
 134 /* PDU pool MEM region #2 */
 135 #define AGNX_PDUPOOL            0x40000 /* PDU pool */
 136 #define AGNX_PDUPOOL_SIZE       0x8000  /* PDU pool size*/
 137 #define AGNX_PDU_TX_WQ          0x41000 /* PDU list TX workqueue */
 138 #define AGNX_PDU_FREE           0x41800 /* Free Pool */
 139 #define PDU_SIZE                0x80    /* Free Pool node size */
 140 #define PDU_FREE_CNT            0xd0 /* Free pool node count */
 141
 142
 143 /* RF stuffs */
 144 extern void rf_chips_init(struct agnx_priv *priv);
 145 extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw);
 146 extern void calibrate_oscillator(struct agnx_priv *priv);
 147 extern void do_calibration(struct agnx_priv *priv);
 148 extern void antenna_calibrate(struct agnx_priv *priv);
 149 extern void __antenna_calibrate(struct agnx_priv *priv);
 150 extern void print_offsets(struct agnx_priv *priv);
 151 extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel);
 152
 153
 154 #endif /* AGNX_H_ */