drivers/staging/agnx/pci.c

   1 /**
   2  * Airgo MIMO wireless driver
   3  *
   4  * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
   5
   6  * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
   7  * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
   8
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/delay.h>
  18
  19 #include "agnx.h"
  20 #include "debug.h"
  21 #include "xmit.h"
  22 #include "phy.h"
  23
  24 MODULE_AUTHOR("Li YanBo <dreamfly281@gmail.com>");
  25 MODULE_DESCRIPTION("Airgo MIMO PCI wireless driver");
  26 MODULE_LICENSE("GPL");
  27
  28 static struct pci_device_id agnx_pci_id_tbl[] __devinitdata = {
  29         { PCI_DEVICE(0x17cb, 0x0001) }, /* Beklin F5d8010, Netgear WGM511 etc */
  30         { PCI_DEVICE(0x17cb, 0x0002) }, /* Netgear Wpnt511 */
  31         { 0 }
  32 };
  33
  34 MODULE_DEVICE_TABLE(pci, agnx_pci_id_tbl);
  35
  36
  37 static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
  38 {
  39         void __iomem *ctl = priv->ctl;
  40         u32 reg;
  41
  42         if ( *reason & AGNX_STAT_RX ) {
  43                 /* Mark complete RX */
  44                 reg = ioread32(ctl + AGNX_CIR_RXCTL);
  45                 reg |= 0x4;
  46                 iowrite32(reg, ctl + AGNX_CIR_RXCTL);
  47                 /* disable Rx interrupt */
  48         }
  49         if ( *reason & AGNX_STAT_TX ) {
  50                 reg = ioread32(ctl + AGNX_CIR_TXDCTL);
  51                 if (reg & 0x4) {
  52                         iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
  53                         *reason |= AGNX_STAT_TXD;
  54                 }
  55                 reg = ioread32(ctl + AGNX_CIR_TXMCTL);
  56                 if (reg & 0x4) {
  57                         iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
  58                         *reason |= AGNX_STAT_TXM;
  59                 }
  60         }
  61         if ( *reason & AGNX_STAT_X ) {
  62 /*              reg = ioread32(ctl + AGNX_INT_STAT); */
  63 /*              iowrite32(reg, ctl + AGNX_INT_STAT); */
  64 /*              /\* FIXME reinit interrupt mask *\/ */
  65 /*              reg = 0xc390bf9 & ~IRQ_TX_BEACON; */
  66 /*              reg &= ~IRQ_TX_DISABLE; */
  67 /*              iowrite32(reg, ctl + AGNX_INT_MASK); */
  68 /*              iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); */
  69         }
  70 } /* agnx_interrupt_ack */
  71
  72 static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
  73 {
  74         struct ieee80211_hw *dev = dev_id;
  75         struct agnx_priv *priv = dev->priv;
  76         void __iomem *ctl = priv->ctl;
  77         irqreturn_t ret = IRQ_NONE;
  78         u32 irq_reason;
  79
  80         spin_lock(&priv->lock);
  81
  82 //      printk(KERN_ERR PFX "Get a interrupt %s\n", __func__);
  83
  84         if (priv->init_status != AGNX_START)
  85                 goto out;
  86
  87         /* FiXME  Here has no lock, Is this will lead to race? */
  88         irq_reason = ioread32(ctl + AGNX_CIR_BLKCTL);
  89         if (!(irq_reason & 0x7))
  90                 goto out;
  91
  92         ret = IRQ_HANDLED;
  93         priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
  94
  95 //      printk(PFX "Interrupt reason is 0x%x\n", irq_reason);
  96         /* Make sure the txm and txd flags don't conflict with other unknown
  97            interrupt flag, maybe is not necessary */
  98         irq_reason &= 0xF;
  99
 100         disable_rx_interrupt(priv);
 101         /* TODO Make sure the card finished initialized */
 102         agnx_interrupt_ack(priv, &irq_reason);
 103
 104         if ( irq_reason & AGNX_STAT_RX )
 105                 handle_rx_irq(priv);
 106         if ( irq_reason & AGNX_STAT_TXD )
 107                 handle_txd_irq(priv);
 108         if ( irq_reason & AGNX_STAT_TXM )
 109                 handle_txm_irq(priv);
 110         if ( irq_reason & AGNX_STAT_X )
 111                 handle_other_irq(priv);
 112
 113         enable_rx_interrupt(priv);
 114 out:
 115         spin_unlock(&priv->lock);
 116         return ret;
 117 } /* agnx_interrupt_handler */
 118
 119
 120 /* FIXME */
 121 static int agnx_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 122 {
 123         AGNX_TRACE;
 124         return _agnx_tx(dev->priv, skb);
 125 } /* agnx_tx */
 126
 127
 128 static int agnx_get_mac_address(struct agnx_priv *priv)
 129 {
 130         void __iomem *ctl = priv->ctl;
 131         u32 reg;
 132         AGNX_TRACE;
 133
 134         /* Attention! directly read the MAC or other date from EEPROM will
 135          lead to cardbus(WGM511) lock up when write to PM PLL register */
 136         reg = agnx_read32(ctl, 0x3544);
 137         udelay(40);
 138         reg = agnx_read32(ctl, 0x354c);
 139         udelay(50);
 140         /* Get the mac address */
 141         reg = agnx_read32(ctl, 0x3544);
 142         udelay(40);
 143
 144         /* HACK */
 145         reg = cpu_to_le32(reg);
 146         priv->mac_addr[0] = ((u8 *)&reg)[2];
 147         priv->mac_addr[1] = ((u8 *)&reg)[3];
 148         reg = agnx_read32(ctl, 0x3548);
 149         udelay(50);
 150         *((u32 *)(priv->mac_addr + 2)) = cpu_to_le32(reg);
 151
 152         if (!is_valid_ether_addr(priv->mac_addr)) {
 153                 DECLARE_MAC_BUF(mbuf);
 154                 printk(KERN_WARNING PFX "read mac %s\n", print_mac(mbuf, priv->mac_addr));
 155                 printk(KERN_WARNING PFX "Invalid hwaddr! Using random hwaddr\n");
 156                 random_ether_addr(priv->mac_addr);
 157         }
 158
 159         return 0;
 160 } /* agnx_get_mac_address */
 161
 162 static int agnx_alloc_rings(struct agnx_priv *priv)
 163 {
 164         unsigned int len;
 165         AGNX_TRACE;
 166
 167         /* Allocate RX/TXM/TXD rings info */
 168         priv->rx.size = AGNX_RX_RING_SIZE;
 169         priv->txm.size = AGNX_TXM_RING_SIZE;
 170         priv->txd.size = AGNX_TXD_RING_SIZE;
 171
 172         len = priv->rx.size + priv->txm.size + priv->txd.size;
 173
 174 //      priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL);
 175         priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
 176         if (!priv->rx.info)
 177                 return -ENOMEM;
 178         priv->txm.info = priv->rx.info + priv->rx.size;
 179         priv->txd.info = priv->txm.info + priv->txm.size;
 180
 181         /* Allocate RX/TXM/TXD descriptors */
 182         priv->rx.desc = pci_alloc_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
 183                                              &priv->rx.dma);
 184         if (!priv->rx.desc) {
 185                 kfree(priv->rx.info);
 186                 return -ENOMEM;
 187         }
 188
 189         priv->txm.desc = priv->rx.desc + priv->rx.size;
 190         priv->txm.dma = priv->rx.dma + sizeof(struct agnx_desc) * priv->rx.size;
 191         priv->txd.desc = priv->txm.desc + priv->txm.size;
 192         priv->txd.dma = priv->txm.dma + sizeof(struct agnx_desc) * priv->txm.size;
 193
 194         return 0;
 195 } /* agnx_alloc_rings */
 196
 197 static void rings_free(struct agnx_priv *priv)
 198 {
 199         unsigned int len = priv->rx.size + priv->txm.size + priv->txd.size;
 200         unsigned long flags;
 201         AGNX_TRACE;
 202
 203         spin_lock_irqsave(&priv->lock, flags);
 204         kfree(priv->rx.info);
 205         pci_free_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
 206                             priv->rx.desc, priv->rx.dma);
 207         spin_unlock_irqrestore(&priv->lock, flags);
 208 }
 209
 210 #if 0
 211 static void agnx_periodic_work_handler(struct work_struct *work)
 212 {
 213         struct agnx_priv *priv = container_of(work, struct agnx_priv,
 214                                              periodic_work.work);
 215 //      unsigned long flags;
 216         unsigned long delay;
 217
 218         /* fixme: using mutex?? */
 219 //      spin_lock_irqsave(&priv->lock, flags);
 220
 221         /* TODO Recalibrate*/
 222 //      calibrate_oscillator(priv);
 223 //      antenna_calibrate(priv);
 224 //      agnx_send_packet(priv, 997);
 225         /* FIXME */
 226 /*      if (debug == 3) */
 227 /*                 delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
 228 /*      else */
 229         delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
 230 //              delay = round_jiffies(HZ * 15);
 231
 232         queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
 233
 234 //      spin_unlock_irqrestore(&priv->lock, flags);
 235 }
 236 #endif
 237
 238 static int agnx_start(struct ieee80211_hw *dev)
 239 {
 240         struct agnx_priv *priv = dev->priv;
 241         /* unsigned long delay; */
 242         int err = 0;
 243         AGNX_TRACE;
 244
 245         err = agnx_alloc_rings(priv);
 246         if (err) {
 247                 printk(KERN_ERR PFX "Can't alloc RX/TXM/TXD rings\n");
 248                 goto out;
 249         }
 250         err = request_irq(priv->pdev->irq, &agnx_interrupt_handler,
 251                           IRQF_SHARED, "agnx_pci", dev);
 252         if (err) {
 253                 printk(KERN_ERR PFX "Failed to register IRQ handler\n");
 254                 rings_free(priv);
 255                 goto out;
 256         }
 257
 258 //      mdelay(500);
 259
 260         might_sleep();
 261         agnx_hw_init(priv);
 262
 263 //      mdelay(500);
 264         might_sleep();
 265
 266         priv->init_status = AGNX_START;
 267 /*         INIT_DELAYED_WORK(&priv->periodic_work, agnx_periodic_work_handler); */
 268 /*      delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
 269 /*         queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay); */
 270 out:
 271         return err;
 272 } /* agnx_start */
 273
 274 static void agnx_stop(struct ieee80211_hw *dev)
 275 {
 276         struct agnx_priv *priv = dev->priv;
 277         AGNX_TRACE;
 278
 279         priv->init_status = AGNX_STOP;
 280         /* make sure hardware will not generate irq */
 281         agnx_hw_reset(priv);
 282         free_irq(priv->pdev->irq, dev);
 283         flush_workqueue(priv->hw->workqueue);
 284 //      cancel_delayed_work_sync(&priv->periodic_work);
 285         unfill_rings(priv);
 286         rings_free(priv);
 287 }
 288
 289 static int agnx_config(struct ieee80211_hw *dev,
 290                        struct ieee80211_conf *conf)
 291 {
 292         struct agnx_priv *priv = dev->priv;
 293         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
 294         AGNX_TRACE;
 295
 296         spin_lock(&priv->lock);
 297         /* FIXME need priv lock? */
 298         if (channel != priv->channel) {
 299                 priv->channel = channel;
 300                 agnx_set_channel(priv, priv->channel);
 301         }
 302
 303         spin_unlock(&priv->lock);
 304         return 0;
 305 }
 306
 307 static int agnx_config_interface(struct ieee80211_hw *dev,
 308                                  struct ieee80211_vif *vif,
 309                                  struct ieee80211_if_conf *conf)
 310 {
 311         struct agnx_priv *priv = dev->priv;
 312         void __iomem *ctl = priv->ctl;
 313         AGNX_TRACE;
 314
 315         spin_lock(&priv->lock);
 316
 317         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
 318 //              u32 reghi, reglo;
 319                 agnx_set_bssid(priv, conf->bssid);
 320                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
 321                 hash_write(priv, conf->bssid, BSSID_STAID);
 322                 sta_init(priv, BSSID_STAID);
 323                 /* FIXME needed? */
 324                 sta_power_init(priv, BSSID_STAID);
 325                 agnx_write32(ctl, AGNX_BM_MTSM, 0xff & ~0x1);
 326         }
 327         spin_unlock(&priv->lock);
 328         return 0;
 329 } /* agnx_config_interface */
 330
 331
 332 static void agnx_configure_filter(struct ieee80211_hw *dev,
 333                                   unsigned int changed_flags,
 334                                   unsigned int *total_flags,
 335                                   int mc_count, struct dev_mc_list *mclist)
 336 {
 337         unsigned int new_flags = 0;
 338
 339         *total_flags = new_flags;
 340         /* TODO */
 341 }
 342
 343 static int agnx_add_interface(struct ieee80211_hw *dev,
 344                               struct ieee80211_if_init_conf *conf)
 345 {
 346         struct agnx_priv *priv = dev->priv;
 347         AGNX_TRACE;
 348
 349         spin_lock(&priv->lock);
 350         /* FIXME */
 351         if (priv->mode != NL80211_IFTYPE_MONITOR)
 352                 return -EOPNOTSUPP;
 353
 354         switch (conf->type) {
 355         case NL80211_IFTYPE_STATION:
 356                 priv->mode = conf->type;
 357                 break;
 358         default:
 359                 return -EOPNOTSUPP;
 360         }
 361
 362         spin_unlock(&priv->lock);
 363
 364         return 0;
 365 }
 366
 367 static void agnx_remove_interface(struct ieee80211_hw *dev,
 368                                   struct ieee80211_if_init_conf *conf)
 369 {
 370         struct agnx_priv *priv = dev->priv;
 371         AGNX_TRACE;
 372
 373         /* TODO */
 374         priv->mode = NL80211_IFTYPE_MONITOR;
 375 }
 376
 377 static int agnx_get_stats(struct ieee80211_hw *dev,
 378                           struct ieee80211_low_level_stats *stats)
 379 {
 380         struct agnx_priv *priv = dev->priv;
 381         AGNX_TRACE;
 382         spin_lock(&priv->lock);
 383         /* TODO !! */
 384         memcpy(stats, &priv->stats, sizeof(*stats));
 385         spin_unlock(&priv->lock);
 386
 387         return 0;
 388 }
 389
 390 static u64 agnx_get_tsft(struct ieee80211_hw *dev)
 391 {
 392         void __iomem *ctl = ((struct agnx_priv *)dev->priv)->ctl;
 393         u32 tsftl;
 394         u64 tsft;
 395         AGNX_TRACE;
 396
 397         /* FIXME */
 398         tsftl = ioread32(ctl + AGNX_TXM_TIMESTAMPLO);
 399         tsft = ioread32(ctl + AGNX_TXM_TIMESTAMPHI);
 400         tsft <<= 32;
 401         tsft |= tsftl;
 402
 403         return tsft;
 404 }
 405
 406 static int agnx_get_tx_stats(struct ieee80211_hw *dev,
 407                              struct ieee80211_tx_queue_stats *stats)
 408 {
 409         struct agnx_priv *priv = dev->priv;
 410         AGNX_TRACE;
 411
 412         /* FIXME now we just using txd queue, but should using txm queue too */
 413         stats[0].len = (priv->txd.idx - priv->txd.idx_sent) / 2;
 414         stats[0].limit = priv->txd.size - 2;
 415         stats[0].count = priv->txd.idx / 2;
 416
 417         return 0;
 418 }
 419
 420 static struct ieee80211_ops agnx_ops = {
 421         .tx                     = agnx_tx,
 422         .start                  = agnx_start,
 423         .stop                   = agnx_stop,
 424         .add_interface          = agnx_add_interface,
 425         .remove_interface       = agnx_remove_interface,
 426         .config                 = agnx_config,
 427         .config_interface       = agnx_config_interface,
 428         .configure_filter       = agnx_configure_filter,
 429         .get_stats              = agnx_get_stats,
 430         .get_tx_stats           = agnx_get_tx_stats,
 431         .get_tsf                = agnx_get_tsft
 432 };
 433
 434 static void __devexit agnx_pci_remove(struct pci_dev *pdev)
 435 {
 436         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 437         struct agnx_priv *priv = dev->priv;
 438         AGNX_TRACE;
 439
 440         if (!dev)
 441                 return;
 442         ieee80211_unregister_hw(dev);
 443         pci_iounmap(pdev, priv->ctl);
 444         pci_iounmap(pdev, priv->data);
 445         pci_release_regions(pdev);
 446         pci_disable_device(pdev);
 447
 448         ieee80211_free_hw(dev);
 449 }
 450
 451 static int __devinit agnx_pci_probe(struct pci_dev *pdev,
 452                                     const struct pci_device_id *id)
 453 {
 454         struct ieee80211_hw *dev;
 455         struct agnx_priv *priv;
 456         u32 mem_addr0, mem_len0;
 457         u32 mem_addr1, mem_len1;
 458         int err;
 459         DECLARE_MAC_BUF(mac);
 460
 461         err = pci_enable_device(pdev);
 462         if (err) {
 463                 printk(KERN_ERR PFX "Can't enable new PCI device\n");
 464                 return err;
 465         }
 466
 467         /* get pci resource */
 468         mem_addr0 = pci_resource_start(pdev, 0);
 469         mem_len0 = pci_resource_len(pdev, 0);
 470         mem_addr1 = pci_resource_start(pdev, 1);
 471         mem_len1 = pci_resource_len(pdev, 1);
 472         printk(KERN_DEBUG PFX "Memaddr0 is %x, length is %x\n", mem_addr0, mem_len0);
 473         printk(KERN_DEBUG PFX "Memaddr1 is %x, length is %x\n", mem_addr1, mem_len1);
 474
 475         err = pci_request_regions(pdev, "agnx-pci");
 476         if (err) {
 477                 printk(KERN_ERR PFX "Can't obtain PCI resource\n");
 478                 return err;
 479         }
 480
 481         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
 482             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
 483                 printk(KERN_ERR PFX "No suitable DMA available\n");
 484                 goto err_free_reg;
 485         }
 486
 487         pci_set_master(pdev);
 488         printk(KERN_DEBUG PFX "pdev->irq is %d\n", pdev->irq);
 489
 490         dev = ieee80211_alloc_hw(sizeof(*priv), &agnx_ops);
 491         if (!dev) {
 492                 printk(KERN_ERR PFX "ieee80211 alloc failed\n");
 493                 err = -ENOMEM;
 494                 goto err_free_reg;
 495         }
 496         /* init priv  */
 497         priv = dev->priv;
 498         memset(priv, 0, sizeof(*priv));
 499         priv->mode = NL80211_IFTYPE_MONITOR;
 500         priv->pdev = pdev;
 501         priv->hw = dev;
 502         spin_lock_init(&priv->lock);
 503         priv->init_status = AGNX_UNINIT;
 504
 505         /* Map mem #1 and #2 */
 506         priv->ctl = pci_iomap(pdev, 0, mem_len0);
 507 //      printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl);
 508         if (!priv->ctl) {
 509                 printk(KERN_ERR PFX "Can't map device memory\n");
 510                 goto err_free_dev;
 511         }
 512         priv->data = pci_iomap(pdev, 1, mem_len1);
 513         printk(KERN_DEBUG PFX "MEM2 mapped address is 0x%p\n", priv->data);
 514         if (!priv->data) {
 515                 printk(KERN_ERR PFX "Can't map device memory\n");
 516                 goto err_iounmap2;
 517         }
 518
 519         pci_read_config_byte(pdev, PCI_REVISION_ID, &priv->revid);
 520
 521         priv->band.channels   = (struct ieee80211_channel *)agnx_channels;
 522         priv->band.n_channels = ARRAY_SIZE(agnx_channels);
 523         priv->band.bitrates   = (struct ieee80211_rate *)agnx_rates_80211g;
 524         priv->band.n_bitrates = ARRAY_SIZE(agnx_rates_80211g);
 525
 526         /* Init ieee802.11 dev  */
 527         SET_IEEE80211_DEV(dev, &pdev->dev);
 528         pci_set_drvdata(pdev, dev);
 529         dev->extra_tx_headroom = sizeof(struct agnx_hdr);
 530
 531         /* FIXME It only include FCS in promious mode but not manage mode */
 532 /*      dev->flags =  IEEE80211_HW_RX_INCLUDES_FCS; */
 533         dev->channel_change_time = 5000;
 534         dev->max_signal = 100;
 535         /* FIXME */
 536         dev->queues = 1;
 537
 538         agnx_get_mac_address(priv);
 539
 540         SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
 541
 542 /*      /\* FIXME *\/ */
 543 /*      for (i = 1; i < NUM_DRIVE_MODES; i++) { */
 544 /*              err = ieee80211_register_hwmode(dev, &priv->modes[i]); */
 545 /*              if (err) { */
 546 /*                      printk(KERN_ERR PFX "Can't register hwmode\n"); */
 547 /*                      goto  err_iounmap; */
 548 /*              } */
 549 /*      } */
 550
 551         priv->channel = 1;
 552         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
 553
 554         err = ieee80211_register_hw(dev);
 555         if (err) {
 556                 printk(KERN_ERR PFX "Can't register hardware\n");
 557                 goto err_iounmap;
 558         }
 559
 560         agnx_hw_reset(priv);
 561
 562
 563         printk(PFX "%s: hwaddr %s, Rev 0x%02x\n", wiphy_name(dev->wiphy),
 564                print_mac(mac, dev->wiphy->perm_addr), priv->revid);
 565         return 0;
 566
 567  err_iounmap:
 568         pci_iounmap(pdev, priv->data);
 569
 570  err_iounmap2:
 571         pci_iounmap(pdev, priv->ctl);
 572
 573  err_free_dev:
 574         pci_set_drvdata(pdev, NULL);
 575         ieee80211_free_hw(dev);
 576
 577  err_free_reg:
 578         pci_release_regions(pdev);
 579
 580         pci_disable_device(pdev);
 581         return err;
 582 } /* agnx_pci_probe*/
 583
 584 #ifdef CONFIG_PM
 585
 586 static int agnx_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 587 {
 588         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 589         AGNX_TRACE;
 590
 591         ieee80211_stop_queues(dev);
 592         agnx_stop(dev);
 593
 594         pci_save_state(pdev);
 595         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 596         return 0;
 597 }
 598
 599 static int agnx_pci_resume(struct pci_dev *pdev)
 600 {
 601         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 602         AGNX_TRACE;
 603
 604         pci_set_power_state(pdev, PCI_D0);
 605         pci_restore_state(pdev);
 606
 607         agnx_start(dev);
 608         ieee80211_wake_queues(dev);
 609
 610         return 0;
 611 }
 612
 613 #else
 614
 615 #define agnx_pci_suspend NULL
 616 #define agnx_pci_resume NULL
 617
 618 #endif /* CONFIG_PM */
 619
 620
 621 static struct pci_driver agnx_pci_driver = {
 622         .name           = "agnx-pci",
 623         .id_table       = agnx_pci_id_tbl,
 624         .probe          = agnx_pci_probe,
 625         .remove         = __devexit_p(agnx_pci_remove),
 626         .suspend        = agnx_pci_suspend,
 627         .resume         = agnx_pci_resume,
 628 };
 629
 630 static int __init agnx_pci_init(void)
 631 {
 632         AGNX_TRACE;
 633         return pci_register_driver(&agnx_pci_driver);
 634 }
 635
 636 static void __exit agnx_pci_exit(void)
 637 {
 638         AGNX_TRACE;
 639         pci_unregister_driver(&agnx_pci_driver);
 640 }
 641
 642
 643 module_init(agnx_pci_init);
 644 module_exit(agnx_pci_exit);