2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 * File contents: support functions for PCI/PCIe
19 #include <linux/delay.h>
20 #include <linux/pci.h>
23 #include <chipcommon.h>
24 #include <brcmu_utils.h>
25 #include <brcm_hw_ids.h>
35 /* slow clock source mask */
36 #define SCC_SS_MASK 0x00000007
37 /* source of slow clock is LPO */
38 #define SCC_SS_LPO 0x00000000
39 /* source of slow clock is crystal */
40 #define SCC_SS_XTAL 0x00000001
41 /* source of slow clock is PCI */
42 #define SCC_SS_PCI 0x00000002
43 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
44 #define SCC_LF 0x00000200
45 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
46 #define SCC_LP 0x00000400
47 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
48 #define SCC_FS 0x00000800
49 /* IgnorePllOffReq, 1/0:
50 * power logic ignores/honors PLL clock disable requests from core
52 #define SCC_IP 0x00001000
53 /* XtalControlEn, 1/0:
54 * power logic does/doesn't disable crystal when appropriate
56 #define SCC_XC 0x00002000
57 /* XtalPU (RO), 1/0: crystal running/disabled */
58 #define SCC_XP 0x00004000
59 /* ClockDivider (SlowClk = 1/(4+divisor)) */
60 #define SCC_CD_MASK 0xffff0000
61 #define SCC_CD_SHIFT 16
64 /* ILPen: Enable Idle Low Power */
65 #define SYCC_IE 0x00000001
66 /* ALPen: Enable Active Low Power */
67 #define SYCC_AE 0x00000002
69 #define SYCC_FP 0x00000004
70 /* Force ALP (or HT if ALPen is not set */
71 #define SYCC_AR 0x00000008
73 #define SYCC_HR 0x00000010
74 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
75 #define SYCC_CD_MASK 0xffff0000
76 #define SYCC_CD_SHIFT 16
78 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
79 /* OTP is powered up, use def. CIS, no SPROM */
80 #define CST4329_DEFCIS_SEL 0
81 /* OTP is powered up, SPROM is present */
82 #define CST4329_SPROM_SEL 1
83 /* OTP is powered up, no SPROM */
84 #define CST4329_OTP_SEL 2
85 /* OTP is powered down, SPROM is present */
86 #define CST4329_OTP_PWRDN 3
88 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
89 #define CST4329_SPI_SDIO_MODE_SHIFT 2
91 /* 43224 chip-specific ChipControl register bits */
92 #define CCTRL43224_GPIO_TOGGLE 0x8000
93 /* 12 mA drive strength */
94 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
95 /* 12 mA drive strength for later 43224s */
96 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
98 /* 43236 Chip specific ChipStatus register bits */
99 #define CST43236_SFLASH_MASK 0x00000040
100 #define CST43236_OTP_MASK 0x00000080
101 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
102 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
103 #define CST43236_BOOT_MASK 0x00001800
104 #define CST43236_BOOT_SHIFT 11
105 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
106 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
107 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
108 #define CST43236_BOOT_FROM_INVALID 3
110 /* 4331 chip-specific ChipControl register bits */
112 #define CCTRL4331_BT_COEXIST (1<<0)
113 /* 0 SECI is disabled (JTAG functional) */
114 #define CCTRL4331_SECI (1<<1)
116 #define CCTRL4331_EXT_LNA (1<<2)
117 /* sprom/gpio13-15 mux */
118 #define CCTRL4331_SPROM_GPIO13_15 (1<<3)
119 /* 0 ext pa disable, 1 ext pa enabled */
120 #define CCTRL4331_EXTPA_EN (1<<4)
121 /* set drive out GPIO_CLK on sprom_cs pin */
122 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
123 /* use sprom_cs pin as PCIE mdio interface */
124 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
125 /* aband extpa will be at gpio2/5 and sprom_dout */
126 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
127 /* override core control on pipe_AuxClkEnable */
128 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
129 /* override core control on pipe_AuxPowerDown */
130 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
131 /* pcie_auxclkenable */
132 #define CCTRL4331_PCIE_AUXCLKEN (1<<10)
133 /* pcie_pipe_pllpowerdown */
134 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
135 /* enable bt_shd0 at gpio4 */
136 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
137 /* enable bt_shd1 at gpio5 */
138 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)
140 /* 4331 Chip specific ChipStatus register bits */
141 /* crystal frequency 20/40Mhz */
142 #define CST4331_XTAL_FREQ 0x00000001
143 #define CST4331_SPROM_PRESENT 0x00000002
144 #define CST4331_OTP_PRESENT 0x00000004
145 #define CST4331_LDO_RF 0x00000008
146 #define CST4331_LDO_PAR 0x00000010
148 /* 4319 chip-specific ChipStatus register bits */
149 #define CST4319_SPI_CPULESSUSB 0x00000001
150 #define CST4319_SPI_CLK_POL 0x00000002
151 #define CST4319_SPI_CLK_PH 0x00000008
152 /* gpio [7:6], SDIO CIS selection */
153 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
154 #define CST4319_SPROM_OTP_SEL_SHIFT 6
155 /* use default CIS, OTP is powered up */
156 #define CST4319_DEFCIS_SEL 0x00000000
157 /* use SPROM, OTP is powered up */
158 #define CST4319_SPROM_SEL 0x00000040
159 /* use OTP, OTP is powered up */
160 #define CST4319_OTP_SEL 0x00000080
161 /* use SPROM, OTP is powered down */
162 #define CST4319_OTP_PWRDN 0x000000c0
163 /* gpio [8], sdio/usb mode */
164 #define CST4319_SDIO_USB_MODE 0x00000100
165 #define CST4319_REMAP_SEL_MASK 0x00000600
166 #define CST4319_ILPDIV_EN 0x00000800
167 #define CST4319_XTAL_PD_POL 0x00001000
168 #define CST4319_LPO_SEL 0x00002000
169 #define CST4319_RES_INIT_MODE 0x0000c000
170 /* PALDO is configured with external PNP */
171 #define CST4319_PALDO_EXTPNP 0x00010000
172 #define CST4319_CBUCK_MODE_MASK 0x00060000
173 #define CST4319_CBUCK_MODE_BURST 0x00020000
174 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
175 #define CST4319_RCAL_VALID 0x01000000
176 #define CST4319_RCAL_VALUE_MASK 0x3e000000
177 #define CST4319_RCAL_VALUE_SHIFT 25
179 /* 4336 chip-specific ChipStatus register bits */
180 #define CST4336_SPI_MODE_MASK 0x00000001
181 #define CST4336_SPROM_PRESENT 0x00000002
182 #define CST4336_OTP_PRESENT 0x00000004
183 #define CST4336_ARMREMAP_0 0x00000008
184 #define CST4336_ILPDIV_EN_MASK 0x00000010
185 #define CST4336_ILPDIV_EN_SHIFT 4
186 #define CST4336_XTAL_PD_POL_MASK 0x00000020
187 #define CST4336_XTAL_PD_POL_SHIFT 5
188 #define CST4336_LPO_SEL_MASK 0x00000040
189 #define CST4336_LPO_SEL_SHIFT 6
190 #define CST4336_RES_INIT_MODE_MASK 0x00000180
191 #define CST4336_RES_INIT_MODE_SHIFT 7
192 #define CST4336_CBUCK_MODE_MASK 0x00000600
193 #define CST4336_CBUCK_MODE_SHIFT 9
195 /* 4313 chip-specific ChipStatus register bits */
196 #define CST4313_SPROM_PRESENT 1
197 #define CST4313_OTP_PRESENT 2
198 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
199 #define CST4313_SPROM_OTP_SEL_SHIFT 0
201 /* 4313 Chip specific ChipControl register bits */
202 /* 12 mA drive strengh for later 4313 */
203 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007
205 #define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
206 (sih->chiprev == 0) && \
207 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
209 /* Manufacturer Ids */
210 #define MFGID_ARM 0x43b
211 #define MFGID_BRCM 0x4bf
212 #define MFGID_MIPS 0x4a7
214 /* Enumeration ROM registers */
215 #define ER_EROMENTRY 0x000
216 #define ER_REMAPCONTROL 0xe00
217 #define ER_REMAPSELECT 0xe04
218 #define ER_MASTERSELECT 0xe10
219 #define ER_ITCR 0xf00
220 #define ER_ITIP 0xf04
230 #define ER_BAD 0xffffffff
232 /* EROM CompIdentA */
233 #define CIA_MFG_MASK 0xfff00000
234 #define CIA_MFG_SHIFT 20
235 #define CIA_CID_MASK 0x000fff00
236 #define CIA_CID_SHIFT 8
237 #define CIA_CCL_MASK 0x000000f0
238 #define CIA_CCL_SHIFT 4
240 /* EROM CompIdentB */
241 #define CIB_REV_MASK 0xff000000
242 #define CIB_REV_SHIFT 24
243 #define CIB_NSW_MASK 0x00f80000
244 #define CIB_NSW_SHIFT 19
245 #define CIB_NMW_MASK 0x0007c000
246 #define CIB_NMW_SHIFT 14
247 #define CIB_NSP_MASK 0x00003e00
248 #define CIB_NSP_SHIFT 9
249 #define CIB_NMP_MASK 0x000001f0
250 #define CIB_NMP_SHIFT 4
253 #define AD_ADDR_MASK 0xfffff000
254 #define AD_SP_MASK 0x00000f00
255 #define AD_SP_SHIFT 8
256 #define AD_ST_MASK 0x000000c0
257 #define AD_ST_SHIFT 6
258 #define AD_ST_SLAVE 0x00000000
259 #define AD_ST_BRIDGE 0x00000040
260 #define AD_ST_SWRAP 0x00000080
261 #define AD_ST_MWRAP 0x000000c0
262 #define AD_SZ_MASK 0x00000030
263 #define AD_SZ_SHIFT 4
264 #define AD_SZ_4K 0x00000000
265 #define AD_SZ_8K 0x00000010
266 #define AD_SZ_16K 0x00000020
267 #define AD_SZ_SZD 0x00000030
268 #define AD_AG32 0x00000008
269 #define AD_ADDR_ALIGN 0x00000fff
270 #define AD_SZ_BASE 0x00001000 /* 4KB */
273 #define SD_SZ_MASK 0xfffff000
274 #define SD_SG32 0x00000008
275 #define SD_SZ_ALIGN 0x00000fff
277 /* PCI config space bit 4 for 4306c0 slow clock source */
278 #define PCI_CFG_GPIO_SCS 0x10
279 /* PCI config space GPIO 14 for Xtal power-up */
280 #define PCI_CFG_GPIO_XTAL 0x40
281 /* PCI config space GPIO 15 for PLL power-down */
282 #define PCI_CFG_GPIO_PLL 0x80
284 /* power control defines */
285 #define PLL_DELAY 150 /* us pll on delay */
286 #define FREF_DELAY 200 /* us fref change delay */
287 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
293 u32 oobselina30
; /* 0x000 */
294 u32 oobselina74
; /* 0x004 */
296 u32 oobselinb30
; /* 0x020 */
297 u32 oobselinb74
; /* 0x024 */
299 u32 oobselinc30
; /* 0x040 */
300 u32 oobselinc74
; /* 0x044 */
302 u32 oobselind30
; /* 0x060 */
303 u32 oobselind74
; /* 0x064 */
305 u32 oobselouta30
; /* 0x100 */
306 u32 oobselouta74
; /* 0x104 */
308 u32 oobseloutb30
; /* 0x120 */
309 u32 oobseloutb74
; /* 0x124 */
311 u32 oobseloutc30
; /* 0x140 */
312 u32 oobseloutc74
; /* 0x144 */
314 u32 oobseloutd30
; /* 0x160 */
315 u32 oobseloutd74
; /* 0x164 */
317 u32 oobsynca
; /* 0x200 */
318 u32 oobseloutaen
; /* 0x204 */
320 u32 oobsyncb
; /* 0x220 */
321 u32 oobseloutben
; /* 0x224 */
323 u32 oobsyncc
; /* 0x240 */
324 u32 oobseloutcen
; /* 0x244 */
326 u32 oobsyncd
; /* 0x260 */
327 u32 oobseloutden
; /* 0x264 */
329 u32 oobaextwidth
; /* 0x300 */
330 u32 oobainwidth
; /* 0x304 */
331 u32 oobaoutwidth
; /* 0x308 */
333 u32 oobbextwidth
; /* 0x320 */
334 u32 oobbinwidth
; /* 0x324 */
335 u32 oobboutwidth
; /* 0x328 */
337 u32 oobcextwidth
; /* 0x340 */
338 u32 oobcinwidth
; /* 0x344 */
339 u32 oobcoutwidth
; /* 0x348 */
341 u32 oobdextwidth
; /* 0x360 */
342 u32 oobdinwidth
; /* 0x364 */
343 u32 oobdoutwidth
; /* 0x368 */
345 u32 ioctrlset
; /* 0x400 */
346 u32 ioctrlclear
; /* 0x404 */
347 u32 ioctrl
; /* 0x408 */
349 u32 iostatus
; /* 0x500 */
351 u32 ioctrlwidth
; /* 0x700 */
352 u32 iostatuswidth
; /* 0x704 */
354 u32 resetctrl
; /* 0x800 */
355 u32 resetstatus
; /* 0x804 */
356 u32 resetreadid
; /* 0x808 */
357 u32 resetwriteid
; /* 0x80c */
359 u32 errlogctrl
; /* 0x900 */
360 u32 errlogdone
; /* 0x904 */
361 u32 errlogstatus
; /* 0x908 */
362 u32 errlogaddrlo
; /* 0x90c */
363 u32 errlogaddrhi
; /* 0x910 */
364 u32 errlogid
; /* 0x914 */
365 u32 errloguser
; /* 0x918 */
366 u32 errlogflags
; /* 0x91c */
368 u32 intstatus
; /* 0xa00 */
370 u32 config
; /* 0xe00 */
372 u32 itcr
; /* 0xf00 */
374 u32 itipooba
; /* 0xf10 */
375 u32 itipoobb
; /* 0xf14 */
376 u32 itipoobc
; /* 0xf18 */
377 u32 itipoobd
; /* 0xf1c */
379 u32 itipoobaout
; /* 0xf30 */
380 u32 itipoobbout
; /* 0xf34 */
381 u32 itipoobcout
; /* 0xf38 */
382 u32 itipoobdout
; /* 0xf3c */
384 u32 itopooba
; /* 0xf50 */
385 u32 itopoobb
; /* 0xf54 */
386 u32 itopoobc
; /* 0xf58 */
387 u32 itopoobd
; /* 0xf5c */
389 u32 itopoobain
; /* 0xf70 */
390 u32 itopoobbin
; /* 0xf74 */
391 u32 itopoobcin
; /* 0xf78 */
392 u32 itopoobdin
; /* 0xf7c */
394 u32 itopreset
; /* 0xf90 */
396 u32 peripherialid4
; /* 0xfd0 */
397 u32 peripherialid5
; /* 0xfd4 */
398 u32 peripherialid6
; /* 0xfd8 */
399 u32 peripherialid7
; /* 0xfdc */
400 u32 peripherialid0
; /* 0xfe0 */
401 u32 peripherialid1
; /* 0xfe4 */
402 u32 peripherialid2
; /* 0xfe8 */
403 u32 peripherialid3
; /* 0xfec */
404 u32 componentid0
; /* 0xff0 */
405 u32 componentid1
; /* 0xff4 */
406 u32 componentid2
; /* 0xff8 */
407 u32 componentid3
; /* 0xffc */
410 /* global kernel resource */
411 static struct si_info ksii
;
416 get_erom_ent(struct si_pub
*sih
, u32
**eromptr
, u32 mask
, u32 match
)
419 uint inv
= 0, nom
= 0;
422 ent
= R_REG(*eromptr
);
428 if ((ent
& ER_VALID
) == 0) {
433 if (ent
== (ER_END
| ER_VALID
))
436 if ((ent
& mask
) == match
)
442 SI_VMSG(("%s: Returning ent 0x%08x\n", __func__
, ent
));
444 SI_VMSG((" after %d invalid and %d non-matching entries\n",
451 get_asd(struct si_pub
*sih
, u32
**eromptr
, uint sp
, uint ad
, uint st
,
452 u32
*addrl
, u32
*addrh
, u32
*sizel
, u32
*sizeh
)
456 asd
= get_erom_ent(sih
, eromptr
, ER_VALID
, ER_VALID
);
457 if (((asd
& ER_TAG1
) != ER_ADD
) ||
458 (((asd
& AD_SP_MASK
) >> AD_SP_SHIFT
) != sp
) ||
459 ((asd
& AD_ST_MASK
) != st
)) {
460 /* This is not what we want, "push" it back */
464 *addrl
= asd
& AD_ADDR_MASK
;
466 *addrh
= get_erom_ent(sih
, eromptr
, 0, 0);
470 sz
= asd
& AD_SZ_MASK
;
471 if (sz
== AD_SZ_SZD
) {
472 szd
= get_erom_ent(sih
, eromptr
, 0, 0);
473 *sizel
= szd
& SD_SZ_MASK
;
475 *sizeh
= get_erom_ent(sih
, eromptr
, 0, 0);
477 *sizel
= AD_SZ_BASE
<< (sz
>> AD_SZ_SHIFT
);
479 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
480 sp
, ad
, st
, *sizeh
, *sizel
, *addrh
, *addrl
));
485 static void ai_hwfixup(struct si_info
*sii
)
489 /* parse the enumeration rom to identify all cores */
490 void ai_scan(struct si_pub
*sih
, struct chipcregs
*cc
)
492 struct si_info
*sii
= SI_INFO(sih
);
493 u32 erombase
, *eromptr
, *eromlim
;
496 erombase
= R_REG(&cc
->eromptr
);
498 /* Set wrappers address */
499 sii
->curwrap
= (void *)((unsigned long)cc
+ SI_CORE_SIZE
);
501 /* Now point the window at the erom */
502 pci_write_config_dword(sii
->pbus
, PCI_BAR0_WIN
, erombase
);
504 eromlim
= eromptr
+ (ER_REMAPCONTROL
/ sizeof(u32
));
506 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, "
507 "eromlim = 0x%p\n", regs
, erombase
, eromptr
, eromlim
));
508 while (eromptr
< eromlim
) {
509 u32 cia
, cib
, cid
, mfg
, crev
, nmw
, nsw
, nmp
, nsp
;
510 u32 mpd
, asd
, addrl
, addrh
, sizel
, sizeh
;
517 /* Grok a component */
518 cia
= get_erom_ent(sih
, &eromptr
, ER_TAG
, ER_CI
);
519 if (cia
== (ER_END
| ER_VALID
)) {
520 SI_VMSG(("Found END of erom after %d cores\n",
526 cib
= get_erom_ent(sih
, &eromptr
, 0, 0);
528 if ((cib
& ER_TAG
) != ER_CI
) {
529 SI_ERROR(("CIA not followed by CIB\n"));
533 cid
= (cia
& CIA_CID_MASK
) >> CIA_CID_SHIFT
;
534 mfg
= (cia
& CIA_MFG_MASK
) >> CIA_MFG_SHIFT
;
535 crev
= (cib
& CIB_REV_MASK
) >> CIB_REV_SHIFT
;
536 nmw
= (cib
& CIB_NMW_MASK
) >> CIB_NMW_SHIFT
;
537 nsw
= (cib
& CIB_NSW_MASK
) >> CIB_NSW_SHIFT
;
538 nmp
= (cib
& CIB_NMP_MASK
) >> CIB_NMP_SHIFT
;
539 nsp
= (cib
& CIB_NSP_MASK
) >> CIB_NSP_SHIFT
;
541 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr "
542 "0x%p, with nmw = %d, nsw = %d, nmp = %d & nsp = %d\n",
543 mfg
, cid
, crev
, base
, nmw
, nsw
, nmp
, nsp
));
545 if (((mfg
== MFGID_ARM
) && (cid
== DEF_AI_COMP
)) || (nsp
== 0))
547 if ((nmw
+ nsw
== 0)) {
548 /* A component which is not a core */
549 if (cid
== OOB_ROUTER_CORE_ID
) {
550 asd
= get_asd(sih
, &eromptr
, 0, 0, AD_ST_SLAVE
,
551 &addrl
, &addrh
, &sizel
, &sizeh
);
553 sii
->oob_router
= addrl
;
559 /* sii->eromptr[idx] = base; */
562 sii
->coreid
[idx
] = cid
;
564 for (i
= 0; i
< nmp
; i
++) {
565 mpd
= get_erom_ent(sih
, &eromptr
, ER_VALID
, ER_VALID
);
566 if ((mpd
& ER_TAG
) != ER_MP
) {
567 SI_ERROR(("Not enough MP entries for "
568 "component 0x%x\n", cid
));
571 SI_VMSG((" Master port %d, mp: %d id: %d\n", i
,
572 (mpd
& MPD_MP_MASK
) >> MPD_MP_SHIFT
,
573 (mpd
& MPD_MUI_MASK
) >> MPD_MUI_SHIFT
));
576 /* First Slave Address Descriptor should be port 0:
577 * the main register space for the core
580 get_asd(sih
, &eromptr
, 0, 0, AD_ST_SLAVE
, &addrl
, &addrh
,
583 /* Try again to see if it is a bridge */
585 get_asd(sih
, &eromptr
, 0, 0, AD_ST_BRIDGE
, &addrl
,
586 &addrh
, &sizel
, &sizeh
);
589 else if ((addrh
!= 0) || (sizeh
!= 0)
590 || (sizel
!= SI_CORE_SIZE
)) {
591 SI_ERROR(("First Slave ASD for core 0x%04x "
592 "malformed (0x%08x)\n", cid
, asd
));
596 sii
->coresba
[idx
] = addrl
;
597 sii
->coresba_size
[idx
] = sizel
;
598 /* Get any more ASDs in port 0 */
602 get_asd(sih
, &eromptr
, 0, j
, AD_ST_SLAVE
, &addrl
,
603 &addrh
, &sizel
, &sizeh
);
604 if ((asd
!= 0) && (j
== 1) && (sizel
== SI_CORE_SIZE
)) {
605 sii
->coresba2
[idx
] = addrl
;
606 sii
->coresba2_size
[idx
] = sizel
;
611 /* Go through the ASDs for other slave ports */
612 for (i
= 1; i
< nsp
; i
++) {
616 get_asd(sih
, &eromptr
, i
, j
++, AD_ST_SLAVE
,
617 &addrl
, &addrh
, &sizel
, &sizeh
);
620 SI_ERROR((" SP %d has no address descriptors\n",
626 /* Now get master wrappers */
627 for (i
= 0; i
< nmw
; i
++) {
629 get_asd(sih
, &eromptr
, i
, 0, AD_ST_MWRAP
, &addrl
,
630 &addrh
, &sizel
, &sizeh
);
632 SI_ERROR(("Missing descriptor for MW %d\n", i
));
635 if ((sizeh
!= 0) || (sizel
!= SI_CORE_SIZE
)) {
636 SI_ERROR(("Master wrapper %d is not 4KB\n", i
));
640 sii
->wrapba
[idx
] = addrl
;
643 /* And finally slave wrappers */
644 for (i
= 0; i
< nsw
; i
++) {
645 uint fwp
= (nsp
== 1) ? 0 : 1;
647 get_asd(sih
, &eromptr
, fwp
+ i
, 0, AD_ST_SWRAP
,
648 &addrl
, &addrh
, &sizel
, &sizeh
);
650 SI_ERROR(("Missing descriptor for SW %d\n", i
));
653 if ((sizeh
!= 0) || (sizel
!= SI_CORE_SIZE
)) {
654 SI_ERROR(("Slave wrapper %d is not 4KB\n", i
));
657 if ((nmw
== 0) && (i
== 0))
658 sii
->wrapba
[idx
] = addrl
;
661 /* Don't record bridges */
669 SI_ERROR(("Reached end of erom without finding END"));
677 * This function changes the logical "focus" to the indicated core.
678 * Return the current core's virtual address. Since each core starts with the
679 * same set of registers (BIST, clock control, etc), the returned address
680 * contains the first register of this 'common' register block (not to be
681 * confused with 'common core').
683 void *ai_setcoreidx(struct si_pub
*sih
, uint coreidx
)
685 struct si_info
*sii
= SI_INFO(sih
);
686 u32 addr
= sii
->coresba
[coreidx
];
687 u32 wrap
= sii
->wrapba
[coreidx
];
689 if (coreidx
>= sii
->numcores
)
692 /* point bar0 window */
693 pci_write_config_dword(sii
->pbus
, PCI_BAR0_WIN
, addr
);
694 /* point bar0 2nd 4KB window */
695 pci_write_config_dword(sii
->pbus
, PCI_BAR0_WIN2
, wrap
);
696 sii
->curidx
= coreidx
;
701 /* Return the number of address spaces in current core */
702 int ai_numaddrspaces(struct si_pub
*sih
)
707 /* Return the address of the nth address space in the current core */
708 u32
ai_addrspace(struct si_pub
*sih
, uint asidx
)
717 return sii
->coresba
[cidx
];
719 return sii
->coresba2
[cidx
];
721 SI_ERROR(("%s: Need to parse the erom again to find addr "
722 "space %d\n", __func__
, asidx
));
727 /* Return the size of the nth address space in the current core */
728 u32
ai_addrspacesize(struct si_pub
*sih
, uint asidx
)
737 return sii
->coresba_size
[cidx
];
739 return sii
->coresba2_size
[cidx
];
741 SI_ERROR(("%s: Need to parse the erom again to find addr "
742 "space %d\n", __func__
, asidx
));
747 uint
ai_flag(struct si_pub
*sih
)
753 if (BCM47162_DMP()) {
754 SI_ERROR(("%s: Attempting to read MIPS DMP registers "
755 "on 47162a0", __func__
));
760 return R_REG(&ai
->oobselouta30
) & 0x1f;
763 void ai_setint(struct si_pub
*sih
, int siflag
)
767 uint
ai_corevendor(struct si_pub
*sih
)
773 cia
= sii
->cia
[sii
->curidx
];
774 return (cia
& CIA_MFG_MASK
) >> CIA_MFG_SHIFT
;
777 uint
ai_corerev(struct si_pub
*sih
)
783 cib
= sii
->cib
[sii
->curidx
];
784 return (cib
& CIB_REV_MASK
) >> CIB_REV_SHIFT
;
787 bool ai_iscoreup(struct si_pub
*sih
)
795 return (((R_REG(&ai
->ioctrl
) & (SICF_FGC
| SICF_CLOCK_EN
)) ==
797 && ((R_REG(&ai
->resetctrl
) & AIRC_RESET
) == 0));
800 void ai_core_cflags_wo(struct si_pub
*sih
, u32 mask
, u32 val
)
808 if (BCM47162_DMP()) {
809 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
817 w
= ((R_REG(&ai
->ioctrl
) & ~mask
) | val
);
818 W_REG(&ai
->ioctrl
, w
);
822 u32
ai_core_cflags(struct si_pub
*sih
, u32 mask
, u32 val
)
829 if (BCM47162_DMP()) {
830 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
838 w
= ((R_REG(&ai
->ioctrl
) & ~mask
) | val
);
839 W_REG(&ai
->ioctrl
, w
);
842 return R_REG(&ai
->ioctrl
);
845 /* return true if PCIE capability exists in the pci config space */
846 static bool ai_ispcie(struct si_info
*sii
)
851 pcicore_find_pci_capability(sii
->pbus
, PCI_CAP_ID_EXP
, NULL
,
859 static bool ai_buscore_prep(struct si_info
*sii
)
861 /* kludge to enable the clock on the 4306 which lacks a slowclock */
863 ai_clkctl_xtal(&sii
->pub
, XTAL
| PLL
, ON
);
867 u32
ai_core_sflags(struct si_pub
*sih
, u32 mask
, u32 val
)
874 if (BCM47162_DMP()) {
875 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) "
876 "on 47162a0", __func__
));
883 w
= ((R_REG(&ai
->iostatus
) & ~mask
) | val
);
884 W_REG(&ai
->iostatus
, w
);
887 return R_REG(&ai
->iostatus
);
891 ai_buscore_setup(struct si_info
*sii
, u32 savewin
, uint
*origidx
)
895 uint pciidx
, pcieidx
, pcirev
, pcierev
;
896 struct chipcregs
*cc
;
898 cc
= ai_setcoreidx(&sii
->pub
, SI_CC_IDX
);
900 /* get chipcommon rev */
901 sii
->pub
.ccrev
= (int)ai_corerev(&sii
->pub
);
903 /* get chipcommon chipstatus */
904 if (sii
->pub
.ccrev
>= 11)
905 sii
->pub
.chipst
= R_REG(&cc
->chipstatus
);
907 /* get chipcommon capabilites */
908 sii
->pub
.cccaps
= R_REG(&cc
->capabilities
);
909 /* get chipcommon extended capabilities */
911 if (sii
->pub
.ccrev
>= 35)
912 sii
->pub
.cccaps_ext
= R_REG(&cc
->capabilities_ext
);
914 /* get pmu rev and caps */
915 if (sii
->pub
.cccaps
& CC_CAP_PMU
) {
916 sii
->pub
.pmucaps
= R_REG(&cc
->pmucapabilities
);
917 sii
->pub
.pmurev
= sii
->pub
.pmucaps
& PCAP_REV_MASK
;
920 /* figure out bus/orignal core idx */
921 sii
->pub
.buscoretype
= NODEV_CORE_ID
;
922 sii
->pub
.buscorerev
= NOREV
;
923 sii
->pub
.buscoreidx
= BADIDX
;
926 pcirev
= pcierev
= NOREV
;
927 pciidx
= pcieidx
= BADIDX
;
929 for (i
= 0; i
< sii
->numcores
; i
++) {
932 ai_setcoreidx(&sii
->pub
, i
);
933 cid
= ai_coreid(&sii
->pub
);
934 crev
= ai_corerev(&sii
->pub
);
936 /* Display cores found */
937 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
938 i
, cid
, crev
, sii
->coresba
[i
], sii
->regs
[i
]));
940 if (cid
== PCI_CORE_ID
) {
944 } else if (cid
== PCIE_CORE_ID
) {
950 /* find the core idx before entering this func. */
951 if ((savewin
&& (savewin
== sii
->coresba
[i
])) ||
952 (cc
== sii
->regs
[i
]))
963 sii
->pub
.buscoretype
= PCI_CORE_ID
;
964 sii
->pub
.buscorerev
= pcirev
;
965 sii
->pub
.buscoreidx
= pciidx
;
967 sii
->pub
.buscoretype
= PCIE_CORE_ID
;
968 sii
->pub
.buscorerev
= pcierev
;
969 sii
->pub
.buscoreidx
= pcieidx
;
972 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii
->pub
.buscoreidx
,
973 sii
->pub
.buscoretype
, sii
->pub
.buscorerev
));
975 /* fixup necessary chip/core configurations */
978 sii
->pch
= pcicore_init(&sii
->pub
, sii
->pbus
,
979 (void *)PCIEREGS(sii
));
980 if (sii
->pch
== NULL
)
984 if (ai_pci_fixcfg(&sii
->pub
)) {
985 SI_ERROR(("si_doattach: si_pci_fixcfg failed\n"));
989 /* return to the original core */
990 ai_setcoreidx(&sii
->pub
, *origidx
);
996 * get boardtype and boardrev
998 static __used
void ai_nvram_process(struct si_info
*sii
, char *pvars
)
1002 /* do a pci config read to get subsystem id and subvendor id */
1003 pci_read_config_dword(sii
->pbus
, PCI_SUBSYSTEM_VENDOR_ID
, &w
);
1004 /* Let nvram variables override subsystem Vend/ID */
1005 sii
->pub
.boardvendor
= (u16
)ai_getdevpathintvar(&sii
->pub
,
1007 if (sii
->pub
.boardvendor
== 0)
1008 sii
->pub
.boardvendor
= w
& 0xffff;
1010 SI_ERROR(("Overriding boardvendor: 0x%x instead of "
1011 "0x%x\n", sii
->pub
.boardvendor
, w
& 0xffff));
1013 sii
->pub
.boardtype
= (u16
)ai_getdevpathintvar(&sii
->pub
,
1015 if (sii
->pub
.boardtype
== 0)
1016 sii
->pub
.boardtype
= (w
>> 16) & 0xffff;
1018 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n"
1019 , sii
->pub
.boardtype
, (w
>> 16) & 0xffff));
1021 if (sii
->pub
.boardtype
== 0)
1022 SI_ERROR(("si_doattach: unknown board type\n"));
1024 sii
->pub
.boardflags
= getintvar(pvars
, "boardflags");
1027 static struct si_info
*ai_doattach(struct si_info
*sii
,
1028 void *regs
, struct pci_dev
*pbus
,
1029 char **vars
, uint
*varsz
)
1031 struct si_pub
*sih
= &sii
->pub
;
1033 struct chipcregs
*cc
;
1038 memset((unsigned char *) sii
, 0, sizeof(struct si_info
));
1042 sih
->buscoreidx
= BADIDX
;
1047 /* find Chipcommon address */
1048 pci_read_config_dword(sii
->pbus
, PCI_BAR0_WIN
, &savewin
);
1049 if (!GOODCOREADDR(savewin
, SI_ENUM_BASE
))
1050 savewin
= SI_ENUM_BASE
;
1052 pci_write_config_dword(sii
->pbus
, PCI_BAR0_WIN
,
1054 cc
= (struct chipcregs
*) regs
;
1056 /* bus/core/clk setup for register access */
1057 if (!ai_buscore_prep(sii
)) {
1058 SI_ERROR(("si_doattach: si_core_clk_prep failed\n"));
1063 * ChipID recognition.
1064 * We assume we can read chipid at offset 0 from the regs arg.
1065 * If we add other chiptypes (or if we need to support old sdio
1066 * hosts w/o chipcommon), some way of recognizing them needs to
1069 w
= R_REG(&cc
->chipid
);
1070 socitype
= (w
& CID_TYPE_MASK
) >> CID_TYPE_SHIFT
;
1071 /* Might as wll fill in chip id rev & pkg */
1072 sih
->chip
= w
& CID_ID_MASK
;
1073 sih
->chiprev
= (w
& CID_REV_MASK
) >> CID_REV_SHIFT
;
1074 sih
->chippkg
= (w
& CID_PKG_MASK
) >> CID_PKG_SHIFT
;
1076 sih
->issim
= IS_SIM(sih
->chippkg
);
1078 /* scan for cores */
1079 if (socitype
== SOCI_AI
) {
1080 SI_MSG(("Found chip type AI (0x%08x)\n", w
));
1081 /* pass chipc address instead of original core base */
1082 ai_scan(&sii
->pub
, cc
);
1084 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w
));
1087 /* no cores found, bail out */
1088 if (sii
->numcores
== 0) {
1089 SI_ERROR(("si_doattach: could not find any cores\n"));
1092 /* bus/core/clk setup */
1093 origidx
= SI_CC_IDX
;
1094 if (!ai_buscore_setup(sii
, savewin
, &origidx
)) {
1095 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
1099 /* Init nvram from sprom/otp if they exist */
1100 if (srom_var_init(&sii
->pub
, cc
, vars
, varsz
)) {
1101 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
1104 pvars
= vars
? *vars
: NULL
;
1105 ai_nvram_process(sii
, pvars
);
1107 /* === NVRAM, clock is ready === */
1108 cc
= (struct chipcregs
*) ai_setcore(sih
, CC_CORE_ID
, 0);
1109 W_REG(&cc
->gpiopullup
, 0);
1110 W_REG(&cc
->gpiopulldown
, 0);
1111 ai_setcoreidx(sih
, origidx
);
1113 /* PMU specific initializations */
1114 if (PMUCTL_ENAB(sih
)) {
1117 si_pmu_chip_init(sih
);
1118 xtalfreq
= getintvar(pvars
, "xtalfreq");
1119 /* If xtalfreq var not available, try to measure it */
1121 xtalfreq
= si_pmu_measure_alpclk(sih
);
1122 si_pmu_pll_init(sih
, xtalfreq
);
1123 si_pmu_res_init(sih
);
1124 si_pmu_swreg_init(sih
);
1127 /* setup the GPIO based LED powersave register */
1128 w
= getintvar(pvars
, "leddc");
1130 w
= DEFAULT_GPIOTIMERVAL
;
1131 ai_corereg(sih
, SI_CC_IDX
, offsetof(struct chipcregs
, gpiotimerval
),
1135 pcicore_attach(sii
->pch
, pvars
, SI_DOATTACH
);
1137 if (sih
->chip
== BCM43224_CHIP_ID
) {
1139 * enable 12 mA drive strenth for 43224 and
1140 * set chipControl register bit 15
1142 if (sih
->chiprev
== 0) {
1143 SI_MSG(("Applying 43224A0 WARs\n"));
1144 ai_corereg(sih
, SI_CC_IDX
,
1145 offsetof(struct chipcregs
, chipcontrol
),
1146 CCTRL43224_GPIO_TOGGLE
,
1147 CCTRL43224_GPIO_TOGGLE
);
1148 si_pmu_chipcontrol(sih
, 0, CCTRL_43224A0_12MA_LED_DRIVE
,
1149 CCTRL_43224A0_12MA_LED_DRIVE
);
1151 if (sih
->chiprev
>= 1) {
1152 SI_MSG(("Applying 43224B0+ WARs\n"));
1153 si_pmu_chipcontrol(sih
, 0, CCTRL_43224B0_12MA_LED_DRIVE
,
1154 CCTRL_43224B0_12MA_LED_DRIVE
);
1158 if (sih
->chip
== BCM4313_CHIP_ID
) {
1160 * enable 12 mA drive strenth for 4313 and
1161 * set chipControl register bit 1
1163 SI_MSG(("Applying 4313 WARs\n"));
1164 si_pmu_chipcontrol(sih
, 0, CCTRL_4313_12MA_LED_DRIVE
,
1165 CCTRL_4313_12MA_LED_DRIVE
);
1172 pcicore_deinit(sii
->pch
);
1179 * Allocate a si handle.
1180 * devid - pci device id (used to determine chip#)
1181 * osh - opaque OS handle
1182 * regs - virtual address of initial core registers
1183 * vars - pointer to a pointer area for "environment" variables
1184 * varsz - pointer to int to return the size of the vars
1187 ai_attach(void *regs
, struct pci_dev
*sdh
, char **vars
, uint
*varsz
)
1189 struct si_info
*sii
;
1191 /* alloc struct si_info */
1192 sii
= kmalloc(sizeof(struct si_info
), GFP_ATOMIC
);
1196 if (ai_doattach(sii
, regs
, sdh
, vars
, varsz
) == NULL
) {
1200 sii
->vars
= vars
? *vars
: NULL
;
1201 sii
->varsz
= varsz
? *varsz
: 0;
1203 return (struct si_pub
*) sii
;
1206 /* may be called with core in reset */
1207 void ai_detach(struct si_pub
*sih
)
1209 struct si_info
*sii
;
1211 struct si_pub
*si_local
= NULL
;
1212 memcpy(&si_local
, &sih
, sizeof(struct si_pub
**));
1220 pcicore_deinit(sii
->pch
);
1227 /* register driver interrupt disabling and restoring callback functions */
1229 ai_register_intr_callback(struct si_pub
*sih
, void *intrsoff_fn
,
1230 void *intrsrestore_fn
,
1231 void *intrsenabled_fn
, void *intr_arg
)
1233 struct si_info
*sii
;
1236 sii
->intr_arg
= intr_arg
;
1237 sii
->intrsoff_fn
= (u32 (*)(void *)) intrsoff_fn
;
1238 sii
->intrsrestore_fn
= (void (*) (void *, u32
)) intrsrestore_fn
;
1239 sii
->intrsenabled_fn
= (bool (*)(void *)) intrsenabled_fn
;
1240 /* save current core id. when this function called, the current core
1241 * must be the core which provides driver functions(il, et, wl, etc.)
1243 sii
->dev_coreid
= sii
->coreid
[sii
->curidx
];
1246 void ai_deregister_intr_callback(struct si_pub
*sih
)
1248 struct si_info
*sii
;
1251 sii
->intrsoff_fn
= NULL
;
1254 uint
ai_coreid(struct si_pub
*sih
)
1256 struct si_info
*sii
;
1259 return sii
->coreid
[sii
->curidx
];
1262 uint
ai_coreidx(struct si_pub
*sih
)
1264 struct si_info
*sii
;
1270 bool ai_backplane64(struct si_pub
*sih
)
1272 return (sih
->cccaps
& CC_CAP_BKPLN64
) != 0;
1275 /* return index of coreid or BADIDX if not found */
1276 uint
ai_findcoreidx(struct si_pub
*sih
, uint coreid
, uint coreunit
)
1278 struct si_info
*sii
;
1286 for (i
= 0; i
< sii
->numcores
; i
++)
1287 if (sii
->coreid
[i
] == coreid
) {
1288 if (found
== coreunit
)
1297 * This function changes logical "focus" to the indicated core;
1298 * must be called with interrupts off.
1299 * Moreover, callers should keep interrupts off during switching
1300 * out of and back to d11 core.
1302 void *ai_setcore(struct si_pub
*sih
, uint coreid
, uint coreunit
)
1306 idx
= ai_findcoreidx(sih
, coreid
, coreunit
);
1310 return ai_setcoreidx(sih
, idx
);
1313 /* Turn off interrupt as required by ai_setcore, before switch core */
1314 void *ai_switch_core(struct si_pub
*sih
, uint coreid
, uint
*origidx
,
1318 struct si_info
*sii
;
1323 /* Overloading the origidx variable to remember the coreid,
1324 * this works because the core ids cannot be confused with
1328 if (coreid
== CC_CORE_ID
)
1329 return CCREGS_FAST(sii
);
1330 else if (coreid
== sih
->buscoretype
)
1331 return PCIEREGS(sii
);
1333 INTR_OFF(sii
, *intr_val
);
1334 *origidx
= sii
->curidx
;
1335 cc
= ai_setcore(sih
, coreid
, 0);
1339 /* restore coreidx and restore interrupt */
1340 void ai_restore_core(struct si_pub
*sih
, uint coreid
, uint intr_val
)
1342 struct si_info
*sii
;
1346 && ((coreid
== CC_CORE_ID
) || (coreid
== sih
->buscoretype
)))
1349 ai_setcoreidx(sih
, coreid
);
1350 INTR_RESTORE(sii
, intr_val
);
1353 void ai_write_wrapperreg(struct si_pub
*sih
, u32 offset
, u32 val
)
1355 struct si_info
*sii
= SI_INFO(sih
);
1356 u32
*w
= (u32
*) sii
->curwrap
;
1357 W_REG(w
+ (offset
/ 4), val
);
1362 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set
1363 * operation, switch back to the original core, and return the new value.
1365 * When using the silicon backplane, no fiddling with interrupts or core
1366 * switches is needed.
1368 * Also, when using pci/pcie, we can optimize away the core switching for pci
1369 * registers and (on newer pci cores) chipcommon registers.
1371 uint
ai_corereg(struct si_pub
*sih
, uint coreidx
, uint regoff
, uint mask
,
1379 struct si_info
*sii
;
1383 if (coreidx
>= SI_MAXCORES
)
1387 * If pci/pcie, we can get at pci/pcie regs
1388 * and on newer cores to chipc
1390 if ((sii
->coreid
[coreidx
] == CC_CORE_ID
) && SI_FAST(sii
)) {
1391 /* Chipc registers are mapped at 12KB */
1393 r
= (u32
*)((char *)sii
->curmap
+
1394 PCI_16KB0_CCREGS_OFFSET
+ regoff
);
1395 } else if (sii
->pub
.buscoreidx
== coreidx
) {
1397 * pci registers are at either in the last 2KB of
1398 * an 8KB window or, in pcie and pci rev 13 at 8KB
1402 r
= (u32
*)((char *)sii
->curmap
+
1403 PCI_16KB0_PCIREGS_OFFSET
+ regoff
);
1405 r
= (u32
*)((char *)sii
->curmap
+
1406 ((regoff
>= SBCONFIGOFF
) ?
1407 PCI_BAR0_PCISBR_OFFSET
:
1408 PCI_BAR0_PCIREGS_OFFSET
) + regoff
);
1412 INTR_OFF(sii
, intr_val
);
1414 /* save current core index */
1415 origidx
= ai_coreidx(&sii
->pub
);
1418 r
= (u32
*) ((unsigned char *) ai_setcoreidx(&sii
->pub
, coreidx
)
1424 w
= (R_REG(r
) & ~mask
) | val
;
1432 /* restore core index */
1433 if (origidx
!= coreidx
)
1434 ai_setcoreidx(&sii
->pub
, origidx
);
1436 INTR_RESTORE(sii
, intr_val
);
1442 void ai_core_disable(struct si_pub
*sih
, u32 bits
)
1444 struct si_info
*sii
;
1452 /* if core is already in reset, just return */
1453 if (R_REG(&ai
->resetctrl
) & AIRC_RESET
)
1456 W_REG(&ai
->ioctrl
, bits
);
1457 dummy
= R_REG(&ai
->ioctrl
);
1460 W_REG(&ai
->resetctrl
, AIRC_RESET
);
1464 /* reset and re-enable a core
1466 * bits - core specific bits that are set during and after reset sequence
1467 * resetbits - core specific bits that are set only during reset sequence
1469 void ai_core_reset(struct si_pub
*sih
, u32 bits
, u32 resetbits
)
1471 struct si_info
*sii
;
1479 * Must do the disable sequence first to work
1480 * for arbitrary current core state.
1482 ai_core_disable(sih
, (bits
| resetbits
));
1485 * Now do the initialization sequence.
1487 W_REG(&ai
->ioctrl
, (bits
| SICF_FGC
| SICF_CLOCK_EN
));
1488 dummy
= R_REG(&ai
->ioctrl
);
1489 W_REG(&ai
->resetctrl
, 0);
1492 W_REG(&ai
->ioctrl
, (bits
| SICF_CLOCK_EN
));
1493 dummy
= R_REG(&ai
->ioctrl
);
1497 /* return the slow clock source - LPO, XTAL, or PCI */
1498 static uint
ai_slowclk_src(struct si_info
*sii
)
1500 struct chipcregs
*cc
;
1503 if (sii
->pub
.ccrev
< 6) {
1504 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUT
,
1506 if (val
& PCI_CFG_GPIO_SCS
)
1509 } else if (sii
->pub
.ccrev
< 10) {
1510 cc
= (struct chipcregs
*) ai_setcoreidx(&sii
->pub
, sii
->curidx
);
1511 return R_REG(&cc
->slow_clk_ctl
) & SCC_SS_MASK
;
1512 } else /* Insta-clock */
1517 * return the ILP (slowclock) min or max frequency
1518 * precondition: we've established the chip has dynamic clk control
1521 ai_slowclk_freq(struct si_info
*sii
, bool max_freq
, struct chipcregs
*cc
)
1526 slowclk
= ai_slowclk_src(sii
);
1527 if (sii
->pub
.ccrev
< 6) {
1528 if (slowclk
== SCC_SS_PCI
)
1529 return max_freq
? (PCIMAXFREQ
/ 64)
1530 : (PCIMINFREQ
/ 64);
1532 return max_freq
? (XTALMAXFREQ
/ 32)
1533 : (XTALMINFREQ
/ 32);
1534 } else if (sii
->pub
.ccrev
< 10) {
1536 (((R_REG(&cc
->slow_clk_ctl
) & SCC_CD_MASK
) >>
1538 if (slowclk
== SCC_SS_LPO
)
1539 return max_freq
? LPOMAXFREQ
: LPOMINFREQ
;
1540 else if (slowclk
== SCC_SS_XTAL
)
1541 return max_freq
? (XTALMAXFREQ
/ div
)
1542 : (XTALMINFREQ
/ div
);
1543 else if (slowclk
== SCC_SS_PCI
)
1544 return max_freq
? (PCIMAXFREQ
/ div
)
1545 : (PCIMINFREQ
/ div
);
1547 /* Chipc rev 10 is InstaClock */
1548 div
= R_REG(&cc
->system_clk_ctl
) >> SYCC_CD_SHIFT
;
1549 div
= 4 * (div
+ 1);
1550 return max_freq
? XTALMAXFREQ
: (XTALMINFREQ
/ div
);
1555 static void ai_clkctl_setdelay(struct si_info
*sii
, struct chipcregs
*cc
)
1557 uint slowmaxfreq
, pll_delay
, slowclk
;
1558 uint pll_on_delay
, fref_sel_delay
;
1560 pll_delay
= PLL_DELAY
;
1563 * If the slow clock is not sourced by the xtal then
1564 * add the xtal_on_delay since the xtal will also be
1565 * powered down by dynamic clk control logic.
1568 slowclk
= ai_slowclk_src(sii
);
1569 if (slowclk
!= SCC_SS_XTAL
)
1570 pll_delay
+= XTAL_ON_DELAY
;
1572 /* Starting with 4318 it is ILP that is used for the delays */
1574 ai_slowclk_freq(sii
, (sii
->pub
.ccrev
>= 10) ? false : true, cc
);
1576 pll_on_delay
= ((slowmaxfreq
* pll_delay
) + 999999) / 1000000;
1577 fref_sel_delay
= ((slowmaxfreq
* FREF_DELAY
) + 999999) / 1000000;
1579 W_REG(&cc
->pll_on_delay
, pll_on_delay
);
1580 W_REG(&cc
->fref_sel_delay
, fref_sel_delay
);
1583 /* initialize power control delay registers */
1584 void ai_clkctl_init(struct si_pub
*sih
)
1586 struct si_info
*sii
;
1588 struct chipcregs
*cc
;
1591 if (!CCCTL_ENAB(sih
))
1595 fast
= SI_FAST(sii
);
1597 origidx
= sii
->curidx
;
1598 cc
= (struct chipcregs
*) ai_setcore(sih
, CC_CORE_ID
, 0);
1602 cc
= (struct chipcregs
*) CCREGS_FAST(sii
);
1607 /* set all Instaclk chip ILP to 1 MHz */
1608 if (sih
->ccrev
>= 10)
1609 SET_REG(&cc
->system_clk_ctl
, SYCC_CD_MASK
,
1610 (ILP_DIV_1MHZ
<< SYCC_CD_SHIFT
));
1612 ai_clkctl_setdelay(sii
, cc
);
1615 ai_setcoreidx(sih
, origidx
);
1619 * return the value suitable for writing to the
1620 * dot11 core FAST_PWRUP_DELAY register
1622 u16
ai_clkctl_fast_pwrup_delay(struct si_pub
*sih
)
1624 struct si_info
*sii
;
1626 struct chipcregs
*cc
;
1633 if (PMUCTL_ENAB(sih
)) {
1634 INTR_OFF(sii
, intr_val
);
1635 fpdelay
= si_pmu_fast_pwrup_delay(sih
);
1636 INTR_RESTORE(sii
, intr_val
);
1640 if (!CCCTL_ENAB(sih
))
1643 fast
= SI_FAST(sii
);
1646 origidx
= sii
->curidx
;
1647 INTR_OFF(sii
, intr_val
);
1648 cc
= (struct chipcregs
*) ai_setcore(sih
, CC_CORE_ID
, 0);
1652 cc
= (struct chipcregs
*) CCREGS_FAST(sii
);
1657 slowminfreq
= ai_slowclk_freq(sii
, false, cc
);
1658 fpdelay
= (((R_REG(&cc
->pll_on_delay
) + 2) * 1000000) +
1659 (slowminfreq
- 1)) / slowminfreq
;
1663 ai_setcoreidx(sih
, origidx
);
1664 INTR_RESTORE(sii
, intr_val
);
1669 /* turn primary xtal and/or pll off/on */
1670 int ai_clkctl_xtal(struct si_pub
*sih
, uint what
, bool on
)
1672 struct si_info
*sii
;
1677 /* pcie core doesn't have any mapping to control the xtal pu */
1681 pci_read_config_dword(sii
->pbus
, PCI_GPIO_IN
, &in
);
1682 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUT
, &out
);
1683 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUTEN
, &outen
);
1686 * Avoid glitching the clock if GPRS is already using it.
1687 * We can't actually read the state of the PLLPD so we infer it
1688 * by the value of XTAL_PU which *is* readable via gpioin.
1690 if (on
&& (in
& PCI_CFG_GPIO_XTAL
))
1694 outen
|= PCI_CFG_GPIO_XTAL
;
1696 outen
|= PCI_CFG_GPIO_PLL
;
1699 /* turn primary xtal on */
1701 out
|= PCI_CFG_GPIO_XTAL
;
1703 out
|= PCI_CFG_GPIO_PLL
;
1704 pci_write_config_dword(sii
->pbus
,
1706 pci_write_config_dword(sii
->pbus
,
1707 PCI_GPIO_OUTEN
, outen
);
1708 udelay(XTAL_ON_DELAY
);
1713 out
&= ~PCI_CFG_GPIO_PLL
;
1714 pci_write_config_dword(sii
->pbus
,
1720 out
&= ~PCI_CFG_GPIO_XTAL
;
1722 out
|= PCI_CFG_GPIO_PLL
;
1723 pci_write_config_dword(sii
->pbus
,
1725 pci_write_config_dword(sii
->pbus
,
1726 PCI_GPIO_OUTEN
, outen
);
1732 /* clk control mechanism through chipcommon, no policy checking */
1733 static bool _ai_clkctl_cc(struct si_info
*sii
, uint mode
)
1736 struct chipcregs
*cc
;
1739 bool fast
= SI_FAST(sii
);
1741 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1742 if (sii
->pub
.ccrev
< 6)
1746 INTR_OFF(sii
, intr_val
);
1747 origidx
= sii
->curidx
;
1748 cc
= (struct chipcregs
*) ai_setcore(&sii
->pub
, CC_CORE_ID
, 0);
1750 cc
= (struct chipcregs
*) CCREGS_FAST(sii
);
1755 if (!CCCTL_ENAB(&sii
->pub
) && (sii
->pub
.ccrev
< 20))
1759 case CLK_FAST
: /* FORCEHT, fast (pll) clock */
1760 if (sii
->pub
.ccrev
< 10) {
1762 * don't forget to force xtal back
1763 * on before we clear SCC_DYN_XTAL..
1765 ai_clkctl_xtal(&sii
->pub
, XTAL
, ON
);
1766 SET_REG(&cc
->slow_clk_ctl
,
1767 (SCC_XC
| SCC_FS
| SCC_IP
), SCC_IP
);
1768 } else if (sii
->pub
.ccrev
< 20) {
1769 OR_REG(&cc
->system_clk_ctl
, SYCC_HR
);
1771 OR_REG(&cc
->clk_ctl_st
, CCS_FORCEHT
);
1774 /* wait for the PLL */
1775 if (PMUCTL_ENAB(&sii
->pub
)) {
1776 u32 htavail
= CCS_HTAVAIL
;
1777 SPINWAIT(((R_REG(&cc
->clk_ctl_st
) & htavail
)
1778 == 0), PMU_MAX_TRANSITION_DLY
);
1784 case CLK_DYNAMIC
: /* enable dynamic clock control */
1785 if (sii
->pub
.ccrev
< 10) {
1786 scc
= R_REG(&cc
->slow_clk_ctl
);
1787 scc
&= ~(SCC_FS
| SCC_IP
| SCC_XC
);
1788 if ((scc
& SCC_SS_MASK
) != SCC_SS_XTAL
)
1790 W_REG(&cc
->slow_clk_ctl
, scc
);
1793 * for dynamic control, we have to
1794 * release our xtal_pu "force on"
1797 ai_clkctl_xtal(&sii
->pub
, XTAL
, OFF
);
1798 } else if (sii
->pub
.ccrev
< 20) {
1800 AND_REG(&cc
->system_clk_ctl
, ~SYCC_HR
);
1802 AND_REG(&cc
->clk_ctl_st
, ~CCS_FORCEHT
);
1812 ai_setcoreidx(&sii
->pub
, origidx
);
1813 INTR_RESTORE(sii
, intr_val
);
1815 return mode
== CLK_FAST
;
1819 * clock control policy function throught chipcommon
1821 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1822 * returns true if we are forcing fast clock
1823 * this is a wrapper over the next internal function
1824 * to allow flexible policy settings for outside caller
1826 bool ai_clkctl_cc(struct si_pub
*sih
, uint mode
)
1828 struct si_info
*sii
;
1832 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1836 if (PCI_FORCEHT(sii
))
1837 return mode
== CLK_FAST
;
1839 return _ai_clkctl_cc(sii
, mode
);
1842 /* Build device path */
1843 int ai_devpath(struct si_pub
*sih
, char *path
, int size
)
1847 if (!path
|| size
<= 0)
1850 slen
= snprintf(path
, (size_t) size
, "pci/%u/%u/",
1851 (((SI_INFO(sih
))->pbus
))->bus
->number
,
1852 PCI_SLOT(((struct pci_dev
*)((SI_INFO(sih
))->pbus
))->devfn
));
1854 if (slen
< 0 || slen
>= size
) {
1862 /* Concatenate the dev path with a varname into the given 'var' buffer
1863 * and return the 'var' pointer. Nothing is done to the arguments if
1864 * len == 0 or var is NULL, var is still returned. On overflow, the
1865 * first char will be set to '\0'.
1867 static char *ai_devpathvar(struct si_pub
*sih
, char *var
, int len
,
1872 if (!var
|| len
<= 0)
1875 if (ai_devpath(sih
, var
, len
) == 0) {
1876 path_len
= strlen(var
);
1878 if (strlen(name
) + 1 > (uint
) (len
- path_len
))
1881 strncpy(var
+ path_len
, name
, len
- path_len
- 1);
1887 /* Get a variable, but only if it has a devpath prefix */
1888 char *ai_getdevpathvar(struct si_pub
*sih
, const char *name
)
1890 char varname
[SI_DEVPATH_BUFSZ
+ 32];
1892 ai_devpathvar(sih
, varname
, sizeof(varname
), name
);
1894 return getvar(NULL
, varname
);
1897 /* Get a variable, but only if it has a devpath prefix */
1898 int ai_getdevpathintvar(struct si_pub
*sih
, const char *name
)
1900 char varname
[SI_DEVPATH_BUFSZ
+ 32];
1902 ai_devpathvar(sih
, varname
, sizeof(varname
), name
);
1904 return getintvar(NULL
, varname
);
1907 char *ai_getnvramflvar(struct si_pub
*sih
, const char *name
)
1909 return getvar(NULL
, name
);
1912 bool ai_pci_war16165(struct si_pub
*sih
)
1914 struct si_info
*sii
;
1918 return PCI(sii
) && (sih
->buscorerev
<= 10);
1921 void ai_pci_up(struct si_pub
*sih
)
1923 struct si_info
*sii
;
1927 if (PCI_FORCEHT(sii
))
1928 _ai_clkctl_cc(sii
, CLK_FAST
);
1931 pcicore_up(sii
->pch
, SI_PCIUP
);
1935 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1936 void ai_pci_sleep(struct si_pub
*sih
)
1938 struct si_info
*sii
;
1942 pcicore_sleep(sii
->pch
);
1945 /* Unconfigure and/or apply various WARs when going down */
1946 void ai_pci_down(struct si_pub
*sih
)
1948 struct si_info
*sii
;
1952 /* release FORCEHT since chip is going to "down" state */
1953 if (PCI_FORCEHT(sii
))
1954 _ai_clkctl_cc(sii
, CLK_DYNAMIC
);
1956 pcicore_down(sii
->pch
, SI_PCIDOWN
);
1960 * Configure the pci core for pci client (NIC) action
1961 * coremask is the bitvec of cores by index to be enabled.
1963 void ai_pci_setup(struct si_pub
*sih
, uint coremask
)
1965 struct si_info
*sii
;
1966 struct sbpciregs
*regs
= NULL
;
1973 /* get current core index */
1976 /* we interrupt on this backplane flag number */
1977 siflag
= ai_flag(sih
);
1979 /* switch over to pci core */
1980 regs
= ai_setcoreidx(sih
, sii
->pub
.buscoreidx
);
1984 * Enable sb->pci interrupts. Assume
1985 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1987 if (PCIE(sii
) || (PCI(sii
) && ((sii
->pub
.buscorerev
) >= 6))) {
1988 /* pci config write to set this core bit in PCIIntMask */
1989 pci_read_config_dword(sii
->pbus
, PCI_INT_MASK
, &w
);
1990 w
|= (coremask
<< PCI_SBIM_SHIFT
);
1991 pci_write_config_dword(sii
->pbus
, PCI_INT_MASK
, w
);
1993 /* set sbintvec bit for our flag number */
1994 ai_setint(sih
, siflag
);
1998 pcicore_pci_setup(sii
->pch
, regs
);
2000 /* switch back to previous core */
2001 ai_setcoreidx(sih
, idx
);
2006 * Fixup SROMless PCI device's configuration.
2007 * The current core may be changed upon return.
2009 int ai_pci_fixcfg(struct si_pub
*sih
)
2013 struct si_info
*sii
= SI_INFO(sih
);
2015 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
2016 /* save the current index */
2017 origidx
= ai_coreidx(&sii
->pub
);
2019 /* check 'pi' is correct and fix it if not */
2020 regs
= ai_setcore(&sii
->pub
, sii
->pub
.buscoretype
, 0);
2021 if (sii
->pub
.buscoretype
== PCIE_CORE_ID
)
2022 pcicore_fixcfg_pcie(sii
->pch
, (struct sbpcieregs
*)regs
);
2023 else if (sii
->pub
.buscoretype
== PCI_CORE_ID
)
2024 pcicore_fixcfg_pci(sii
->pch
, (struct sbpciregs
*)regs
);
2026 /* restore the original index */
2027 ai_setcoreidx(&sii
->pub
, origidx
);
2029 pcicore_hwup(sii
->pch
);
2033 /* mask&set gpiocontrol bits */
2034 u32
ai_gpiocontrol(struct si_pub
*sih
, u32 mask
, u32 val
, u8 priority
)
2038 regoff
= offsetof(struct chipcregs
, gpiocontrol
);
2039 return ai_corereg(sih
, SI_CC_IDX
, regoff
, mask
, val
);
2042 void ai_chipcontrl_epa4331(struct si_pub
*sih
, bool on
)
2044 struct si_info
*sii
;
2045 struct chipcregs
*cc
;
2050 origidx
= ai_coreidx(sih
);
2052 cc
= (struct chipcregs
*) ai_setcore(sih
, CC_CORE_ID
, 0);
2054 val
= R_REG(&cc
->chipcontrol
);
2057 if (sih
->chippkg
== 9 || sih
->chippkg
== 0xb)
2058 /* Ext PA Controls for 4331 12x9 Package */
2059 W_REG(&cc
->chipcontrol
, val
|
2060 (CCTRL4331_EXTPA_EN
|
2061 CCTRL4331_EXTPA_ON_GPIO2_5
));
2063 /* Ext PA Controls for 4331 12x12 Package */
2064 W_REG(&cc
->chipcontrol
,
2065 val
| (CCTRL4331_EXTPA_EN
));
2067 val
&= ~(CCTRL4331_EXTPA_EN
| CCTRL4331_EXTPA_ON_GPIO2_5
);
2068 W_REG(&cc
->chipcontrol
, val
);
2071 ai_setcoreidx(sih
, origidx
);
2074 /* Enable BT-COEX & Ex-PA for 4313 */
2075 void ai_epa_4313war(struct si_pub
*sih
)
2077 struct si_info
*sii
;
2078 struct chipcregs
*cc
;
2082 origidx
= ai_coreidx(sih
);
2084 cc
= ai_setcore(sih
, CC_CORE_ID
, 0);
2087 W_REG(&cc
->gpiocontrol
,
2088 R_REG(&cc
->gpiocontrol
) | GPIO_CTRL_EPA_EN_MASK
);
2090 ai_setcoreidx(sih
, origidx
);
2093 /* check if the device is removed */
2094 bool ai_deviceremoved(struct si_pub
*sih
)
2097 struct si_info
*sii
;
2101 pci_read_config_dword(sii
->pbus
, PCI_VENDOR_ID
, &w
);
2102 if ((w
& 0xFFFF) != PCI_VENDOR_ID_BROADCOM
)
2108 bool ai_is_sprom_available(struct si_pub
*sih
)
2110 if (sih
->ccrev
>= 31) {
2111 struct si_info
*sii
;
2113 struct chipcregs
*cc
;
2116 if ((sih
->cccaps
& CC_CAP_SROM
) == 0)
2120 origidx
= sii
->curidx
;
2121 cc
= ai_setcoreidx(sih
, SI_CC_IDX
);
2122 sromctrl
= R_REG(&cc
->sromcontrol
);
2123 ai_setcoreidx(sih
, origidx
);
2124 return sromctrl
& SRC_PRESENT
;
2127 switch (sih
->chip
) {
2128 case BCM4313_CHIP_ID
:
2129 return (sih
->chipst
& CST4313_SPROM_PRESENT
) != 0;
2135 bool ai_is_otp_disabled(struct si_pub
*sih
)
2137 switch (sih
->chip
) {
2138 case BCM4313_CHIP_ID
:
2139 return (sih
->chipst
& CST4313_OTP_PRESENT
) == 0;
2140 /* These chips always have their OTP on */
2141 case BCM43224_CHIP_ID
:
2142 case BCM43225_CHIP_ID
: