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2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/slab.h>
17 #include <linux/skbuff.h>
18 #include <linux/delay.h>
19 #include <linux/pci.h>
21 #include <brcmu_utils.h>
27 * Each descriptor ring must be 8kB aligned, and fit within a
28 * contiguous 8kB physical address.
30 #define D64RINGALIGN_BITS 13
31 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
32 #define D64RINGALIGN (1 << D64RINGALIGN_BITS)
34 #define D64MAXDD (D64MAXRINGSZ / sizeof(struct dma64desc))
36 /* transmit channel control */
37 #define D64_XC_XE 0x00000001 /* transmit enable */
38 #define D64_XC_SE 0x00000002 /* transmit suspend request */
39 #define D64_XC_LE 0x00000004 /* loopback enable */
40 #define D64_XC_FL 0x00000010 /* flush request */
41 #define D64_XC_PD 0x00000800 /* parity check disable */
42 #define D64_XC_AE 0x00030000 /* address extension bits */
43 #define D64_XC_AE_SHIFT 16
45 /* transmit descriptor table pointer */
46 #define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
48 /* transmit channel status */
49 #define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
50 #define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
51 #define D64_XS0_XS_SHIFT 28
52 #define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
53 #define D64_XS0_XS_ACTIVE 0x10000000 /* active */
54 #define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
55 #define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
56 #define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
58 #define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
59 #define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
60 #define D64_XS1_XE_SHIFT 28
61 #define D64_XS1_XE_NOERR 0x00000000 /* no error */
62 #define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
63 #define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
64 #define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
65 #define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
66 #define D64_XS1_XE_COREE 0x50000000 /* core error */
68 /* receive channel control */
70 #define D64_RC_RE 0x00000001
71 /* receive frame offset */
72 #define D64_RC_RO_MASK 0x000000fe
73 #define D64_RC_RO_SHIFT 1
74 /* direct fifo receive (pio) mode */
75 #define D64_RC_FM 0x00000100
76 /* separate rx header descriptor enable */
77 #define D64_RC_SH 0x00000200
78 /* overflow continue */
79 #define D64_RC_OC 0x00000400
80 /* parity check disable */
81 #define D64_RC_PD 0x00000800
82 /* address extension bits */
83 #define D64_RC_AE 0x00030000
84 #define D64_RC_AE_SHIFT 16
86 /* flags for dma controller */
88 #define DMA_CTRL_PEN (1 << 0)
89 /* rx overflow continue */
90 #define DMA_CTRL_ROC (1 << 1)
91 /* allow rx scatter to multiple descriptors */
92 #define DMA_CTRL_RXMULTI (1 << 2)
93 /* Unframed Rx/Tx data */
94 #define DMA_CTRL_UNFRAMED (1 << 3)
96 /* receive descriptor table pointer */
97 #define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
99 /* receive channel status */
100 #define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
101 #define D64_RS0_RS_MASK 0xf0000000 /* receive state */
102 #define D64_RS0_RS_SHIFT 28
103 #define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
104 #define D64_RS0_RS_ACTIVE 0x10000000 /* active */
105 #define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
106 #define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
107 #define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
109 #define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
110 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
111 #define D64_RS1_RE_SHIFT 28
112 #define D64_RS1_RE_NOERR 0x00000000 /* no error */
113 #define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
114 #define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
115 #define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
116 #define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
117 #define D64_RS1_RE_COREE 0x50000000 /* core error */
120 #define D64_FA_OFF_MASK 0xffff /* offset */
121 #define D64_FA_SEL_MASK 0xf0000 /* select */
122 #define D64_FA_SEL_SHIFT 16
123 #define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
124 #define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
125 #define D64_FA_SEL_RDD 0x40000 /* receive dma data */
126 #define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
127 #define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
128 #define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
129 #define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
130 #define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
131 #define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
132 #define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
134 /* descriptor control flags 1 */
135 #define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
136 #define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
137 #define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
138 #define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
139 #define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
141 /* descriptor control flags 2 */
142 /* buffer byte count. real data len must <= 16KB */
143 #define D64_CTRL2_BC_MASK 0x00007fff
144 /* address extension bits */
145 #define D64_CTRL2_AE 0x00030000
146 #define D64_CTRL2_AE_SHIFT 16
148 #define D64_CTRL2_PARITY 0x00040000
150 /* control flags in the range [27:20] are core-specific and not defined here */
151 #define D64_CTRL_CORE_MASK 0x0ff00000
153 #define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
154 #define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
155 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */
156 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
158 #define DMA64_DD_PARITY(dd) \
159 parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
162 * packet headroom necessary to accommodate the largest header
163 * in the system, (i.e TXOFF). By doing, we avoid the need to
164 * allocate an extra buffer for the header when bridging to WL.
165 * There is a compile time check in wlc.c which ensure that this
166 * value is at least as big as TXOFF. This value is used in
170 #define BCMEXTRAHDROOM 172
174 #define DMA_ERROR(args) \
176 if (!(*di->msg_level & 1)) \
181 #define DMA_TRACE(args) \
183 if (!(*di->msg_level & 2)) \
189 #define DMA_ERROR(args)
190 #define DMA_TRACE(args)
193 #define DMA_NONE(args)
195 #define d64txregs dregs.d64_u.txregs_64
196 #define d64rxregs dregs.d64_u.rxregs_64
197 #define txd64 dregs.d64_u.txd_64
198 #define rxd64 dregs.d64_u.rxd_64
200 #define MAXNAMEL 8 /* 8 char names */
202 #define DI_INFO(dmah) ((dma_info_t *)dmah)
204 /* descriptor bumping macros */
205 /* faster than %, but n must be power of 2 */
206 #define XXD(x, n) ((x) & ((n) - 1))
208 #define TXD(x) XXD((x), di->ntxd)
209 #define RXD(x) XXD((x), di->nrxd)
210 #define NEXTTXD(i) TXD((i) + 1)
211 #define PREVTXD(i) TXD((i) - 1)
212 #define NEXTRXD(i) RXD((i) + 1)
213 #define PREVRXD(i) RXD((i) - 1)
215 #define NTXDACTIVE(h, t) TXD((t) - (h))
216 #define NRXDACTIVE(h, t) RXD((t) - (h))
218 /* macros to convert between byte offsets and indexes */
219 #define B2I(bytes, type) ((bytes) / sizeof(type))
220 #define I2B(index, type) ((index) * sizeof(type))
222 #define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
223 #define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
225 #define PCI64ADDR_HIGH 0x80000000 /* address[63] */
226 #define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
230 * Descriptors are only read by the hardware, never written back.
233 u32 ctrl1
; /* misc control bits & bufcount */
234 u32 ctrl2
; /* buffer count and address extension */
235 u32 addrlow
; /* memory address of the date buffer, bits 31:0 */
236 u32 addrhigh
; /* memory address of the date buffer, bits 63:32 */
239 /* dma engine software state */
241 struct dma_pub dma
; /* exported structure */
242 uint
*msg_level
; /* message level pointer */
243 char name
[MAXNAMEL
]; /* callers name for diag msgs */
245 struct pci_dev
*pbus
; /* bus handle */
247 bool dma64
; /* this dma engine is operating in 64-bit mode */
248 bool addrext
; /* this dma engine supports DmaExtendedAddrChanges */
252 /* 64-bit dma tx engine registers */
253 struct dma64regs
*txregs_64
;
254 /* 64-bit dma rx engine registers */
255 struct dma64regs
*rxregs_64
;
256 /* pointer to dma64 tx descriptor ring */
257 struct dma64desc
*txd_64
;
258 /* pointer to dma64 rx descriptor ring */
259 struct dma64desc
*rxd_64
;
263 u16 dmadesc_align
; /* alignment requirement for dma descriptors */
265 u16 ntxd
; /* # tx descriptors tunable */
266 u16 txin
; /* index of next descriptor to reclaim */
267 u16 txout
; /* index of next descriptor to post */
268 /* pointer to parallel array of pointers to packets */
269 struct sk_buff
**txp
;
270 /* Aligned physical address of descriptor ring */
272 /* Original physical address of descriptor ring */
273 dma_addr_t txdpaorig
;
274 u16 txdalign
; /* #bytes added to alloc'd mem to align txd */
275 u32 txdalloc
; /* #bytes allocated for the ring */
276 u32 xmtptrbase
; /* When using unaligned descriptors, the ptr register
277 * is not just an index, it needs all 13 bits to be
278 * an offset from the addr register.
281 u16 nrxd
; /* # rx descriptors tunable */
282 u16 rxin
; /* index of next descriptor to reclaim */
283 u16 rxout
; /* index of next descriptor to post */
284 /* pointer to parallel array of pointers to packets */
285 struct sk_buff
**rxp
;
286 /* Aligned physical address of descriptor ring */
288 /* Original physical address of descriptor ring */
289 dma_addr_t rxdpaorig
;
290 u16 rxdalign
; /* #bytes added to alloc'd mem to align rxd */
291 u32 rxdalloc
; /* #bytes allocated for the ring */
292 u32 rcvptrbase
; /* Base for ptr reg when using unaligned descriptors */
295 unsigned int rxbufsize
; /* rx buffer size in bytes, not including
298 uint rxextrahdrroom
; /* extra rx headroom, reverseved to assist upper
299 * stack, e.g. some rx pkt buffers will be
300 * bridged to tx side without byte copying.
301 * The extra headroom needs to be large enough
302 * to fit txheader needs. Some dongle driver may
305 uint nrxpost
; /* # rx buffers to keep posted */
306 unsigned int rxoffset
; /* rxcontrol offset */
307 /* add to get dma address of descriptor ring, low 32 bits */
311 /* add to get dma address of data buffer, low 32 bits */
315 /* descriptor base need to be aligned or not */
320 * default dma message level (if input msg_level
321 * pointer is null in dma_attach())
323 static uint dma_msg_level
;
325 static uint
_dma_ctrlflags(struct dma_info
*di
, uint mask
, uint flags
)
327 uint dmactrlflags
= di
->dma
.dmactrlflags
;
330 DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di
->name
));
334 dmactrlflags
&= ~mask
;
335 dmactrlflags
|= flags
;
337 /* If trying to enable parity, check if parity is actually supported */
338 if (dmactrlflags
& DMA_CTRL_PEN
) {
341 control
= R_REG(&di
->d64txregs
->control
);
342 W_REG(&di
->d64txregs
->control
,
343 control
| D64_XC_PD
);
344 if (R_REG(&di
->d64txregs
->control
) & D64_XC_PD
)
345 /* We *can* disable it so it is supported,
346 * restore control register
348 W_REG(&di
->d64txregs
->control
,
351 /* Not supported, don't allow it to be enabled */
352 dmactrlflags
&= ~DMA_CTRL_PEN
;
355 di
->dma
.dmactrlflags
= dmactrlflags
;
360 static bool _dma64_addrext(struct dma64regs
*dma64regs
)
363 OR_REG(&dma64regs
->control
, D64_XC_AE
);
364 w
= R_REG(&dma64regs
->control
);
365 AND_REG(&dma64regs
->control
, ~D64_XC_AE
);
366 return (w
& D64_XC_AE
) == D64_XC_AE
;
370 * return true if this dma engine supports DmaExtendedAddrChanges,
373 static bool _dma_isaddrext(struct dma_info
*di
)
375 /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
377 /* not all tx or rx channel are available */
378 if (di
->d64txregs
!= NULL
) {
379 if (!_dma64_addrext(di
->d64txregs
))
380 DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
381 "AE set\n", di
->name
));
383 } else if (di
->d64rxregs
!= NULL
) {
384 if (!_dma64_addrext(di
->d64rxregs
))
385 DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
386 "AE set\n", di
->name
));
393 static bool _dma_descriptor_align(struct dma_info
*di
)
397 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
398 if (di
->d64txregs
!= NULL
) {
399 W_REG(&di
->d64txregs
->addrlow
, 0xff0);
400 addrl
= R_REG(&di
->d64txregs
->addrlow
);
403 } else if (di
->d64rxregs
!= NULL
) {
404 W_REG(&di
->d64rxregs
->addrlow
, 0xff0);
405 addrl
= R_REG(&di
->d64rxregs
->addrlow
);
412 static void *dma_alloc_consistent(struct pci_dev
*pdev
, uint size
,
413 u16 align_bits
, uint
*alloced
,
417 u16 align
= (1 << align_bits
);
418 if (!IS_ALIGNED(PAGE_SIZE
, align
))
422 return pci_alloc_consistent(pdev
, size
, pap
);
426 u8
dma_align_sizetobits(uint size
)
434 /* This function ensures that the DMA descriptor ring will not get allocated
435 * across Page boundary. If the allocation is done across the page boundary
436 * at the first time, then it is freed and the allocation is done at
437 * descriptor ring size aligned location. This will ensure that the ring will
438 * not cross page boundary
440 static void *dma_ringalloc(struct dma_info
*di
, u32 boundary
, uint size
,
441 u16
*alignbits
, uint
*alloced
,
446 u32 alignbytes
= 1 << *alignbits
;
448 va
= dma_alloc_consistent(di
->pbus
, size
, *alignbits
, alloced
, descpa
);
453 desc_strtaddr
= (u32
) roundup((unsigned long)va
, alignbytes
);
454 if (((desc_strtaddr
+ size
- 1) & boundary
) != (desc_strtaddr
456 *alignbits
= dma_align_sizetobits(size
);
457 pci_free_consistent(di
->pbus
, size
, va
, *descpa
);
458 va
= dma_alloc_consistent(di
->pbus
, size
, *alignbits
,
464 static bool dma64_alloc(struct dma_info
*di
, uint direction
)
473 ddlen
= sizeof(struct dma64desc
);
475 size
= (direction
== DMA_TX
) ? (di
->ntxd
* ddlen
) : (di
->nrxd
* ddlen
);
476 align_bits
= di
->dmadesc_align
;
477 align
= (1 << align_bits
);
479 if (direction
== DMA_TX
) {
480 va
= dma_ringalloc(di
, D64RINGALIGN
, size
, &align_bits
,
481 &alloced
, &di
->txdpaorig
);
483 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd)"
484 " failed\n", di
->name
));
487 align
= (1 << align_bits
);
488 di
->txd64
= (struct dma64desc
*)
489 roundup((unsigned long)va
, align
);
490 di
->txdalign
= (uint
) ((s8
*)di
->txd64
- (s8
*) va
);
491 di
->txdpa
= di
->txdpaorig
+ di
->txdalign
;
492 di
->txdalloc
= alloced
;
494 va
= dma_ringalloc(di
, D64RINGALIGN
, size
, &align_bits
,
495 &alloced
, &di
->rxdpaorig
);
497 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd)"
498 " failed\n", di
->name
));
501 align
= (1 << align_bits
);
502 di
->rxd64
= (struct dma64desc
*)
503 roundup((unsigned long)va
, align
);
504 di
->rxdalign
= (uint
) ((s8
*)di
->rxd64
- (s8
*) va
);
505 di
->rxdpa
= di
->rxdpaorig
+ di
->rxdalign
;
506 di
->rxdalloc
= alloced
;
512 static bool _dma_alloc(struct dma_info
*di
, uint direction
)
514 return dma64_alloc(di
, direction
);
517 struct dma_pub
*dma_attach(char *name
, struct si_pub
*sih
,
518 void *dmaregstx
, void *dmaregsrx
, uint ntxd
,
519 uint nrxd
, uint rxbufsize
, int rxextheadroom
,
520 uint nrxpost
, uint rxoffset
, uint
*msg_level
)
525 /* allocate private info structure */
526 di
= kzalloc(sizeof(struct dma_info
), GFP_ATOMIC
);
529 printk(KERN_ERR
"dma_attach: out of memory\n");
534 di
->msg_level
= msg_level
? msg_level
: &dma_msg_level
;
537 di
->dma64
= ((ai_core_sflags(sih
, 0, 0) & SISF_DMA64
) == SISF_DMA64
);
539 /* init dma reg pointer */
540 di
->d64txregs
= (struct dma64regs
*) dmaregstx
;
541 di
->d64rxregs
= (struct dma64regs
*) dmaregsrx
;
544 * Default flags (which can be changed by the driver calling
545 * dma_ctrlflags before enable): For backwards compatibility
546 * both Rx Overflow Continue and Parity are DISABLED.
548 _dma_ctrlflags(di
, DMA_CTRL_ROC
| DMA_CTRL_PEN
, 0);
550 DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
551 "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
552 "dmaregstx %p dmaregsrx %p\n", name
, "DMA64",
553 di
->dma
.dmactrlflags
, ntxd
, nrxd
, rxbufsize
,
554 rxextheadroom
, nrxpost
, rxoffset
, dmaregstx
, dmaregsrx
));
556 /* make a private copy of our callers name */
557 strncpy(di
->name
, name
, MAXNAMEL
);
558 di
->name
[MAXNAMEL
- 1] = '\0';
560 di
->pbus
= ((struct si_info
*)sih
)->pbus
;
563 di
->ntxd
= (u16
) ntxd
;
564 di
->nrxd
= (u16
) nrxd
;
566 /* the actual dma size doesn't include the extra headroom */
568 (rxextheadroom
== -1) ? BCMEXTRAHDROOM
: rxextheadroom
;
569 if (rxbufsize
> BCMEXTRAHDROOM
)
570 di
->rxbufsize
= (u16
) (rxbufsize
- di
->rxextrahdrroom
);
572 di
->rxbufsize
= (u16
) rxbufsize
;
574 di
->nrxpost
= (u16
) nrxpost
;
575 di
->rxoffset
= (u8
) rxoffset
;
578 * figure out the DMA physical address offset for dd and data
579 * PCI/PCIE: they map silicon backplace address to zero
580 * based memory, need offset
581 * Other bus: use zero SI_BUS BIGENDIAN kludge: use sdram
582 * swapped region for data buffer, not descriptor
585 di
->dataoffsetlow
= 0;
586 /* add offset for pcie with DMA64 bus */
588 di
->ddoffsethigh
= SI_PCIE_DMA_H32
;
589 di
->dataoffsetlow
= di
->ddoffsetlow
;
590 di
->dataoffsethigh
= di
->ddoffsethigh
;
591 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
592 if ((ai_coreid(sih
) == SDIOD_CORE_ID
)
593 && ((ai_corerev(sih
) > 0) && (ai_corerev(sih
) <= 2)))
595 else if ((ai_coreid(sih
) == I2S_CORE_ID
) &&
596 ((ai_corerev(sih
) == 0) || (ai_corerev(sih
) == 1)))
599 di
->addrext
= _dma_isaddrext(di
);
601 /* does the descriptor need to be aligned and if yes, on 4K/8K or not */
602 di
->aligndesc_4k
= _dma_descriptor_align(di
);
603 if (di
->aligndesc_4k
) {
604 di
->dmadesc_align
= D64RINGALIGN_BITS
;
605 if ((ntxd
< D64MAXDD
/ 2) && (nrxd
< D64MAXDD
/ 2))
606 /* for smaller dd table, HW relax alignment reqmnt */
607 di
->dmadesc_align
= D64RINGALIGN_BITS
- 1;
609 di
->dmadesc_align
= 4; /* 16 byte alignment */
612 DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
613 di
->aligndesc_4k
, di
->dmadesc_align
));
615 /* allocate tx packet pointer vector */
617 size
= ntxd
* sizeof(void *);
618 di
->txp
= kzalloc(size
, GFP_ATOMIC
);
619 if (di
->txp
== NULL
) {
620 DMA_ERROR(("%s: dma_attach: out of tx memory\n",
626 /* allocate rx packet pointer vector */
628 size
= nrxd
* sizeof(void *);
629 di
->rxp
= kzalloc(size
, GFP_ATOMIC
);
630 if (di
->rxp
== NULL
) {
631 DMA_ERROR(("%s: dma_attach: out of rx memory\n",
638 * allocate transmit descriptor ring, only need ntxd descriptors
639 * but it must be aligned
642 if (!_dma_alloc(di
, DMA_TX
))
647 * allocate receive descriptor ring, only need nrxd descriptors
648 * but it must be aligned
651 if (!_dma_alloc(di
, DMA_RX
))
655 if ((di
->ddoffsetlow
!= 0) && !di
->addrext
) {
656 if (di
->txdpa
> SI_PCI_DMA_SZ
) {
657 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not "
658 "supported\n", di
->name
, (u32
)di
->txdpa
));
661 if (di
->rxdpa
> SI_PCI_DMA_SZ
) {
662 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not "
663 "supported\n", di
->name
, (u32
)di
->rxdpa
));
668 DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x "
669 "dataoffsethigh " "0x%x addrext %d\n", di
->ddoffsetlow
,
670 di
->ddoffsethigh
, di
->dataoffsetlow
, di
->dataoffsethigh
,
673 return (struct dma_pub
*) di
;
676 dma_detach((struct dma_pub
*)di
);
680 /* Check for odd number of 1's */
681 static inline u32
parity32(u32 data
)
693 dma64_dd_upd(struct dma_info
*di
, struct dma64desc
*ddring
,
694 dma_addr_t pa
, uint outidx
, u32
*flags
, u32 bufcount
)
696 u32 ctrl2
= bufcount
& D64_CTRL2_BC_MASK
;
698 /* PCI bus with big(>1G) physical address, use address extension */
699 if ((di
->dataoffsetlow
== 0) || !(pa
& PCI32ADDR_HIGH
)) {
700 ddring
[outidx
].addrlow
= cpu_to_le32(pa
+ di
->dataoffsetlow
);
701 ddring
[outidx
].addrhigh
= cpu_to_le32(di
->dataoffsethigh
);
702 ddring
[outidx
].ctrl1
= cpu_to_le32(*flags
);
703 ddring
[outidx
].ctrl2
= cpu_to_le32(ctrl2
);
705 /* address extension for 32-bit PCI */
708 ae
= (pa
& PCI32ADDR_HIGH
) >> PCI32ADDR_HIGH_SHIFT
;
709 pa
&= ~PCI32ADDR_HIGH
;
711 ctrl2
|= (ae
<< D64_CTRL2_AE_SHIFT
) & D64_CTRL2_AE
;
712 ddring
[outidx
].addrlow
= cpu_to_le32(pa
+ di
->dataoffsetlow
);
713 ddring
[outidx
].addrhigh
= cpu_to_le32(di
->dataoffsethigh
);
714 ddring
[outidx
].ctrl1
= cpu_to_le32(*flags
);
715 ddring
[outidx
].ctrl2
= cpu_to_le32(ctrl2
);
717 if (di
->dma
.dmactrlflags
& DMA_CTRL_PEN
) {
718 if (DMA64_DD_PARITY(&ddring
[outidx
]))
719 ddring
[outidx
].ctrl2
=
720 cpu_to_le32(ctrl2
| D64_CTRL2_PARITY
);
724 /* !! may be called with core in reset */
725 void dma_detach(struct dma_pub
*pub
)
727 struct dma_info
*di
= (struct dma_info
*)pub
;
729 DMA_TRACE(("%s: dma_detach\n", di
->name
));
731 /* free dma descriptor rings */
733 pci_free_consistent(di
->pbus
, di
->txdalloc
,
734 ((s8
*)di
->txd64
- di
->txdalign
),
737 pci_free_consistent(di
->pbus
, di
->rxdalloc
,
738 ((s8
*)di
->rxd64
- di
->rxdalign
),
741 /* free packet pointer vectors */
745 /* free our private info structure */
750 /* initialize descriptor table base address */
752 _dma_ddtable_init(struct dma_info
*di
, uint direction
, dma_addr_t pa
)
754 if (!di
->aligndesc_4k
) {
755 if (direction
== DMA_TX
)
761 if ((di
->ddoffsetlow
== 0)
762 || !(pa
& PCI32ADDR_HIGH
)) {
763 if (direction
== DMA_TX
) {
764 W_REG(&di
->d64txregs
->addrlow
, pa
+ di
->ddoffsetlow
);
765 W_REG(&di
->d64txregs
->addrhigh
, di
->ddoffsethigh
);
767 W_REG(&di
->d64rxregs
->addrlow
, pa
+ di
->ddoffsetlow
);
768 W_REG(&di
->d64rxregs
->addrhigh
, di
->ddoffsethigh
);
771 /* DMA64 32bits address extension */
774 /* shift the high bit(s) from pa to ae */
775 ae
= (pa
& PCI32ADDR_HIGH
) >> PCI32ADDR_HIGH_SHIFT
;
776 pa
&= ~PCI32ADDR_HIGH
;
778 if (direction
== DMA_TX
) {
779 W_REG(&di
->d64txregs
->addrlow
, pa
+ di
->ddoffsetlow
);
780 W_REG(&di
->d64txregs
->addrhigh
, di
->ddoffsethigh
);
781 SET_REG(&di
->d64txregs
->control
,
782 D64_XC_AE
, (ae
<< D64_XC_AE_SHIFT
));
784 W_REG(&di
->d64rxregs
->addrlow
, pa
+ di
->ddoffsetlow
);
785 W_REG(&di
->d64rxregs
->addrhigh
, di
->ddoffsethigh
);
786 SET_REG(&di
->d64rxregs
->control
,
787 D64_RC_AE
, (ae
<< D64_RC_AE_SHIFT
));
792 static void _dma_rxenable(struct dma_info
*di
)
794 uint dmactrlflags
= di
->dma
.dmactrlflags
;
797 DMA_TRACE(("%s: dma_rxenable\n", di
->name
));
800 (R_REG(&di
->d64rxregs
->control
) & D64_RC_AE
) |
803 if ((dmactrlflags
& DMA_CTRL_PEN
) == 0)
804 control
|= D64_RC_PD
;
806 if (dmactrlflags
& DMA_CTRL_ROC
)
807 control
|= D64_RC_OC
;
809 W_REG(&di
->d64rxregs
->control
,
810 ((di
->rxoffset
<< D64_RC_RO_SHIFT
) | control
));
813 void dma_rxinit(struct dma_pub
*pub
)
815 struct dma_info
*di
= (struct dma_info
*)pub
;
817 DMA_TRACE(("%s: dma_rxinit\n", di
->name
));
822 di
->rxin
= di
->rxout
= 0;
824 /* clear rx descriptor ring */
825 memset(di
->rxd64
, '\0', di
->nrxd
* sizeof(struct dma64desc
));
827 /* DMA engine with out alignment requirement requires table to be inited
828 * before enabling the engine
830 if (!di
->aligndesc_4k
)
831 _dma_ddtable_init(di
, DMA_RX
, di
->rxdpa
);
835 if (di
->aligndesc_4k
)
836 _dma_ddtable_init(di
, DMA_RX
, di
->rxdpa
);
839 static struct sk_buff
*dma64_getnextrxp(struct dma_info
*di
, bool forceall
)
847 /* return if no packets posted */
852 B2I(((R_REG(&di
->d64rxregs
->status0
) & D64_RS0_CD_MASK
) -
853 di
->rcvptrbase
) & D64_RS0_CD_MASK
, struct dma64desc
);
855 /* ignore curr if forceall */
856 if (!forceall
&& (i
== curr
))
859 /* get the packet pointer that corresponds to the rx descriptor */
863 pa
= cpu_to_le32(di
->rxd64
[i
].addrlow
) - di
->dataoffsetlow
;
865 /* clear this packet from the descriptor ring */
866 pci_unmap_single(di
->pbus
, pa
, di
->rxbufsize
, PCI_DMA_FROMDEVICE
);
868 di
->rxd64
[i
].addrlow
= 0xdeadbeef;
869 di
->rxd64
[i
].addrhigh
= 0xdeadbeef;
871 di
->rxin
= NEXTRXD(i
);
876 static struct sk_buff
*_dma_getnextrxp(struct dma_info
*di
, bool forceall
)
881 return dma64_getnextrxp(di
, forceall
);
885 * !! rx entry routine
886 * returns a pointer to the next frame received, or NULL if there are no more
887 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is
888 * supported with pkts chain
889 * otherwise, it's treated as giant pkt and will be tossed.
890 * The DMA scattering starts with normal DMA header, followed by first
891 * buffer data. After it reaches the max size of buffer, the data continues
892 * in next DMA descriptor buffer WITHOUT DMA header
894 struct sk_buff
*dma_rx(struct dma_pub
*pub
)
896 struct dma_info
*di
= (struct dma_info
*)pub
;
897 struct sk_buff
*p
, *head
, *tail
;
903 head
= _dma_getnextrxp(di
, false);
907 len
= le16_to_cpu(*(u16
*) (head
->data
));
908 DMA_TRACE(("%s: dma_rx len %d\n", di
->name
, len
));
909 dma_spin_for_len(len
, head
);
911 /* set actual length */
912 pkt_len
= min((di
->rxoffset
+ len
), di
->rxbufsize
);
913 __skb_trim(head
, pkt_len
);
914 resid
= len
- (di
->rxbufsize
- di
->rxoffset
);
916 /* check for single or multi-buffer rx */
919 while ((resid
> 0) && (p
= _dma_getnextrxp(di
, false))) {
921 pkt_len
= min_t(uint
, resid
, di
->rxbufsize
);
922 __skb_trim(p
, pkt_len
);
925 resid
-= di
->rxbufsize
;
932 B2I(((R_REG(&di
->d64rxregs
->status0
) &
934 di
->rcvptrbase
) & D64_RS0_CD_MASK
,
936 DMA_ERROR(("dma_rx, rxin %d rxout %d, hw_curr %d\n",
937 di
->rxin
, di
->rxout
, cur
));
941 if ((di
->dma
.dmactrlflags
& DMA_CTRL_RXMULTI
) == 0) {
942 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
944 brcmu_pkt_buf_free_skb(head
);
953 static bool dma64_rxidle(struct dma_info
*di
)
955 DMA_TRACE(("%s: dma_rxidle\n", di
->name
));
960 return ((R_REG(&di
->d64rxregs
->status0
) & D64_RS0_CD_MASK
) ==
961 (R_REG(&di
->d64rxregs
->ptr
) & D64_RS0_CD_MASK
));
965 * post receive buffers
966 * return false is refill failed completely and ring is empty this will stall
967 * the rx dma and user might want to call rxfill again asap. This unlikely
968 * happens on memory-rich NIC, but often on memory-constrained dongle
970 bool dma_rxfill(struct dma_pub
*pub
)
972 struct dma_info
*di
= (struct dma_info
*)pub
;
979 uint extra_offset
= 0;
985 * Determine how many receive buffers we're lacking
986 * from the full complement, allocate, initialize,
987 * and post them, then update the chip rx lastdscr.
993 n
= di
->nrxpost
- NRXDACTIVE(rxin
, rxout
);
995 DMA_TRACE(("%s: dma_rxfill: post %d\n", di
->name
, n
));
997 if (di
->rxbufsize
> BCMEXTRAHDROOM
)
998 extra_offset
= di
->rxextrahdrroom
;
1000 for (i
= 0; i
< n
; i
++) {
1002 * the di->rxbufsize doesn't include the extra headroom,
1003 * we need to add it to the size to be allocated
1005 p
= brcmu_pkt_buf_get_skb(di
->rxbufsize
+ extra_offset
);
1008 DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
1010 if (i
== 0 && dma64_rxidle(di
)) {
1011 DMA_ERROR(("%s: rxfill64: ring is empty !\n",
1018 /* reserve an extra headroom, if applicable */
1020 skb_pull(p
, extra_offset
);
1022 /* Do a cached write instead of uncached write since DMA_MAP
1023 * will flush the cache.
1025 *(u32
*) (p
->data
) = 0;
1027 pa
= pci_map_single(di
->pbus
, p
->data
,
1028 di
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1030 /* save the free packet pointer */
1033 /* reset flags for each descriptor */
1035 if (rxout
== (di
->nrxd
- 1))
1036 flags
= D64_CTRL1_EOT
;
1038 dma64_dd_upd(di
, di
->rxd64
, pa
, rxout
, &flags
,
1040 rxout
= NEXTRXD(rxout
);
1045 /* update the chip lastdscr pointer */
1046 W_REG(&di
->d64rxregs
->ptr
,
1047 di
->rcvptrbase
+ I2B(rxout
, struct dma64desc
));
1052 void dma_rxreclaim(struct dma_pub
*pub
)
1054 struct dma_info
*di
= (struct dma_info
*)pub
;
1057 DMA_TRACE(("%s: dma_rxreclaim\n", di
->name
));
1059 while ((p
= _dma_getnextrxp(di
, true)))
1060 brcmu_pkt_buf_free_skb(p
);
1063 void dma_counterreset(struct dma_pub
*pub
)
1065 /* reset all software counters */
1071 /* get the address of the var in order to change later */
1072 unsigned long dma_getvar(struct dma_pub
*pub
, const char *name
)
1074 struct dma_info
*di
= (struct dma_info
*)pub
;
1076 if (!strcmp(name
, "&txavail"))
1077 return (unsigned long)&(di
->dma
.txavail
);
1081 /* 64-bit DMA functions */
1083 void dma_txinit(struct dma_pub
*pub
)
1085 struct dma_info
*di
= (struct dma_info
*)pub
;
1086 u32 control
= D64_XC_XE
;
1088 DMA_TRACE(("%s: dma_txinit\n", di
->name
));
1093 di
->txin
= di
->txout
= 0;
1094 di
->dma
.txavail
= di
->ntxd
- 1;
1096 /* clear tx descriptor ring */
1097 memset(di
->txd64
, '\0', (di
->ntxd
* sizeof(struct dma64desc
)));
1099 /* DMA engine with out alignment requirement requires table to be inited
1100 * before enabling the engine
1102 if (!di
->aligndesc_4k
)
1103 _dma_ddtable_init(di
, DMA_TX
, di
->txdpa
);
1105 if ((di
->dma
.dmactrlflags
& DMA_CTRL_PEN
) == 0)
1106 control
|= D64_XC_PD
;
1107 OR_REG(&di
->d64txregs
->control
, control
);
1109 /* DMA engine with alignment requirement requires table to be inited
1110 * before enabling the engine
1112 if (di
->aligndesc_4k
)
1113 _dma_ddtable_init(di
, DMA_TX
, di
->txdpa
);
1116 void dma_txsuspend(struct dma_pub
*pub
)
1118 struct dma_info
*di
= (struct dma_info
*)pub
;
1120 DMA_TRACE(("%s: dma_txsuspend\n", di
->name
));
1125 OR_REG(&di
->d64txregs
->control
, D64_XC_SE
);
1128 void dma_txresume(struct dma_pub
*pub
)
1130 struct dma_info
*di
= (struct dma_info
*)pub
;
1132 DMA_TRACE(("%s: dma_txresume\n", di
->name
));
1137 AND_REG(&di
->d64txregs
->control
, ~D64_XC_SE
);
1140 bool dma_txsuspended(struct dma_pub
*pub
)
1142 struct dma_info
*di
= (struct dma_info
*)pub
;
1144 return (di
->ntxd
== 0) ||
1145 ((R_REG(&di
->d64txregs
->control
) & D64_XC_SE
) ==
1149 void dma_txreclaim(struct dma_pub
*pub
, enum txd_range range
)
1151 struct dma_info
*di
= (struct dma_info
*)pub
;
1154 DMA_TRACE(("%s: dma_txreclaim %s\n", di
->name
,
1155 (range
== DMA_RANGE_ALL
) ? "all" :
1157 DMA_RANGE_TRANSMITTED
) ? "transmitted" :
1160 if (di
->txin
== di
->txout
)
1163 while ((p
= dma_getnexttxp(pub
, range
))) {
1164 /* For unframed data, we don't have any packets to free */
1165 if (!(di
->dma
.dmactrlflags
& DMA_CTRL_UNFRAMED
))
1166 brcmu_pkt_buf_free_skb(p
);
1170 bool dma_txreset(struct dma_pub
*pub
)
1172 struct dma_info
*di
= (struct dma_info
*)pub
;
1178 /* suspend tx DMA first */
1179 W_REG(&di
->d64txregs
->control
, D64_XC_SE
);
1181 (R_REG(&di
->d64txregs
->status0
) & D64_XS0_XS_MASK
))
1182 != D64_XS0_XS_DISABLED
) && (status
!= D64_XS0_XS_IDLE
)
1183 && (status
!= D64_XS0_XS_STOPPED
), 10000);
1185 W_REG(&di
->d64txregs
->control
, 0);
1187 (R_REG(&di
->d64txregs
->status0
) & D64_XS0_XS_MASK
))
1188 != D64_XS0_XS_DISABLED
), 10000);
1190 /* wait for the last transaction to complete */
1193 return status
== D64_XS0_XS_DISABLED
;
1196 bool dma_rxreset(struct dma_pub
*pub
)
1198 struct dma_info
*di
= (struct dma_info
*)pub
;
1204 W_REG(&di
->d64rxregs
->control
, 0);
1206 (R_REG(&di
->d64rxregs
->status0
) & D64_RS0_RS_MASK
))
1207 != D64_RS0_RS_DISABLED
), 10000);
1209 return status
== D64_RS0_RS_DISABLED
;
1213 * !! tx entry routine
1214 * WARNING: call must check the return value for error.
1215 * the error(toss frames) could be fatal and cause many subsequent hard
1218 int dma_txfast(struct dma_pub
*pub
, struct sk_buff
*p0
, bool commit
)
1220 struct dma_info
*di
= (struct dma_info
*)pub
;
1221 struct sk_buff
*p
, *next
;
1222 unsigned char *data
;
1228 DMA_TRACE(("%s: dma_txfast\n", di
->name
));
1233 * Walk the chain of packet buffers
1234 * allocating and initializing transmit descriptor entries.
1236 for (p
= p0
; p
; p
= next
) {
1241 /* return nonzero if out of tx descriptors */
1242 if (NEXTTXD(txout
) == di
->txin
)
1248 /* get physical address of buffer start */
1249 pa
= pci_map_single(di
->pbus
, data
, len
, PCI_DMA_TODEVICE
);
1253 flags
|= D64_CTRL1_SOF
;
1255 /* With a DMA segment list, Descriptor table is filled
1256 * using the segment list instead of looping over
1257 * buffers in multi-chain DMA. Therefore, EOF for SGLIST
1258 * is when end of segment list is reached.
1261 flags
|= (D64_CTRL1_IOC
| D64_CTRL1_EOF
);
1262 if (txout
== (di
->ntxd
- 1))
1263 flags
|= D64_CTRL1_EOT
;
1265 dma64_dd_upd(di
, di
->txd64
, pa
, txout
, &flags
, len
);
1267 txout
= NEXTTXD(txout
);
1270 /* if last txd eof not set, fix it */
1271 if (!(flags
& D64_CTRL1_EOF
))
1272 di
->txd64
[PREVTXD(txout
)].ctrl1
=
1273 cpu_to_le32(flags
| D64_CTRL1_IOC
| D64_CTRL1_EOF
);
1275 /* save the packet */
1276 di
->txp
[PREVTXD(txout
)] = p0
;
1278 /* bump the tx descriptor index */
1283 W_REG(&di
->d64txregs
->ptr
,
1284 di
->xmtptrbase
+ I2B(txout
, struct dma64desc
));
1286 /* tx flow control */
1287 di
->dma
.txavail
= di
->ntxd
- NTXDACTIVE(di
->txin
, di
->txout
) - 1;
1292 DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di
->name
));
1293 brcmu_pkt_buf_free_skb(p0
);
1294 di
->dma
.txavail
= 0;
1300 * Reclaim next completed txd (txds if using chained buffers) in the range
1301 * specified and return associated packet.
1302 * If range is DMA_RANGE_TRANSMITTED, reclaim descriptors that have be
1303 * transmitted as noted by the hardware "CurrDescr" pointer.
1304 * If range is DMA_RANGE_TRANSFERED, reclaim descriptors that have be
1305 * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
1306 * If range is DMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
1307 * return associated packet regardless of the value of hardware pointers.
1309 struct sk_buff
*dma_getnexttxp(struct dma_pub
*pub
, enum txd_range range
)
1311 struct dma_info
*di
= (struct dma_info
*)pub
;
1314 struct sk_buff
*txp
;
1316 DMA_TRACE(("%s: dma_getnexttxp %s\n", di
->name
,
1317 (range
== DMA_RANGE_ALL
) ? "all" :
1319 DMA_RANGE_TRANSMITTED
) ? "transmitted" :
1328 if (range
== DMA_RANGE_ALL
)
1331 struct dma64regs
*dregs
= di
->d64txregs
;
1333 end
= (u16
) (B2I(((R_REG(&dregs
->status0
) &
1335 di
->xmtptrbase
) & D64_XS0_CD_MASK
,
1338 if (range
== DMA_RANGE_TRANSFERED
) {
1340 (u16
) (R_REG(&dregs
->status1
) &
1343 (active_desc
- di
->xmtptrbase
) & D64_XS0_CD_MASK
;
1344 active_desc
= B2I(active_desc
, struct dma64desc
);
1345 if (end
!= active_desc
)
1346 end
= PREVTXD(active_desc
);
1350 if ((start
== 0) && (end
> di
->txout
))
1353 for (i
= start
; i
!= end
&& !txp
; i
= NEXTTXD(i
)) {
1357 pa
= cpu_to_le32(di
->txd64
[i
].addrlow
) - di
->dataoffsetlow
;
1360 (cpu_to_le32(di
->txd64
[i
].ctrl2
) &
1363 di
->txd64
[i
].addrlow
= 0xdeadbeef;
1364 di
->txd64
[i
].addrhigh
= 0xdeadbeef;
1369 pci_unmap_single(di
->pbus
, pa
, size
, PCI_DMA_TODEVICE
);
1374 /* tx flow control */
1375 di
->dma
.txavail
= di
->ntxd
- NTXDACTIVE(di
->txin
, di
->txout
) - 1;
1380 DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d "
1381 "force %d\n", start
, end
, di
->txout
, forceall
));
1386 * Mac80211 initiated actions sometimes require packets in the DMA queue to be
1387 * modified. The modified portion of the packet is not under control of the DMA
1388 * engine. This function calls a caller-supplied function for each packet in
1389 * the caller specified dma chain.
1391 void dma_walk_packets(struct dma_pub
*dmah
, void (*callback_fnc
)
1392 (void *pkt
, void *arg_a
), void *arg_a
)
1394 struct dma_info
*di
= (struct dma_info
*) dmah
;
1396 uint end
= di
->txout
;
1397 struct sk_buff
*skb
;
1398 struct ieee80211_tx_info
*tx_info
;
1401 skb
= (struct sk_buff
*)di
->txp
[i
];
1403 tx_info
= (struct ieee80211_tx_info
*)skb
->cb
;
1404 (callback_fnc
)(tx_info
, arg_a
);