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1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23
24 #include <proto/802.11.h>
25 #include <bcmdefs.h>
26 #include <bcmdevs.h>
27 #include <bcmwifi.h>
28 #include <siutils.h>
29 #include <bcmsrom.h>
30 #include <bcmotp.h>
31 #include <bcmutils.h>
32 #include <wlioctl.h>
33 #include <sbconfig.h>
34 #include <sbchipc.h>
35 #include <pcicfg.h>
36 #include <sbhnddma.h>
37 #include <hnddma.h>
38 #include <hndpmu.h>
39
40 #include "wlc_types.h"
41 #include "d11.h"
42 #include "wlc_cfg.h"
43 #include "wlc_rate.h"
44 #include "wlc_scb.h"
45 #include "wlc_pub.h"
46 #include "wlc_key.h"
47 #include "wlc_phy_shim.h"
48 #include "phy/wlc_phy_hal.h"
49 #include "wlc_channel.h"
50 #include "wlc_main.h"
51 #include "wl_export.h"
52 #include "wl_ucode.h"
53 #include "wlc_antsel.h"
54 #include "pcie_core.h"
55 #include "wlc_alloc.h"
56 #include "wl_dbg.h"
57 #include "wlc_bmac.h"
58
59 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
60
61 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
62 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
63 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
64 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
65
66 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
67
68 #ifndef BMAC_DUP_TO_REMOVE
69 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
70
71 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
72
73 #endif /* BMAC_DUP_TO_REMOVE */
74
75 #define DMAREG(wlc_hw, direction, fifonum) \
76 ((direction == DMA_TX) ? \
77 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
78 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
79
80 /*
81 * The following table lists the buffer memory allocated to xmt fifos in HW.
82 * the size is in units of 256bytes(one block), total size is HW dependent
83 * ucode has default fifo partition, sw can overwrite if necessary
84 *
85 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
86 * the twiki is updated before making changes.
87 */
88
89 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
90
91 static u16 xmtfifo_sz[][NFIFO] = {
92 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
93 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
94 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
95 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
96 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
97 };
98
99 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
100 static void wlc_coreinit(struct wlc_info *wlc);
101
102 /* used by wlc_wakeucode_init() */
103 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
104 const struct d11init *inits);
105 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
106 const uint nbytes);
107 static void wlc_ucode_download(struct wlc_hw_info *wlc);
108 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
109
110 /* used by wlc_dpc() */
111 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
112 u32 s2);
113 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
114 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
115
116 /* used by wlc_down() */
117 static void wlc_flushqueues(struct wlc_info *wlc);
118
119 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
120 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
121 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
122 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
123 uint tx_fifo);
124 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
125 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
126
127 /* Low Level Prototypes */
128 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
129 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
130 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
131 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
132 u32 sel);
133 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
134 u16 v, u32 sel);
135 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
136 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
137 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
138 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
139 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
140 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
141 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
142 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
143 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
144 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
145 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
146 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
147 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
148 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
149 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
150 static void wlc_gpio_init(struct wlc_info *wlc);
151 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
152 int len);
153 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
154 int len);
155 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
156 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
157 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
158 chanspec_t chanspec);
159 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
160 bool shortslot);
161 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
162 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
163 u8 rate);
164
165 /* === Low Level functions === */
166
167 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
168 {
169 wlc_hw->shortslot = shortslot;
170
171 if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
172 wlc_suspend_mac_and_wait(wlc_hw->wlc);
173 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
174 wlc_enable_mac(wlc_hw->wlc);
175 }
176 }
177
178 /*
179 * Update the slot timing for standard 11b/g (20us slots)
180 * or shortslot 11g (9us slots)
181 * The PSM needs to be suspended for this call.
182 */
183 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
184 bool shortslot)
185 {
186 d11regs_t *regs;
187
188 regs = wlc_hw->regs;
189
190 if (shortslot) {
191 /* 11g short slot: 11a timing */
192 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
193 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
194 } else {
195 /* 11g long slot: 11b timing */
196 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
197 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
198 }
199 }
200
201 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
202 {
203 /* init microcode host flags */
204 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
205
206 /* do band-specific ucode IHR, SHM, and SCR inits */
207 if (D11REV_IS(wlc_hw->corerev, 23)) {
208 if (WLCISNPHY(wlc_hw->band)) {
209 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
210 } else {
211 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
212 __func__, wlc_hw->unit, wlc_hw->corerev);
213 }
214 } else {
215 if (D11REV_IS(wlc_hw->corerev, 24)) {
216 if (WLCISLCNPHY(wlc_hw->band)) {
217 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
218 } else
219 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
220 __func__, wlc_hw->unit,
221 wlc_hw->corerev);
222 } else {
223 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
224 __func__, wlc_hw->unit, wlc_hw->corerev);
225 }
226 }
227 }
228
229 /* switch to new band but leave it inactive */
230 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
231 {
232 struct wlc_hw_info *wlc_hw = wlc->hw;
233 u32 macintmask;
234
235 WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
236
237 ASSERT(bandunit != wlc_hw->band->bandunit);
238 ASSERT(si_iscoreup(wlc_hw->sih));
239 ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
240 0);
241
242 /* disable interrupts */
243 macintmask = wl_intrsoff(wlc->wl);
244
245 /* radio off */
246 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
247
248 ASSERT(wlc_hw->clk);
249
250 wlc_bmac_core_phy_clk(wlc_hw, OFF);
251
252 wlc_setxband(wlc_hw, bandunit);
253
254 return macintmask;
255 }
256
257 /* Process received frames */
258 /*
259 * Return true if more frames need to be processed. false otherwise.
260 * Param 'bound' indicates max. # frames to process before break out.
261 */
262 static bool BCMFASTPATH
263 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
264 {
265 struct sk_buff *p;
266 struct sk_buff *head = NULL;
267 struct sk_buff *tail = NULL;
268 uint n = 0;
269 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
270 u32 tsf_h, tsf_l;
271 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
272
273 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
274 /* gather received frames */
275 while ((p = dma_rx(wlc_hw->di[fifo]))) {
276
277 if (!tail)
278 head = tail = p;
279 else {
280 tail->prev = p;
281 tail = p;
282 }
283
284 /* !give others some time to run! */
285 if (++n >= bound_limit)
286 break;
287 }
288
289 /* get the TSF REG reading */
290 wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
291
292 /* post more rbufs */
293 dma_rxfill(wlc_hw->di[fifo]);
294
295 /* process each frame */
296 while ((p = head) != NULL) {
297 head = head->prev;
298 p->prev = NULL;
299
300 /* record the tsf_l in wlc_rxd11hdr */
301 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
302 wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
303
304 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
305 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
306
307 wlc_recv(wlc_hw->wlc, p);
308 }
309
310 return n >= bound_limit;
311 }
312
313 /* second-level interrupt processing
314 * Return true if another dpc needs to be re-scheduled. false otherwise.
315 * Param 'bounded' indicates if applicable loops should be bounded.
316 */
317 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
318 {
319 u32 macintstatus;
320 struct wlc_hw_info *wlc_hw = wlc->hw;
321 d11regs_t *regs = wlc_hw->regs;
322 bool fatal = false;
323
324 if (DEVICEREMOVED(wlc)) {
325 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
326 wl_down(wlc->wl);
327 return false;
328 }
329
330 /* grab and clear the saved software intstatus bits */
331 macintstatus = wlc->macintstatus;
332 wlc->macintstatus = 0;
333
334 WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
335 wlc_hw->unit, macintstatus);
336
337 if (macintstatus & MI_PRQ) {
338 /* Process probe request FIFO */
339 ASSERT(0 && "PRQ Interrupt in non-MBSS");
340 }
341
342 /* BCN template is available */
343 /* ZZZ: Use AP_ACTIVE ? */
344 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
345 && (macintstatus & MI_BCNTPL)) {
346 wlc_update_beacon(wlc);
347 }
348
349 /* PMQ entry addition */
350 if (macintstatus & MI_PMQ) {
351 }
352
353 /* tx status */
354 if (macintstatus & MI_TFS) {
355 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
356 wlc->macintstatus |= MI_TFS;
357 if (fatal) {
358 WL_ERROR("MI_TFS: fatal\n");
359 goto fatal;
360 }
361 }
362
363 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
364 wlc_tbtt(wlc, regs);
365
366 /* ATIM window end */
367 if (macintstatus & MI_ATIMWINEND) {
368 WL_TRACE("wlc_isr: end of ATIM window\n");
369
370 OR_REG(&regs->maccommand, wlc->qvalid);
371 wlc->qvalid = 0;
372 }
373
374 /* phy tx error */
375 if (macintstatus & MI_PHYTXERR) {
376 wlc->pub->_cnt->txphyerr++;
377 }
378
379 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
380 if (macintstatus & MI_DMAINT) {
381 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
382 wlc->macintstatus |= MI_DMAINT;
383 }
384 }
385
386 /* TX FIFO suspend/flush completion */
387 if (macintstatus & MI_TXSTOP) {
388 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
389 /* WL_ERROR("dpc: fifo_suspend_comlete\n"); */
390 }
391 }
392
393 /* noise sample collected */
394 if (macintstatus & MI_BG_NOISE) {
395 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
396 }
397
398 if (macintstatus & MI_GP0) {
399 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
400 wlc_hw->unit, wlc_hw->now);
401
402 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
403 __func__, wlc_hw->sih->chip,
404 wlc_hw->sih->chiprev);
405
406 wlc->pub->_cnt->psmwds++;
407
408 /* big hammer */
409 wl_init(wlc->wl);
410 }
411
412 /* gptimer timeout */
413 if (macintstatus & MI_TO) {
414 W_REG(&regs->gptimer, 0);
415 }
416
417 if (macintstatus & MI_RFDISABLE) {
418 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
419
420 wlc->pub->_cnt->rfdisable++;
421 wl_rfkill_set_hw_state(wlc->wl);
422 }
423
424 /* send any enq'd tx packets. Just makes sure to jump start tx */
425 if (!pktq_empty(&wlc->active_queue->q))
426 wlc_send_q(wlc, wlc->active_queue);
427
428 ASSERT(wlc_ps_check(wlc));
429
430 /* make sure the bound indication and the implementation are in sync */
431 ASSERT(bounded == true || wlc->macintstatus == 0);
432
433 /* it isn't done and needs to be resched if macintstatus is non-zero */
434 return wlc->macintstatus != 0;
435
436 fatal:
437 wl_init(wlc->wl);
438 return wlc->macintstatus != 0;
439 }
440
441 /* common low-level watchdog code */
442 void wlc_bmac_watchdog(void *arg)
443 {
444 struct wlc_info *wlc = (struct wlc_info *) arg;
445 struct wlc_hw_info *wlc_hw = wlc->hw;
446
447 WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
448
449 if (!wlc_hw->up)
450 return;
451
452 /* increment second count */
453 wlc_hw->now++;
454
455 /* Check for FIFO error interrupts */
456 wlc_bmac_fifoerrors(wlc_hw);
457
458 /* make sure RX dma has buffers */
459 dma_rxfill(wlc->hw->di[RX_FIFO]);
460
461 wlc_phy_watchdog(wlc_hw->band->pi);
462 }
463
464 void
465 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
466 bool mute, struct txpwr_limits *txpwr)
467 {
468 uint bandunit;
469
470 WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
471 wlc_hw->unit, chanspec);
472
473 wlc_hw->chanspec = chanspec;
474
475 /* Switch bands if necessary */
476 if (NBANDS_HW(wlc_hw) > 1) {
477 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
478 if (wlc_hw->band->bandunit != bandunit) {
479 /* wlc_bmac_setband disables other bandunit,
480 * use light band switch if not up yet
481 */
482 if (wlc_hw->up) {
483 wlc_phy_chanspec_radio_set(wlc_hw->
484 bandstate[bandunit]->
485 pi, chanspec);
486 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
487 } else {
488 wlc_setxband(wlc_hw, bandunit);
489 }
490 }
491 }
492
493 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
494
495 if (!wlc_hw->up) {
496 if (wlc_hw->clk)
497 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
498 chanspec);
499 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
500 } else {
501 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
502 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
503
504 /* Update muting of the channel */
505 wlc_bmac_mute(wlc_hw, mute, 0);
506 }
507 }
508
509 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
510 {
511 state->machwcap = wlc_hw->machwcap;
512
513 return 0;
514 }
515
516 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
517 {
518 uint i;
519 char name[8];
520 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
521 u16 pio_mhf2 = 0;
522 struct wlc_hw_info *wlc_hw = wlc->hw;
523 uint unit = wlc_hw->unit;
524 wlc_tunables_t *tune = wlc->pub->tunables;
525
526 /* name and offsets for dma_attach */
527 snprintf(name, sizeof(name), "wl%d", unit);
528
529 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
530 uint addrwidth;
531 int dma_attach_err = 0;
532 /* Find out the DMA addressing capability and let OS know
533 * All the channels within one DMA core have 'common-minimum' same
534 * capability
535 */
536 addrwidth =
537 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
538
539 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
540 WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
541 unit);
542 return false;
543 }
544
545 /*
546 * FIFO 0
547 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
548 * RX: RX_FIFO (RX data packets)
549 */
550 ASSERT(TX_AC_BK_FIFO == 0);
551 ASSERT(RX_FIFO == 0);
552 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
553 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
554 NULL), DMAREG(wlc_hw, DMA_RX, 0),
555 (wme ? tune->ntxd : 0), tune->nrxd,
556 tune->rxbufsz, -1, tune->nrxbufpost,
557 WL_HWRXOFF, &wl_msg_level);
558 dma_attach_err |= (NULL == wlc_hw->di[0]);
559
560 /*
561 * FIFO 1
562 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
563 * (legacy) TX_DATA_FIFO (TX data packets)
564 * RX: UNUSED
565 */
566 ASSERT(TX_AC_BE_FIFO == 1);
567 ASSERT(TX_DATA_FIFO == 1);
568 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
569 DMAREG(wlc_hw, DMA_TX, 1), NULL,
570 tune->ntxd, 0, 0, -1, 0, 0,
571 &wl_msg_level);
572 dma_attach_err |= (NULL == wlc_hw->di[1]);
573
574 /*
575 * FIFO 2
576 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
577 * RX: UNUSED
578 */
579 ASSERT(TX_AC_VI_FIFO == 2);
580 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
581 DMAREG(wlc_hw, DMA_TX, 2), NULL,
582 tune->ntxd, 0, 0, -1, 0, 0,
583 &wl_msg_level);
584 dma_attach_err |= (NULL == wlc_hw->di[2]);
585 /*
586 * FIFO 3
587 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
588 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
589 */
590 ASSERT(TX_AC_VO_FIFO == 3);
591 ASSERT(TX_CTL_FIFO == 3);
592 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
593 DMAREG(wlc_hw, DMA_TX, 3),
594 NULL, tune->ntxd, 0, 0, -1,
595 0, 0, &wl_msg_level);
596 dma_attach_err |= (NULL == wlc_hw->di[3]);
597 /* Cleaner to leave this as if with AP defined */
598
599 if (dma_attach_err) {
600 WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
601 return false;
602 }
603
604 /* get pointer to dma engine tx flow control variable */
605 for (i = 0; i < NFIFO; i++)
606 if (wlc_hw->di[i])
607 wlc_hw->txavail[i] =
608 (uint *) dma_getvar(wlc_hw->di[i],
609 "&txavail");
610 }
611
612 /* initial ucode host flags */
613 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
614
615 return true;
616 }
617
618 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
619 {
620 uint j;
621
622 for (j = 0; j < NFIFO; j++) {
623 if (wlc_hw->di[j]) {
624 dma_detach(wlc_hw->di[j]);
625 wlc_hw->di[j] = NULL;
626 }
627 }
628 }
629
630 /* low level attach
631 * run backplane attach, init nvram
632 * run phy attach
633 * initialize software state for each core and band
634 * put the whole chip in reset(driver down state), no clock
635 */
636 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
637 bool piomode, void *regsva, uint bustype, void *btparam)
638 {
639 struct wlc_hw_info *wlc_hw;
640 d11regs_t *regs;
641 char *macaddr = NULL;
642 char *vars;
643 uint err = 0;
644 uint j;
645 bool wme = false;
646 shared_phy_params_t sha_params;
647
648 WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
649 unit, vendor, device);
650
651 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
652
653 wme = true;
654
655 wlc_hw = wlc->hw;
656 wlc_hw->wlc = wlc;
657 wlc_hw->unit = unit;
658 wlc_hw->band = wlc_hw->bandstate[0];
659 wlc_hw->_piomode = piomode;
660
661 /* populate struct wlc_hw_info with default values */
662 wlc_bmac_info_init(wlc_hw);
663
664 /*
665 * Do the hardware portion of the attach.
666 * Also initialize software state that depends on the particular hardware
667 * we are running.
668 */
669 wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
670 &wlc_hw->vars, &wlc_hw->vars_size);
671 if (wlc_hw->sih == NULL) {
672 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
673 err = 11;
674 goto fail;
675 }
676 vars = wlc_hw->vars;
677
678 /*
679 * Get vendid/devid nvram overwrites, which could be different
680 * than those the BIOS recognizes for devices on PCMCIA_BUS,
681 * SDIO_BUS, and SROMless devices on PCI_BUS.
682 */
683 #ifdef BCMBUSTYPE
684 bustype = BCMBUSTYPE;
685 #endif
686 if (bustype != SI_BUS) {
687 char *var;
688
689 var = getvar(vars, "vendid");
690 if (var) {
691 vendor = (u16) simple_strtoul(var, NULL, 0);
692 WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
693 }
694 var = getvar(vars, "devid");
695 if (var) {
696 u16 devid = (u16) simple_strtoul(var, NULL, 0);
697 if (devid != 0xffff) {
698 device = devid;
699 WL_ERROR("Overriding device id = 0x%x\n",
700 device);
701 }
702 }
703
704 /* verify again the device is supported */
705 if (!wlc_chipmatch(vendor, device)) {
706 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
707 unit, vendor, device);
708 err = 12;
709 goto fail;
710 }
711 }
712
713 wlc_hw->vendorid = vendor;
714 wlc_hw->deviceid = device;
715
716 /* set bar0 window to point at D11 core */
717 wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
718 wlc_hw->corerev = si_corerev(wlc_hw->sih);
719
720 regs = wlc_hw->regs;
721
722 wlc->regs = wlc_hw->regs;
723
724 /* validate chip, chiprev and corerev */
725 if (!wlc_isgoodchip(wlc_hw)) {
726 err = 13;
727 goto fail;
728 }
729
730 /* initialize power control registers */
731 si_clkctl_init(wlc_hw->sih);
732
733 /* request fastclock and force fastclock for the rest of attach
734 * bring the d11 core out of reset.
735 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
736 * But it will be called again inside wlc_corereset, after d11 is out of reset.
737 */
738 wlc_clkctl_clk(wlc_hw, CLK_FAST);
739 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
740
741 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
742 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
743 unit);
744 err = 14;
745 goto fail;
746 }
747
748 /* get the board rev, used just below */
749 j = getintvar(vars, "boardrev");
750 /* promote srom boardrev of 0xFF to 1 */
751 if (j == BOARDREV_PROMOTABLE)
752 j = BOARDREV_PROMOTED;
753 wlc_hw->boardrev = (u16) j;
754 if (!wlc_validboardtype(wlc_hw)) {
755 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
756 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
757 err = 15;
758 goto fail;
759 }
760 wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
761 wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
762 wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
763
764 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
765 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
766
767 if ((wlc_hw->sih->bustype == PCI_BUS)
768 && (si_pci_war16165(wlc_hw->sih)))
769 wlc->war16165 = true;
770
771 /* check device id(srom, nvram etc.) to set bands */
772 if (wlc_hw->deviceid == BCM43224_D11N_ID) {
773 /* Dualband boards */
774 wlc_hw->_nbands = 2;
775 } else
776 wlc_hw->_nbands = 1;
777
778 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
779 wlc_hw->_nbands = 1;
780
781 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
782 * init of these values
783 */
784 wlc->vendorid = wlc_hw->vendorid;
785 wlc->deviceid = wlc_hw->deviceid;
786 wlc->pub->sih = wlc_hw->sih;
787 wlc->pub->corerev = wlc_hw->corerev;
788 wlc->pub->sromrev = wlc_hw->sromrev;
789 wlc->pub->boardrev = wlc_hw->boardrev;
790 wlc->pub->boardflags = wlc_hw->boardflags;
791 wlc->pub->boardflags2 = wlc_hw->boardflags2;
792 wlc->pub->_nbands = wlc_hw->_nbands;
793
794 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
795
796 if (wlc_hw->physhim == NULL) {
797 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
798 unit);
799 err = 25;
800 goto fail;
801 }
802
803 /* pass all the parameters to wlc_phy_shared_attach in one struct */
804 sha_params.sih = wlc_hw->sih;
805 sha_params.physhim = wlc_hw->physhim;
806 sha_params.unit = unit;
807 sha_params.corerev = wlc_hw->corerev;
808 sha_params.vars = vars;
809 sha_params.vid = wlc_hw->vendorid;
810 sha_params.did = wlc_hw->deviceid;
811 sha_params.chip = wlc_hw->sih->chip;
812 sha_params.chiprev = wlc_hw->sih->chiprev;
813 sha_params.chippkg = wlc_hw->sih->chippkg;
814 sha_params.sromrev = wlc_hw->sromrev;
815 sha_params.boardtype = wlc_hw->sih->boardtype;
816 sha_params.boardrev = wlc_hw->boardrev;
817 sha_params.boardvendor = wlc_hw->sih->boardvendor;
818 sha_params.boardflags = wlc_hw->boardflags;
819 sha_params.boardflags2 = wlc_hw->boardflags2;
820 sha_params.bustype = wlc_hw->sih->bustype;
821 sha_params.buscorerev = wlc_hw->sih->buscorerev;
822
823 /* alloc and save pointer to shared phy state area */
824 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
825 if (!wlc_hw->phy_sh) {
826 err = 16;
827 goto fail;
828 }
829
830 /* initialize software state for each core and band */
831 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
832 /*
833 * band0 is always 2.4Ghz
834 * band1, if present, is 5Ghz
835 */
836
837 /* So if this is a single band 11a card, use band 1 */
838 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
839 j = BAND_5G_INDEX;
840
841 wlc_setxband(wlc_hw, j);
842
843 wlc_hw->band->bandunit = j;
844 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
845 wlc->band->bandunit = j;
846 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
847 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
848
849 wlc_hw->machwcap = R_REG(&regs->machwcap);
850 wlc_hw->machwcap_backup = wlc_hw->machwcap;
851
852 /* init tx fifo size */
853 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
854 ARRAY_SIZE(xmtfifo_sz));
855 wlc_hw->xmtfifo_sz =
856 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
857
858 /* Get a phy for this band */
859 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
860 (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
861 if (wlc_hw->band->pi == NULL) {
862 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
863 unit);
864 err = 17;
865 goto fail;
866 }
867
868 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
869
870 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
871 &wlc_hw->band->phyrev,
872 &wlc_hw->band->radioid,
873 &wlc_hw->band->radiorev);
874 wlc_hw->band->abgphy_encore =
875 wlc_phy_get_encore(wlc_hw->band->pi);
876 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
877 wlc_hw->band->core_flags =
878 wlc_phy_get_coreflags(wlc_hw->band->pi);
879
880 /* verify good phy_type & supported phy revision */
881 if (WLCISNPHY(wlc_hw->band)) {
882 if (NCONF_HAS(wlc_hw->band->phyrev))
883 goto good_phy;
884 else
885 goto bad_phy;
886 } else if (WLCISLCNPHY(wlc_hw->band)) {
887 if (LCNCONF_HAS(wlc_hw->band->phyrev))
888 goto good_phy;
889 else
890 goto bad_phy;
891 } else {
892 bad_phy:
893 WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
894 unit,
895 wlc_hw->band->phytype, wlc_hw->band->phyrev);
896 err = 18;
897 goto fail;
898 }
899
900 good_phy:
901 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
902 * high level attach. However we can not make that change until all low level access
903 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
904 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
905 * low only init when all fns updated.
906 */
907 wlc->band->pi = wlc_hw->band->pi;
908 wlc->band->phytype = wlc_hw->band->phytype;
909 wlc->band->phyrev = wlc_hw->band->phyrev;
910 wlc->band->radioid = wlc_hw->band->radioid;
911 wlc->band->radiorev = wlc_hw->band->radiorev;
912
913 /* default contention windows size limits */
914 wlc_hw->band->CWmin = APHY_CWMIN;
915 wlc_hw->band->CWmax = PHY_CWMAX;
916
917 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
918 err = 19;
919 goto fail;
920 }
921 }
922
923 /* disable core to match driver "down" state */
924 wlc_coredisable(wlc_hw);
925
926 /* Match driver "down" state */
927 if (wlc_hw->sih->bustype == PCI_BUS)
928 si_pci_down(wlc_hw->sih);
929
930 /* register sb interrupt callback functions */
931 si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
932 (void *)wlc_wlintrsrestore, NULL, wlc);
933
934 /* turn off pll and xtal to match driver "down" state */
935 wlc_bmac_xtal(wlc_hw, OFF);
936
937 /* *********************************************************************
938 * The hardware is in the DOWN state at this point. D11 core
939 * or cores are in reset with clocks off, and the board PLLs
940 * are off if possible.
941 *
942 * Beyond this point, wlc->sbclk == false and chip registers
943 * should not be touched.
944 *********************************************************************
945 */
946
947 /* init etheraddr state variables */
948 macaddr = wlc_get_macaddr(wlc_hw);
949 if (macaddr == NULL) {
950 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
951 err = 21;
952 goto fail;
953 }
954 bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
955 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
956 is_zero_ether_addr(wlc_hw->etheraddr)) {
957 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
958 unit, macaddr);
959 err = 22;
960 goto fail;
961 }
962
963 WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
964 __func__, wlc_hw->deviceid, wlc_hw->_nbands,
965 wlc_hw->sih->boardtype, macaddr);
966
967 return err;
968
969 fail:
970 WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
971 return err;
972 }
973
974 /*
975 * Initialize wlc_info default values ...
976 * may get overrides later in this function
977 * BMAC_NOTES, move low out and resolve the dangling ones
978 */
979 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
980 {
981 struct wlc_info *wlc = wlc_hw->wlc;
982
983 /* set default sw macintmask value */
984 wlc->defmacintmask = DEF_MACINTMASK;
985
986 /* various 802.11g modes */
987 wlc_hw->shortslot = false;
988
989 wlc_hw->SFBL = RETRY_SHORT_FB;
990 wlc_hw->LFBL = RETRY_LONG_FB;
991
992 /* default mac retry limits */
993 wlc_hw->SRL = RETRY_SHORT_DEF;
994 wlc_hw->LRL = RETRY_LONG_DEF;
995 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
996 }
997
998 /*
999 * low level detach
1000 */
1001 int wlc_bmac_detach(struct wlc_info *wlc)
1002 {
1003 uint i;
1004 struct wlc_hwband *band;
1005 struct wlc_hw_info *wlc_hw = wlc->hw;
1006 int callbacks;
1007
1008 callbacks = 0;
1009
1010 if (wlc_hw->sih) {
1011 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1012 * interrupt object may has been freed. this must be done before sb core switch
1013 */
1014 si_deregister_intr_callback(wlc_hw->sih);
1015
1016 if (wlc_hw->sih->bustype == PCI_BUS)
1017 si_pci_sleep(wlc_hw->sih);
1018 }
1019
1020 wlc_bmac_detach_dmapio(wlc_hw);
1021
1022 band = wlc_hw->band;
1023 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1024 if (band->pi) {
1025 /* Detach this band's phy */
1026 wlc_phy_detach(band->pi);
1027 band->pi = NULL;
1028 }
1029 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1030 }
1031
1032 /* Free shared phy state */
1033 wlc_phy_shared_detach(wlc_hw->phy_sh);
1034
1035 wlc_phy_shim_detach(wlc_hw->physhim);
1036
1037 /* free vars */
1038 kfree(wlc_hw->vars);
1039 wlc_hw->vars = NULL;
1040
1041 if (wlc_hw->sih) {
1042 si_detach(wlc_hw->sih);
1043 wlc_hw->sih = NULL;
1044 }
1045
1046 return callbacks;
1047
1048 }
1049
1050 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1051 {
1052 WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1053
1054 wlc_hw->wlc->pub->_cnt->reset++;
1055
1056 /* reset the core */
1057 if (!DEVICEREMOVED(wlc_hw->wlc))
1058 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1059
1060 /* purge the dma rings */
1061 wlc_flushqueues(wlc_hw->wlc);
1062
1063 wlc_reset_bmac_done(wlc_hw->wlc);
1064 }
1065
1066 void
1067 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1068 bool mute) {
1069 u32 macintmask;
1070 bool fastclk;
1071 struct wlc_info *wlc = wlc_hw->wlc;
1072
1073 WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1074
1075 /* request FAST clock if not on */
1076 fastclk = wlc_hw->forcefastclk;
1077 if (!fastclk)
1078 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1079
1080 /* disable interrupts */
1081 macintmask = wl_intrsoff(wlc->wl);
1082
1083 /* set up the specified band and chanspec */
1084 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1085 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1086
1087 /* do one-time phy inits and calibration */
1088 wlc_phy_cal_init(wlc_hw->band->pi);
1089
1090 /* core-specific initialization */
1091 wlc_coreinit(wlc);
1092
1093 /* suspend the tx fifos and mute the phy for preism cac time */
1094 if (mute)
1095 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1096
1097 /* band-specific inits */
1098 wlc_bmac_bsinit(wlc, chanspec);
1099
1100 /* restore macintmask */
1101 wl_intrsrestore(wlc->wl, macintmask);
1102
1103 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1104 * and wlc_enable_mac() will clear this override bit.
1105 */
1106 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1107
1108 /*
1109 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1110 */
1111 wlc_hw->mac_suspend_depth = 1;
1112
1113 /* restore the clk */
1114 if (!fastclk)
1115 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1116 }
1117
1118 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1119 {
1120 uint coremask;
1121
1122 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1123
1124 ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1125
1126 /*
1127 * Enable pll and xtal, initialize the power control registers,
1128 * and force fastclock for the remainder of wlc_up().
1129 */
1130 wlc_bmac_xtal(wlc_hw, ON);
1131 si_clkctl_init(wlc_hw->sih);
1132 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1133
1134 /*
1135 * Configure pci/pcmcia here instead of in wlc_attach()
1136 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1137 */
1138 coremask = (1 << wlc_hw->wlc->core->coreidx);
1139
1140 if (wlc_hw->sih->bustype == PCI_BUS)
1141 si_pci_setup(wlc_hw->sih, coremask);
1142
1143 ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1144
1145 /*
1146 * Need to read the hwradio status here to cover the case where the system
1147 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1148 */
1149 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1150 /* put SB PCI in down state again */
1151 if (wlc_hw->sih->bustype == PCI_BUS)
1152 si_pci_down(wlc_hw->sih);
1153 wlc_bmac_xtal(wlc_hw, OFF);
1154 return BCME_RADIOOFF;
1155 }
1156
1157 if (wlc_hw->sih->bustype == PCI_BUS)
1158 si_pci_up(wlc_hw->sih);
1159
1160 /* reset the d11 core */
1161 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1162
1163 return 0;
1164 }
1165
1166 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1167 {
1168 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1169
1170 wlc_hw->up = true;
1171 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1172
1173 /* FULLY enable dynamic power control and d11 core interrupt */
1174 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1175 ASSERT(wlc_hw->wlc->macintmask == 0);
1176 wl_intrson(wlc_hw->wlc->wl);
1177 return 0;
1178 }
1179
1180 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1181 {
1182 bool dev_gone;
1183 uint callbacks = 0;
1184
1185 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1186
1187 if (!wlc_hw->up)
1188 return callbacks;
1189
1190 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1191
1192 /* disable interrupts */
1193 if (dev_gone)
1194 wlc_hw->wlc->macintmask = 0;
1195 else {
1196 /* now disable interrupts */
1197 wl_intrsoff(wlc_hw->wlc->wl);
1198
1199 /* ensure we're running on the pll clock again */
1200 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1201 }
1202 /* down phy at the last of this stage */
1203 callbacks += wlc_phy_down(wlc_hw->band->pi);
1204
1205 return callbacks;
1206 }
1207
1208 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1209 {
1210 uint callbacks = 0;
1211 bool dev_gone;
1212
1213 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1214
1215 if (!wlc_hw->up)
1216 return callbacks;
1217
1218 wlc_hw->up = false;
1219 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1220
1221 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1222
1223 if (dev_gone) {
1224 wlc_hw->sbclk = false;
1225 wlc_hw->clk = false;
1226 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1227
1228 /* reclaim any posted packets */
1229 wlc_flushqueues(wlc_hw->wlc);
1230 } else {
1231
1232 /* Reset and disable the core */
1233 if (si_iscoreup(wlc_hw->sih)) {
1234 if (R_REG(&wlc_hw->regs->maccontrol) &
1235 MCTL_EN_MAC)
1236 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1237 callbacks += wl_reset(wlc_hw->wlc->wl);
1238 wlc_coredisable(wlc_hw);
1239 }
1240
1241 /* turn off primary xtal and pll */
1242 if (!wlc_hw->noreset) {
1243 if (wlc_hw->sih->bustype == PCI_BUS)
1244 si_pci_down(wlc_hw->sih);
1245 wlc_bmac_xtal(wlc_hw, OFF);
1246 }
1247 }
1248
1249 return callbacks;
1250 }
1251
1252 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1253 {
1254 /* delay before first read of ucode state */
1255 udelay(40);
1256
1257 /* wait until ucode is no longer asleep */
1258 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1259 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1260
1261 ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1262 }
1263
1264 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1265 {
1266 memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1267 }
1268
1269 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1270 {
1271 return wlc_hw->band->bandtype;
1272 }
1273
1274 /* control chip clock to save power, enable dynamic clock or force fast clock */
1275 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1276 {
1277 if (PMUCTL_ENAB(wlc_hw->sih)) {
1278 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1279 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1280 * which means the FCA bit may not be set.
1281 * should wakeup mac if driver wants it to run on HT.
1282 */
1283
1284 if (wlc_hw->clk) {
1285 if (mode == CLK_FAST) {
1286 OR_REG(&wlc_hw->regs->clk_ctl_st,
1287 CCS_FORCEHT);
1288
1289 udelay(64);
1290
1291 SPINWAIT(((R_REG
1292 (&wlc_hw->regs->
1293 clk_ctl_st) & CCS_HTAVAIL) == 0),
1294 PMU_MAX_TRANSITION_DLY);
1295 ASSERT(R_REG
1296 (&wlc_hw->regs->
1297 clk_ctl_st) & CCS_HTAVAIL);
1298 } else {
1299 if ((wlc_hw->sih->pmurev == 0) &&
1300 (R_REG
1301 (&wlc_hw->regs->
1302 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1303 SPINWAIT(((R_REG
1304 (&wlc_hw->regs->
1305 clk_ctl_st) & CCS_HTAVAIL)
1306 == 0),
1307 PMU_MAX_TRANSITION_DLY);
1308 AND_REG(&wlc_hw->regs->clk_ctl_st,
1309 ~CCS_FORCEHT);
1310 }
1311 }
1312 wlc_hw->forcefastclk = (mode == CLK_FAST);
1313 } else {
1314
1315 /* old chips w/o PMU, force HT through cc,
1316 * then use FCA to verify mac is running fast clock
1317 */
1318
1319 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1320
1321 /* check fast clock is available (if core is not in reset) */
1322 if (wlc_hw->forcefastclk && wlc_hw->clk)
1323 ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1324
1325 /* keep the ucode wake bit on if forcefastclk is on
1326 * since we do not want ucode to put us back to slow clock
1327 * when it dozes for PM mode.
1328 * Code below matches the wake override bit with current forcefastclk state
1329 * Only setting bit in wake_override instead of waking ucode immediately
1330 * since old code (wlc.c 1.4499) had this behavior. Older code set
1331 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1332 * (protected by an up check) was executed just below.
1333 */
1334 if (wlc_hw->forcefastclk)
1335 mboolset(wlc_hw->wake_override,
1336 WLC_WAKE_OVERRIDE_FORCEFAST);
1337 else
1338 mboolclr(wlc_hw->wake_override,
1339 WLC_WAKE_OVERRIDE_FORCEFAST);
1340 }
1341 }
1342
1343 /* set initial host flags value */
1344 static void
1345 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1346 {
1347 struct wlc_hw_info *wlc_hw = wlc->hw;
1348
1349 memset(mhfs, 0, MHFMAX * sizeof(u16));
1350
1351 mhfs[MHF2] |= mhf2_init;
1352
1353 /* prohibit use of slowclock on multifunction boards */
1354 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1355 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1356
1357 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1358 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1359 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1360 }
1361 }
1362
1363 /* set or clear ucode host flag bits
1364 * it has an optimization for no-change write
1365 * it only writes through shared memory when the core has clock;
1366 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1367 *
1368 *
1369 * bands values are: WLC_BAND_AUTO <--- Current band only
1370 * WLC_BAND_5G <--- 5G band only
1371 * WLC_BAND_2G <--- 2G band only
1372 * WLC_BAND_ALL <--- All bands
1373 */
1374 void
1375 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1376 int bands)
1377 {
1378 u16 save;
1379 u16 addr[MHFMAX] = {
1380 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1381 M_HOST_FLAGS5
1382 };
1383 struct wlc_hwband *band;
1384
1385 ASSERT((val & ~mask) == 0);
1386 ASSERT(idx < MHFMAX);
1387 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1388
1389 switch (bands) {
1390 /* Current band only or all bands,
1391 * then set the band to current band
1392 */
1393 case WLC_BAND_AUTO:
1394 case WLC_BAND_ALL:
1395 band = wlc_hw->band;
1396 break;
1397 case WLC_BAND_5G:
1398 band = wlc_hw->bandstate[BAND_5G_INDEX];
1399 break;
1400 case WLC_BAND_2G:
1401 band = wlc_hw->bandstate[BAND_2G_INDEX];
1402 break;
1403 default:
1404 ASSERT(0);
1405 band = NULL;
1406 }
1407
1408 if (band) {
1409 save = band->mhfs[idx];
1410 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1411
1412 /* optimization: only write through if changed, and
1413 * changed band is the current band
1414 */
1415 if (wlc_hw->clk && (band->mhfs[idx] != save)
1416 && (band == wlc_hw->band))
1417 wlc_bmac_write_shm(wlc_hw, addr[idx],
1418 (u16) band->mhfs[idx]);
1419 }
1420
1421 if (bands == WLC_BAND_ALL) {
1422 wlc_hw->bandstate[0]->mhfs[idx] =
1423 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1424 wlc_hw->bandstate[1]->mhfs[idx] =
1425 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1426 }
1427 }
1428
1429 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1430 {
1431 struct wlc_hwband *band;
1432 ASSERT(idx < MHFMAX);
1433
1434 switch (bands) {
1435 case WLC_BAND_AUTO:
1436 band = wlc_hw->band;
1437 break;
1438 case WLC_BAND_5G:
1439 band = wlc_hw->bandstate[BAND_5G_INDEX];
1440 break;
1441 case WLC_BAND_2G:
1442 band = wlc_hw->bandstate[BAND_2G_INDEX];
1443 break;
1444 default:
1445 ASSERT(0);
1446 band = NULL;
1447 }
1448
1449 if (!band)
1450 return 0;
1451
1452 return band->mhfs[idx];
1453 }
1454
1455 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1456 {
1457 u8 idx;
1458 u16 addr[] = {
1459 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1460 M_HOST_FLAGS5
1461 };
1462
1463 ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1464
1465 for (idx = 0; idx < MHFMAX; idx++) {
1466 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1467 }
1468 }
1469
1470 /* set the maccontrol register to desired reset state and
1471 * initialize the sw cache of the register
1472 */
1473 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1474 {
1475 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1476 wlc_hw->maccontrol = 0;
1477 wlc_hw->suspended_fifos = 0;
1478 wlc_hw->wake_override = 0;
1479 wlc_hw->mute_override = 0;
1480 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1481 }
1482
1483 /* set or clear maccontrol bits */
1484 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1485 {
1486 u32 maccontrol;
1487 u32 new_maccontrol;
1488
1489 ASSERT((val & ~mask) == 0);
1490
1491 maccontrol = wlc_hw->maccontrol;
1492 new_maccontrol = (maccontrol & ~mask) | val;
1493
1494 /* if the new maccontrol value is the same as the old, nothing to do */
1495 if (new_maccontrol == maccontrol)
1496 return;
1497
1498 /* something changed, cache the new value */
1499 wlc_hw->maccontrol = new_maccontrol;
1500
1501 /* write the new values with overrides applied */
1502 wlc_mctrl_write(wlc_hw);
1503 }
1504
1505 /* write the software state of maccontrol and overrides to the maccontrol register */
1506 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1507 {
1508 u32 maccontrol = wlc_hw->maccontrol;
1509
1510 /* OR in the wake bit if overridden */
1511 if (wlc_hw->wake_override)
1512 maccontrol |= MCTL_WAKE;
1513
1514 /* set AP and INFRA bits for mute if needed */
1515 if (wlc_hw->mute_override) {
1516 maccontrol &= ~(MCTL_AP);
1517 maccontrol |= MCTL_INFRA;
1518 }
1519
1520 W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1521 }
1522
1523 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1524 {
1525 ASSERT((wlc_hw->wake_override & override_bit) == 0);
1526
1527 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1528 mboolset(wlc_hw->wake_override, override_bit);
1529 return;
1530 }
1531
1532 mboolset(wlc_hw->wake_override, override_bit);
1533
1534 wlc_mctrl_write(wlc_hw);
1535 wlc_bmac_wait_for_wake(wlc_hw);
1536
1537 return;
1538 }
1539
1540 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1541 {
1542 ASSERT(wlc_hw->wake_override & override_bit);
1543
1544 mboolclr(wlc_hw->wake_override, override_bit);
1545
1546 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1547 return;
1548
1549 wlc_mctrl_write(wlc_hw);
1550
1551 return;
1552 }
1553
1554 /* When driver needs ucode to stop beaconing, it has to make sure that
1555 * MCTL_AP is clear and MCTL_INFRA is set
1556 * Mode MCTL_AP MCTL_INFRA
1557 * AP 1 1
1558 * STA 0 1 <--- This will ensure no beacons
1559 * IBSS 0 0
1560 */
1561 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1562 {
1563 wlc_hw->mute_override = 1;
1564
1565 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1566 * override, then there is no change to write
1567 */
1568 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1569 return;
1570
1571 wlc_mctrl_write(wlc_hw);
1572
1573 return;
1574 }
1575
1576 /* Clear the override on AP and INFRA bits */
1577 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1578 {
1579 if (wlc_hw->mute_override == 0)
1580 return;
1581
1582 wlc_hw->mute_override = 0;
1583
1584 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1585 * override, then there is no change to write
1586 */
1587 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1588 return;
1589
1590 wlc_mctrl_write(wlc_hw);
1591 }
1592
1593 /*
1594 * Write a MAC address to the rcmta structure
1595 */
1596 void
1597 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1598 const u8 *addr)
1599 {
1600 d11regs_t *regs = wlc_hw->regs;
1601 volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1602 u32 mac_hm;
1603 u16 mac_l;
1604
1605 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1606
1607 mac_hm =
1608 (addr[3] << 24) | (addr[2] << 16) |
1609 (addr[1] << 8) | addr[0];
1610 mac_l = (addr[5] << 8) | addr[4];
1611
1612 W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1613 (void)R_REG(&regs->objaddr);
1614 W_REG(&regs->objdata, mac_hm);
1615 W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1616 (void)R_REG(&regs->objaddr);
1617 W_REG(objdata16, mac_l);
1618 }
1619
1620 /*
1621 * Write a MAC address to the given match reg offset in the RXE match engine.
1622 */
1623 void
1624 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1625 const u8 *addr)
1626 {
1627 d11regs_t *regs;
1628 u16 mac_l;
1629 u16 mac_m;
1630 u16 mac_h;
1631
1632 WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1633
1634 ASSERT(match_reg_offset < RCM_SIZE);
1635
1636 regs = wlc_hw->regs;
1637 mac_l = addr[0] | (addr[1] << 8);
1638 mac_m = addr[2] | (addr[3] << 8);
1639 mac_h = addr[4] | (addr[5] << 8);
1640
1641 /* enter the MAC addr into the RXE match registers */
1642 W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1643 W_REG(&regs->rcm_mat_data, mac_l);
1644 W_REG(&regs->rcm_mat_data, mac_m);
1645 W_REG(&regs->rcm_mat_data, mac_h);
1646
1647 }
1648
1649 void
1650 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1651 void *buf)
1652 {
1653 d11regs_t *regs;
1654 u32 word;
1655 bool be_bit;
1656 #ifdef IL_BIGENDIAN
1657 volatile u16 *dptr = NULL;
1658 #endif /* IL_BIGENDIAN */
1659 WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1660
1661 regs = wlc_hw->regs;
1662
1663 ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1664 ASSERT(IS_ALIGNED(len, sizeof(u32)));
1665 ASSERT((offset & ~0xffff) == 0);
1666
1667 W_REG(&regs->tplatewrptr, offset);
1668
1669 /* if MCTL_BIGEND bit set in mac control register,
1670 * the chip swaps data in fifo, as well as data in
1671 * template ram
1672 */
1673 be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1674
1675 while (len > 0) {
1676 memcpy(&word, buf, sizeof(u32));
1677
1678 if (be_bit)
1679 word = cpu_to_be32(word);
1680 else
1681 word = cpu_to_le32(word);
1682
1683 W_REG(&regs->tplatewrdata, word);
1684
1685 buf = (u8 *) buf + sizeof(u32);
1686 len -= sizeof(u32);
1687 }
1688 }
1689
1690 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1691 {
1692 wlc_hw->band->CWmin = newmin;
1693
1694 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1695 (void)R_REG(&wlc_hw->regs->objaddr);
1696 W_REG(&wlc_hw->regs->objdata, newmin);
1697 }
1698
1699 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1700 {
1701 wlc_hw->band->CWmax = newmax;
1702
1703 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1704 (void)R_REG(&wlc_hw->regs->objaddr);
1705 W_REG(&wlc_hw->regs->objdata, newmax);
1706 }
1707
1708 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1709 {
1710 bool fastclk;
1711
1712 /* request FAST clock if not on */
1713 fastclk = wlc_hw->forcefastclk;
1714 if (!fastclk)
1715 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1716
1717 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1718
1719 ASSERT(wlc_hw->clk);
1720
1721 wlc_bmac_phy_reset(wlc_hw);
1722 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1723
1724 /* restore the clk */
1725 if (!fastclk)
1726 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1727 }
1728
1729 static void
1730 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1731 {
1732 d11regs_t *regs = wlc_hw->regs;
1733
1734 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1735 bcn);
1736 /* write beacon length to SCR */
1737 ASSERT(len < 65536);
1738 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1739 /* mark beacon0 valid */
1740 OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1741 }
1742
1743 static void
1744 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1745 {
1746 d11regs_t *regs = wlc_hw->regs;
1747
1748 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1749 bcn);
1750 /* write beacon length to SCR */
1751 ASSERT(len < 65536);
1752 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1753 /* mark beacon1 valid */
1754 OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1755 }
1756
1757 /* mac is assumed to be suspended at this point */
1758 void
1759 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1760 bool both)
1761 {
1762 d11regs_t *regs = wlc_hw->regs;
1763
1764 if (both) {
1765 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1766 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1767 } else {
1768 /* bcn 0 */
1769 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1770 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1771 /* bcn 1 */
1772 else if (!
1773 (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1774 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1775 else /* one template should always have been available */
1776 ASSERT(0);
1777 }
1778 }
1779
1780 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1781 {
1782 u16 v;
1783 struct wlc_info *wlc = wlc_hw->wlc;
1784 /* update SYNTHPU_DLY */
1785
1786 if (WLCISLCNPHY(wlc->band)) {
1787 v = SYNTHPU_DLY_LPPHY_US;
1788 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1789 v = SYNTHPU_DLY_NPHY_US;
1790 } else {
1791 v = SYNTHPU_DLY_BPHY_US;
1792 }
1793
1794 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1795 }
1796
1797 /* band-specific init */
1798 static void
1799 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1800 {
1801 struct wlc_hw_info *wlc_hw = wlc->hw;
1802
1803 WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1804 wlc_hw->unit, wlc_hw->band->bandunit);
1805
1806 /* sanity check */
1807 if (PHY_TYPE(R_REG(&wlc_hw->regs->phyversion)) !=
1808 PHY_TYPE_LCNXN)
1809 ASSERT((uint)
1810 PHY_TYPE(R_REG(&wlc_hw->regs->phyversion))
1811 == wlc_hw->band->phytype);
1812
1813 wlc_ucode_bsinit(wlc_hw);
1814
1815 wlc_phy_init(wlc_hw->band->pi, chanspec);
1816
1817 wlc_ucode_txant_set(wlc_hw);
1818
1819 /* cwmin is band-specific, update hardware with value for current band */
1820 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1821 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1822
1823 wlc_bmac_update_slot_timing(wlc_hw,
1824 BAND_5G(wlc_hw->band->
1825 bandtype) ? true : wlc_hw->
1826 shortslot);
1827
1828 /* write phytype and phyvers */
1829 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1830 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1831
1832 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1833 wlc_upd_ofdm_pctl1_table(wlc_hw);
1834
1835 wlc_bmac_upd_synthpu(wlc_hw);
1836 }
1837
1838 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1839 {
1840 WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1841
1842 wlc_hw->phyclk = clk;
1843
1844 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1845
1846 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1847 (SICF_PRST | SICF_FGC));
1848 udelay(1);
1849 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1850 udelay(1);
1851
1852 } else { /* take phy out of reset */
1853
1854 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1855 udelay(1);
1856 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1857 udelay(1);
1858
1859 }
1860 }
1861
1862 /* Perform a soft reset of the PHY PLL */
1863 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1864 {
1865 WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1866
1867 si_corereg(wlc_hw->sih, SI_CC_IDX,
1868 offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1869 udelay(1);
1870 si_corereg(wlc_hw->sih, SI_CC_IDX,
1871 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1872 udelay(1);
1873 si_corereg(wlc_hw->sih, SI_CC_IDX,
1874 offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1875 udelay(1);
1876 si_corereg(wlc_hw->sih, SI_CC_IDX,
1877 offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1878 udelay(1);
1879 }
1880
1881 /* light way to turn on phy clock without reset for NPHY only
1882 * refer to wlc_bmac_core_phy_clk for full version
1883 */
1884 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1885 {
1886 /* support(necessary for NPHY and HYPHY) only */
1887 if (!WLCISNPHY(wlc_hw->band))
1888 return;
1889
1890 if (ON == clk)
1891 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1892 else
1893 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1894
1895 }
1896
1897 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1898 {
1899 if (ON == clk)
1900 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1901 else
1902 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1903 }
1904
1905 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1906 {
1907 wlc_phy_t *pih = wlc_hw->band->pi;
1908 u32 phy_bw_clkbits;
1909 bool phy_in_reset = false;
1910
1911 WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1912
1913 if (pih == NULL)
1914 return;
1915
1916 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1917
1918 /* Specific reset sequence required for NPHY rev 3 and 4 */
1919 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1920 NREV_LE(wlc_hw->band->phyrev, 4)) {
1921 /* Set the PHY bandwidth */
1922 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1923
1924 udelay(1);
1925
1926 /* Perform a soft reset of the PHY PLL */
1927 wlc_bmac_core_phypll_reset(wlc_hw);
1928
1929 /* reset the PHY */
1930 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1931 (SICF_PRST | SICF_PCLKE));
1932 phy_in_reset = true;
1933 } else {
1934
1935 si_core_cflags(wlc_hw->sih,
1936 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1937 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1938 }
1939
1940 udelay(2);
1941 wlc_bmac_core_phy_clk(wlc_hw, ON);
1942
1943 if (pih)
1944 wlc_phy_anacore(pih, ON);
1945 }
1946
1947 /* switch to and initialize new band */
1948 static void
1949 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1950 chanspec_t chanspec) {
1951 struct wlc_info *wlc = wlc_hw->wlc;
1952 u32 macintmask;
1953
1954 ASSERT(NBANDS_HW(wlc_hw) > 1);
1955 ASSERT(bandunit != wlc_hw->band->bandunit);
1956
1957 /* Enable the d11 core before accessing it */
1958 if (!si_iscoreup(wlc_hw->sih)) {
1959 si_core_reset(wlc_hw->sih, 0, 0);
1960 ASSERT(si_iscoreup(wlc_hw->sih));
1961 wlc_mctrl_reset(wlc_hw);
1962 }
1963
1964 macintmask = wlc_setband_inact(wlc, bandunit);
1965
1966 if (!wlc_hw->up)
1967 return;
1968
1969 wlc_bmac_core_phy_clk(wlc_hw, ON);
1970
1971 /* band-specific initializations */
1972 wlc_bmac_bsinit(wlc, chanspec);
1973
1974 /*
1975 * If there are any pending software interrupt bits,
1976 * then replace these with a harmless nonzero value
1977 * so wlc_dpc() will re-enable interrupts when done.
1978 */
1979 if (wlc->macintstatus)
1980 wlc->macintstatus = MI_DMAINT;
1981
1982 /* restore macintmask */
1983 wl_intrsrestore(wlc->wl, macintmask);
1984
1985 /* ucode should still be suspended.. */
1986 ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
1987 0);
1988 }
1989
1990 /* low-level band switch utility routine */
1991 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1992 {
1993 WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
1994
1995 wlc_hw->band = wlc_hw->bandstate[bandunit];
1996
1997 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1998 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1999
2000 /* set gmode core flag */
2001 if (wlc_hw->sbclk && !wlc_hw->noreset) {
2002 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2003 ((bandunit == 0) ? SICF_GMODE : 0));
2004 }
2005 }
2006
2007 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2008 {
2009
2010 /* reject unsupported corerev */
2011 if (!VALID_COREREV(wlc_hw->corerev)) {
2012 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2013 return false;
2014 }
2015
2016 return true;
2017 }
2018
2019 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2020 {
2021 bool goodboard = true;
2022 uint boardrev = wlc_hw->boardrev;
2023
2024 if (boardrev == 0)
2025 goodboard = false;
2026 else if (boardrev > 0xff) {
2027 uint brt = (boardrev & 0xf000) >> 12;
2028 uint b0 = (boardrev & 0xf00) >> 8;
2029 uint b1 = (boardrev & 0xf0) >> 4;
2030 uint b2 = boardrev & 0xf;
2031
2032 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2033 || (b2 > 9))
2034 goodboard = false;
2035 }
2036
2037 if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2038 return goodboard;
2039
2040 return goodboard;
2041 }
2042
2043 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2044 {
2045 const char *varname = "macaddr";
2046 char *macaddr;
2047
2048 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2049 macaddr = getvar(wlc_hw->vars, varname);
2050 if (macaddr != NULL)
2051 return macaddr;
2052
2053 if (NBANDS_HW(wlc_hw) > 1)
2054 varname = "et1macaddr";
2055 else
2056 varname = "il0macaddr";
2057
2058 macaddr = getvar(wlc_hw->vars, varname);
2059 if (macaddr == NULL) {
2060 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2061 wlc_hw->unit, varname);
2062 }
2063
2064 return macaddr;
2065 }
2066
2067 /*
2068 * Return true if radio is disabled, otherwise false.
2069 * hw radio disable signal is an external pin, users activate it asynchronously
2070 * this function could be called when driver is down and w/o clock
2071 * it operates on different registers depending on corerev and boardflag.
2072 */
2073 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2074 {
2075 bool v, clk, xtal;
2076 u32 resetbits = 0, flags = 0;
2077
2078 xtal = wlc_hw->sbclk;
2079 if (!xtal)
2080 wlc_bmac_xtal(wlc_hw, ON);
2081
2082 /* may need to take core out of reset first */
2083 clk = wlc_hw->clk;
2084 if (!clk) {
2085 /*
2086 * mac no longer enables phyclk automatically when driver
2087 * accesses phyreg throughput mac. This can be skipped since
2088 * only mac reg is accessed below
2089 */
2090 flags |= SICF_PCLKE;
2091
2092 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2093 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2094 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2095 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2096 wlc_hw->regs =
2097 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2098 0);
2099 si_core_reset(wlc_hw->sih, flags, resetbits);
2100 wlc_mctrl_reset(wlc_hw);
2101 }
2102
2103 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2104
2105 /* put core back into reset */
2106 if (!clk)
2107 si_core_disable(wlc_hw->sih, 0);
2108
2109 if (!xtal)
2110 wlc_bmac_xtal(wlc_hw, OFF);
2111
2112 return v;
2113 }
2114
2115 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2116 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2117 {
2118 if (wlc_hw->wlc->pub->hw_up)
2119 return;
2120
2121 WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2122
2123 /*
2124 * Enable pll and xtal, initialize the power control registers,
2125 * and force fastclock for the remainder of wlc_up().
2126 */
2127 wlc_bmac_xtal(wlc_hw, ON);
2128 si_clkctl_init(wlc_hw->sih);
2129 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2130
2131 if (wlc_hw->sih->bustype == PCI_BUS) {
2132 si_pci_fixcfg(wlc_hw->sih);
2133
2134 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2135 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2136 (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2137 (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2138 wlc_hw->regs =
2139 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2140 0);
2141 }
2142
2143 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2144 wlc_phy_por_inform(wlc_hw->band->pi);
2145
2146 wlc_hw->ucode_loaded = false;
2147 wlc_hw->wlc->pub->hw_up = true;
2148
2149 if ((wlc_hw->boardflags & BFL_FEM)
2150 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2151 if (!
2152 (wlc_hw->boardrev >= 0x1250
2153 && (wlc_hw->boardflags & BFL_FEM_BT)))
2154 si_epa_4313war(wlc_hw->sih);
2155 }
2156 }
2157
2158 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2159 {
2160 struct hnddma_pub *di = wlc_hw->di[fifo];
2161 return dma_rxreset(di);
2162 }
2163
2164 /* d11 core reset
2165 * ensure fask clock during reset
2166 * reset dma
2167 * reset d11(out of reset)
2168 * reset phy(out of reset)
2169 * clear software macintstatus for fresh new start
2170 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2171 */
2172 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2173 {
2174 d11regs_t *regs;
2175 uint i;
2176 bool fastclk;
2177 u32 resetbits = 0;
2178
2179 if (flags == WLC_USE_COREFLAGS)
2180 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2181
2182 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2183
2184 regs = wlc_hw->regs;
2185
2186 /* request FAST clock if not on */
2187 fastclk = wlc_hw->forcefastclk;
2188 if (!fastclk)
2189 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2190
2191 /* reset the dma engines except first time thru */
2192 if (si_iscoreup(wlc_hw->sih)) {
2193 for (i = 0; i < NFIFO; i++)
2194 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2195 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2196 wlc_hw->unit, __func__, i);
2197 }
2198
2199 if ((wlc_hw->di[RX_FIFO])
2200 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2201 WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2202 wlc_hw->unit, __func__, RX_FIFO);
2203 }
2204 }
2205 /* if noreset, just stop the psm and return */
2206 if (wlc_hw->noreset) {
2207 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2208 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2209 return;
2210 }
2211
2212 /*
2213 * mac no longer enables phyclk automatically when driver accesses
2214 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2215 * band->pi is invalid. need to enable PHY CLK
2216 */
2217 flags |= SICF_PCLKE;
2218
2219 /* reset the core
2220 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2221 * is cleared by the core_reset. have to re-request it.
2222 * This adds some delay and we can optimize it by also requesting fastclk through
2223 * chipcommon during this period if necessary. But that has to work coordinate
2224 * with other driver like mips/arm since they may touch chipcommon as well.
2225 */
2226 wlc_hw->clk = false;
2227 si_core_reset(wlc_hw->sih, flags, resetbits);
2228 wlc_hw->clk = true;
2229 if (wlc_hw->band && wlc_hw->band->pi)
2230 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2231
2232 wlc_mctrl_reset(wlc_hw);
2233
2234 if (PMUCTL_ENAB(wlc_hw->sih))
2235 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2236
2237 wlc_bmac_phy_reset(wlc_hw);
2238
2239 /* turn on PHY_PLL */
2240 wlc_bmac_core_phypll_ctl(wlc_hw, true);
2241
2242 /* clear sw intstatus */
2243 wlc_hw->wlc->macintstatus = 0;
2244
2245 /* restore the clk setting */
2246 if (!fastclk)
2247 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2248 }
2249
2250 /* txfifo sizes needs to be modified(increased) since the newer cores
2251 * have more memory.
2252 */
2253 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2254 {
2255 d11regs_t *regs = wlc_hw->regs;
2256 u16 fifo_nu;
2257 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2258 u16 txfifo_def, txfifo_def1;
2259 u16 txfifo_cmd;
2260
2261 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2262 txfifo_startblk = TXFIFO_START_BLK;
2263
2264 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2265 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2266
2267 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2268 txfifo_def = (txfifo_startblk & 0xff) |
2269 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2270 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2271 ((((txfifo_endblk -
2272 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2273 txfifo_cmd =
2274 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2275
2276 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2277 W_REG(&regs->xmtfifodef, txfifo_def);
2278 W_REG(&regs->xmtfifodef1, txfifo_def1);
2279
2280 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2281
2282 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2283 }
2284 /*
2285 * need to propagate to shm location to be in sync since ucode/hw won't
2286 * do this
2287 */
2288 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2289 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2290 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2291 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2292 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2293 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2294 xmtfifo_sz[TX_AC_BK_FIFO]));
2295 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2296 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2297 xmtfifo_sz[TX_BCMC_FIFO]));
2298 }
2299
2300 /* d11 core init
2301 * reset PSM
2302 * download ucode/PCM
2303 * let ucode run to suspended
2304 * download ucode inits
2305 * config other core registers
2306 * init dma
2307 */
2308 static void wlc_coreinit(struct wlc_info *wlc)
2309 {
2310 struct wlc_hw_info *wlc_hw = wlc->hw;
2311 d11regs_t *regs;
2312 u32 sflags;
2313 uint bcnint_us;
2314 uint i = 0;
2315 bool fifosz_fixup = false;
2316 int err = 0;
2317 u16 buf[NFIFO];
2318
2319 regs = wlc_hw->regs;
2320
2321 WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2322
2323 /* reset PSM */
2324 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2325
2326 wlc_ucode_download(wlc_hw);
2327 /*
2328 * FIFOSZ fixup. driver wants to controls the fifo allocation.
2329 */
2330 fifosz_fixup = true;
2331
2332 /* let the PSM run to the suspended state, set mode to BSS STA */
2333 W_REG(&regs->macintstatus, -1);
2334 wlc_bmac_mctrl(wlc_hw, ~0,
2335 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2336
2337 /* wait for ucode to self-suspend after auto-init */
2338 SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2339 1000 * 1000);
2340 if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2341 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2342 wlc_hw->unit);
2343
2344 wlc_gpio_init(wlc);
2345
2346 sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2347
2348 if (D11REV_IS(wlc_hw->corerev, 23)) {
2349 if (WLCISNPHY(wlc_hw->band))
2350 wlc_write_inits(wlc_hw, d11n0initvals16);
2351 else
2352 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2353 __func__, wlc_hw->unit, wlc_hw->corerev);
2354 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2355 if (WLCISLCNPHY(wlc_hw->band)) {
2356 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2357 } else {
2358 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2359 __func__, wlc_hw->unit, wlc_hw->corerev);
2360 }
2361 } else {
2362 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2363 __func__, wlc_hw->unit, wlc_hw->corerev);
2364 }
2365
2366 /* For old ucode, txfifo sizes needs to be modified(increased) */
2367 if (fifosz_fixup == true) {
2368 wlc_corerev_fifofixup(wlc_hw);
2369 }
2370
2371 /* check txfifo allocations match between ucode and driver */
2372 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2373 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2374 i = TX_AC_BE_FIFO;
2375 err = -1;
2376 }
2377 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2378 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2379 i = TX_AC_VI_FIFO;
2380 err = -1;
2381 }
2382 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2383 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2384 buf[TX_AC_BK_FIFO] &= 0xff;
2385 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2386 i = TX_AC_BK_FIFO;
2387 err = -1;
2388 }
2389 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2390 i = TX_AC_VO_FIFO;
2391 err = -1;
2392 }
2393 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2394 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2395 buf[TX_BCMC_FIFO] &= 0xff;
2396 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2397 i = TX_BCMC_FIFO;
2398 err = -1;
2399 }
2400 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2401 i = TX_ATIM_FIFO;
2402 err = -1;
2403 }
2404 if (err != 0) {
2405 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2406 buf[i], wlc_hw->xmtfifo_sz[i], i);
2407 ASSERT(0);
2408 }
2409
2410 /* make sure we can still talk to the mac */
2411 ASSERT(R_REG(&regs->maccontrol) != 0xffffffff);
2412
2413 /* band-specific inits done by wlc_bsinit() */
2414
2415 /* Set up frame burst size and antenna swap threshold init values */
2416 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2417 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2418
2419 /* enable one rx interrupt per received frame */
2420 W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2421
2422 /* set the station mode (BSS STA) */
2423 wlc_bmac_mctrl(wlc_hw,
2424 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2425 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2426
2427 /* set up Beacon interval */
2428 bcnint_us = 0x8000 << 10;
2429 W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2430 W_REG(&regs->tsf_cfpstart, bcnint_us);
2431 W_REG(&regs->macintstatus, MI_GP1);
2432
2433 /* write interrupt mask */
2434 W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2435
2436 /* allow the MAC to control the PHY clock (dynamic on/off) */
2437 wlc_bmac_macphyclk_set(wlc_hw, ON);
2438
2439 /* program dynamic clock control fast powerup delay register */
2440 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2441 W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2442
2443 /* tell the ucode the corerev */
2444 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2445
2446 /* tell the ucode MAC capabilities */
2447 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2448 (u16) (wlc_hw->machwcap & 0xffff));
2449 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2450 (u16) ((wlc_hw->
2451 machwcap >> 16) & 0xffff));
2452
2453 /* write retry limits to SCR, this done after PSM init */
2454 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2455 (void)R_REG(&regs->objaddr);
2456 W_REG(&regs->objdata, wlc_hw->SRL);
2457 W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2458 (void)R_REG(&regs->objaddr);
2459 W_REG(&regs->objdata, wlc_hw->LRL);
2460
2461 /* write rate fallback retry limits */
2462 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2463 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2464
2465 AND_REG(&regs->ifs_ctl, 0x0FFF);
2466 W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2467
2468 /* dma initializations */
2469 wlc->txpend16165war = 0;
2470
2471 /* init the tx dma engines */
2472 for (i = 0; i < NFIFO; i++) {
2473 if (wlc_hw->di[i])
2474 dma_txinit(wlc_hw->di[i]);
2475 }
2476
2477 /* init the rx dma engine(s) and post receive buffers */
2478 dma_rxinit(wlc_hw->di[RX_FIFO]);
2479 dma_rxfill(wlc_hw->di[RX_FIFO]);
2480 }
2481
2482 /* This function is used for changing the tsf frac register
2483 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2484 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2485 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2486 * HTPHY Formula is 2^26/freq(MHz) e.g.
2487 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2488 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2489 * For spuron: 123MHz -> 2^26/123 = 545600.5
2490 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2491 * For spur off: 120MHz -> 2^26/120 = 559240.5
2492 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2493 */
2494
2495 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2496 {
2497 d11regs_t *regs;
2498 regs = wlc_hw->regs;
2499
2500 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2501 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2502 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2503 W_REG(&regs->tsf_clk_frac_l, 0x2082);
2504 W_REG(&regs->tsf_clk_frac_h, 0x8);
2505 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2506 W_REG(&regs->tsf_clk_frac_l, 0x5341);
2507 W_REG(&regs->tsf_clk_frac_h, 0x8);
2508 } else { /* 120Mhz */
2509 W_REG(&regs->tsf_clk_frac_l, 0x8889);
2510 W_REG(&regs->tsf_clk_frac_h, 0x8);
2511 }
2512 } else if (WLCISLCNPHY(wlc_hw->band)) {
2513 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2514 W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2515 W_REG(&regs->tsf_clk_frac_h, 0xC);
2516 } else { /* 80Mhz */
2517 W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2518 W_REG(&regs->tsf_clk_frac_h, 0xC);
2519 }
2520 }
2521 }
2522
2523 /* Initialize GPIOs that are controlled by D11 core */
2524 static void wlc_gpio_init(struct wlc_info *wlc)
2525 {
2526 struct wlc_hw_info *wlc_hw = wlc->hw;
2527 d11regs_t *regs;
2528 u32 gc, gm;
2529
2530 regs = wlc_hw->regs;
2531
2532 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2533 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2534
2535 /*
2536 * Common GPIO setup:
2537 * G0 = LED 0 = WLAN Activity
2538 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2539 * G2 = LED 2 = WLAN 5 GHz Radio State
2540 * G4 = radio disable input (HI enabled, LO disabled)
2541 */
2542
2543 gc = gm = 0;
2544
2545 /* Allocate GPIOs for mimo antenna diversity feature */
2546 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2547 /* Enable antenna diversity, use 2x3 mode */
2548 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2549 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2550 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2551 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2552
2553 /* init superswitch control */
2554 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2555
2556 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2557 ASSERT((gm & BOARD_GPIO_12) == 0);
2558 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2559 /*
2560 * The board itself is powered by these GPIOs
2561 * (when not sending pattern) so set them high
2562 */
2563 OR_REG(&regs->psm_gpio_oe,
2564 (BOARD_GPIO_12 | BOARD_GPIO_13));
2565 OR_REG(&regs->psm_gpio_out,
2566 (BOARD_GPIO_12 | BOARD_GPIO_13));
2567
2568 /* Enable antenna diversity, use 2x4 mode */
2569 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2570 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2571 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2572 WLC_BAND_ALL);
2573
2574 /* Configure the desired clock to be 4Mhz */
2575 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2576 ANTSEL_CLKDIV_4MHZ);
2577 }
2578
2579 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2580 if (wlc_hw->boardflags & BFL_PACTRL)
2581 gm |= gc |= BOARD_GPIO_PACTRL;
2582
2583 /* apply to gpiocontrol register */
2584 si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2585 }
2586
2587 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2588 {
2589 struct wlc_info *wlc;
2590 wlc = wlc_hw->wlc;
2591
2592 if (wlc_hw->ucode_loaded)
2593 return;
2594
2595 if (D11REV_IS(wlc_hw->corerev, 23)) {
2596 if (WLCISNPHY(wlc_hw->band)) {
2597 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2598 bcm43xx_16_mimosz);
2599 wlc_hw->ucode_loaded = true;
2600 } else
2601 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2602 __func__, wlc_hw->unit, wlc_hw->corerev);
2603 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2604 if (WLCISLCNPHY(wlc_hw->band)) {
2605 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2606 bcm43xx_24_lcnsz);
2607 wlc_hw->ucode_loaded = true;
2608 } else {
2609 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2610 __func__, wlc_hw->unit, wlc_hw->corerev);
2611 }
2612 }
2613 }
2614
2615 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2616 const uint nbytes) {
2617 d11regs_t *regs = wlc_hw->regs;
2618 uint i;
2619 uint count;
2620
2621 WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2622
2623 ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2624
2625 count = (nbytes / sizeof(u32));
2626
2627 W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2628 (void)R_REG(&regs->objaddr);
2629 for (i = 0; i < count; i++)
2630 W_REG(&regs->objdata, ucode[i]);
2631 }
2632
2633 static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2634 const struct d11init *inits)
2635 {
2636 int i;
2637 volatile u8 *base;
2638
2639 WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2640
2641 base = (volatile u8 *)wlc_hw->regs;
2642
2643 for (i = 0; inits[i].addr != 0xffff; i++) {
2644 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2645
2646 if (inits[i].size == 2)
2647 W_REG((u16 *)(base + inits[i].addr),
2648 inits[i].value);
2649 else if (inits[i].size == 4)
2650 W_REG((u32 *)(base + inits[i].addr),
2651 inits[i].value);
2652 }
2653 }
2654
2655 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2656 {
2657 u16 phyctl;
2658 u16 phytxant = wlc_hw->bmac_phytxant;
2659 u16 mask = PHY_TXC_ANT_MASK;
2660
2661 /* set the Probe Response frame phy control word */
2662 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2663 phyctl = (phyctl & ~mask) | phytxant;
2664 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2665
2666 /* set the Response (ACK/CTS) frame phy control word */
2667 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2668 phyctl = (phyctl & ~mask) | phytxant;
2669 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2670 }
2671
2672 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2673 {
2674 /* update sw state */
2675 wlc_hw->bmac_phytxant = phytxant;
2676
2677 /* push to ucode if up */
2678 if (!wlc_hw->up)
2679 return;
2680 wlc_ucode_txant_set(wlc_hw);
2681
2682 }
2683
2684 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2685 {
2686 return (u16) wlc_hw->wlc->stf->txant;
2687 }
2688
2689 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2690 {
2691 wlc_hw->antsel_type = antsel_type;
2692
2693 /* Update the antsel type for phy module to use */
2694 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2695 }
2696
2697 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2698 {
2699 bool fatal = false;
2700 uint unit;
2701 uint intstatus, idx;
2702 d11regs_t *regs = wlc_hw->regs;
2703
2704 unit = wlc_hw->unit;
2705
2706 for (idx = 0; idx < NFIFO; idx++) {
2707 /* read intstatus register and ignore any non-error bits */
2708 intstatus =
2709 R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2710 if (!intstatus)
2711 continue;
2712
2713 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2714 unit, idx, intstatus);
2715
2716 if (intstatus & I_RO) {
2717 WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2718 unit, idx);
2719 wlc_hw->wlc->pub->_cnt->rxoflo++;
2720 fatal = true;
2721 }
2722
2723 if (intstatus & I_PC) {
2724 WL_ERROR("wl%d: fifo %d: descriptor error\n",
2725 unit, idx);
2726 wlc_hw->wlc->pub->_cnt->dmade++;
2727 fatal = true;
2728 }
2729
2730 if (intstatus & I_PD) {
2731 WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2732 wlc_hw->wlc->pub->_cnt->dmada++;
2733 fatal = true;
2734 }
2735
2736 if (intstatus & I_DE) {
2737 WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2738 unit, idx);
2739 wlc_hw->wlc->pub->_cnt->dmape++;
2740 fatal = true;
2741 }
2742
2743 if (intstatus & I_RU) {
2744 WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2745 idx, unit);
2746 wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2747 }
2748
2749 if (intstatus & I_XU) {
2750 WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2751 idx, unit);
2752 wlc_hw->wlc->pub->_cnt->txuflo++;
2753 fatal = true;
2754 }
2755
2756 if (fatal) {
2757 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2758 break;
2759 } else
2760 W_REG(&regs->intctrlregs[idx].intstatus,
2761 intstatus);
2762 }
2763 }
2764
2765 void wlc_intrson(struct wlc_info *wlc)
2766 {
2767 struct wlc_hw_info *wlc_hw = wlc->hw;
2768 ASSERT(wlc->defmacintmask);
2769 wlc->macintmask = wlc->defmacintmask;
2770 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2771 }
2772
2773 /* callback for siutils.c, which has only wlc handler, no wl
2774 * they both check up, not only because there is no need to off/restore d11 interrupt
2775 * but also because per-port code may require sync with valid interrupt.
2776 */
2777
2778 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2779 {
2780 if (!wlc->hw->up)
2781 return 0;
2782
2783 return wl_intrsoff(wlc->wl);
2784 }
2785
2786 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2787 {
2788 if (!wlc->hw->up)
2789 return;
2790
2791 wl_intrsrestore(wlc->wl, macintmask);
2792 }
2793
2794 u32 wlc_intrsoff(struct wlc_info *wlc)
2795 {
2796 struct wlc_hw_info *wlc_hw = wlc->hw;
2797 u32 macintmask;
2798
2799 if (!wlc_hw->clk)
2800 return 0;
2801
2802 macintmask = wlc->macintmask; /* isr can still happen */
2803
2804 W_REG(&wlc_hw->regs->macintmask, 0);
2805 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2806 udelay(1); /* ensure int line is no longer driven */
2807 wlc->macintmask = 0;
2808
2809 /* return previous macintmask; resolve race between us and our isr */
2810 return wlc->macintstatus ? 0 : macintmask;
2811 }
2812
2813 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2814 {
2815 struct wlc_hw_info *wlc_hw = wlc->hw;
2816 if (!wlc_hw->clk)
2817 return;
2818
2819 wlc->macintmask = macintmask;
2820 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2821 }
2822
2823 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2824 {
2825 u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2826
2827 if (on) {
2828 /* suspend tx fifos */
2829 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2830 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2831 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2832 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2833
2834 /* zero the address match register so we do not send ACKs */
2835 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2836 null_ether_addr);
2837 } else {
2838 /* resume tx fifos */
2839 if (!wlc_hw->wlc->tx_suspended) {
2840 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2841 }
2842 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2843 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2844 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2845
2846 /* Restore address */
2847 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2848 wlc_hw->etheraddr);
2849 }
2850
2851 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2852
2853 if (on)
2854 wlc_ucode_mute_override_set(wlc_hw);
2855 else
2856 wlc_ucode_mute_override_clear(wlc_hw);
2857 }
2858
2859 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2860 {
2861 if (fifo >= NFIFO)
2862 return BCME_RANGE;
2863
2864 *blocks = wlc_hw->xmtfifo_sz[fifo];
2865
2866 return 0;
2867 }
2868
2869 /* wlc_bmac_tx_fifo_suspended:
2870 * Check the MAC's tx suspend status for a tx fifo.
2871 *
2872 * When the MAC acknowledges a tx suspend, it indicates that no more
2873 * packets will be transmitted out the radio. This is independent of
2874 * DMA channel suspension---the DMA may have finished suspending, or may still
2875 * be pulling data into a tx fifo, by the time the MAC acks the suspend
2876 * request.
2877 */
2878 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2879 {
2880 /* check that a suspend has been requested and is no longer pending */
2881
2882 /*
2883 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2884 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2885 * chnstatus register.
2886 * The tx fifo suspend completion is independent of the DMA suspend completion and
2887 * may be acked before or after the DMA is suspended.
2888 */
2889 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2890 (R_REG(&wlc_hw->regs->chnstatus) &
2891 (1 << tx_fifo)) == 0)
2892 return true;
2893
2894 return false;
2895 }
2896
2897 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2898 {
2899 u8 fifo = 1 << tx_fifo;
2900
2901 /* Two clients of this code, 11h Quiet period and scanning. */
2902
2903 /* only suspend if not already suspended */
2904 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2905 return;
2906
2907 /* force the core awake only if not already */
2908 if (wlc_hw->suspended_fifos == 0)
2909 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2910
2911 wlc_hw->suspended_fifos |= fifo;
2912
2913 if (wlc_hw->di[tx_fifo]) {
2914 /* Suspending AMPDU transmissions in the middle can cause underflow
2915 * which may result in mismatch between ucode and driver
2916 * so suspend the mac before suspending the FIFO
2917 */
2918 if (WLC_PHY_11N_CAP(wlc_hw->band))
2919 wlc_suspend_mac_and_wait(wlc_hw->wlc);
2920
2921 dma_txsuspend(wlc_hw->di[tx_fifo]);
2922
2923 if (WLC_PHY_11N_CAP(wlc_hw->band))
2924 wlc_enable_mac(wlc_hw->wlc);
2925 }
2926 }
2927
2928 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2929 {
2930 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2931 * here for PIO otherwise the watchdog will catch the inconsistency and fire
2932 */
2933 /* Two clients of this code, 11h Quiet period and scanning. */
2934 if (wlc_hw->di[tx_fifo])
2935 dma_txresume(wlc_hw->di[tx_fifo]);
2936
2937 /* allow core to sleep again */
2938 if (wlc_hw->suspended_fifos == 0)
2939 return;
2940 else {
2941 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2942 if (wlc_hw->suspended_fifos == 0)
2943 wlc_ucode_wake_override_clear(wlc_hw,
2944 WLC_WAKE_OVERRIDE_TXFIFO);
2945 }
2946 }
2947
2948 /*
2949 * Read and clear macintmask and macintstatus and intstatus registers.
2950 * This routine should be called with interrupts off
2951 * Return:
2952 * -1 if DEVICEREMOVED(wlc) evaluates to true;
2953 * 0 if the interrupt is not for us, or we are in some special cases;
2954 * device interrupt status bits otherwise.
2955 */
2956 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2957 {
2958 struct wlc_hw_info *wlc_hw = wlc->hw;
2959 d11regs_t *regs = wlc_hw->regs;
2960 u32 macintstatus;
2961
2962 /* macintstatus includes a DMA interrupt summary bit */
2963 macintstatus = R_REG(&regs->macintstatus);
2964
2965 WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
2966
2967 /* detect cardbus removed, in power down(suspend) and in reset */
2968 if (DEVICEREMOVED(wlc))
2969 return -1;
2970
2971 /* DEVICEREMOVED succeeds even when the core is still resetting,
2972 * handle that case here.
2973 */
2974 if (macintstatus == 0xffffffff)
2975 return 0;
2976
2977 /* defer unsolicited interrupts */
2978 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2979
2980 /* if not for us */
2981 if (macintstatus == 0)
2982 return 0;
2983
2984 /* interrupts are already turned off for CFE build
2985 * Caution: For CFE Turning off the interrupts again has some undesired
2986 * consequences
2987 */
2988 /* turn off the interrupts */
2989 W_REG(&regs->macintmask, 0);
2990 (void)R_REG(&regs->macintmask); /* sync readback */
2991 wlc->macintmask = 0;
2992
2993 /* clear device interrupts */
2994 W_REG(&regs->macintstatus, macintstatus);
2995
2996 /* MI_DMAINT is indication of non-zero intstatus */
2997 if (macintstatus & MI_DMAINT) {
2998 /*
2999 * only fifo interrupt enabled is I_RI in
3000 * RX_FIFO. If MI_DMAINT is set, assume it
3001 * is set and clear the interrupt.
3002 */
3003 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
3004 DEF_RXINTMASK);
3005 }
3006
3007 return macintstatus;
3008 }
3009
3010 /* Update wlc->macintstatus and wlc->intstatus[]. */
3011 /* Return true if they are updated successfully. false otherwise */
3012 bool wlc_intrsupd(struct wlc_info *wlc)
3013 {
3014 u32 macintstatus;
3015
3016 ASSERT(wlc->macintstatus != 0);
3017
3018 /* read and clear macintstatus and intstatus registers */
3019 macintstatus = wlc_intstatus(wlc, false);
3020
3021 /* device is removed */
3022 if (macintstatus == 0xffffffff)
3023 return false;
3024
3025 /* update interrupt status in software */
3026 wlc->macintstatus |= macintstatus;
3027
3028 return true;
3029 }
3030
3031 /*
3032 * First-level interrupt processing.
3033 * Return true if this was our interrupt, false otherwise.
3034 * *wantdpc will be set to true if further wlc_dpc() processing is required,
3035 * false otherwise.
3036 */
3037 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3038 {
3039 struct wlc_hw_info *wlc_hw = wlc->hw;
3040 u32 macintstatus;
3041
3042 *wantdpc = false;
3043
3044 if (!wlc_hw->up || !wlc->macintmask)
3045 return false;
3046
3047 /* read and clear macintstatus and intstatus registers */
3048 macintstatus = wlc_intstatus(wlc, true);
3049
3050 if (macintstatus == 0xffffffff)
3051 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3052
3053 /* it is not for us */
3054 if (macintstatus == 0)
3055 return false;
3056
3057 *wantdpc = true;
3058
3059 /* save interrupt status bits */
3060 ASSERT(wlc->macintstatus == 0);
3061 wlc->macintstatus = macintstatus;
3062
3063 return true;
3064
3065 }
3066
3067 static bool BCMFASTPATH
3068 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3069 {
3070 /* discard intermediate indications for ucode with one legitimate case:
3071 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3072 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3073 * transmission count)
3074 */
3075 if (!(txs->status & TX_STATUS_AMPDU)
3076 && (txs->status & TX_STATUS_INTERMEDIATE)) {
3077 return false;
3078 }
3079
3080 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3081 }
3082
3083 /* process tx completion events in BMAC
3084 * Return true if more tx status need to be processed. false otherwise.
3085 */
3086 static bool BCMFASTPATH
3087 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3088 {
3089 bool morepending = false;
3090 struct wlc_info *wlc = wlc_hw->wlc;
3091 d11regs_t *regs;
3092 tx_status_t txstatus, *txs;
3093 u32 s1, s2;
3094 uint n = 0;
3095 /*
3096 * Param 'max_tx_num' indicates max. # tx status to process before
3097 * break out.
3098 */
3099 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3100
3101 WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3102
3103 txs = &txstatus;
3104 regs = wlc_hw->regs;
3105 while (!(*fatal)
3106 && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
3107
3108 if (s1 == 0xffffffff) {
3109 WL_ERROR("wl%d: %s: dead chip\n",
3110 wlc_hw->unit, __func__);
3111 ASSERT(s1 != 0xffffffff);
3112 return morepending;
3113 }
3114
3115 s2 = R_REG(&regs->frmtxstatus2);
3116
3117 txs->status = s1 & TXS_STATUS_MASK;
3118 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3119 txs->sequence = s2 & TXS_SEQ_MASK;
3120 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3121 txs->lasttxtime = 0;
3122
3123 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3124
3125 /* !give others some time to run! */
3126 if (++n >= max_tx_num)
3127 break;
3128 }
3129
3130 if (*fatal)
3131 return 0;
3132
3133 if (n >= max_tx_num)
3134 morepending = true;
3135
3136 if (!pktq_empty(&wlc->active_queue->q))
3137 wlc_send_q(wlc, wlc->active_queue);
3138
3139 return morepending;
3140 }
3141
3142 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3143 {
3144 struct wlc_hw_info *wlc_hw = wlc->hw;
3145 d11regs_t *regs = wlc_hw->regs;
3146 u32 mc, mi;
3147
3148 WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3149 wlc_hw->unit, wlc_hw->band->bandunit);
3150
3151 /*
3152 * Track overlapping suspend requests
3153 */
3154 wlc_hw->mac_suspend_depth++;
3155 if (wlc_hw->mac_suspend_depth > 1)
3156 return;
3157
3158 /* force the core awake */
3159 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3160
3161 mc = R_REG(&regs->maccontrol);
3162
3163 if (mc == 0xffffffff) {
3164 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3165 wl_down(wlc->wl);
3166 return;
3167 }
3168 ASSERT(!(mc & MCTL_PSM_JMP_0));
3169 ASSERT(mc & MCTL_PSM_RUN);
3170 ASSERT(mc & MCTL_EN_MAC);
3171
3172 mi = R_REG(&regs->macintstatus);
3173 if (mi == 0xffffffff) {
3174 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3175 wl_down(wlc->wl);
3176 return;
3177 }
3178 ASSERT(!(mi & MI_MACSSPNDD));
3179
3180 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3181
3182 SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3183 WLC_MAX_MAC_SUSPEND);
3184
3185 if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3186 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3187 wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3188 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3189 wlc_hw->unit,
3190 R_REG(&regs->psmdebug),
3191 R_REG(&regs->phydebug),
3192 R_REG(&regs->psm_brc));
3193 }
3194
3195 mc = R_REG(&regs->maccontrol);
3196 if (mc == 0xffffffff) {
3197 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3198 wl_down(wlc->wl);
3199 return;
3200 }
3201 ASSERT(!(mc & MCTL_PSM_JMP_0));
3202 ASSERT(mc & MCTL_PSM_RUN);
3203 ASSERT(!(mc & MCTL_EN_MAC));
3204 }
3205
3206 void wlc_enable_mac(struct wlc_info *wlc)
3207 {
3208 struct wlc_hw_info *wlc_hw = wlc->hw;
3209 d11regs_t *regs = wlc_hw->regs;
3210 u32 mc, mi;
3211
3212 WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3213 wlc_hw->unit, wlc->band->bandunit);
3214
3215 /*
3216 * Track overlapping suspend requests
3217 */
3218 ASSERT(wlc_hw->mac_suspend_depth > 0);
3219 wlc_hw->mac_suspend_depth--;
3220 if (wlc_hw->mac_suspend_depth > 0)
3221 return;
3222
3223 mc = R_REG(&regs->maccontrol);
3224 ASSERT(!(mc & MCTL_PSM_JMP_0));
3225 ASSERT(!(mc & MCTL_EN_MAC));
3226 ASSERT(mc & MCTL_PSM_RUN);
3227
3228 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3229 W_REG(&regs->macintstatus, MI_MACSSPNDD);
3230
3231 mc = R_REG(&regs->maccontrol);
3232 ASSERT(!(mc & MCTL_PSM_JMP_0));
3233 ASSERT(mc & MCTL_EN_MAC);
3234 ASSERT(mc & MCTL_PSM_RUN);
3235
3236 mi = R_REG(&regs->macintstatus);
3237 ASSERT(!(mi & MI_MACSSPNDD));
3238
3239 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3240 }
3241
3242 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3243 {
3244 u8 rate;
3245 u8 rates[8] = {
3246 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3247 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3248 };
3249 u16 entry_ptr;
3250 u16 pctl1;
3251 uint i;
3252
3253 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3254 return;
3255
3256 /* walk the phy rate table and update the entries */
3257 for (i = 0; i < ARRAY_SIZE(rates); i++) {
3258 rate = rates[i];
3259
3260 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3261
3262 /* read the SHM Rate Table entry OFDM PCTL1 values */
3263 pctl1 =
3264 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3265
3266 /* modify the value */
3267 pctl1 &= ~PHY_TXC1_MODE_MASK;
3268 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3269
3270 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3271 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3272 pctl1);
3273 }
3274 }
3275
3276 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3277 {
3278 uint i;
3279 u8 plcp_rate = 0;
3280 struct plcp_signal_rate_lookup {
3281 u8 rate;
3282 u8 signal_rate;
3283 };
3284 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3285 const struct plcp_signal_rate_lookup rate_lookup[] = {
3286 {WLC_RATE_6M, 0xB},
3287 {WLC_RATE_9M, 0xF},
3288 {WLC_RATE_12M, 0xA},
3289 {WLC_RATE_18M, 0xE},
3290 {WLC_RATE_24M, 0x9},
3291 {WLC_RATE_36M, 0xD},
3292 {WLC_RATE_48M, 0x8},
3293 {WLC_RATE_54M, 0xC}
3294 };
3295
3296 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3297 if (rate == rate_lookup[i].rate) {
3298 plcp_rate = rate_lookup[i].signal_rate;
3299 break;
3300 }
3301 }
3302
3303 /* Find the SHM pointer to the rate table entry by looking in the
3304 * Direct-map Table
3305 */
3306 return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3307 }
3308
3309 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3310 {
3311 wlc_hw->hw_stf_ss_opmode = stf_mode;
3312
3313 if (wlc_hw->clk)
3314 wlc_upd_ofdm_pctl1_table(wlc_hw);
3315 }
3316
3317 void BCMFASTPATH
3318 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3319 u32 *tsf_h_ptr)
3320 {
3321 d11regs_t *regs = wlc_hw->regs;
3322
3323 /* read the tsf timer low, then high to get an atomic read */
3324 *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3325 *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3326
3327 return;
3328 }
3329
3330 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3331 {
3332 d11regs_t *regs;
3333 u32 w, val;
3334
3335 WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3336
3337 regs = wlc_hw->regs;
3338
3339 /* Validate dchip register access */
3340
3341 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3342 (void)R_REG(&regs->objaddr);
3343 w = R_REG(&regs->objdata);
3344
3345 /* Can we write and read back a 32bit register? */
3346 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3347 (void)R_REG(&regs->objaddr);
3348 W_REG(&regs->objdata, (u32) 0xaa5555aa);
3349
3350 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3351 (void)R_REG(&regs->objaddr);
3352 val = R_REG(&regs->objdata);
3353 if (val != (u32) 0xaa5555aa) {
3354 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3355 wlc_hw->unit, val);
3356 return false;
3357 }
3358
3359 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3360 (void)R_REG(&regs->objaddr);
3361 W_REG(&regs->objdata, (u32) 0x55aaaa55);
3362
3363 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3364 (void)R_REG(&regs->objaddr);
3365 val = R_REG(&regs->objdata);
3366 if (val != (u32) 0x55aaaa55) {
3367 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3368 wlc_hw->unit, val);
3369 return false;
3370 }
3371
3372 W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3373 (void)R_REG(&regs->objaddr);
3374 W_REG(&regs->objdata, w);
3375
3376 /* clear CFPStart */
3377 W_REG(&regs->tsf_cfpstart, 0);
3378
3379 w = R_REG(&regs->maccontrol);
3380 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3381 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3382 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3383 wlc_hw->unit, w,
3384 (MCTL_IHR_EN | MCTL_WAKE),
3385 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3386 return false;
3387 }
3388
3389 return true;
3390 }
3391
3392 #define PHYPLL_WAIT_US 100000
3393
3394 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3395 {
3396 d11regs_t *regs;
3397 u32 tmp;
3398
3399 WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3400
3401 tmp = 0;
3402 regs = wlc_hw->regs;
3403
3404 if (on) {
3405 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3406 OR_REG(&regs->clk_ctl_st,
3407 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3408 CCS_ERSRC_REQ_PHYPLL));
3409 SPINWAIT((R_REG(&regs->clk_ctl_st) &
3410 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3411 PHYPLL_WAIT_US);
3412
3413 tmp = R_REG(&regs->clk_ctl_st);
3414 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3415 (CCS_ERSRC_AVAIL_HT)) {
3416 WL_ERROR("%s: turn on PHY PLL failed\n",
3417 __func__);
3418 ASSERT(0);
3419 }
3420 } else {
3421 OR_REG(&regs->clk_ctl_st,
3422 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3423 SPINWAIT((R_REG(&regs->clk_ctl_st) &
3424 (CCS_ERSRC_AVAIL_D11PLL |
3425 CCS_ERSRC_AVAIL_PHYPLL)) !=
3426 (CCS_ERSRC_AVAIL_D11PLL |
3427 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3428
3429 tmp = R_REG(&regs->clk_ctl_st);
3430 if ((tmp &
3431 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3432 !=
3433 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3434 WL_ERROR("%s: turn on PHY PLL failed\n",
3435 __func__);
3436 ASSERT(0);
3437 }
3438 }
3439 } else {
3440 /* Since the PLL may be shared, other cores can still be requesting it;
3441 * so we'll deassert the request but not wait for status to comply.
3442 */
3443 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3444 tmp = R_REG(&regs->clk_ctl_st);
3445 }
3446 }
3447
3448 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3449 {
3450 bool dev_gone;
3451
3452 WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3453
3454 ASSERT(!wlc_hw->up);
3455
3456 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3457
3458 if (dev_gone)
3459 return;
3460
3461 if (wlc_hw->noreset)
3462 return;
3463
3464 /* radio off */
3465 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3466
3467 /* turn off analog core */
3468 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3469
3470 /* turn off PHYPLL to save power */
3471 wlc_bmac_core_phypll_ctl(wlc_hw, false);
3472
3473 /* No need to set wlc->pub->radio_active = OFF
3474 * because this function needs down capability and
3475 * radio_active is designed for BCMNODOWN.
3476 */
3477
3478 /* remove gpio controls */
3479 if (wlc_hw->ucode_dbgsel)
3480 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3481
3482 wlc_hw->clk = false;
3483 si_core_disable(wlc_hw->sih, 0);
3484 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3485 }
3486
3487 /* power both the pll and external oscillator on/off */
3488 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3489 {
3490 WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3491
3492 /* dont power down if plldown is false or we must poll hw radio disable */
3493 if (!want && wlc_hw->pllreq)
3494 return;
3495
3496 if (wlc_hw->sih)
3497 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3498
3499 wlc_hw->sbclk = want;
3500 if (!wlc_hw->sbclk) {
3501 wlc_hw->clk = false;
3502 if (wlc_hw->band && wlc_hw->band->pi)
3503 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3504 }
3505 }
3506
3507 static void wlc_flushqueues(struct wlc_info *wlc)
3508 {
3509 struct wlc_hw_info *wlc_hw = wlc->hw;
3510 uint i;
3511
3512 wlc->txpend16165war = 0;
3513
3514 /* free any posted tx packets */
3515 for (i = 0; i < NFIFO; i++)
3516 if (wlc_hw->di[i]) {
3517 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3518 TXPKTPENDCLR(wlc, i);
3519 WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3520 i);
3521 }
3522
3523 /* free any posted rx packets */
3524 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3525 }
3526
3527 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3528 {
3529 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3530 }
3531
3532 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3533 {
3534 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3535 }
3536
3537 /* Set a range of shared memory to a value.
3538 * SHM 'offset' needs to be an even address and
3539 * Buffer length 'len' must be an even number of bytes
3540 */
3541 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3542 {
3543 int i;
3544
3545 /* offset and len need to be even */
3546 ASSERT((offset & 1) == 0);
3547 ASSERT((len & 1) == 0);
3548
3549 if (len <= 0)
3550 return;
3551
3552 for (i = 0; i < len; i += 2) {
3553 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3554 }
3555 }
3556
3557 static u16
3558 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3559 {
3560 d11regs_t *regs = wlc_hw->regs;
3561 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3562 volatile u16 *objdata_hi = objdata_lo + 1;
3563 u16 v;
3564
3565 ASSERT((offset & 1) == 0);
3566
3567 W_REG(&regs->objaddr, sel | (offset >> 2));
3568 (void)R_REG(&regs->objaddr);
3569 if (offset & 2) {
3570 v = R_REG(objdata_hi);
3571 } else {
3572 v = R_REG(objdata_lo);
3573 }
3574
3575 return v;
3576 }
3577
3578 static void
3579 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3580 {
3581 d11regs_t *regs = wlc_hw->regs;
3582 volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3583 volatile u16 *objdata_hi = objdata_lo + 1;
3584
3585 ASSERT((offset & 1) == 0);
3586
3587 W_REG(&regs->objaddr, sel | (offset >> 2));
3588 (void)R_REG(&regs->objaddr);
3589 if (offset & 2) {
3590 W_REG(objdata_hi, v);
3591 } else {
3592 W_REG(objdata_lo, v);
3593 }
3594 }
3595
3596 /* Copy a buffer to shared memory of specified type .
3597 * SHM 'offset' needs to be an even address and
3598 * Buffer length 'len' must be an even number of bytes
3599 * 'sel' selects the type of memory
3600 */
3601 void
3602 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3603 int len, u32 sel)
3604 {
3605 u16 v;
3606 const u8 *p = (const u8 *)buf;
3607 int i;
3608
3609 /* offset and len need to be even */
3610 ASSERT((offset & 1) == 0);
3611 ASSERT((len & 1) == 0);
3612
3613 if (len <= 0)
3614 return;
3615
3616 for (i = 0; i < len; i += 2) {
3617 v = p[i] | (p[i + 1] << 8);
3618 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3619 }
3620 }
3621
3622 /* Copy a piece of shared memory of specified type to a buffer .
3623 * SHM 'offset' needs to be an even address and
3624 * Buffer length 'len' must be an even number of bytes
3625 * 'sel' selects the type of memory
3626 */
3627 void
3628 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3629 int len, u32 sel)
3630 {
3631 u16 v;
3632 u8 *p = (u8 *) buf;
3633 int i;
3634
3635 /* offset and len need to be even */
3636 ASSERT((offset & 1) == 0);
3637 ASSERT((len & 1) == 0);
3638
3639 if (len <= 0)
3640 return;
3641
3642 for (i = 0; i < len; i += 2) {
3643 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3644 p[i] = v & 0xFF;
3645 p[i + 1] = (v >> 8) & 0xFF;
3646 }
3647 }
3648
3649 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3650 {
3651 WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3652 wlc_hw->vars_size);
3653
3654 *buf = wlc_hw->vars;
3655 *len = wlc_hw->vars_size;
3656 }
3657
3658 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3659 {
3660 wlc_hw->SRL = SRL;
3661 wlc_hw->LRL = LRL;
3662
3663 /* write retry limit to SCR, shouldn't need to suspend */
3664 if (wlc_hw->up) {
3665 W_REG(&wlc_hw->regs->objaddr,
3666 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3667 (void)R_REG(&wlc_hw->regs->objaddr);
3668 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3669 W_REG(&wlc_hw->regs->objaddr,
3670 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3671 (void)R_REG(&wlc_hw->regs->objaddr);
3672 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3673 }
3674 }
3675
3676 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3677 {
3678 wlc_hw->noreset = noreset_flag;
3679 }
3680
3681 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3682 {
3683 ASSERT(req_bit);
3684
3685 if (set) {
3686 if (mboolisset(wlc_hw->pllreq, req_bit))
3687 return;
3688
3689 mboolset(wlc_hw->pllreq, req_bit);
3690
3691 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3692 if (!wlc_hw->sbclk) {
3693 wlc_bmac_xtal(wlc_hw, ON);
3694 }
3695 }
3696 } else {
3697 if (!mboolisset(wlc_hw->pllreq, req_bit))
3698 return;
3699
3700 mboolclr(wlc_hw->pllreq, req_bit);
3701
3702 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3703 if (wlc_hw->sbclk) {
3704 wlc_bmac_xtal(wlc_hw, OFF);
3705 }
3706 }
3707 }
3708
3709 return;
3710 }
3711
3712 /* this will be true for all ai chips */
3713 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
3714 {
3715 return true;
3716 }
3717
3718 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3719 {
3720 u16 table_ptr;
3721 u8 phy_rate, index;
3722
3723 /* get the phy specific rate encoding for the PLCP SIGNAL field */
3724 /* XXX4321 fixup needed ? */
3725 if (IS_OFDM(rate))
3726 table_ptr = M_RT_DIRMAP_A;
3727 else
3728 table_ptr = M_RT_DIRMAP_B;
3729
3730 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3731 * the index into the rate table.
3732 */
3733 phy_rate = rate_info[rate] & RATE_MASK;
3734 index = phy_rate & 0xf;
3735
3736 /* Find the SHM pointer to the rate table entry by looking in the
3737 * Direct-map Table
3738 */
3739 return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3740 }
3741
3742 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3743 {
3744 wlc_hw->antsel_avail = antsel_avail;
3745 }
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