2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
25 #include <proto/802.11.h>
29 #include <bcmendian.h>
41 #include <wlc_channel.h>
45 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
46 * dependencies. Need to include these to files to allow a clean include of wlc.h
47 * with WLC_HIGH defined.
48 * At some point we may be able to skip the include of wlc.h and instead just
49 * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
51 #include <wlc_event.h>
52 #include <wlc_mac80211.h>
54 #include <wlc_phy_shim.h>
55 #include <wlc_phy_hal.h>
56 #include <wl_export.h>
58 #include "d11ucode_ext.h"
61 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
62 * functions defined in the headers below. We should be eliminating those calls and
63 * will be able to delete these include lines.
65 #include <wlc_antsel.h>
67 #include <pcie_core.h>
69 #include <wlc_alloc.h>
72 #define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
74 #define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
75 #define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
76 #define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
77 #define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
79 #define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
81 #ifndef BMAC_DUP_TO_REMOVE
82 #define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
84 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
86 #endif /* BMAC_DUP_TO_REMOVE */
88 #define DMAREG(wlc_hw, direction, fifonum) (D11REV_LT(wlc_hw->corerev, 11) ? \
89 ((direction == DMA_TX) ? \
90 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
91 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
92 ((direction == DMA_TX) ? \
93 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
94 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
97 * The following table lists the buffer memory allocated to xmt fifos in HW.
98 * the size is in units of 256bytes(one block), total size is HW dependent
99 * ucode has default fifo partition, sw can overwrite if necessary
101 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
102 * the twiki is updated before making changes.
105 #define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
107 static u16 xmtfifo_sz
[][NFIFO
] = {
108 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
109 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
110 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
111 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
112 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
115 static void wlc_clkctl_clk(wlc_hw_info_t
*wlc
, uint mode
);
116 static void wlc_coreinit(wlc_info_t
*wlc
);
118 /* used by wlc_wakeucode_init() */
119 static void wlc_write_inits(wlc_hw_info_t
*wlc_hw
, const d11init_t
*inits
);
120 static void wlc_ucode_write(wlc_hw_info_t
*wlc_hw
, const u32 ucode
[],
122 static void wlc_ucode_download(wlc_hw_info_t
*wlc
);
123 static void wlc_ucode_txant_set(wlc_hw_info_t
*wlc_hw
);
125 /* used by wlc_dpc() */
126 static bool wlc_bmac_dotxstatus(wlc_hw_info_t
*wlc
, tx_status_t
*txs
,
128 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t
*wlc
);
129 static bool wlc_bmac_txstatus(wlc_hw_info_t
*wlc
, bool bound
, bool *fatal
);
130 static bool wlc_bmac_recv(wlc_hw_info_t
*wlc_hw
, uint fifo
, bool bound
);
132 /* used by wlc_down() */
133 static void wlc_flushqueues(wlc_info_t
*wlc
);
135 static void wlc_write_mhf(wlc_hw_info_t
*wlc_hw
, u16
*mhfs
);
136 static void wlc_mctrl_reset(wlc_hw_info_t
*wlc_hw
);
137 static void wlc_corerev_fifofixup(wlc_hw_info_t
*wlc_hw
);
139 /* Low Level Prototypes */
140 static u16
wlc_bmac_read_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
,
142 static void wlc_bmac_write_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
, u16 v
,
144 static bool wlc_bmac_attach_dmapio(wlc_info_t
*wlc
, uint j
, bool wme
);
145 static void wlc_bmac_detach_dmapio(wlc_hw_info_t
*wlc_hw
);
146 static void wlc_ucode_bsinit(wlc_hw_info_t
*wlc_hw
);
147 static bool wlc_validboardtype(wlc_hw_info_t
*wlc
);
148 static bool wlc_isgoodchip(wlc_hw_info_t
*wlc_hw
);
149 static char *wlc_get_macaddr(wlc_hw_info_t
*wlc_hw
);
150 static void wlc_mhfdef(wlc_info_t
*wlc
, u16
*mhfs
, u16 mhf2_init
);
151 static void wlc_mctrl_write(wlc_hw_info_t
*wlc_hw
);
152 static void wlc_ucode_mute_override_set(wlc_hw_info_t
*wlc_hw
);
153 static void wlc_ucode_mute_override_clear(wlc_hw_info_t
*wlc_hw
);
154 static u32
wlc_wlintrsoff(wlc_info_t
*wlc
);
155 static void wlc_wlintrsrestore(wlc_info_t
*wlc
, u32 macintmask
);
156 static void wlc_gpio_init(wlc_info_t
*wlc
);
157 static void wlc_write_hw_bcntemplate0(wlc_hw_info_t
*wlc_hw
, void *bcn
,
159 static void wlc_write_hw_bcntemplate1(wlc_hw_info_t
*wlc_hw
, void *bcn
,
161 static void wlc_bmac_bsinit(wlc_info_t
*wlc
, chanspec_t chanspec
);
162 static u32
wlc_setband_inact(wlc_info_t
*wlc
, uint bandunit
);
163 static void wlc_bmac_setband(wlc_hw_info_t
*wlc_hw
, uint bandunit
,
164 chanspec_t chanspec
);
165 static void wlc_bmac_update_slot_timing(wlc_hw_info_t
*wlc_hw
, bool shortslot
);
166 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t
*wlc_hw
);
167 static u16
wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t
*wlc_hw
,
170 /* === Low Level functions === */
172 void wlc_bmac_set_shortslot(wlc_hw_info_t
*wlc_hw
, bool shortslot
)
174 wlc_hw
->shortslot
= shortslot
;
176 if (BAND_2G(wlc_hw
->band
->bandtype
) && wlc_hw
->up
) {
177 wlc_suspend_mac_and_wait(wlc_hw
->wlc
);
178 wlc_bmac_update_slot_timing(wlc_hw
, shortslot
);
179 wlc_enable_mac(wlc_hw
->wlc
);
184 * Update the slot timing for standard 11b/g (20us slots)
185 * or shortslot 11g (9us slots)
186 * The PSM needs to be suspended for this call.
188 static void wlc_bmac_update_slot_timing(wlc_hw_info_t
*wlc_hw
, bool shortslot
)
190 struct osl_info
*osh
;
197 /* 11g short slot: 11a timing */
198 W_REG(osh
, ®s
->ifs_slot
, 0x0207); /* APHY_SLOT_TIME */
199 wlc_bmac_write_shm(wlc_hw
, M_DOT11_SLOT
, APHY_SLOT_TIME
);
201 /* 11g long slot: 11b timing */
202 W_REG(osh
, ®s
->ifs_slot
, 0x0212); /* BPHY_SLOT_TIME */
203 wlc_bmac_write_shm(wlc_hw
, M_DOT11_SLOT
, BPHY_SLOT_TIME
);
207 static void WLBANDINITFN(wlc_ucode_bsinit
) (wlc_hw_info_t
*wlc_hw
)
209 /* init microcode host flags */
210 wlc_write_mhf(wlc_hw
, wlc_hw
->band
->mhfs
);
212 /* do band-specific ucode IHR, SHM, and SCR inits */
213 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
214 if (WLCISNPHY(wlc_hw
->band
)) {
215 wlc_write_inits(wlc_hw
, d11n0bsinitvals16
);
217 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
218 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
221 if (D11REV_IS(wlc_hw
->corerev
, 24)) {
222 if (WLCISLCNPHY(wlc_hw
->band
)) {
223 wlc_write_inits(wlc_hw
, d11lcn0bsinitvals24
);
225 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
227 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
228 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
233 /* switch to new band but leave it inactive */
234 static u32
WLBANDINITFN(wlc_setband_inact
) (wlc_info_t
*wlc
, uint bandunit
)
236 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
240 WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw
->unit
));
242 ASSERT(bandunit
!= wlc_hw
->band
->bandunit
);
243 ASSERT(si_iscoreup(wlc_hw
->sih
));
244 ASSERT((R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
) & MCTL_EN_MAC
) ==
247 /* disable interrupts */
248 macintmask
= wl_intrsoff(wlc
->wl
);
251 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
255 if (D11REV_LT(wlc_hw
->corerev
, 17))
256 tmp
= R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
);
258 wlc_bmac_core_phy_clk(wlc_hw
, OFF
);
260 wlc_setxband(wlc_hw
, bandunit
);
265 /* Process received frames */
267 * Return true if more frames need to be processed. false otherwise.
268 * Param 'bound' indicates max. # frames to process before break out.
270 static bool BCMFASTPATH
271 wlc_bmac_recv(wlc_hw_info_t
*wlc_hw
, uint fifo
, bool bound
)
274 struct sk_buff
*head
= NULL
;
275 struct sk_buff
*tail
= NULL
;
277 uint bound_limit
= bound
? wlc_hw
->wlc
->pub
->tunables
->rxbnd
: -1;
279 wlc_d11rxhdr_t
*wlc_rxhdr
= NULL
;
281 WL_TRACE(("wl%d: %s\n", wlc_hw
->unit
, __func__
));
282 /* gather received frames */
283 while ((p
= dma_rx(wlc_hw
->di
[fifo
]))) {
292 /* !give others some time to run! */
293 if (++n
>= bound_limit
)
297 /* get the TSF REG reading */
298 wlc_bmac_read_tsf(wlc_hw
, &tsf_l
, &tsf_h
);
300 /* post more rbufs */
301 dma_rxfill(wlc_hw
->di
[fifo
]);
303 /* process each frame */
304 while ((p
= head
) != NULL
) {
308 /* record the tsf_l in wlc_rxd11hdr */
309 wlc_rxhdr
= (wlc_d11rxhdr_t
*) p
->data
;
310 wlc_rxhdr
->tsf_l
= htol32(tsf_l
);
312 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
313 wlc_phy_rssi_compute(wlc_hw
->band
->pi
, wlc_rxhdr
);
315 wlc_recv(wlc_hw
->wlc
, p
);
318 return n
>= bound_limit
;
321 /* second-level interrupt processing
322 * Return true if another dpc needs to be re-scheduled. false otherwise.
323 * Param 'bounded' indicates if applicable loops should be bounded.
325 bool BCMFASTPATH
wlc_dpc(wlc_info_t
*wlc
, bool bounded
)
328 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
329 d11regs_t
*regs
= wlc_hw
->regs
;
332 if (DEVICEREMOVED(wlc
)) {
333 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw
->unit
, __func__
));
338 /* grab and clear the saved software intstatus bits */
339 macintstatus
= wlc
->macintstatus
;
340 wlc
->macintstatus
= 0;
342 WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw
->unit
,
345 if (macintstatus
& MI_PRQ
) {
346 /* Process probe request FIFO */
347 ASSERT(0 && "PRQ Interrupt in non-MBSS");
350 /* BCN template is available */
351 /* ZZZ: Use AP_ACTIVE ? */
352 if (AP_ENAB(wlc
->pub
) && (!APSTA_ENAB(wlc
->pub
) || wlc
->aps_associated
)
353 && (macintstatus
& MI_BCNTPL
)) {
354 wlc_update_beacon(wlc
);
357 /* PMQ entry addition */
358 if (macintstatus
& MI_PMQ
) {
362 if (macintstatus
& MI_TFS
) {
363 if (wlc_bmac_txstatus(wlc
->hw
, bounded
, &fatal
))
364 wlc
->macintstatus
|= MI_TFS
;
366 WL_ERROR(("MI_TFS: fatal\n"));
371 if (macintstatus
& (MI_TBTT
| MI_DTIM_TBTT
))
374 /* ATIM window end */
375 if (macintstatus
& MI_ATIMWINEND
) {
376 WL_TRACE(("wlc_isr: end of ATIM window\n"));
378 OR_REG(wlc_hw
->osh
, ®s
->maccommand
, wlc
->qvalid
);
383 if (macintstatus
& MI_PHYTXERR
) {
384 WLCNTINCR(wlc
->pub
->_cnt
->txphyerr
);
387 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
388 if (macintstatus
& MI_DMAINT
) {
389 if (wlc_bmac_recv(wlc_hw
, RX_FIFO
, bounded
)) {
390 wlc
->macintstatus
|= MI_DMAINT
;
394 /* TX FIFO suspend/flush completion */
395 if (macintstatus
& MI_TXSTOP
) {
396 if (wlc_bmac_tx_fifo_suspended(wlc_hw
, TX_DATA_FIFO
)) {
397 /* WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
401 /* noise sample collected */
402 if (macintstatus
& MI_BG_NOISE
) {
403 wlc_phy_noise_sample_intr(wlc_hw
->band
->pi
);
406 if (macintstatus
& MI_GP0
) {
407 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw
->unit
, wlc_hw
->now
));
409 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
410 __func__
, CHIPID(wlc_hw
->sih
->chip
),
411 CHIPREV(wlc_hw
->sih
->chiprev
));
413 WLCNTINCR(wlc
->pub
->_cnt
->psmwds
);
419 /* gptimer timeout */
420 if (macintstatus
& MI_TO
) {
421 W_REG(wlc_hw
->osh
, ®s
->gptimer
, 0);
424 if (macintstatus
& MI_RFDISABLE
) {
426 u32 rfd
= R_REG(wlc_hw
->osh
, ®s
->phydebug
) & PDBG_RFD
;
429 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw
->unit
, rfd
));
431 WLCNTINCR(wlc
->pub
->_cnt
->rfdisable
);
434 /* send any enq'd tx packets. Just makes sure to jump start tx */
435 if (!pktq_empty(&wlc
->active_queue
->q
))
436 wlc_send_q(wlc
, wlc
->active_queue
);
438 ASSERT(wlc_ps_check(wlc
));
440 /* make sure the bound indication and the implementation are in sync */
441 ASSERT(bounded
== true || wlc
->macintstatus
== 0);
443 /* it isn't done and needs to be resched if macintstatus is non-zero */
444 return wlc
->macintstatus
!= 0;
448 return wlc
->macintstatus
!= 0;
451 /* common low-level watchdog code */
452 void wlc_bmac_watchdog(void *arg
)
454 wlc_info_t
*wlc
= (wlc_info_t
*) arg
;
455 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
457 WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw
->unit
));
462 /* increment second count */
465 /* Check for FIFO error interrupts */
466 wlc_bmac_fifoerrors(wlc_hw
);
468 /* make sure RX dma has buffers */
469 dma_rxfill(wlc
->hw
->di
[RX_FIFO
]);
470 if (D11REV_IS(wlc_hw
->corerev
, 4)) {
471 dma_rxfill(wlc
->hw
->di
[RX_TXSTATUS_FIFO
]);
474 wlc_phy_watchdog(wlc_hw
->band
->pi
);
478 wlc_bmac_set_chanspec(wlc_hw_info_t
*wlc_hw
, chanspec_t chanspec
, bool mute
,
479 struct txpwr_limits
*txpwr
)
483 WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw
->unit
,
486 wlc_hw
->chanspec
= chanspec
;
488 /* Switch bands if necessary */
489 if (NBANDS_HW(wlc_hw
) > 1) {
490 bandunit
= CHSPEC_WLCBANDUNIT(chanspec
);
491 if (wlc_hw
->band
->bandunit
!= bandunit
) {
492 /* wlc_bmac_setband disables other bandunit,
493 * use light band switch if not up yet
496 wlc_phy_chanspec_radio_set(wlc_hw
->
497 bandstate
[bandunit
]->
499 wlc_bmac_setband(wlc_hw
, bandunit
, chanspec
);
501 wlc_setxband(wlc_hw
, bandunit
);
506 wlc_phy_initcal_enable(wlc_hw
->band
->pi
, !mute
);
510 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
,
512 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
514 wlc_phy_chanspec_set(wlc_hw
->band
->pi
, chanspec
);
515 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
, chanspec
);
517 /* Update muting of the channel */
518 wlc_bmac_mute(wlc_hw
, mute
, 0);
522 int wlc_bmac_revinfo_get(wlc_hw_info_t
*wlc_hw
, wlc_bmac_revinfo_t
*revinfo
)
524 si_t
*sih
= wlc_hw
->sih
;
527 revinfo
->vendorid
= wlc_hw
->vendorid
;
528 revinfo
->deviceid
= wlc_hw
->deviceid
;
530 revinfo
->boardrev
= wlc_hw
->boardrev
;
531 revinfo
->corerev
= wlc_hw
->corerev
;
532 revinfo
->sromrev
= wlc_hw
->sromrev
;
533 revinfo
->chiprev
= sih
->chiprev
;
534 revinfo
->chip
= sih
->chip
;
535 revinfo
->chippkg
= sih
->chippkg
;
536 revinfo
->boardtype
= sih
->boardtype
;
537 revinfo
->boardvendor
= sih
->boardvendor
;
538 revinfo
->bustype
= sih
->bustype
;
539 revinfo
->buscoretype
= sih
->buscoretype
;
540 revinfo
->buscorerev
= sih
->buscorerev
;
541 revinfo
->issim
= sih
->issim
;
543 revinfo
->nbands
= NBANDS_HW(wlc_hw
);
545 for (idx
= 0; idx
< NBANDS_HW(wlc_hw
); idx
++) {
546 wlc_hwband_t
*band
= wlc_hw
->bandstate
[idx
];
547 revinfo
->band
[idx
].bandunit
= band
->bandunit
;
548 revinfo
->band
[idx
].bandtype
= band
->bandtype
;
549 revinfo
->band
[idx
].phytype
= band
->phytype
;
550 revinfo
->band
[idx
].phyrev
= band
->phyrev
;
551 revinfo
->band
[idx
].radioid
= band
->radioid
;
552 revinfo
->band
[idx
].radiorev
= band
->radiorev
;
553 revinfo
->band
[idx
].abgphy_encore
= band
->abgphy_encore
;
554 revinfo
->band
[idx
].anarev
= 0;
560 int wlc_bmac_state_get(wlc_hw_info_t
*wlc_hw
, wlc_bmac_state_t
*state
)
562 state
->machwcap
= wlc_hw
->machwcap
;
567 static bool wlc_bmac_attach_dmapio(wlc_info_t
*wlc
, uint j
, bool wme
)
571 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
573 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
574 uint unit
= wlc_hw
->unit
;
575 wlc_tunables_t
*tune
= wlc
->pub
->tunables
;
577 /* name and offsets for dma_attach */
578 snprintf(name
, sizeof(name
), "wl%d", unit
);
580 if (wlc_hw
->di
[0] == 0) { /* Init FIFOs */
582 int dma_attach_err
= 0;
583 struct osl_info
*osh
= wlc_hw
->osh
;
585 /* Find out the DMA addressing capability and let OS know
586 * All the channels within one DMA core have 'common-minimum' same
590 dma_addrwidth(wlc_hw
->sih
, DMAREG(wlc_hw
, DMA_TX
, 0));
591 OSL_DMADDRWIDTH(osh
, addrwidth
);
593 if (!wl_alloc_dma_resources(wlc_hw
->wlc
->wl
, addrwidth
)) {
594 WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit
));
600 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
601 * RX: RX_FIFO (RX data packets)
603 ASSERT(TX_AC_BK_FIFO
== 0);
604 ASSERT(RX_FIFO
== 0);
605 wlc_hw
->di
[0] = dma_attach(osh
, name
, wlc_hw
->sih
,
606 (wme
? DMAREG(wlc_hw
, DMA_TX
, 0) :
607 NULL
), DMAREG(wlc_hw
, DMA_RX
, 0),
608 (wme
? tune
->ntxd
: 0), tune
->nrxd
,
609 tune
->rxbufsz
, -1, tune
->nrxbufpost
,
610 WL_HWRXOFF
, &wl_msg_level
);
611 dma_attach_err
|= (NULL
== wlc_hw
->di
[0]);
615 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
616 * (legacy) TX_DATA_FIFO (TX data packets)
619 ASSERT(TX_AC_BE_FIFO
== 1);
620 ASSERT(TX_DATA_FIFO
== 1);
621 wlc_hw
->di
[1] = dma_attach(osh
, name
, wlc_hw
->sih
,
622 DMAREG(wlc_hw
, DMA_TX
, 1), NULL
,
623 tune
->ntxd
, 0, 0, -1, 0, 0,
625 dma_attach_err
|= (NULL
== wlc_hw
->di
[1]);
629 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
632 ASSERT(TX_AC_VI_FIFO
== 2);
633 wlc_hw
->di
[2] = dma_attach(osh
, name
, wlc_hw
->sih
,
634 DMAREG(wlc_hw
, DMA_TX
, 2), NULL
,
635 tune
->ntxd
, 0, 0, -1, 0, 0,
637 dma_attach_err
|= (NULL
== wlc_hw
->di
[2]);
640 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
641 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
642 * RX: RX_TXSTATUS_FIFO (transmit-status packets)
643 * for corerev < 5 only
645 ASSERT(TX_AC_VO_FIFO
== 3);
646 ASSERT(TX_CTL_FIFO
== 3);
647 if (D11REV_IS(wlc_hw
->corerev
, 4)) {
648 ASSERT(RX_TXSTATUS_FIFO
== 3);
649 wlc_hw
->di
[3] = dma_attach(osh
, name
, wlc_hw
->sih
,
650 DMAREG(wlc_hw
, DMA_TX
, 3),
651 DMAREG(wlc_hw
, DMA_RX
, 3),
652 tune
->ntxd
, tune
->nrxd
,
653 sizeof(tx_status_t
), -1,
656 dma_attach_err
|= (NULL
== wlc_hw
->di
[3]);
658 wlc_hw
->di
[3] = dma_attach(osh
, name
, wlc_hw
->sih
,
659 DMAREG(wlc_hw
, DMA_TX
, 3),
660 NULL
, tune
->ntxd
, 0, 0, -1,
661 0, 0, &wl_msg_level
);
662 dma_attach_err
|= (NULL
== wlc_hw
->di
[3]);
664 /* Cleaner to leave this as if with AP defined */
666 if (dma_attach_err
) {
667 WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
672 /* get pointer to dma engine tx flow control variable */
673 for (i
= 0; i
< NFIFO
; i
++)
676 (uint
*) dma_getvar(wlc_hw
->di
[i
],
680 /* initial ucode host flags */
681 wlc_mhfdef(wlc
, wlc_hw
->band
->mhfs
, pio_mhf2
);
686 static void wlc_bmac_detach_dmapio(wlc_hw_info_t
*wlc_hw
)
690 for (j
= 0; j
< NFIFO
; j
++) {
692 dma_detach(wlc_hw
->di
[j
]);
693 wlc_hw
->di
[j
] = NULL
;
699 * run backplane attach, init nvram
701 * initialize software state for each core and band
702 * put the whole chip in reset(driver down state), no clock
704 int wlc_bmac_attach(wlc_info_t
*wlc
, u16 vendor
, u16 device
, uint unit
,
705 bool piomode
, struct osl_info
*osh
, void *regsva
,
706 uint bustype
, void *btparam
)
708 wlc_hw_info_t
*wlc_hw
;
710 char *macaddr
= NULL
;
715 shared_phy_params_t sha_params
;
717 WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit
,
720 ASSERT(sizeof(wlc_d11rxhdr_t
) <= WL_HWRXOFF
);
728 wlc_hw
->band
= wlc_hw
->bandstate
[0];
729 wlc_hw
->_piomode
= piomode
;
731 /* populate wlc_hw_info_t with default values */
732 wlc_bmac_info_init(wlc_hw
);
735 * Do the hardware portion of the attach.
736 * Also initialize software state that depends on the particular hardware
739 wlc_hw
->sih
= si_attach((uint
) device
, osh
, regsva
, bustype
, btparam
,
740 &wlc_hw
->vars
, &wlc_hw
->vars_size
);
741 if (wlc_hw
->sih
== NULL
) {
742 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit
));
749 * Get vendid/devid nvram overwrites, which could be different
750 * than those the BIOS recognizes for devices on PCMCIA_BUS,
751 * SDIO_BUS, and SROMless devices on PCI_BUS.
754 bustype
= BCMBUSTYPE
;
756 if (bustype
!= SI_BUS
) {
759 var
= getvar(vars
, "vendid");
761 vendor
= (u16
) simple_strtoul(var
, NULL
, 0);
762 WL_ERROR(("Overriding vendor id = 0x%x\n", vendor
));
764 var
= getvar(vars
, "devid");
766 u16 devid
= (u16
) simple_strtoul(var
, NULL
, 0);
767 if (devid
!= 0xffff) {
769 WL_ERROR(("Overriding device id = 0x%x\n",
774 /* verify again the device is supported */
775 if (!wlc_chipmatch(vendor
, device
)) {
776 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit
, vendor
, device
));
782 wlc_hw
->vendorid
= vendor
;
783 wlc_hw
->deviceid
= device
;
785 /* set bar0 window to point at D11 core */
786 wlc_hw
->regs
= (d11regs_t
*) si_setcore(wlc_hw
->sih
, D11_CORE_ID
, 0);
787 wlc_hw
->corerev
= si_corerev(wlc_hw
->sih
);
791 wlc
->regs
= wlc_hw
->regs
;
793 /* validate chip, chiprev and corerev */
794 if (!wlc_isgoodchip(wlc_hw
)) {
799 /* initialize power control registers */
800 si_clkctl_init(wlc_hw
->sih
);
802 /* request fastclock and force fastclock for the rest of attach
803 * bring the d11 core out of reset.
804 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
805 * But it will be called again inside wlc_corereset, after d11 is out of reset.
807 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
808 wlc_bmac_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
810 if (!wlc_bmac_validate_chip_access(wlc_hw
)) {
811 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit
));
816 /* get the board rev, used just below */
817 j
= getintvar(vars
, "boardrev");
818 /* promote srom boardrev of 0xFF to 1 */
819 if (j
== BOARDREV_PROMOTABLE
)
820 j
= BOARDREV_PROMOTED
;
821 wlc_hw
->boardrev
= (u16
) j
;
822 if (!wlc_validboardtype(wlc_hw
)) {
823 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit
, wlc_hw
->sih
->boardtype
, wlc_hw
->boardrev
));
827 wlc_hw
->sromrev
= (u8
) getintvar(vars
, "sromrev");
828 wlc_hw
->boardflags
= (u32
) getintvar(vars
, "boardflags");
829 wlc_hw
->boardflags2
= (u32
) getintvar(vars
, "boardflags2");
831 if (D11REV_LE(wlc_hw
->corerev
, 4)
832 || (wlc_hw
->boardflags
& BFL_NOPLLDOWN
))
833 wlc_bmac_pllreq(wlc_hw
, true, WLC_PLLREQ_SHARED
);
835 if ((wlc_hw
->sih
->bustype
== PCI_BUS
)
836 && (si_pci_war16165(wlc_hw
->sih
)))
837 wlc
->war16165
= true;
839 /* check device id(srom, nvram etc.) to set bands */
840 if (wlc_hw
->deviceid
== BCM43224_D11N_ID
) {
841 /* Dualband boards */
846 if ((CHIPID(wlc_hw
->sih
->chip
) == BCM43225_CHIP_ID
))
849 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
850 * init of these values
852 wlc
->vendorid
= wlc_hw
->vendorid
;
853 wlc
->deviceid
= wlc_hw
->deviceid
;
854 wlc
->pub
->sih
= wlc_hw
->sih
;
855 wlc
->pub
->corerev
= wlc_hw
->corerev
;
856 wlc
->pub
->sromrev
= wlc_hw
->sromrev
;
857 wlc
->pub
->boardrev
= wlc_hw
->boardrev
;
858 wlc
->pub
->boardflags
= wlc_hw
->boardflags
;
859 wlc
->pub
->boardflags2
= wlc_hw
->boardflags2
;
860 wlc
->pub
->_nbands
= wlc_hw
->_nbands
;
862 wlc_hw
->physhim
= wlc_phy_shim_attach(wlc_hw
, wlc
->wl
, wlc
);
864 if (wlc_hw
->physhim
== NULL
) {
865 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
871 /* pass all the parameters to wlc_phy_shared_attach in one struct */
872 sha_params
.osh
= osh
;
873 sha_params
.sih
= wlc_hw
->sih
;
874 sha_params
.physhim
= wlc_hw
->physhim
;
875 sha_params
.unit
= unit
;
876 sha_params
.corerev
= wlc_hw
->corerev
;
877 sha_params
.vars
= vars
;
878 sha_params
.vid
= wlc_hw
->vendorid
;
879 sha_params
.did
= wlc_hw
->deviceid
;
880 sha_params
.chip
= wlc_hw
->sih
->chip
;
881 sha_params
.chiprev
= wlc_hw
->sih
->chiprev
;
882 sha_params
.chippkg
= wlc_hw
->sih
->chippkg
;
883 sha_params
.sromrev
= wlc_hw
->sromrev
;
884 sha_params
.boardtype
= wlc_hw
->sih
->boardtype
;
885 sha_params
.boardrev
= wlc_hw
->boardrev
;
886 sha_params
.boardvendor
= wlc_hw
->sih
->boardvendor
;
887 sha_params
.boardflags
= wlc_hw
->boardflags
;
888 sha_params
.boardflags2
= wlc_hw
->boardflags2
;
889 sha_params
.bustype
= wlc_hw
->sih
->bustype
;
890 sha_params
.buscorerev
= wlc_hw
->sih
->buscorerev
;
892 /* alloc and save pointer to shared phy state area */
893 wlc_hw
->phy_sh
= wlc_phy_shared_attach(&sha_params
);
894 if (!wlc_hw
->phy_sh
) {
899 /* initialize software state for each core and band */
900 for (j
= 0; j
< NBANDS_HW(wlc_hw
); j
++) {
902 * band0 is always 2.4Ghz
903 * band1, if present, is 5Ghz
906 /* So if this is a single band 11a card, use band 1 */
907 if (IS_SINGLEBAND_5G(wlc_hw
->deviceid
))
910 wlc_setxband(wlc_hw
, j
);
912 wlc_hw
->band
->bandunit
= j
;
913 wlc_hw
->band
->bandtype
= j
? WLC_BAND_5G
: WLC_BAND_2G
;
914 wlc
->band
->bandunit
= j
;
915 wlc
->band
->bandtype
= j
? WLC_BAND_5G
: WLC_BAND_2G
;
916 wlc
->core
->coreidx
= si_coreidx(wlc_hw
->sih
);
918 if (D11REV_GE(wlc_hw
->corerev
, 13)) {
919 wlc_hw
->machwcap
= R_REG(wlc_hw
->osh
, ®s
->machwcap
);
920 wlc_hw
->machwcap_backup
= wlc_hw
->machwcap
;
923 /* init tx fifo size */
924 ASSERT((wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
) <
925 ARRAY_SIZE(xmtfifo_sz
));
927 xmtfifo_sz
[(wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
)];
929 /* Get a phy for this band */
930 wlc_hw
->band
->pi
= wlc_phy_attach(wlc_hw
->phy_sh
,
931 (void *)regs
, wlc_hw
->band
->bandtype
, vars
);
932 if (wlc_hw
->band
->pi
== NULL
) {
933 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit
));
938 wlc_phy_machwcap_set(wlc_hw
->band
->pi
, wlc_hw
->machwcap
);
940 wlc_phy_get_phyversion(wlc_hw
->band
->pi
, &wlc_hw
->band
->phytype
,
941 &wlc_hw
->band
->phyrev
,
942 &wlc_hw
->band
->radioid
,
943 &wlc_hw
->band
->radiorev
);
944 wlc_hw
->band
->abgphy_encore
=
945 wlc_phy_get_encore(wlc_hw
->band
->pi
);
946 wlc
->band
->abgphy_encore
= wlc_phy_get_encore(wlc_hw
->band
->pi
);
947 wlc_hw
->band
->core_flags
=
948 wlc_phy_get_coreflags(wlc_hw
->band
->pi
);
950 /* verify good phy_type & supported phy revision */
951 if (WLCISNPHY(wlc_hw
->band
)) {
952 if (NCONF_HAS(wlc_hw
->band
->phyrev
))
956 } else if (WLCISLCNPHY(wlc_hw
->band
)) {
957 if (LCNCONF_HAS(wlc_hw
->band
->phyrev
))
963 WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit
, wlc_hw
->band
->phytype
, wlc_hw
->band
->phyrev
));
969 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
970 * high level attach. However we can not make that change until all low level access
971 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
972 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
973 * low only init when all fns updated.
975 wlc
->band
->pi
= wlc_hw
->band
->pi
;
976 wlc
->band
->phytype
= wlc_hw
->band
->phytype
;
977 wlc
->band
->phyrev
= wlc_hw
->band
->phyrev
;
978 wlc
->band
->radioid
= wlc_hw
->band
->radioid
;
979 wlc
->band
->radiorev
= wlc_hw
->band
->radiorev
;
981 /* default contention windows size limits */
982 wlc_hw
->band
->CWmin
= APHY_CWMIN
;
983 wlc_hw
->band
->CWmax
= PHY_CWMAX
;
985 if (!wlc_bmac_attach_dmapio(wlc
, j
, wme
)) {
991 /* disable core to match driver "down" state */
992 wlc_coredisable(wlc_hw
);
994 /* Match driver "down" state */
995 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
996 si_pci_down(wlc_hw
->sih
);
998 /* register sb interrupt callback functions */
999 si_register_intr_callback(wlc_hw
->sih
, (void *)wlc_wlintrsoff
,
1000 (void *)wlc_wlintrsrestore
, NULL
, wlc
);
1002 /* turn off pll and xtal to match driver "down" state */
1003 wlc_bmac_xtal(wlc_hw
, OFF
);
1005 /* *********************************************************************
1006 * The hardware is in the DOWN state at this point. D11 core
1007 * or cores are in reset with clocks off, and the board PLLs
1008 * are off if possible.
1010 * Beyond this point, wlc->sbclk == false and chip registers
1011 * should not be touched.
1012 *********************************************************************
1015 /* init etheraddr state variables */
1016 macaddr
= wlc_get_macaddr(wlc_hw
);
1017 if (macaddr
== NULL
) {
1018 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit
));
1022 bcm_ether_atoe(macaddr
, &wlc_hw
->etheraddr
);
1023 if (ETHER_ISBCAST((char *)&wlc_hw
->etheraddr
) ||
1024 ETHER_ISNULLADDR((char *)&wlc_hw
->etheraddr
)) {
1025 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit
,
1031 WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1032 __func__
, wlc_hw
->deviceid
, wlc_hw
->_nbands
,
1033 wlc_hw
->sih
->boardtype
, macaddr
));
1038 WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit
, err
));
1043 * Initialize wlc_info default values ...
1044 * may get overrides later in this function
1045 * BMAC_NOTES, move low out and resolve the dangling ones
1047 void wlc_bmac_info_init(wlc_hw_info_t
*wlc_hw
)
1049 wlc_info_t
*wlc
= wlc_hw
->wlc
;
1051 /* set default sw macintmask value */
1052 wlc
->defmacintmask
= DEF_MACINTMASK
;
1054 /* various 802.11g modes */
1055 wlc_hw
->shortslot
= false;
1057 wlc_hw
->SFBL
= RETRY_SHORT_FB
;
1058 wlc_hw
->LFBL
= RETRY_LONG_FB
;
1060 /* default mac retry limits */
1061 wlc_hw
->SRL
= RETRY_SHORT_DEF
;
1062 wlc_hw
->LRL
= RETRY_LONG_DEF
;
1063 wlc_hw
->chanspec
= CH20MHZ_CHSPEC(1);
1069 int wlc_bmac_detach(wlc_info_t
*wlc
)
1073 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
1079 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1080 * interrupt object may has been freed. this must be done before sb core switch
1082 si_deregister_intr_callback(wlc_hw
->sih
);
1084 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1085 si_pci_sleep(wlc_hw
->sih
);
1088 wlc_bmac_detach_dmapio(wlc_hw
);
1090 band
= wlc_hw
->band
;
1091 for (i
= 0; i
< NBANDS_HW(wlc_hw
); i
++) {
1093 /* Detach this band's phy */
1094 wlc_phy_detach(band
->pi
);
1097 band
= wlc_hw
->bandstate
[OTHERBANDUNIT(wlc
)];
1100 /* Free shared phy state */
1101 wlc_phy_shared_detach(wlc_hw
->phy_sh
);
1103 wlc_phy_shim_detach(wlc_hw
->physhim
);
1107 kfree(wlc_hw
->vars
);
1108 wlc_hw
->vars
= NULL
;
1112 si_detach(wlc_hw
->sih
);
1120 void wlc_bmac_reset(wlc_hw_info_t
*wlc_hw
)
1122 WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw
->unit
));
1124 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->reset
);
1126 /* reset the core */
1127 if (!DEVICEREMOVED(wlc_hw
->wlc
))
1128 wlc_bmac_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
1130 /* purge the dma rings */
1131 wlc_flushqueues(wlc_hw
->wlc
);
1133 wlc_reset_bmac_done(wlc_hw
->wlc
);
1137 wlc_bmac_init(wlc_hw_info_t
*wlc_hw
, chanspec_t chanspec
,
1141 wlc_info_t
*wlc
= wlc_hw
->wlc
;
1143 WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw
->unit
));
1145 /* request FAST clock if not on */
1146 fastclk
= wlc_hw
->forcefastclk
;
1148 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
1150 /* disable interrupts */
1151 macintmask
= wl_intrsoff(wlc
->wl
);
1153 /* set up the specified band and chanspec */
1154 wlc_setxband(wlc_hw
, CHSPEC_WLCBANDUNIT(chanspec
));
1155 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
1157 /* do one-time phy inits and calibration */
1158 wlc_phy_cal_init(wlc_hw
->band
->pi
);
1160 /* core-specific initialization */
1163 /* suspend the tx fifos and mute the phy for preism cac time */
1165 wlc_bmac_mute(wlc_hw
, ON
, PHY_MUTE_FOR_PREISM
);
1167 /* band-specific inits */
1168 wlc_bmac_bsinit(wlc
, chanspec
);
1170 /* restore macintmask */
1171 wl_intrsrestore(wlc
->wl
, macintmask
);
1173 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1174 * and wlc_enable_mac() will clear this override bit.
1176 mboolset(wlc_hw
->wake_override
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
1179 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1181 wlc_hw
->mac_suspend_depth
= 1;
1183 /* restore the clk */
1185 wlc_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1188 int wlc_bmac_up_prep(wlc_hw_info_t
*wlc_hw
)
1192 WL_TRACE(("wl%d: %s:\n", wlc_hw
->unit
, __func__
));
1194 ASSERT(wlc_hw
->wlc
->pub
->hw_up
&& wlc_hw
->wlc
->macintmask
== 0);
1197 * Enable pll and xtal, initialize the power control registers,
1198 * and force fastclock for the remainder of wlc_up().
1200 wlc_bmac_xtal(wlc_hw
, ON
);
1201 si_clkctl_init(wlc_hw
->sih
);
1202 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
1205 * Configure pci/pcmcia here instead of in wlc_attach()
1206 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1208 coremask
= (1 << wlc_hw
->wlc
->core
->coreidx
);
1210 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1211 si_pci_setup(wlc_hw
->sih
, coremask
);
1213 ASSERT(si_coreid(wlc_hw
->sih
) == D11_CORE_ID
);
1216 * Need to read the hwradio status here to cover the case where the system
1217 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1219 if (wlc_bmac_radio_read_hwdisabled(wlc_hw
)) {
1220 /* put SB PCI in down state again */
1221 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1222 si_pci_down(wlc_hw
->sih
);
1223 wlc_bmac_xtal(wlc_hw
, OFF
);
1224 return BCME_RADIOOFF
;
1227 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1228 si_pci_up(wlc_hw
->sih
);
1230 /* reset the d11 core */
1231 wlc_bmac_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
1236 int wlc_bmac_up_finish(wlc_hw_info_t
*wlc_hw
)
1238 WL_TRACE(("wl%d: %s:\n", wlc_hw
->unit
, __func__
));
1241 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, true);
1243 /* FULLY enable dynamic power control and d11 core interrupt */
1244 wlc_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1245 ASSERT(wlc_hw
->wlc
->macintmask
== 0);
1246 wl_intrson(wlc_hw
->wlc
->wl
);
1250 int wlc_bmac_down_prep(wlc_hw_info_t
*wlc_hw
)
1255 WL_TRACE(("wl%d: %s:\n", wlc_hw
->unit
, __func__
));
1260 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
1262 /* disable interrupts */
1264 wlc_hw
->wlc
->macintmask
= 0;
1266 /* now disable interrupts */
1267 wl_intrsoff(wlc_hw
->wlc
->wl
);
1269 /* ensure we're running on the pll clock again */
1270 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
1272 /* down phy at the last of this stage */
1273 callbacks
+= wlc_phy_down(wlc_hw
->band
->pi
);
1278 int wlc_bmac_down_finish(wlc_hw_info_t
*wlc_hw
)
1283 WL_TRACE(("wl%d: %s:\n", wlc_hw
->unit
, __func__
));
1289 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, false);
1291 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
1294 wlc_hw
->sbclk
= false;
1295 wlc_hw
->clk
= false;
1296 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
1298 /* reclaim any posted packets */
1299 wlc_flushqueues(wlc_hw
->wlc
);
1302 /* Reset and disable the core */
1303 if (si_iscoreup(wlc_hw
->sih
)) {
1304 if (R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
) &
1306 wlc_suspend_mac_and_wait(wlc_hw
->wlc
);
1307 callbacks
+= wl_reset(wlc_hw
->wlc
->wl
);
1308 wlc_coredisable(wlc_hw
);
1311 /* turn off primary xtal and pll */
1312 if (!wlc_hw
->noreset
) {
1313 if (wlc_hw
->sih
->bustype
== PCI_BUS
)
1314 si_pci_down(wlc_hw
->sih
);
1315 wlc_bmac_xtal(wlc_hw
, OFF
);
1322 void wlc_bmac_wait_for_wake(wlc_hw_info_t
*wlc_hw
)
1324 if (D11REV_IS(wlc_hw
->corerev
, 4)) /* no slowclock */
1327 /* delay before first read of ucode state */
1330 /* wait until ucode is no longer asleep */
1331 SPINWAIT((wlc_bmac_read_shm(wlc_hw
, M_UCODE_DBGST
) ==
1332 DBGST_ASLEEP
), wlc_hw
->wlc
->fastpwrup_dly
);
1335 ASSERT(wlc_bmac_read_shm(wlc_hw
, M_UCODE_DBGST
) != DBGST_ASLEEP
);
1338 void wlc_bmac_hw_etheraddr(wlc_hw_info_t
*wlc_hw
, struct ether_addr
*ea
)
1340 bcopy(&wlc_hw
->etheraddr
, ea
, ETHER_ADDR_LEN
);
1343 void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t
*wlc_hw
, struct ether_addr
*ea
)
1345 bcopy(ea
, &wlc_hw
->etheraddr
, ETHER_ADDR_LEN
);
1348 int wlc_bmac_bandtype(wlc_hw_info_t
*wlc_hw
)
1350 return wlc_hw
->band
->bandtype
;
1353 void *wlc_cur_phy(wlc_info_t
*wlc
)
1355 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
1356 return (void *)wlc_hw
->band
->pi
;
1359 /* control chip clock to save power, enable dynamic clock or force fast clock */
1360 static void wlc_clkctl_clk(wlc_hw_info_t
*wlc_hw
, uint mode
)
1362 if (PMUCTL_ENAB(wlc_hw
->sih
)) {
1363 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1364 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1365 * which means the FCA bit may not be set.
1366 * should wakeup mac if driver wants it to run on HT.
1370 if (mode
== CLK_FAST
) {
1371 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->clk_ctl_st
,
1379 clk_ctl_st
) & CCS_HTAVAIL
) == 0),
1380 PMU_MAX_TRANSITION_DLY
);
1384 clk_ctl_st
) & CCS_HTAVAIL
);
1386 if ((wlc_hw
->sih
->pmurev
== 0) &&
1390 clk_ctl_st
) & (CCS_FORCEHT
| CCS_HTAREQ
)))
1394 clk_ctl_st
) & CCS_HTAVAIL
)
1396 PMU_MAX_TRANSITION_DLY
);
1397 AND_REG(wlc_hw
->osh
, &wlc_hw
->regs
->clk_ctl_st
,
1401 wlc_hw
->forcefastclk
= (mode
== CLK_FAST
);
1405 /* old chips w/o PMU, force HT through cc,
1406 * then use FCA to verify mac is running fast clock
1409 wakeup_ucode
= D11REV_LT(wlc_hw
->corerev
, 9);
1411 if (wlc_hw
->up
&& wakeup_ucode
)
1412 wlc_ucode_wake_override_set(wlc_hw
,
1413 WLC_WAKE_OVERRIDE_CLKCTL
);
1415 wlc_hw
->forcefastclk
= si_clkctl_cc(wlc_hw
->sih
, mode
);
1417 if (D11REV_LT(wlc_hw
->corerev
, 11)) {
1418 /* ucode WAR for old chips */
1419 if (wlc_hw
->forcefastclk
)
1420 wlc_bmac_mhf(wlc_hw
, MHF1
, MHF1_FORCEFASTCLK
,
1421 MHF1_FORCEFASTCLK
, WLC_BAND_ALL
);
1423 wlc_bmac_mhf(wlc_hw
, MHF1
, MHF1_FORCEFASTCLK
, 0,
1427 /* check fast clock is available (if core is not in reset) */
1428 if (D11REV_GT(wlc_hw
->corerev
, 4) && wlc_hw
->forcefastclk
1430 ASSERT(si_core_sflags(wlc_hw
->sih
, 0, 0) & SISF_FCLKA
);
1432 /* keep the ucode wake bit on if forcefastclk is on
1433 * since we do not want ucode to put us back to slow clock
1434 * when it dozes for PM mode.
1435 * Code below matches the wake override bit with current forcefastclk state
1436 * Only setting bit in wake_override instead of waking ucode immediately
1437 * since old code (wlc.c 1.4499) had this behavior. Older code set
1438 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1439 * (protected by an up check) was executed just below.
1441 if (wlc_hw
->forcefastclk
)
1442 mboolset(wlc_hw
->wake_override
,
1443 WLC_WAKE_OVERRIDE_FORCEFAST
);
1445 mboolclr(wlc_hw
->wake_override
,
1446 WLC_WAKE_OVERRIDE_FORCEFAST
);
1448 /* ok to clear the wakeup now */
1449 if (wlc_hw
->up
&& wakeup_ucode
)
1450 wlc_ucode_wake_override_clear(wlc_hw
,
1451 WLC_WAKE_OVERRIDE_CLKCTL
);
1455 /* set initial host flags value */
1457 wlc_mhfdef(wlc_info_t
*wlc
, u16
*mhfs
, u16 mhf2_init
)
1459 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
1461 bzero(mhfs
, sizeof(u16
) * MHFMAX
);
1463 mhfs
[MHF2
] |= mhf2_init
;
1465 /* prohibit use of slowclock on multifunction boards */
1466 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
1467 mhfs
[MHF1
] |= MHF1_FORCEFASTCLK
;
1469 if (WLCISNPHY(wlc_hw
->band
) && NREV_LT(wlc_hw
->band
->phyrev
, 2)) {
1470 mhfs
[MHF2
] |= MHF2_NPHY40MHZ_WAR
;
1471 mhfs
[MHF1
] |= MHF1_IQSWAP_WAR
;
1475 /* set or clear ucode host flag bits
1476 * it has an optimization for no-change write
1477 * it only writes through shared memory when the core has clock;
1478 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1481 * bands values are: WLC_BAND_AUTO <--- Current band only
1482 * WLC_BAND_5G <--- 5G band only
1483 * WLC_BAND_2G <--- 2G band only
1484 * WLC_BAND_ALL <--- All bands
1487 wlc_bmac_mhf(wlc_hw_info_t
*wlc_hw
, u8 idx
, u16 mask
, u16 val
,
1491 u16 addr
[MHFMAX
] = {
1492 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1497 ASSERT((val
& ~mask
) == 0);
1498 ASSERT(idx
< MHFMAX
);
1499 ASSERT(ARRAY_SIZE(addr
) == MHFMAX
);
1502 /* Current band only or all bands,
1503 * then set the band to current band
1507 band
= wlc_hw
->band
;
1510 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1513 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1521 save
= band
->mhfs
[idx
];
1522 band
->mhfs
[idx
] = (band
->mhfs
[idx
] & ~mask
) | val
;
1524 /* optimization: only write through if changed, and
1525 * changed band is the current band
1527 if (wlc_hw
->clk
&& (band
->mhfs
[idx
] != save
)
1528 && (band
== wlc_hw
->band
))
1529 wlc_bmac_write_shm(wlc_hw
, addr
[idx
],
1530 (u16
) band
->mhfs
[idx
]);
1533 if (bands
== WLC_BAND_ALL
) {
1534 wlc_hw
->bandstate
[0]->mhfs
[idx
] =
1535 (wlc_hw
->bandstate
[0]->mhfs
[idx
] & ~mask
) | val
;
1536 wlc_hw
->bandstate
[1]->mhfs
[idx
] =
1537 (wlc_hw
->bandstate
[1]->mhfs
[idx
] & ~mask
) | val
;
1541 u16
wlc_bmac_mhf_get(wlc_hw_info_t
*wlc_hw
, u8 idx
, int bands
)
1544 ASSERT(idx
< MHFMAX
);
1548 band
= wlc_hw
->band
;
1551 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1554 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1564 return band
->mhfs
[idx
];
1567 static void wlc_write_mhf(wlc_hw_info_t
*wlc_hw
, u16
*mhfs
)
1571 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1575 ASSERT(ARRAY_SIZE(addr
) == MHFMAX
);
1577 for (idx
= 0; idx
< MHFMAX
; idx
++) {
1578 wlc_bmac_write_shm(wlc_hw
, addr
[idx
], mhfs
[idx
]);
1582 /* set the maccontrol register to desired reset state and
1583 * initialize the sw cache of the register
1585 static void wlc_mctrl_reset(wlc_hw_info_t
*wlc_hw
)
1587 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1588 wlc_hw
->maccontrol
= 0;
1589 wlc_hw
->suspended_fifos
= 0;
1590 wlc_hw
->wake_override
= 0;
1591 wlc_hw
->mute_override
= 0;
1592 wlc_bmac_mctrl(wlc_hw
, ~0, MCTL_IHR_EN
| MCTL_WAKE
);
1595 /* set or clear maccontrol bits */
1596 void wlc_bmac_mctrl(wlc_hw_info_t
*wlc_hw
, u32 mask
, u32 val
)
1601 ASSERT((val
& ~mask
) == 0);
1603 maccontrol
= wlc_hw
->maccontrol
;
1604 new_maccontrol
= (maccontrol
& ~mask
) | val
;
1606 /* if the new maccontrol value is the same as the old, nothing to do */
1607 if (new_maccontrol
== maccontrol
)
1610 /* something changed, cache the new value */
1611 wlc_hw
->maccontrol
= new_maccontrol
;
1613 /* write the new values with overrides applied */
1614 wlc_mctrl_write(wlc_hw
);
1617 /* write the software state of maccontrol and overrides to the maccontrol register */
1618 static void wlc_mctrl_write(wlc_hw_info_t
*wlc_hw
)
1620 u32 maccontrol
= wlc_hw
->maccontrol
;
1622 /* OR in the wake bit if overridden */
1623 if (wlc_hw
->wake_override
)
1624 maccontrol
|= MCTL_WAKE
;
1626 /* set AP and INFRA bits for mute if needed */
1627 if (wlc_hw
->mute_override
) {
1628 maccontrol
&= ~(MCTL_AP
);
1629 maccontrol
|= MCTL_INFRA
;
1632 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
, maccontrol
);
1635 void wlc_ucode_wake_override_set(wlc_hw_info_t
*wlc_hw
, u32 override_bit
)
1637 ASSERT((wlc_hw
->wake_override
& override_bit
) == 0);
1639 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
)) {
1640 mboolset(wlc_hw
->wake_override
, override_bit
);
1644 mboolset(wlc_hw
->wake_override
, override_bit
);
1646 wlc_mctrl_write(wlc_hw
);
1647 wlc_bmac_wait_for_wake(wlc_hw
);
1652 void wlc_ucode_wake_override_clear(wlc_hw_info_t
*wlc_hw
, u32 override_bit
)
1654 ASSERT(wlc_hw
->wake_override
& override_bit
);
1656 mboolclr(wlc_hw
->wake_override
, override_bit
);
1658 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
))
1661 wlc_mctrl_write(wlc_hw
);
1666 /* When driver needs ucode to stop beaconing, it has to make sure that
1667 * MCTL_AP is clear and MCTL_INFRA is set
1668 * Mode MCTL_AP MCTL_INFRA
1670 * STA 0 1 <--- This will ensure no beacons
1673 static void wlc_ucode_mute_override_set(wlc_hw_info_t
*wlc_hw
)
1675 wlc_hw
->mute_override
= 1;
1677 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1678 * override, then there is no change to write
1680 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1683 wlc_mctrl_write(wlc_hw
);
1688 /* Clear the override on AP and INFRA bits */
1689 static void wlc_ucode_mute_override_clear(wlc_hw_info_t
*wlc_hw
)
1691 if (wlc_hw
->mute_override
== 0)
1694 wlc_hw
->mute_override
= 0;
1696 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1697 * override, then there is no change to write
1699 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1702 wlc_mctrl_write(wlc_hw
);
1706 * Write a MAC address to the rcmta structure
1709 wlc_bmac_set_rcmta(wlc_hw_info_t
*wlc_hw
, int idx
,
1710 const struct ether_addr
*addr
)
1712 d11regs_t
*regs
= wlc_hw
->regs
;
1713 volatile u16
*objdata16
= (volatile u16
*)®s
->objdata
;
1716 struct osl_info
*osh
;
1718 WL_TRACE(("wl%d: %s\n", wlc_hw
->unit
, __func__
));
1720 ASSERT(wlc_hw
->corerev
> 4);
1723 (addr
->octet
[3] << 24) | (addr
->octet
[2] << 16) | (addr
->
1726 mac_l
= (addr
->octet
[5] << 8) | addr
->octet
[4];
1730 W_REG(osh
, ®s
->objaddr
, (OBJADDR_RCMTA_SEL
| (idx
* 2)));
1731 (void)R_REG(osh
, ®s
->objaddr
);
1732 W_REG(osh
, ®s
->objdata
, mac_hm
);
1733 W_REG(osh
, ®s
->objaddr
, (OBJADDR_RCMTA_SEL
| ((idx
* 2) + 1)));
1734 (void)R_REG(osh
, ®s
->objaddr
);
1735 W_REG(osh
, objdata16
, mac_l
);
1739 * Write a MAC address to the given match reg offset in the RXE match engine.
1742 wlc_bmac_set_addrmatch(wlc_hw_info_t
*wlc_hw
, int match_reg_offset
,
1743 const struct ether_addr
*addr
)
1749 struct osl_info
*osh
;
1751 WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw
->unit
));
1753 ASSERT((match_reg_offset
< RCM_SIZE
) || (wlc_hw
->corerev
== 4));
1755 regs
= wlc_hw
->regs
;
1756 mac_l
= addr
->octet
[0] | (addr
->octet
[1] << 8);
1757 mac_m
= addr
->octet
[2] | (addr
->octet
[3] << 8);
1758 mac_h
= addr
->octet
[4] | (addr
->octet
[5] << 8);
1762 /* enter the MAC addr into the RXE match registers */
1763 W_REG(osh
, ®s
->rcm_ctl
, RCM_INC_DATA
| match_reg_offset
);
1764 W_REG(osh
, ®s
->rcm_mat_data
, mac_l
);
1765 W_REG(osh
, ®s
->rcm_mat_data
, mac_m
);
1766 W_REG(osh
, ®s
->rcm_mat_data
, mac_h
);
1771 wlc_bmac_write_template_ram(wlc_hw_info_t
*wlc_hw
, int offset
, int len
,
1778 volatile u16
*dptr
= NULL
;
1779 #endif /* IL_BIGENDIAN */
1780 struct osl_info
*osh
;
1782 WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw
->unit
));
1784 regs
= wlc_hw
->regs
;
1787 ASSERT(IS_ALIGNED(offset
, sizeof(u32
)));
1788 ASSERT(IS_ALIGNED(len
, sizeof(u32
)));
1789 ASSERT((offset
& ~0xffff) == 0);
1791 W_REG(osh
, ®s
->tplatewrptr
, offset
);
1793 /* if MCTL_BIGEND bit set in mac control register,
1794 * the chip swaps data in fifo, as well as data in
1797 be_bit
= (R_REG(osh
, ®s
->maccontrol
) & MCTL_BIGEND
) != 0;
1800 bcopy((u8
*) buf
, &word
, sizeof(u32
));
1803 word
= hton32(word
);
1805 word
= htol32(word
);
1807 W_REG(osh
, ®s
->tplatewrdata
, word
);
1809 buf
= (u8
*) buf
+ sizeof(u32
);
1814 void wlc_bmac_set_cwmin(wlc_hw_info_t
*wlc_hw
, u16 newmin
)
1816 struct osl_info
*osh
;
1819 wlc_hw
->band
->CWmin
= newmin
;
1821 W_REG(osh
, &wlc_hw
->regs
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_CWMIN
);
1822 (void)R_REG(osh
, &wlc_hw
->regs
->objaddr
);
1823 W_REG(osh
, &wlc_hw
->regs
->objdata
, newmin
);
1826 void wlc_bmac_set_cwmax(wlc_hw_info_t
*wlc_hw
, u16 newmax
)
1828 struct osl_info
*osh
;
1831 wlc_hw
->band
->CWmax
= newmax
;
1833 W_REG(osh
, &wlc_hw
->regs
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_CWMAX
);
1834 (void)R_REG(osh
, &wlc_hw
->regs
->objaddr
);
1835 W_REG(osh
, &wlc_hw
->regs
->objdata
, newmax
);
1838 void wlc_bmac_bw_set(wlc_hw_info_t
*wlc_hw
, u16 bw
)
1843 /* request FAST clock if not on */
1844 fastclk
= wlc_hw
->forcefastclk
;
1846 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
1848 wlc_phy_bw_state_set(wlc_hw
->band
->pi
, bw
);
1850 ASSERT(wlc_hw
->clk
);
1851 if (D11REV_LT(wlc_hw
->corerev
, 17))
1852 tmp
= R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
);
1854 wlc_bmac_phy_reset(wlc_hw
);
1855 wlc_phy_init(wlc_hw
->band
->pi
, wlc_phy_chanspec_get(wlc_hw
->band
->pi
));
1857 /* restore the clk */
1859 wlc_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
1863 wlc_write_hw_bcntemplate0(wlc_hw_info_t
*wlc_hw
, void *bcn
, int len
)
1865 d11regs_t
*regs
= wlc_hw
->regs
;
1867 wlc_bmac_write_template_ram(wlc_hw
, T_BCN0_TPL_BASE
, (len
+ 3) & ~3,
1869 /* write beacon length to SCR */
1870 ASSERT(len
< 65536);
1871 wlc_bmac_write_shm(wlc_hw
, M_BCN0_FRM_BYTESZ
, (u16
) len
);
1872 /* mark beacon0 valid */
1873 OR_REG(wlc_hw
->osh
, ®s
->maccommand
, MCMD_BCN0VLD
);
1877 wlc_write_hw_bcntemplate1(wlc_hw_info_t
*wlc_hw
, void *bcn
, int len
)
1879 d11regs_t
*regs
= wlc_hw
->regs
;
1881 wlc_bmac_write_template_ram(wlc_hw
, T_BCN1_TPL_BASE
, (len
+ 3) & ~3,
1883 /* write beacon length to SCR */
1884 ASSERT(len
< 65536);
1885 wlc_bmac_write_shm(wlc_hw
, M_BCN1_FRM_BYTESZ
, (u16
) len
);
1886 /* mark beacon1 valid */
1887 OR_REG(wlc_hw
->osh
, ®s
->maccommand
, MCMD_BCN1VLD
);
1890 /* mac is assumed to be suspended at this point */
1892 wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t
*wlc_hw
, void *bcn
, int len
,
1895 d11regs_t
*regs
= wlc_hw
->regs
;
1898 wlc_write_hw_bcntemplate0(wlc_hw
, bcn
, len
);
1899 wlc_write_hw_bcntemplate1(wlc_hw
, bcn
, len
);
1902 if (!(R_REG(wlc_hw
->osh
, ®s
->maccommand
) & MCMD_BCN0VLD
))
1903 wlc_write_hw_bcntemplate0(wlc_hw
, bcn
, len
);
1906 (R_REG(wlc_hw
->osh
, ®s
->maccommand
) & MCMD_BCN1VLD
))
1907 wlc_write_hw_bcntemplate1(wlc_hw
, bcn
, len
);
1908 else /* one template should always have been available */
1913 static void WLBANDINITFN(wlc_bmac_upd_synthpu
) (wlc_hw_info_t
*wlc_hw
)
1916 wlc_info_t
*wlc
= wlc_hw
->wlc
;
1917 /* update SYNTHPU_DLY */
1919 if (WLCISLCNPHY(wlc
->band
)) {
1920 v
= SYNTHPU_DLY_LPPHY_US
;
1921 } else if (WLCISNPHY(wlc
->band
) && (NREV_GE(wlc
->band
->phyrev
, 3))) {
1922 v
= SYNTHPU_DLY_NPHY_US
;
1924 v
= SYNTHPU_DLY_BPHY_US
;
1927 wlc_bmac_write_shm(wlc_hw
, M_SYNTHPU_DLY
, v
);
1930 /* band-specific init */
1932 WLBANDINITFN(wlc_bmac_bsinit
) (wlc_info_t
*wlc
, chanspec_t chanspec
)
1934 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
1936 WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw
->unit
,
1937 wlc_hw
->band
->bandunit
));
1940 if (PHY_TYPE(R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->phyversion
)) !=
1943 PHY_TYPE(R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->phyversion
))
1944 == wlc_hw
->band
->phytype
);
1946 wlc_ucode_bsinit(wlc_hw
);
1948 wlc_phy_init(wlc_hw
->band
->pi
, chanspec
);
1950 wlc_ucode_txant_set(wlc_hw
);
1952 /* cwmin is band-specific, update hardware with value for current band */
1953 wlc_bmac_set_cwmin(wlc_hw
, wlc_hw
->band
->CWmin
);
1954 wlc_bmac_set_cwmax(wlc_hw
, wlc_hw
->band
->CWmax
);
1956 wlc_bmac_update_slot_timing(wlc_hw
,
1957 BAND_5G(wlc_hw
->band
->
1958 bandtype
) ? true : wlc_hw
->
1961 /* write phytype and phyvers */
1962 wlc_bmac_write_shm(wlc_hw
, M_PHYTYPE
, (u16
) wlc_hw
->band
->phytype
);
1963 wlc_bmac_write_shm(wlc_hw
, M_PHYVER
, (u16
) wlc_hw
->band
->phyrev
);
1965 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1966 wlc_upd_ofdm_pctl1_table(wlc_hw
);
1968 wlc_bmac_upd_synthpu(wlc_hw
);
1971 void wlc_bmac_core_phy_clk(wlc_hw_info_t
*wlc_hw
, bool clk
)
1973 WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw
->unit
, clk
));
1975 wlc_hw
->phyclk
= clk
;
1977 if (OFF
== clk
) { /* clear gmode bit, put phy into reset */
1979 si_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
| SICF_GMODE
),
1980 (SICF_PRST
| SICF_FGC
));
1982 si_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
), SICF_PRST
);
1985 } else { /* take phy out of reset */
1987 si_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_FGC
), SICF_FGC
);
1989 si_core_cflags(wlc_hw
->sih
, (SICF_FGC
), 0);
1995 /* Perform a soft reset of the PHY PLL */
1996 void wlc_bmac_core_phypll_reset(wlc_hw_info_t
*wlc_hw
)
1998 WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw
->unit
));
2000 si_corereg(wlc_hw
->sih
, SI_CC_IDX
,
2001 offsetof(chipcregs_t
, chipcontrol_addr
), ~0, 0);
2003 si_corereg(wlc_hw
->sih
, SI_CC_IDX
,
2004 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 0);
2006 si_corereg(wlc_hw
->sih
, SI_CC_IDX
,
2007 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 4);
2009 si_corereg(wlc_hw
->sih
, SI_CC_IDX
,
2010 offsetof(chipcregs_t
, chipcontrol_data
), 0x4, 0);
2014 /* light way to turn on phy clock without reset for NPHY only
2015 * refer to wlc_bmac_core_phy_clk for full version
2017 void wlc_bmac_phyclk_fgc(wlc_hw_info_t
*wlc_hw
, bool clk
)
2019 /* support(necessary for NPHY and HYPHY) only */
2020 if (!WLCISNPHY(wlc_hw
->band
))
2024 si_core_cflags(wlc_hw
->sih
, SICF_FGC
, SICF_FGC
);
2026 si_core_cflags(wlc_hw
->sih
, SICF_FGC
, 0);
2030 void wlc_bmac_macphyclk_set(wlc_hw_info_t
*wlc_hw
, bool clk
)
2033 si_core_cflags(wlc_hw
->sih
, SICF_MPCLKE
, SICF_MPCLKE
);
2035 si_core_cflags(wlc_hw
->sih
, SICF_MPCLKE
, 0);
2038 void wlc_bmac_phy_reset(wlc_hw_info_t
*wlc_hw
)
2040 wlc_phy_t
*pih
= wlc_hw
->band
->pi
;
2042 bool phy_in_reset
= false;
2044 WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw
->unit
));
2049 phy_bw_clkbits
= wlc_phy_clk_bwbits(wlc_hw
->band
->pi
);
2051 /* Specfic reset sequence required for NPHY rev 3 and 4 */
2052 if (WLCISNPHY(wlc_hw
->band
) && NREV_GE(wlc_hw
->band
->phyrev
, 3) &&
2053 NREV_LE(wlc_hw
->band
->phyrev
, 4)) {
2054 /* Set the PHY bandwidth */
2055 si_core_cflags(wlc_hw
->sih
, SICF_BWMASK
, phy_bw_clkbits
);
2059 /* Perform a soft reset of the PHY PLL */
2060 wlc_bmac_core_phypll_reset(wlc_hw
);
2063 si_core_cflags(wlc_hw
->sih
, (SICF_PRST
| SICF_PCLKE
),
2064 (SICF_PRST
| SICF_PCLKE
));
2065 phy_in_reset
= true;
2068 si_core_cflags(wlc_hw
->sih
,
2069 (SICF_PRST
| SICF_PCLKE
| SICF_BWMASK
),
2070 (SICF_PRST
| SICF_PCLKE
| phy_bw_clkbits
));
2074 wlc_bmac_core_phy_clk(wlc_hw
, ON
);
2077 wlc_phy_anacore(pih
, ON
);
2080 /* switch to and initialize new band */
2082 WLBANDINITFN(wlc_bmac_setband
) (wlc_hw_info_t
*wlc_hw
, uint bandunit
,
2083 chanspec_t chanspec
) {
2084 wlc_info_t
*wlc
= wlc_hw
->wlc
;
2087 ASSERT(NBANDS_HW(wlc_hw
) > 1);
2088 ASSERT(bandunit
!= wlc_hw
->band
->bandunit
);
2090 /* Enable the d11 core before accessing it */
2091 if (!si_iscoreup(wlc_hw
->sih
)) {
2092 si_core_reset(wlc_hw
->sih
, 0, 0);
2093 ASSERT(si_iscoreup(wlc_hw
->sih
));
2094 wlc_mctrl_reset(wlc_hw
);
2097 macintmask
= wlc_setband_inact(wlc
, bandunit
);
2102 wlc_bmac_core_phy_clk(wlc_hw
, ON
);
2104 /* band-specific initializations */
2105 wlc_bmac_bsinit(wlc
, chanspec
);
2108 * If there are any pending software interrupt bits,
2109 * then replace these with a harmless nonzero value
2110 * so wlc_dpc() will re-enable interrupts when done.
2112 if (wlc
->macintstatus
)
2113 wlc
->macintstatus
= MI_DMAINT
;
2115 /* restore macintmask */
2116 wl_intrsrestore(wlc
->wl
, macintmask
);
2118 /* ucode should still be suspended.. */
2119 ASSERT((R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->maccontrol
) & MCTL_EN_MAC
) ==
2123 /* low-level band switch utility routine */
2124 void WLBANDINITFN(wlc_setxband
) (wlc_hw_info_t
*wlc_hw
, uint bandunit
)
2126 WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw
->unit
, bandunit
));
2128 wlc_hw
->band
= wlc_hw
->bandstate
[bandunit
];
2130 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2131 wlc_hw
->wlc
->band
= wlc_hw
->wlc
->bandstate
[bandunit
];
2133 /* set gmode core flag */
2134 if (wlc_hw
->sbclk
&& !wlc_hw
->noreset
) {
2135 si_core_cflags(wlc_hw
->sih
, SICF_GMODE
,
2136 ((bandunit
== 0) ? SICF_GMODE
: 0));
2140 static bool wlc_isgoodchip(wlc_hw_info_t
*wlc_hw
)
2143 /* reject unsupported corerev */
2144 if (!VALID_COREREV(wlc_hw
->corerev
)) {
2145 WL_ERROR(("unsupported core rev %d\n", wlc_hw
->corerev
));
2152 static bool wlc_validboardtype(wlc_hw_info_t
*wlc_hw
)
2154 bool goodboard
= true;
2155 uint boardrev
= wlc_hw
->boardrev
;
2159 else if (boardrev
> 0xff) {
2160 uint brt
= (boardrev
& 0xf000) >> 12;
2161 uint b0
= (boardrev
& 0xf00) >> 8;
2162 uint b1
= (boardrev
& 0xf0) >> 4;
2163 uint b2
= boardrev
& 0xf;
2165 if ((brt
> 2) || (brt
== 0) || (b0
> 9) || (b0
== 0) || (b1
> 9)
2170 if (wlc_hw
->sih
->boardvendor
!= VENDOR_BROADCOM
)
2176 static char *wlc_get_macaddr(wlc_hw_info_t
*wlc_hw
)
2178 const char *varname
= "macaddr";
2181 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2182 macaddr
= getvar(wlc_hw
->vars
, varname
);
2183 if (macaddr
!= NULL
)
2186 if (NBANDS_HW(wlc_hw
) > 1)
2187 varname
= "et1macaddr";
2189 varname
= "il0macaddr";
2191 macaddr
= getvar(wlc_hw
->vars
, varname
);
2192 if (macaddr
== NULL
) {
2193 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw
->unit
, varname
));
2200 * Return true if radio is disabled, otherwise false.
2201 * hw radio disable signal is an external pin, users activate it asynchronously
2202 * this function could be called when driver is down and w/o clock
2203 * it operates on different registers depending on corerev and boardflag.
2205 bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t
*wlc_hw
)
2208 u32 resetbits
= 0, flags
= 0;
2210 xtal
= wlc_hw
->sbclk
;
2212 wlc_bmac_xtal(wlc_hw
, ON
);
2214 /* may need to take core out of reset first */
2217 if (D11REV_LE(wlc_hw
->corerev
, 11))
2218 resetbits
|= SICF_PCLKE
;
2221 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2222 * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2224 if (D11REV_GE(wlc_hw
->corerev
, 18))
2225 flags
|= SICF_PCLKE
;
2227 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2228 if ((CHIPID(wlc_hw
->sih
->chip
) == BCM43224_CHIP_ID
) ||
2229 (CHIPID(wlc_hw
->sih
->chip
) == BCM43225_CHIP_ID
) ||
2230 (CHIPID(wlc_hw
->sih
->chip
) == BCM43421_CHIP_ID
))
2232 (d11regs_t
*) si_setcore(wlc_hw
->sih
, D11_CORE_ID
,
2234 si_core_reset(wlc_hw
->sih
, flags
, resetbits
);
2235 wlc_mctrl_reset(wlc_hw
);
2238 v
= ((R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->phydebug
) & PDBG_RFD
) != 0);
2240 /* put core back into reset */
2242 si_core_disable(wlc_hw
->sih
, 0);
2245 wlc_bmac_xtal(wlc_hw
, OFF
);
2250 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2251 void wlc_bmac_hw_up(wlc_hw_info_t
*wlc_hw
)
2253 if (wlc_hw
->wlc
->pub
->hw_up
)
2256 WL_TRACE(("wl%d: %s:\n", wlc_hw
->unit
, __func__
));
2259 * Enable pll and xtal, initialize the power control registers,
2260 * and force fastclock for the remainder of wlc_up().
2262 wlc_bmac_xtal(wlc_hw
, ON
);
2263 si_clkctl_init(wlc_hw
->sih
);
2264 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
2266 if (wlc_hw
->sih
->bustype
== PCI_BUS
) {
2267 si_pci_fixcfg(wlc_hw
->sih
);
2269 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2270 if ((CHIPID(wlc_hw
->sih
->chip
) == BCM43224_CHIP_ID
) ||
2271 (CHIPID(wlc_hw
->sih
->chip
) == BCM43225_CHIP_ID
) ||
2272 (CHIPID(wlc_hw
->sih
->chip
) == BCM43421_CHIP_ID
))
2274 (d11regs_t
*) si_setcore(wlc_hw
->sih
, D11_CORE_ID
,
2278 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2279 wlc_phy_por_inform(wlc_hw
->band
->pi
);
2281 wlc_hw
->ucode_loaded
= false;
2282 wlc_hw
->wlc
->pub
->hw_up
= true;
2284 if ((wlc_hw
->boardflags
& BFL_FEM
)
2285 && (CHIPID(wlc_hw
->sih
->chip
) == BCM4313_CHIP_ID
)) {
2287 (wlc_hw
->boardrev
>= 0x1250
2288 && (wlc_hw
->boardflags
& BFL_FEM_BT
)))
2289 si_epa_4313war(wlc_hw
->sih
);
2293 static bool wlc_dma_rxreset(wlc_hw_info_t
*wlc_hw
, uint fifo
)
2295 hnddma_t
*di
= wlc_hw
->di
[fifo
];
2296 struct osl_info
*osh
;
2298 if (D11REV_LT(wlc_hw
->corerev
, 12)) {
2300 u16 rcv_frm_cnt
= 0;
2304 W_REG(osh
, &wlc_hw
->regs
->rcv_fifo_ctl
, fifo
<< 8);
2305 SPINWAIT((!(rxidle
= dma_rxidle(di
))) &&
2307 R_REG(osh
, &wlc_hw
->regs
->rcv_frm_cnt
)) != 0),
2310 if (!rxidle
&& (rcv_frm_cnt
!= 0))
2311 WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw
->unit
, __func__
, fifo
, rcv_frm_cnt
));
2315 return dma_rxreset(di
);
2319 * ensure fask clock during reset
2321 * reset d11(out of reset)
2322 * reset phy(out of reset)
2323 * clear software macintstatus for fresh new start
2324 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2326 void wlc_bmac_corereset(wlc_hw_info_t
*wlc_hw
, u32 flags
)
2333 if (flags
== WLC_USE_COREFLAGS
)
2334 flags
= (wlc_hw
->band
->pi
? wlc_hw
->band
->core_flags
: 0);
2336 WL_TRACE(("wl%d: %s\n", wlc_hw
->unit
, __func__
));
2338 regs
= wlc_hw
->regs
;
2340 /* request FAST clock if not on */
2341 fastclk
= wlc_hw
->forcefastclk
;
2343 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
2345 /* reset the dma engines except first time thru */
2346 if (si_iscoreup(wlc_hw
->sih
)) {
2347 for (i
= 0; i
< NFIFO
; i
++)
2348 if ((wlc_hw
->di
[i
]) && (!dma_txreset(wlc_hw
->di
[i
]))) {
2349 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw
->unit
, __func__
, i
));
2352 if ((wlc_hw
->di
[RX_FIFO
])
2353 && (!wlc_dma_rxreset(wlc_hw
, RX_FIFO
))) {
2354 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw
->unit
, __func__
, RX_FIFO
));
2356 if (D11REV_IS(wlc_hw
->corerev
, 4)
2357 && wlc_hw
->di
[RX_TXSTATUS_FIFO
]
2358 && (!wlc_dma_rxreset(wlc_hw
, RX_TXSTATUS_FIFO
))) {
2359 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw
->unit
, __func__
, RX_TXSTATUS_FIFO
));
2362 /* if noreset, just stop the psm and return */
2363 if (wlc_hw
->noreset
) {
2364 wlc_hw
->wlc
->macintstatus
= 0; /* skip wl_dpc after down */
2365 wlc_bmac_mctrl(wlc_hw
, MCTL_PSM_RUN
| MCTL_EN_MAC
, 0);
2369 if (D11REV_LE(wlc_hw
->corerev
, 11))
2370 resetbits
|= SICF_PCLKE
;
2373 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2374 * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2375 * need to enable PHY CLK
2377 if (D11REV_GE(wlc_hw
->corerev
, 18))
2378 flags
|= SICF_PCLKE
;
2381 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2382 * is cleared by the core_reset. have to re-request it.
2383 * This adds some delay and we can optimize it by also requesting fastclk through
2384 * chipcommon during this period if necessary. But that has to work coordinate
2385 * with other driver like mips/arm since they may touch chipcommon as well.
2387 wlc_hw
->clk
= false;
2388 si_core_reset(wlc_hw
->sih
, flags
, resetbits
);
2390 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
2391 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, true);
2393 wlc_mctrl_reset(wlc_hw
);
2395 if (PMUCTL_ENAB(wlc_hw
->sih
))
2396 wlc_clkctl_clk(wlc_hw
, CLK_FAST
);
2398 wlc_bmac_phy_reset(wlc_hw
);
2400 /* turn on PHY_PLL */
2401 wlc_bmac_core_phypll_ctl(wlc_hw
, true);
2403 /* clear sw intstatus */
2404 wlc_hw
->wlc
->macintstatus
= 0;
2406 /* restore the clk setting */
2408 wlc_clkctl_clk(wlc_hw
, CLK_DYNAMIC
);
2411 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2412 * txfifo sizes needs to be modified(increased) since the newer cores
2415 static void wlc_corerev_fifofixup(wlc_hw_info_t
*wlc_hw
)
2417 d11regs_t
*regs
= wlc_hw
->regs
;
2419 u16 txfifo_startblk
= TXFIFO_START_BLK
, txfifo_endblk
;
2420 u16 txfifo_def
, txfifo_def1
;
2422 struct osl_info
*osh
;
2424 if (D11REV_LT(wlc_hw
->corerev
, 9))
2427 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2428 txfifo_startblk
= TXFIFO_START_BLK
;
2432 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2433 for (fifo_nu
= 0; fifo_nu
< NFIFO
; fifo_nu
++) {
2435 txfifo_endblk
= txfifo_startblk
+ wlc_hw
->xmtfifo_sz
[fifo_nu
];
2436 txfifo_def
= (txfifo_startblk
& 0xff) |
2437 (((txfifo_endblk
- 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT
);
2438 txfifo_def1
= ((txfifo_startblk
>> 8) & 0x1) |
2440 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT
);
2442 TXFIFOCMD_RESET_MASK
| (fifo_nu
<< TXFIFOCMD_FIFOSEL_SHIFT
);
2444 W_REG(osh
, ®s
->xmtfifocmd
, txfifo_cmd
);
2445 W_REG(osh
, ®s
->xmtfifodef
, txfifo_def
);
2446 if (D11REV_GE(wlc_hw
->corerev
, 16))
2447 W_REG(osh
, ®s
->xmtfifodef1
, txfifo_def1
);
2449 W_REG(osh
, ®s
->xmtfifocmd
, txfifo_cmd
);
2451 txfifo_startblk
+= wlc_hw
->xmtfifo_sz
[fifo_nu
];
2454 /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2455 wlc_bmac_write_shm(wlc_hw
, M_FIFOSIZE0
,
2456 wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]);
2457 wlc_bmac_write_shm(wlc_hw
, M_FIFOSIZE1
,
2458 wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]);
2459 wlc_bmac_write_shm(wlc_hw
, M_FIFOSIZE2
,
2460 ((wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
] << 8) | wlc_hw
->
2461 xmtfifo_sz
[TX_AC_BK_FIFO
]));
2462 wlc_bmac_write_shm(wlc_hw
, M_FIFOSIZE3
,
2463 ((wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
] << 8) | wlc_hw
->
2464 xmtfifo_sz
[TX_BCMC_FIFO
]));
2469 * download ucode/PCM
2470 * let ucode run to suspended
2471 * download ucode inits
2472 * config other core registers
2475 static void wlc_coreinit(wlc_info_t
*wlc
)
2477 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
2482 bool fifosz_fixup
= false;
2483 struct osl_info
*osh
;
2487 regs
= wlc_hw
->regs
;
2490 WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw
->unit
));
2493 wlc_bmac_mctrl(wlc_hw
, ~0, (MCTL_IHR_EN
| MCTL_PSM_JMP_0
| MCTL_WAKE
));
2495 wlc_ucode_download(wlc_hw
);
2498 * 1) core5-9 use ucode 5 to save space since the PSM is the same
2499 * 2) newer chips, driver wants to controls the fifo allocation
2501 if (D11REV_GE(wlc_hw
->corerev
, 4))
2502 fifosz_fixup
= true;
2504 /* let the PSM run to the suspended state, set mode to BSS STA */
2505 W_REG(osh
, ®s
->macintstatus
, -1);
2506 wlc_bmac_mctrl(wlc_hw
, ~0,
2507 (MCTL_IHR_EN
| MCTL_INFRA
| MCTL_PSM_RUN
| MCTL_WAKE
));
2509 /* wait for ucode to self-suspend after auto-init */
2510 SPINWAIT(((R_REG(osh
, ®s
->macintstatus
) & MI_MACSSPNDD
) == 0),
2512 if ((R_REG(osh
, ®s
->macintstatus
) & MI_MACSSPNDD
) == 0)
2513 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2518 sflags
= si_core_sflags(wlc_hw
->sih
, 0, 0);
2520 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
2521 if (WLCISNPHY(wlc_hw
->band
))
2522 wlc_write_inits(wlc_hw
, d11n0initvals16
);
2524 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2525 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
2526 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2527 if (WLCISLCNPHY(wlc_hw
->band
)) {
2528 wlc_write_inits(wlc_hw
, d11lcn0initvals24
);
2530 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2531 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
2534 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2535 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
2538 /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2539 if (fifosz_fixup
== true) {
2540 wlc_corerev_fifofixup(wlc_hw
);
2543 /* check txfifo allocations match between ucode and driver */
2544 buf
[TX_AC_BE_FIFO
] = wlc_bmac_read_shm(wlc_hw
, M_FIFOSIZE0
);
2545 if (buf
[TX_AC_BE_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]) {
2549 buf
[TX_AC_VI_FIFO
] = wlc_bmac_read_shm(wlc_hw
, M_FIFOSIZE1
);
2550 if (buf
[TX_AC_VI_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]) {
2554 buf
[TX_AC_BK_FIFO
] = wlc_bmac_read_shm(wlc_hw
, M_FIFOSIZE2
);
2555 buf
[TX_AC_VO_FIFO
] = (buf
[TX_AC_BK_FIFO
] >> 8) & 0xff;
2556 buf
[TX_AC_BK_FIFO
] &= 0xff;
2557 if (buf
[TX_AC_BK_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BK_FIFO
]) {
2561 if (buf
[TX_AC_VO_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
]) {
2565 buf
[TX_BCMC_FIFO
] = wlc_bmac_read_shm(wlc_hw
, M_FIFOSIZE3
);
2566 buf
[TX_ATIM_FIFO
] = (buf
[TX_BCMC_FIFO
] >> 8) & 0xff;
2567 buf
[TX_BCMC_FIFO
] &= 0xff;
2568 if (buf
[TX_BCMC_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_BCMC_FIFO
]) {
2572 if (buf
[TX_ATIM_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
]) {
2577 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf
[i
], wlc_hw
->xmtfifo_sz
[i
], i
));
2578 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2579 * shmem, since driver don't overwrite those chip and
2580 * ucode initialize data will be used.
2582 if (D11REV_GE(wlc_hw
->corerev
, 4))
2586 /* make sure we can still talk to the mac */
2587 ASSERT(R_REG(osh
, ®s
->maccontrol
) != 0xffffffff);
2589 /* band-specific inits done by wlc_bsinit() */
2591 /* Set up frame burst size and antenna swap threshold init values */
2592 wlc_bmac_write_shm(wlc_hw
, M_MBURST_SIZE
, MAXTXFRAMEBURST
);
2593 wlc_bmac_write_shm(wlc_hw
, M_MAX_ANTCNT
, ANTCNT
);
2595 /* enable one rx interrupt per received frame */
2596 W_REG(osh
, ®s
->intrcvlazy
[0], (1 << IRL_FC_SHIFT
));
2597 if (D11REV_IS(wlc_hw
->corerev
, 4))
2598 W_REG(osh
, ®s
->intrcvlazy
[3], (1 << IRL_FC_SHIFT
));
2600 /* set the station mode (BSS STA) */
2601 wlc_bmac_mctrl(wlc_hw
,
2602 (MCTL_INFRA
| MCTL_DISCARD_PMQ
| MCTL_AP
),
2603 (MCTL_INFRA
| MCTL_DISCARD_PMQ
));
2605 /* set up Beacon interval */
2606 bcnint_us
= 0x8000 << 10;
2607 W_REG(osh
, ®s
->tsf_cfprep
, (bcnint_us
<< CFPREP_CBI_SHIFT
));
2608 W_REG(osh
, ®s
->tsf_cfpstart
, bcnint_us
);
2609 W_REG(osh
, ®s
->macintstatus
, MI_GP1
);
2611 /* write interrupt mask */
2612 W_REG(osh
, ®s
->intctrlregs
[RX_FIFO
].intmask
, DEF_RXINTMASK
);
2613 if (D11REV_IS(wlc_hw
->corerev
, 4))
2614 W_REG(osh
, ®s
->intctrlregs
[RX_TXSTATUS_FIFO
].intmask
,
2617 /* allow the MAC to control the PHY clock (dynamic on/off) */
2618 wlc_bmac_macphyclk_set(wlc_hw
, ON
);
2620 /* program dynamic clock control fast powerup delay register */
2621 if (D11REV_GT(wlc_hw
->corerev
, 4)) {
2622 wlc
->fastpwrup_dly
= si_clkctl_fast_pwrup_delay(wlc_hw
->sih
);
2623 W_REG(osh
, ®s
->scc_fastpwrup_dly
, wlc
->fastpwrup_dly
);
2626 /* tell the ucode the corerev */
2627 wlc_bmac_write_shm(wlc_hw
, M_MACHW_VER
, (u16
) wlc_hw
->corerev
);
2629 /* tell the ucode MAC capabilities */
2630 if (D11REV_GE(wlc_hw
->corerev
, 13)) {
2631 wlc_bmac_write_shm(wlc_hw
, M_MACHW_CAP_L
,
2632 (u16
) (wlc_hw
->machwcap
& 0xffff));
2633 wlc_bmac_write_shm(wlc_hw
, M_MACHW_CAP_H
,
2635 machwcap
>> 16) & 0xffff));
2638 /* write retry limits to SCR, this done after PSM init */
2639 W_REG(osh
, ®s
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
2640 (void)R_REG(osh
, ®s
->objaddr
);
2641 W_REG(osh
, ®s
->objdata
, wlc_hw
->SRL
);
2642 W_REG(osh
, ®s
->objaddr
, OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
2643 (void)R_REG(osh
, ®s
->objaddr
);
2644 W_REG(osh
, ®s
->objdata
, wlc_hw
->LRL
);
2646 /* write rate fallback retry limits */
2647 wlc_bmac_write_shm(wlc_hw
, M_SFRMTXCNTFBRTHSD
, wlc_hw
->SFBL
);
2648 wlc_bmac_write_shm(wlc_hw
, M_LFRMTXCNTFBRTHSD
, wlc_hw
->LFBL
);
2650 if (D11REV_GE(wlc_hw
->corerev
, 16)) {
2651 AND_REG(osh
, ®s
->ifs_ctl
, 0x0FFF);
2652 W_REG(osh
, ®s
->ifs_aifsn
, EDCF_AIFSN_MIN
);
2655 /* dma initializations */
2656 wlc
->txpend16165war
= 0;
2658 /* init the tx dma engines */
2659 for (i
= 0; i
< NFIFO
; i
++) {
2661 dma_txinit(wlc_hw
->di
[i
]);
2664 /* init the rx dma engine(s) and post receive buffers */
2665 dma_rxinit(wlc_hw
->di
[RX_FIFO
]);
2666 dma_rxfill(wlc_hw
->di
[RX_FIFO
]);
2667 if (D11REV_IS(wlc_hw
->corerev
, 4)) {
2668 dma_rxinit(wlc_hw
->di
[RX_TXSTATUS_FIFO
]);
2669 dma_rxfill(wlc_hw
->di
[RX_TXSTATUS_FIFO
]);
2673 /* This function is used for changing the tsf frac register
2674 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2675 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2676 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2677 * HTPHY Formula is 2^26/freq(MHz) e.g.
2678 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2679 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2680 * For spuron: 123MHz -> 2^26/123 = 545600.5
2681 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2682 * For spur off: 120MHz -> 2^26/120 = 559240.5
2683 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2686 void wlc_bmac_switch_macfreq(wlc_hw_info_t
*wlc_hw
, u8 spurmode
)
2689 struct osl_info
*osh
;
2690 regs
= wlc_hw
->regs
;
2693 if ((CHIPID(wlc_hw
->sih
->chip
) == BCM43224_CHIP_ID
) ||
2694 (CHIPID(wlc_hw
->sih
->chip
) == BCM43225_CHIP_ID
)) {
2695 if (spurmode
== WL_SPURAVOID_ON2
) { /* 126Mhz */
2696 W_REG(osh
, ®s
->tsf_clk_frac_l
, 0x2082);
2697 W_REG(osh
, ®s
->tsf_clk_frac_h
, 0x8);
2698 } else if (spurmode
== WL_SPURAVOID_ON1
) { /* 123Mhz */
2699 W_REG(osh
, ®s
->tsf_clk_frac_l
, 0x5341);
2700 W_REG(osh
, ®s
->tsf_clk_frac_h
, 0x8);
2701 } else { /* 120Mhz */
2702 W_REG(osh
, ®s
->tsf_clk_frac_l
, 0x8889);
2703 W_REG(osh
, ®s
->tsf_clk_frac_h
, 0x8);
2705 } else if (WLCISLCNPHY(wlc_hw
->band
)) {
2706 if (spurmode
== WL_SPURAVOID_ON1
) { /* 82Mhz */
2707 W_REG(osh
, ®s
->tsf_clk_frac_l
, 0x7CE0);
2708 W_REG(osh
, ®s
->tsf_clk_frac_h
, 0xC);
2709 } else { /* 80Mhz */
2710 W_REG(osh
, ®s
->tsf_clk_frac_l
, 0xCCCD);
2711 W_REG(osh
, ®s
->tsf_clk_frac_h
, 0xC);
2716 /* Initialize GPIOs that are controlled by D11 core */
2717 static void wlc_gpio_init(wlc_info_t
*wlc
)
2719 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
2722 struct osl_info
*osh
;
2724 regs
= wlc_hw
->regs
;
2727 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2728 wlc_bmac_mctrl(wlc_hw
, MCTL_GPOUT_SEL_MASK
, 0);
2731 * Common GPIO setup:
2732 * G0 = LED 0 = WLAN Activity
2733 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2734 * G2 = LED 2 = WLAN 5 GHz Radio State
2735 * G4 = radio disable input (HI enabled, LO disabled)
2740 /* Allocate GPIOs for mimo antenna diversity feature */
2741 if (WLANTSEL_ENAB(wlc
)) {
2742 if (wlc_hw
->antsel_type
== ANTSEL_2x3
) {
2743 /* Enable antenna diversity, use 2x3 mode */
2744 wlc_bmac_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2745 MHF3_ANTSEL_EN
, WLC_BAND_ALL
);
2746 wlc_bmac_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
,
2747 MHF3_ANTSEL_MODE
, WLC_BAND_ALL
);
2749 /* init superswitch control */
2750 wlc_phy_antsel_init(wlc_hw
->band
->pi
, false);
2752 } else if (wlc_hw
->antsel_type
== ANTSEL_2x4
) {
2753 ASSERT((gm
& BOARD_GPIO_12
) == 0);
2754 gm
|= gc
|= (BOARD_GPIO_12
| BOARD_GPIO_13
);
2755 /* The board itself is powered by these GPIOs (when not sending pattern)
2758 OR_REG(osh
, ®s
->psm_gpio_oe
,
2759 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2760 OR_REG(osh
, ®s
->psm_gpio_out
,
2761 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2763 /* Enable antenna diversity, use 2x4 mode */
2764 wlc_bmac_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2765 MHF3_ANTSEL_EN
, WLC_BAND_ALL
);
2766 wlc_bmac_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
, 0,
2769 /* Configure the desired clock to be 4Mhz */
2770 wlc_bmac_write_shm(wlc_hw
, M_ANTSEL_CLKDIV
,
2771 ANTSEL_CLKDIV_4MHZ
);
2774 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2775 if (wlc_hw
->boardflags
& BFL_PACTRL
)
2776 gm
|= gc
|= BOARD_GPIO_PACTRL
;
2778 /* apply to gpiocontrol register */
2779 si_gpiocontrol(wlc_hw
->sih
, gm
, gc
, GPIO_DRV_PRIORITY
);
2782 static void wlc_ucode_download(wlc_hw_info_t
*wlc_hw
)
2787 if (wlc_hw
->ucode_loaded
)
2790 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
2791 if (WLCISNPHY(wlc_hw
->band
)) {
2792 wlc_ucode_write(wlc_hw
, bcm43xx_16_mimo
,
2794 wlc_hw
->ucode_loaded
= true;
2796 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2797 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
2798 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2799 if (WLCISLCNPHY(wlc_hw
->band
)) {
2800 wlc_ucode_write(wlc_hw
, bcm43xx_24_lcn
,
2802 wlc_hw
->ucode_loaded
= true;
2804 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2805 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
));
2810 static void wlc_ucode_write(wlc_hw_info_t
*wlc_hw
, const u32 ucode
[],
2811 const uint nbytes
) {
2812 struct osl_info
*osh
;
2813 d11regs_t
*regs
= wlc_hw
->regs
;
2819 WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw
->unit
));
2821 ASSERT(IS_ALIGNED(nbytes
, sizeof(u32
)));
2823 count
= (nbytes
/ sizeof(u32
));
2825 W_REG(osh
, ®s
->objaddr
, (OBJADDR_AUTO_INC
| OBJADDR_UCM_SEL
));
2826 (void)R_REG(osh
, ®s
->objaddr
);
2827 for (i
= 0; i
< count
; i
++)
2828 W_REG(osh
, ®s
->objdata
, ucode
[i
]);
2831 static void wlc_write_inits(wlc_hw_info_t
*wlc_hw
, const d11init_t
*inits
)
2834 struct osl_info
*osh
;
2837 WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw
->unit
));
2840 base
= (volatile u8
*)wlc_hw
->regs
;
2842 for (i
= 0; inits
[i
].addr
!= 0xffff; i
++) {
2843 ASSERT((inits
[i
].size
== 2) || (inits
[i
].size
== 4));
2845 if (inits
[i
].size
== 2)
2846 W_REG(osh
, (u16
*)(base
+ inits
[i
].addr
),
2848 else if (inits
[i
].size
== 4)
2849 W_REG(osh
, (u32
*)(base
+ inits
[i
].addr
),
2854 static void wlc_ucode_txant_set(wlc_hw_info_t
*wlc_hw
)
2857 u16 phytxant
= wlc_hw
->bmac_phytxant
;
2858 u16 mask
= PHY_TXC_ANT_MASK
;
2860 /* set the Probe Response frame phy control word */
2861 phyctl
= wlc_bmac_read_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
);
2862 phyctl
= (phyctl
& ~mask
) | phytxant
;
2863 wlc_bmac_write_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
, phyctl
);
2865 /* set the Response (ACK/CTS) frame phy control word */
2866 phyctl
= wlc_bmac_read_shm(wlc_hw
, M_RSP_PCTLWD
);
2867 phyctl
= (phyctl
& ~mask
) | phytxant
;
2868 wlc_bmac_write_shm(wlc_hw
, M_RSP_PCTLWD
, phyctl
);
2871 void wlc_bmac_txant_set(wlc_hw_info_t
*wlc_hw
, u16 phytxant
)
2873 /* update sw state */
2874 wlc_hw
->bmac_phytxant
= phytxant
;
2876 /* push to ucode if up */
2879 wlc_ucode_txant_set(wlc_hw
);
2883 u16
wlc_bmac_get_txant(wlc_hw_info_t
*wlc_hw
)
2885 return (u16
) wlc_hw
->wlc
->stf
->txant
;
2888 void wlc_bmac_antsel_type_set(wlc_hw_info_t
*wlc_hw
, u8 antsel_type
)
2890 wlc_hw
->antsel_type
= antsel_type
;
2892 /* Update the antsel type for phy module to use */
2893 wlc_phy_antsel_type_set(wlc_hw
->band
->pi
, antsel_type
);
2896 void wlc_bmac_fifoerrors(wlc_hw_info_t
*wlc_hw
)
2900 uint intstatus
, idx
;
2901 d11regs_t
*regs
= wlc_hw
->regs
;
2903 unit
= wlc_hw
->unit
;
2905 for (idx
= 0; idx
< NFIFO
; idx
++) {
2906 /* read intstatus register and ignore any non-error bits */
2909 ®s
->intctrlregs
[idx
].intstatus
) & I_ERRORS
;
2913 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit
,
2916 if (intstatus
& I_RO
) {
2917 WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2919 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->rxoflo
);
2923 if (intstatus
& I_PC
) {
2924 WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit
,
2926 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->dmade
);
2930 if (intstatus
& I_PD
) {
2931 WL_ERROR(("wl%d: fifo %d: data error\n", unit
, idx
));
2932 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->dmada
);
2936 if (intstatus
& I_DE
) {
2937 WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2939 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->dmape
);
2943 if (intstatus
& I_RU
) {
2944 WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit
, idx
));
2945 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->rxuflo
[idx
]);
2948 if (intstatus
& I_XU
) {
2949 WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2951 WLCNTINCR(wlc_hw
->wlc
->pub
->_cnt
->txuflo
);
2956 wlc_fatal_error(wlc_hw
->wlc
); /* big hammer */
2959 W_REG(wlc_hw
->osh
, ®s
->intctrlregs
[idx
].intstatus
,
2964 void wlc_intrson(wlc_info_t
*wlc
)
2966 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
2967 ASSERT(wlc
->defmacintmask
);
2968 wlc
->macintmask
= wlc
->defmacintmask
;
2969 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->macintmask
, wlc
->macintmask
);
2972 /* callback for siutils.c, which has only wlc handler, no wl
2973 * they both check up, not only because there is no need to off/restore d11 interrupt
2974 * but also because per-port code may require sync with valid interrupt.
2977 static u32
wlc_wlintrsoff(wlc_info_t
*wlc
)
2982 return wl_intrsoff(wlc
->wl
);
2985 static void wlc_wlintrsrestore(wlc_info_t
*wlc
, u32 macintmask
)
2990 wl_intrsrestore(wlc
->wl
, macintmask
);
2993 u32
wlc_intrsoff(wlc_info_t
*wlc
)
2995 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3001 macintmask
= wlc
->macintmask
; /* isr can still happen */
3003 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->macintmask
, 0);
3004 (void)R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->macintmask
); /* sync readback */
3005 udelay(1); /* ensure int line is no longer driven */
3006 wlc
->macintmask
= 0;
3008 /* return previous macintmask; resolve race between us and our isr */
3009 return wlc
->macintstatus
? 0 : macintmask
;
3012 void wlc_intrsrestore(wlc_info_t
*wlc
, u32 macintmask
)
3014 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3018 wlc
->macintmask
= macintmask
;
3019 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->macintmask
, wlc
->macintmask
);
3022 void wlc_bmac_mute(wlc_hw_info_t
*wlc_hw
, bool on
, mbool flags
)
3024 struct ether_addr null_ether_addr
= { {0, 0, 0, 0, 0, 0} };
3027 /* suspend tx fifos */
3028 wlc_bmac_tx_fifo_suspend(wlc_hw
, TX_DATA_FIFO
);
3029 wlc_bmac_tx_fifo_suspend(wlc_hw
, TX_CTL_FIFO
);
3030 wlc_bmac_tx_fifo_suspend(wlc_hw
, TX_AC_BK_FIFO
);
3031 wlc_bmac_tx_fifo_suspend(wlc_hw
, TX_AC_VI_FIFO
);
3033 /* zero the address match register so we do not send ACKs */
3034 wlc_bmac_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
3037 /* resume tx fifos */
3038 if (!wlc_hw
->wlc
->tx_suspended
) {
3039 wlc_bmac_tx_fifo_resume(wlc_hw
, TX_DATA_FIFO
);
3041 wlc_bmac_tx_fifo_resume(wlc_hw
, TX_CTL_FIFO
);
3042 wlc_bmac_tx_fifo_resume(wlc_hw
, TX_AC_BK_FIFO
);
3043 wlc_bmac_tx_fifo_resume(wlc_hw
, TX_AC_VI_FIFO
);
3045 /* Restore address */
3046 wlc_bmac_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
3047 &wlc_hw
->etheraddr
);
3050 wlc_phy_mute_upd(wlc_hw
->band
->pi
, on
, flags
);
3053 wlc_ucode_mute_override_set(wlc_hw
);
3055 wlc_ucode_mute_override_clear(wlc_hw
);
3058 void wlc_bmac_set_deaf(wlc_hw_info_t
*wlc_hw
, bool user_flag
)
3060 wlc_phy_set_deaf(wlc_hw
->band
->pi
, user_flag
);
3063 int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t
*wlc_hw
, uint fifo
, uint
*blocks
)
3068 *blocks
= wlc_hw
->xmtfifo_sz
[fifo
];
3073 int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t
*wlc_hw
, uint fifo
, uint blocks
)
3075 if (fifo
>= NFIFO
|| blocks
> 299)
3078 /* BMAC_NOTE, change blocks to u16 */
3079 wlc_hw
->xmtfifo_sz
[fifo
] = (u16
) blocks
;
3084 /* wlc_bmac_tx_fifo_suspended:
3085 * Check the MAC's tx suspend status for a tx fifo.
3087 * When the MAC acknowledges a tx suspend, it indicates that no more
3088 * packets will be transmitted out the radio. This is independent of
3089 * DMA channel suspension---the DMA may have finished suspending, or may still
3090 * be pulling data into a tx fifo, by the time the MAC acks the suspend
3093 bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t
*wlc_hw
, uint tx_fifo
)
3095 /* check that a suspend has been requested and is no longer pending */
3098 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3099 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3100 * chnstatus register.
3101 * The tx fifo suspend completion is independent of the DMA suspend completion and
3102 * may be acked before or after the DMA is suspended.
3104 if (dma_txsuspended(wlc_hw
->di
[tx_fifo
]) &&
3105 (R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->chnstatus
) &
3106 (1 << tx_fifo
)) == 0)
3112 void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t
*wlc_hw
, uint tx_fifo
)
3114 u8 fifo
= 1 << tx_fifo
;
3116 /* Two clients of this code, 11h Quiet period and scanning. */
3118 /* only suspend if not already suspended */
3119 if ((wlc_hw
->suspended_fifos
& fifo
) == fifo
)
3122 /* force the core awake only if not already */
3123 if (wlc_hw
->suspended_fifos
== 0)
3124 wlc_ucode_wake_override_set(wlc_hw
, WLC_WAKE_OVERRIDE_TXFIFO
);
3126 wlc_hw
->suspended_fifos
|= fifo
;
3128 if (wlc_hw
->di
[tx_fifo
]) {
3129 /* Suspending AMPDU transmissions in the middle can cause underflow
3130 * which may result in mismatch between ucode and driver
3131 * so suspend the mac before suspending the FIFO
3133 if (WLC_PHY_11N_CAP(wlc_hw
->band
))
3134 wlc_suspend_mac_and_wait(wlc_hw
->wlc
);
3136 dma_txsuspend(wlc_hw
->di
[tx_fifo
]);
3138 if (WLC_PHY_11N_CAP(wlc_hw
->band
))
3139 wlc_enable_mac(wlc_hw
->wlc
);
3143 void wlc_bmac_tx_fifo_resume(wlc_hw_info_t
*wlc_hw
, uint tx_fifo
)
3145 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3146 * here for PIO otherwise the watchdog will catch the inconsistency and fire
3148 /* Two clients of this code, 11h Quiet period and scanning. */
3149 if (wlc_hw
->di
[tx_fifo
])
3150 dma_txresume(wlc_hw
->di
[tx_fifo
]);
3152 /* allow core to sleep again */
3153 if (wlc_hw
->suspended_fifos
== 0)
3156 wlc_hw
->suspended_fifos
&= ~(1 << tx_fifo
);
3157 if (wlc_hw
->suspended_fifos
== 0)
3158 wlc_ucode_wake_override_clear(wlc_hw
,
3159 WLC_WAKE_OVERRIDE_TXFIFO
);
3164 * Read and clear macintmask and macintstatus and intstatus registers.
3165 * This routine should be called with interrupts off
3167 * -1 if DEVICEREMOVED(wlc) evaluates to true;
3168 * 0 if the interrupt is not for us, or we are in some special cases;
3169 * device interrupt status bits otherwise.
3171 static inline u32
wlc_intstatus(wlc_info_t
*wlc
, bool in_isr
)
3173 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3174 d11regs_t
*regs
= wlc_hw
->regs
;
3176 u32 intstatus_rxfifo
, intstatus_txsfifo
;
3177 struct osl_info
*osh
;
3181 /* macintstatus includes a DMA interrupt summary bit */
3182 macintstatus
= R_REG(osh
, ®s
->macintstatus
);
3184 WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw
->unit
, macintstatus
));
3186 /* detect cardbus removed, in power down(suspend) and in reset */
3187 if (DEVICEREMOVED(wlc
))
3190 /* DEVICEREMOVED succeeds even when the core is still resetting,
3191 * handle that case here.
3193 if (macintstatus
== 0xffffffff)
3196 /* defer unsolicited interrupts */
3197 macintstatus
&= (in_isr
? wlc
->macintmask
: wlc
->defmacintmask
);
3200 if (macintstatus
== 0)
3203 /* interrupts are already turned off for CFE build
3204 * Caution: For CFE Turning off the interrupts again has some undesired
3207 /* turn off the interrupts */
3208 W_REG(osh
, ®s
->macintmask
, 0);
3209 (void)R_REG(osh
, ®s
->macintmask
); /* sync readback */
3210 wlc
->macintmask
= 0;
3212 /* clear device interrupts */
3213 W_REG(osh
, ®s
->macintstatus
, macintstatus
);
3215 /* MI_DMAINT is indication of non-zero intstatus */
3216 if (macintstatus
& MI_DMAINT
) {
3217 if (D11REV_IS(wlc_hw
->corerev
, 4)) {
3219 R_REG(osh
, ®s
->intctrlregs
[RX_FIFO
].intstatus
);
3222 ®s
->intctrlregs
[RX_TXSTATUS_FIFO
].
3224 WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw
->unit
, intstatus_rxfifo
, intstatus_txsfifo
));
3226 /* defer unsolicited interrupt hints */
3227 intstatus_rxfifo
&= DEF_RXINTMASK
;
3228 intstatus_txsfifo
&= DEF_RXINTMASK
;
3230 /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3231 /* clear interrupt hints */
3232 if (intstatus_rxfifo
)
3234 ®s
->intctrlregs
[RX_FIFO
].intstatus
,
3237 macintstatus
&= ~MI_DMAINT
;
3239 /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3240 if (intstatus_txsfifo
) {
3242 ®s
->intctrlregs
[RX_TXSTATUS_FIFO
].
3243 intstatus
, intstatus_txsfifo
);
3244 macintstatus
|= MI_TFS
;
3248 * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3249 * If MI_DMAINT is set, assume it is set and clear the interrupt.
3251 W_REG(osh
, ®s
->intctrlregs
[RX_FIFO
].intstatus
,
3256 return macintstatus
;
3259 /* Update wlc->macintstatus and wlc->intstatus[]. */
3260 /* Return true if they are updated successfully. false otherwise */
3261 bool wlc_intrsupd(wlc_info_t
*wlc
)
3265 ASSERT(wlc
->macintstatus
!= 0);
3267 /* read and clear macintstatus and intstatus registers */
3268 macintstatus
= wlc_intstatus(wlc
, false);
3270 /* device is removed */
3271 if (macintstatus
== 0xffffffff)
3274 /* update interrupt status in software */
3275 wlc
->macintstatus
|= macintstatus
;
3281 * First-level interrupt processing.
3282 * Return true if this was our interrupt, false otherwise.
3283 * *wantdpc will be set to true if further wlc_dpc() processing is required,
3286 bool BCMFASTPATH
wlc_isr(wlc_info_t
*wlc
, bool *wantdpc
)
3288 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3293 if (!wlc_hw
->up
|| !wlc
->macintmask
)
3296 /* read and clear macintstatus and intstatus registers */
3297 macintstatus
= wlc_intstatus(wlc
, true);
3299 if (macintstatus
== 0xffffffff)
3300 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3302 /* it is not for us */
3303 if (macintstatus
== 0)
3308 /* save interrupt status bits */
3309 ASSERT(wlc
->macintstatus
== 0);
3310 wlc
->macintstatus
= macintstatus
;
3316 /* process tx completion events for corerev < 5 */
3317 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t
*wlc_hw
)
3319 struct sk_buff
*status_p
;
3321 struct osl_info
*osh
;
3324 WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw
->unit
));
3328 while (!fatal
&& (status_p
= dma_rx(wlc_hw
->di
[RX_TXSTATUS_FIFO
]))) {
3330 txs
= (tx_status_t
*) status_p
->data
;
3331 /* MAC uses little endian only */
3332 ltoh16_buf((void *)txs
, sizeof(tx_status_t
));
3334 /* shift low bits for tx_status_t status compatibility */
3335 txs
->status
= (txs
->status
& ~TXS_COMPAT_MASK
)
3336 | (((txs
->status
& TXS_COMPAT_MASK
) << TXS_COMPAT_SHIFT
));
3338 fatal
= wlc_bmac_dotxstatus(wlc_hw
, txs
, 0);
3340 PKTFREE(osh
, status_p
, false);
3346 /* post more rbufs */
3347 dma_rxfill(wlc_hw
->di
[RX_TXSTATUS_FIFO
]);
3352 static bool BCMFASTPATH
3353 wlc_bmac_dotxstatus(wlc_hw_info_t
*wlc_hw
, tx_status_t
*txs
, u32 s2
)
3355 /* discard intermediate indications for ucode with one legitimate case:
3356 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3357 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3358 * transmission count)
3360 if (!(txs
->status
& TX_STATUS_AMPDU
)
3361 && (txs
->status
& TX_STATUS_INTERMEDIATE
)) {
3365 return wlc_dotxstatus(wlc_hw
->wlc
, txs
, s2
);
3368 /* process tx completion events in BMAC
3369 * Return true if more tx status need to be processed. false otherwise.
3371 static bool BCMFASTPATH
3372 wlc_bmac_txstatus(wlc_hw_info_t
*wlc_hw
, bool bound
, bool *fatal
)
3374 bool morepending
= false;
3375 wlc_info_t
*wlc
= wlc_hw
->wlc
;
3377 WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw
->unit
));
3379 if (D11REV_IS(wlc_hw
->corerev
, 4)) {
3380 /* to retire soon */
3381 *fatal
= wlc_bmac_txstatus_corerev4(wlc
->hw
);
3388 struct osl_info
*osh
;
3389 tx_status_t txstatus
, *txs
;
3392 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3393 uint max_tx_num
= bound
? wlc
->pub
->tunables
->txsbnd
: -1;
3396 regs
= wlc_hw
->regs
;
3399 && (s1
= R_REG(osh
, ®s
->frmtxstatus
)) & TXS_V
) {
3401 if (s1
== 0xffffffff) {
3402 WL_ERROR(("wl%d: %s: dead chip\n",
3403 wlc_hw
->unit
, __func__
));
3404 ASSERT(s1
!= 0xffffffff);
3408 s2
= R_REG(osh
, ®s
->frmtxstatus2
);
3410 txs
->status
= s1
& TXS_STATUS_MASK
;
3411 txs
->frameid
= (s1
& TXS_FID_MASK
) >> TXS_FID_SHIFT
;
3412 txs
->sequence
= s2
& TXS_SEQ_MASK
;
3413 txs
->phyerr
= (s2
& TXS_PTX_MASK
) >> TXS_PTX_SHIFT
;
3414 txs
->lasttxtime
= 0;
3416 *fatal
= wlc_bmac_dotxstatus(wlc_hw
, txs
, s2
);
3418 /* !give others some time to run! */
3419 if (++n
>= max_tx_num
)
3426 if (n
>= max_tx_num
)
3430 if (!pktq_empty(&wlc
->active_queue
->q
))
3431 wlc_send_q(wlc
, wlc
->active_queue
);
3436 void wlc_suspend_mac_and_wait(wlc_info_t
*wlc
)
3438 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3439 d11regs_t
*regs
= wlc_hw
->regs
;
3441 struct osl_info
*osh
;
3443 WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw
->unit
,
3444 wlc_hw
->band
->bandunit
));
3447 * Track overlapping suspend requests
3449 wlc_hw
->mac_suspend_depth
++;
3450 if (wlc_hw
->mac_suspend_depth
> 1)
3455 /* force the core awake */
3456 wlc_ucode_wake_override_set(wlc_hw
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
3458 mc
= R_REG(osh
, ®s
->maccontrol
);
3460 if (mc
== 0xffffffff) {
3461 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw
->unit
, __func__
));
3465 ASSERT(!(mc
& MCTL_PSM_JMP_0
));
3466 ASSERT(mc
& MCTL_PSM_RUN
);
3467 ASSERT(mc
& MCTL_EN_MAC
);
3469 mi
= R_REG(osh
, ®s
->macintstatus
);
3470 if (mi
== 0xffffffff) {
3471 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw
->unit
, __func__
));
3475 ASSERT(!(mi
& MI_MACSSPNDD
));
3477 wlc_bmac_mctrl(wlc_hw
, MCTL_EN_MAC
, 0);
3479 SPINWAIT(!(R_REG(osh
, ®s
->macintstatus
) & MI_MACSSPNDD
),
3480 WLC_MAX_MAC_SUSPEND
);
3482 if (!(R_REG(osh
, ®s
->macintstatus
) & MI_MACSSPNDD
)) {
3483 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3484 "MI_MACSSPNDD is still not on.\n",
3485 wlc_hw
->unit
, WLC_MAX_MAC_SUSPEND
));
3486 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw
->unit
, R_REG(osh
, ®s
->psmdebug
), R_REG(osh
, ®s
->phydebug
), R_REG(osh
, ®s
->psm_brc
)));
3489 mc
= R_REG(osh
, ®s
->maccontrol
);
3490 if (mc
== 0xffffffff) {
3491 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw
->unit
, __func__
));
3495 ASSERT(!(mc
& MCTL_PSM_JMP_0
));
3496 ASSERT(mc
& MCTL_PSM_RUN
);
3497 ASSERT(!(mc
& MCTL_EN_MAC
));
3500 void wlc_enable_mac(wlc_info_t
*wlc
)
3502 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3503 d11regs_t
*regs
= wlc_hw
->regs
;
3505 struct osl_info
*osh
;
3507 WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw
->unit
,
3508 wlc
->band
->bandunit
));
3511 * Track overlapping suspend requests
3513 ASSERT(wlc_hw
->mac_suspend_depth
> 0);
3514 wlc_hw
->mac_suspend_depth
--;
3515 if (wlc_hw
->mac_suspend_depth
> 0)
3520 mc
= R_REG(osh
, ®s
->maccontrol
);
3521 ASSERT(!(mc
& MCTL_PSM_JMP_0
));
3522 ASSERT(!(mc
& MCTL_EN_MAC
));
3523 ASSERT(mc
& MCTL_PSM_RUN
);
3525 wlc_bmac_mctrl(wlc_hw
, MCTL_EN_MAC
, MCTL_EN_MAC
);
3526 W_REG(osh
, ®s
->macintstatus
, MI_MACSSPNDD
);
3528 mc
= R_REG(osh
, ®s
->maccontrol
);
3529 ASSERT(!(mc
& MCTL_PSM_JMP_0
));
3530 ASSERT(mc
& MCTL_EN_MAC
);
3531 ASSERT(mc
& MCTL_PSM_RUN
);
3533 mi
= R_REG(osh
, ®s
->macintstatus
);
3534 ASSERT(!(mi
& MI_MACSSPNDD
));
3536 wlc_ucode_wake_override_clear(wlc_hw
, WLC_WAKE_OVERRIDE_MACSUSPEND
);
3539 void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t
*wlc_hw
, bool abie
, bool isht
)
3541 if (!(WLCISNPHY(wlc_hw
->band
) && (D11REV_GE(wlc_hw
->corerev
, 16))))
3545 if (WLCISNPHY(wlc_hw
->band
) && NREV_LT(wlc_hw
->band
->phyrev
, 3)) {
3546 AND_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3550 /* enable EDCRS for non-11n association */
3551 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
, IFS_CTL1_EDCRS
);
3554 if (WLCISNPHY(wlc_hw
->band
) && NREV_GE(wlc_hw
->band
->phyrev
, 3)) {
3555 if (CHSPEC_IS20(wlc_hw
->chanspec
)) {
3556 /* 20 mhz, use 20U ED only */
3557 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3559 AND_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3560 ~IFS_CTL1_EDCRS_20L
);
3561 AND_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3562 ~IFS_CTL1_EDCRS_40
);
3564 /* 40 mhz, use 20U 20L and 40 ED */
3565 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3567 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3568 IFS_CTL1_EDCRS_20L
);
3569 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->ifs_ctl1
,
3575 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t
*wlc_hw
)
3579 WLC_RATE_6M
, WLC_RATE_9M
, WLC_RATE_12M
, WLC_RATE_18M
,
3580 WLC_RATE_24M
, WLC_RATE_36M
, WLC_RATE_48M
, WLC_RATE_54M
3586 if (!WLC_PHY_11N_CAP(wlc_hw
->band
))
3589 /* walk the phy rate table and update the entries */
3590 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
3593 entry_ptr
= wlc_bmac_ofdm_ratetable_offset(wlc_hw
, rate
);
3595 /* read the SHM Rate Table entry OFDM PCTL1 values */
3597 wlc_bmac_read_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
);
3599 /* modify the value */
3600 pctl1
&= ~PHY_TXC1_MODE_MASK
;
3601 pctl1
|= (wlc_hw
->hw_stf_ss_opmode
<< PHY_TXC1_MODE_SHIFT
);
3603 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3604 wlc_bmac_write_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
,
3609 static u16
wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t
*wlc_hw
, u8 rate
)
3613 struct plcp_signal_rate_lookup
{
3617 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3618 const struct plcp_signal_rate_lookup rate_lookup
[] = {
3621 {WLC_RATE_12M
, 0xA},
3622 {WLC_RATE_18M
, 0xE},
3623 {WLC_RATE_24M
, 0x9},
3624 {WLC_RATE_36M
, 0xD},
3625 {WLC_RATE_48M
, 0x8},
3629 for (i
= 0; i
< ARRAY_SIZE(rate_lookup
); i
++) {
3630 if (rate
== rate_lookup
[i
].rate
) {
3631 plcp_rate
= rate_lookup
[i
].signal_rate
;
3636 /* Find the SHM pointer to the rate table entry by looking in the
3639 return 2 * wlc_bmac_read_shm(wlc_hw
, M_RT_DIRMAP_A
+ (plcp_rate
* 2));
3642 void wlc_bmac_band_stf_ss_set(wlc_hw_info_t
*wlc_hw
, u8 stf_mode
)
3644 wlc_hw
->hw_stf_ss_opmode
= stf_mode
;
3647 wlc_upd_ofdm_pctl1_table(wlc_hw
);
3651 wlc_bmac_read_tsf(wlc_hw_info_t
*wlc_hw
, u32
*tsf_l_ptr
,
3654 d11regs_t
*regs
= wlc_hw
->regs
;
3656 /* read the tsf timer low, then high to get an atomic read */
3657 *tsf_l_ptr
= R_REG(wlc_hw
->osh
, ®s
->tsf_timerlow
);
3658 *tsf_h_ptr
= R_REG(wlc_hw
->osh
, ®s
->tsf_timerhigh
);
3663 bool wlc_bmac_validate_chip_access(wlc_hw_info_t
*wlc_hw
)
3667 volatile u16
*reg16
;
3668 struct osl_info
*osh
;
3670 WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw
->unit
));
3672 regs
= wlc_hw
->regs
;
3675 /* Validate dchip register access */
3677 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3678 (void)R_REG(osh
, ®s
->objaddr
);
3679 w
= R_REG(osh
, ®s
->objdata
);
3681 /* Can we write and read back a 32bit register? */
3682 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3683 (void)R_REG(osh
, ®s
->objaddr
);
3684 W_REG(osh
, ®s
->objdata
, (u32
) 0xaa5555aa);
3686 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3687 (void)R_REG(osh
, ®s
->objaddr
);
3688 val
= R_REG(osh
, ®s
->objdata
);
3689 if (val
!= (u32
) 0xaa5555aa) {
3690 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw
->unit
, val
));
3694 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3695 (void)R_REG(osh
, ®s
->objaddr
);
3696 W_REG(osh
, ®s
->objdata
, (u32
) 0x55aaaa55);
3698 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3699 (void)R_REG(osh
, ®s
->objaddr
);
3700 val
= R_REG(osh
, ®s
->objdata
);
3701 if (val
!= (u32
) 0x55aaaa55) {
3702 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw
->unit
, val
));
3706 W_REG(osh
, ®s
->objaddr
, OBJADDR_SHM_SEL
| 0);
3707 (void)R_REG(osh
, ®s
->objaddr
);
3708 W_REG(osh
, ®s
->objdata
, w
);
3710 if (D11REV_LT(wlc_hw
->corerev
, 11)) {
3711 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3712 * for our interface, low to high
3714 reg16
= (volatile u16
*)®s
->tsf_cfpstart
;
3716 /* write the CFPStart register low half explicitly, starting a buffered write */
3717 W_REG(osh
, reg16
, 0xAAAA);
3719 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3720 * If the low 16 bits are written first, followed by the high 16 bits then the
3721 * 32 bit value 0xCCCCBBBB should end up in the register.
3722 * If the order is reversed, then the write to the high half will trigger a buffered
3723 * write of 0xCCCCAAAA.
3724 * If the bus is 32 bits, then this is not much of a test, and the reg should
3725 * have the correct value 0xCCCCBBBB.
3727 W_REG(osh
, ®s
->tsf_cfpstart
, 0xCCCCBBBB);
3729 /* verify with the 16 bit registers that have no side effects */
3730 val
= R_REG(osh
, ®s
->tsf_cfpstrt_l
);
3731 if (val
!= (uint
) 0xBBBB) {
3732 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw
->unit
, val
, 0xBBBB));
3735 val
= R_REG(osh
, ®s
->tsf_cfpstrt_h
);
3736 if (val
!= (uint
) 0xCCCC) {
3737 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw
->unit
, val
, 0xCCCC));
3743 /* clear CFPStart */
3744 W_REG(osh
, ®s
->tsf_cfpstart
, 0);
3746 w
= R_REG(osh
, ®s
->maccontrol
);
3747 if ((w
!= (MCTL_IHR_EN
| MCTL_WAKE
)) &&
3748 (w
!= (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
))) {
3749 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw
->unit
, w
, (MCTL_IHR_EN
| MCTL_WAKE
), (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
)));
3756 #define PHYPLL_WAIT_US 100000
3758 void wlc_bmac_core_phypll_ctl(wlc_hw_info_t
*wlc_hw
, bool on
)
3761 struct osl_info
*osh
;
3764 WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw
->unit
));
3767 regs
= wlc_hw
->regs
;
3770 if (D11REV_LE(wlc_hw
->corerev
, 16) || D11REV_IS(wlc_hw
->corerev
, 20))
3774 if ((wlc_hw
->sih
->chip
== BCM4313_CHIP_ID
)) {
3775 OR_REG(osh
, ®s
->clk_ctl_st
,
3776 (CCS_ERSRC_REQ_HT
| CCS_ERSRC_REQ_D11PLL
|
3777 CCS_ERSRC_REQ_PHYPLL
));
3778 SPINWAIT((R_REG(osh
, ®s
->clk_ctl_st
) &
3779 (CCS_ERSRC_AVAIL_HT
)) != (CCS_ERSRC_AVAIL_HT
),
3782 tmp
= R_REG(osh
, ®s
->clk_ctl_st
);
3783 if ((tmp
& (CCS_ERSRC_AVAIL_HT
)) !=
3784 (CCS_ERSRC_AVAIL_HT
)) {
3785 WL_ERROR(("%s: turn on PHY PLL failed\n",
3790 OR_REG(osh
, ®s
->clk_ctl_st
,
3791 (CCS_ERSRC_REQ_D11PLL
| CCS_ERSRC_REQ_PHYPLL
));
3792 SPINWAIT((R_REG(osh
, ®s
->clk_ctl_st
) &
3793 (CCS_ERSRC_AVAIL_D11PLL
|
3794 CCS_ERSRC_AVAIL_PHYPLL
)) !=
3795 (CCS_ERSRC_AVAIL_D11PLL
|
3796 CCS_ERSRC_AVAIL_PHYPLL
), PHYPLL_WAIT_US
);
3798 tmp
= R_REG(osh
, ®s
->clk_ctl_st
);
3800 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
3802 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
)) {
3803 WL_ERROR(("%s: turn on PHY PLL failed\n",
3809 /* Since the PLL may be shared, other cores can still be requesting it;
3810 * so we'll deassert the request but not wait for status to comply.
3812 AND_REG(osh
, ®s
->clk_ctl_st
, ~CCS_ERSRC_REQ_PHYPLL
);
3813 tmp
= R_REG(osh
, ®s
->clk_ctl_st
);
3817 void wlc_coredisable(wlc_hw_info_t
*wlc_hw
)
3821 WL_TRACE(("wl%d: %s\n", wlc_hw
->unit
, __func__
));
3823 ASSERT(!wlc_hw
->up
);
3825 dev_gone
= DEVICEREMOVED(wlc_hw
->wlc
);
3830 if (wlc_hw
->noreset
)
3834 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
3836 /* turn off analog core */
3837 wlc_phy_anacore(wlc_hw
->band
->pi
, OFF
);
3839 /* turn off PHYPLL to save power */
3840 wlc_bmac_core_phypll_ctl(wlc_hw
, false);
3842 /* No need to set wlc->pub->radio_active = OFF
3843 * because this function needs down capability and
3844 * radio_active is designed for BCMNODOWN.
3847 /* remove gpio controls */
3848 if (wlc_hw
->ucode_dbgsel
)
3849 si_gpiocontrol(wlc_hw
->sih
, ~0, 0, GPIO_DRV_PRIORITY
);
3851 wlc_hw
->clk
= false;
3852 si_core_disable(wlc_hw
->sih
, 0);
3853 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
3856 /* power both the pll and external oscillator on/off */
3857 void wlc_bmac_xtal(wlc_hw_info_t
*wlc_hw
, bool want
)
3859 WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw
->unit
, want
));
3861 /* dont power down if plldown is false or we must poll hw radio disable */
3862 if (!want
&& wlc_hw
->pllreq
)
3866 si_clkctl_xtal(wlc_hw
->sih
, XTAL
| PLL
, want
);
3868 wlc_hw
->sbclk
= want
;
3869 if (!wlc_hw
->sbclk
) {
3870 wlc_hw
->clk
= false;
3871 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
3872 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
3876 static void wlc_flushqueues(wlc_info_t
*wlc
)
3878 wlc_hw_info_t
*wlc_hw
= wlc
->hw
;
3881 wlc
->txpend16165war
= 0;
3883 /* free any posted tx packets */
3884 for (i
= 0; i
< NFIFO
; i
++)
3885 if (wlc_hw
->di
[i
]) {
3886 dma_txreclaim(wlc_hw
->di
[i
], HNDDMA_RANGE_ALL
);
3887 TXPKTPENDCLR(wlc
, i
);
3888 WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3892 /* free any posted rx packets */
3893 dma_rxreclaim(wlc_hw
->di
[RX_FIFO
]);
3894 if (D11REV_IS(wlc_hw
->corerev
, 4))
3895 dma_rxreclaim(wlc_hw
->di
[RX_TXSTATUS_FIFO
]);
3898 u16
wlc_bmac_read_shm(wlc_hw_info_t
*wlc_hw
, uint offset
)
3900 return wlc_bmac_read_objmem(wlc_hw
, offset
, OBJADDR_SHM_SEL
);
3903 void wlc_bmac_write_shm(wlc_hw_info_t
*wlc_hw
, uint offset
, u16 v
)
3905 wlc_bmac_write_objmem(wlc_hw
, offset
, v
, OBJADDR_SHM_SEL
);
3908 /* Set a range of shared memory to a value.
3909 * SHM 'offset' needs to be an even address and
3910 * Buffer length 'len' must be an even number of bytes
3912 void wlc_bmac_set_shm(wlc_hw_info_t
*wlc_hw
, uint offset
, u16 v
, int len
)
3916 /* offset and len need to be even */
3917 ASSERT((offset
& 1) == 0);
3918 ASSERT((len
& 1) == 0);
3923 for (i
= 0; i
< len
; i
+= 2) {
3924 wlc_bmac_write_objmem(wlc_hw
, offset
+ i
, v
, OBJADDR_SHM_SEL
);
3929 wlc_bmac_read_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
, u32 sel
)
3931 d11regs_t
*regs
= wlc_hw
->regs
;
3932 volatile u16
*objdata_lo
= (volatile u16
*)®s
->objdata
;
3933 volatile u16
*objdata_hi
= objdata_lo
+ 1;
3936 ASSERT((offset
& 1) == 0);
3938 W_REG(wlc_hw
->osh
, ®s
->objaddr
, sel
| (offset
>> 2));
3939 (void)R_REG(wlc_hw
->osh
, ®s
->objaddr
);
3941 v
= R_REG(wlc_hw
->osh
, objdata_hi
);
3943 v
= R_REG(wlc_hw
->osh
, objdata_lo
);
3950 wlc_bmac_write_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
, u16 v
, u32 sel
)
3952 d11regs_t
*regs
= wlc_hw
->regs
;
3953 volatile u16
*objdata_lo
= (volatile u16
*)®s
->objdata
;
3954 volatile u16
*objdata_hi
= objdata_lo
+ 1;
3956 ASSERT((offset
& 1) == 0);
3958 W_REG(wlc_hw
->osh
, ®s
->objaddr
, sel
| (offset
>> 2));
3959 (void)R_REG(wlc_hw
->osh
, ®s
->objaddr
);
3961 W_REG(wlc_hw
->osh
, objdata_hi
, v
);
3963 W_REG(wlc_hw
->osh
, objdata_lo
, v
);
3967 /* Copy a buffer to shared memory of specified type .
3968 * SHM 'offset' needs to be an even address and
3969 * Buffer length 'len' must be an even number of bytes
3970 * 'sel' selects the type of memory
3973 wlc_bmac_copyto_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
, const void *buf
,
3977 const u8
*p
= (const u8
*)buf
;
3980 /* offset and len need to be even */
3981 ASSERT((offset
& 1) == 0);
3982 ASSERT((len
& 1) == 0);
3987 for (i
= 0; i
< len
; i
+= 2) {
3988 v
= p
[i
] | (p
[i
+ 1] << 8);
3989 wlc_bmac_write_objmem(wlc_hw
, offset
+ i
, v
, sel
);
3993 /* Copy a piece of shared memory of specified type to a buffer .
3994 * SHM 'offset' needs to be an even address and
3995 * Buffer length 'len' must be an even number of bytes
3996 * 'sel' selects the type of memory
3999 wlc_bmac_copyfrom_objmem(wlc_hw_info_t
*wlc_hw
, uint offset
, void *buf
,
4006 /* offset and len need to be even */
4007 ASSERT((offset
& 1) == 0);
4008 ASSERT((len
& 1) == 0);
4013 for (i
= 0; i
< len
; i
+= 2) {
4014 v
= wlc_bmac_read_objmem(wlc_hw
, offset
+ i
, sel
);
4016 p
[i
+ 1] = (v
>> 8) & 0xFF;
4020 void wlc_bmac_copyfrom_vars(wlc_hw_info_t
*wlc_hw
, char **buf
, uint
*len
)
4022 WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4023 wlc_hw
->vars_size
));
4025 *buf
= wlc_hw
->vars
;
4026 *len
= wlc_hw
->vars_size
;
4029 void wlc_bmac_retrylimit_upd(wlc_hw_info_t
*wlc_hw
, u16 SRL
, u16 LRL
)
4034 /* write retry limit to SCR, shouldn't need to suspend */
4036 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objaddr
,
4037 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
4038 (void)R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objaddr
);
4039 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objdata
, wlc_hw
->SRL
);
4040 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objaddr
,
4041 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
4042 (void)R_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objaddr
);
4043 W_REG(wlc_hw
->osh
, &wlc_hw
->regs
->objdata
, wlc_hw
->LRL
);
4047 void wlc_bmac_set_noreset(wlc_hw_info_t
*wlc_hw
, bool noreset_flag
)
4049 wlc_hw
->noreset
= noreset_flag
;
4052 void wlc_bmac_set_ucode_loaded(wlc_hw_info_t
*wlc_hw
, bool ucode_loaded
)
4054 wlc_hw
->ucode_loaded
= ucode_loaded
;
4057 void wlc_bmac_pllreq(wlc_hw_info_t
*wlc_hw
, bool set
, mbool req_bit
)
4062 if (mboolisset(wlc_hw
->pllreq
, req_bit
))
4065 mboolset(wlc_hw
->pllreq
, req_bit
);
4067 if (mboolisset(wlc_hw
->pllreq
, WLC_PLLREQ_FLIP
)) {
4068 if (!wlc_hw
->sbclk
) {
4069 wlc_bmac_xtal(wlc_hw
, ON
);
4073 if (!mboolisset(wlc_hw
->pllreq
, req_bit
))
4076 mboolclr(wlc_hw
->pllreq
, req_bit
);
4078 if (mboolisset(wlc_hw
->pllreq
, WLC_PLLREQ_FLIP
)) {
4079 if (wlc_hw
->sbclk
) {
4080 wlc_bmac_xtal(wlc_hw
, OFF
);
4088 void wlc_bmac_set_clk(wlc_hw_info_t
*wlc_hw
, bool on
)
4091 /* power up pll and oscillator */
4092 wlc_bmac_xtal(wlc_hw
, ON
);
4094 /* enable core(s), ignore bandlocked
4095 * Leave with the same band selected as we entered
4097 wlc_bmac_corereset(wlc_hw
, WLC_USE_COREFLAGS
);
4099 /* if already down, must skip the core disable */
4101 /* disable core(s), ignore bandlocked */
4102 wlc_coredisable(wlc_hw
);
4104 /* power down pll and oscillator */
4105 wlc_bmac_xtal(wlc_hw
, OFF
);
4109 /* this will be true for all ai chips */
4110 bool wlc_bmac_taclear(wlc_hw_info_t
*wlc_hw
, bool ta_ok
)
4115 /* Lower down relevant GPIOs like LED when going down w/o
4116 * doing PCI config cycles or touching interrupts
4118 void wlc_gpio_fast_deinit(wlc_hw_info_t
*wlc_hw
)
4120 if ((wlc_hw
== NULL
) || (wlc_hw
->sih
== NULL
))
4123 /* Only chips with internal bus or PCIE cores or certain PCI cores
4124 * are able to switch cores w/o disabling interrupts
4126 if (!((wlc_hw
->sih
->bustype
== SI_BUS
) ||
4127 ((wlc_hw
->sih
->bustype
== PCI_BUS
) &&
4128 ((wlc_hw
->sih
->buscoretype
== PCIE_CORE_ID
) ||
4129 (wlc_hw
->sih
->buscorerev
>= 13)))))
4132 WL_TRACE(("wl%d: %s\n", wlc_hw
->unit
, __func__
));
4136 bool wlc_bmac_radio_hw(wlc_hw_info_t
*wlc_hw
, bool enable
)
4138 /* Do not access Phy registers if core is not up */
4139 if (si_iscoreup(wlc_hw
->sih
) == false)
4143 if (PMUCTL_ENAB(wlc_hw
->sih
)) {
4144 AND_REG(wlc_hw
->osh
, &wlc_hw
->regs
->clk_ctl_st
,
4145 ~CCS_FORCEHWREQOFF
);
4146 si_pmu_radio_enable(wlc_hw
->sih
, true);
4149 wlc_phy_anacore(wlc_hw
->band
->pi
, ON
);
4150 wlc_phy_switch_radio(wlc_hw
->band
->pi
, ON
);
4152 /* resume d11 core */
4153 wlc_enable_mac(wlc_hw
->wlc
);
4155 /* suspend d11 core */
4156 wlc_suspend_mac_and_wait(wlc_hw
->wlc
);
4158 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
4159 wlc_phy_anacore(wlc_hw
->band
->pi
, OFF
);
4161 if (PMUCTL_ENAB(wlc_hw
->sih
)) {
4162 si_pmu_radio_enable(wlc_hw
->sih
, false);
4163 OR_REG(wlc_hw
->osh
, &wlc_hw
->regs
->clk_ctl_st
,
4171 u16
wlc_bmac_rate_shm_offset(wlc_hw_info_t
*wlc_hw
, u8 rate
)
4176 /* get the phy specific rate encoding for the PLCP SIGNAL field */
4177 /* XXX4321 fixup needed ? */
4179 table_ptr
= M_RT_DIRMAP_A
;
4181 table_ptr
= M_RT_DIRMAP_B
;
4183 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4184 * the index into the rate table.
4186 phy_rate
= rate_info
[rate
] & RATE_MASK
;
4187 index
= phy_rate
& 0xf;
4189 /* Find the SHM pointer to the rate table entry by looking in the
4192 return 2 * wlc_bmac_read_shm(wlc_hw
, table_ptr
+ (index
* 2));
4195 void wlc_bmac_set_txpwr_percent(wlc_hw_info_t
*wlc_hw
, u8 val
)
4197 wlc_phy_txpwr_percent_set(wlc_hw
->band
->pi
, val
);
4200 void wlc_bmac_antsel_set(wlc_hw_info_t
*wlc_hw
, u32 antsel_avail
)
4202 wlc_hw
->antsel_avail
= antsel_avail
;