1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
9 * Tel: +19(0)7223/9493-0
10 * Fax: +49(0)7223/9493-92
11 * http://www.addi-data.com
16 * Driver: addi_apci_1564
17 * Description: ADDI-DATA APCI-1564 Digital I/O board
18 * Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564)
19 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
20 * Updated: Thu, 02 Jun 2016 13:12:46 -0700
23 * Configuration Options: not applicable, uses comedi PCI auto config
25 * This board has the following features:
26 * - 32 optically isolated digital inputs (24V), 16 of which can
27 * generate change-of-state (COS) interrupts (channels 4 to 19)
28 * - 32 optically isolated digital outputs (10V to 36V)
29 * - 1 8-bit watchdog for resetting the outputs
32 * - 2 diagnostic inputs
34 * The COS, timer, and counter subdevices all use the dev->read_subdev to
35 * return the interrupt status. The sample data is updated and returned when
36 * any of these subdevices generate an interrupt. The sample data format is:
39 * ----- ------------------------------------------
42 * 29 counter 2 interrupt
43 * 28 counter 1 interrupt
44 * 27 counter 0 interrupt
46 * 19:4 COS digital input state (channels 19 to 4)
49 * The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
50 * instruction before they can be enabled by an async command. The COS
51 * interrupts will stay active until canceled.
53 * The timer subdevice does not use an async command. All control is handled
54 * by the (*insn_config).
56 * FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the
57 * datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes
58 * the raw data[1] to this register along with the raw data[2] value to the
59 * ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual
60 * timebase/reload operation please let me know.
62 * The counter subdevice also does not use an async command. All control is
63 * handled by the (*insn_config).
65 * FIXME: The operation of the counters is not really described in the
66 * datasheet I have. The (*insn_config) needs more work.
69 #include <linux/module.h>
70 #include <linux/interrupt.h>
72 #include "../comedi_pci.h"
74 #include "addi_watchdog.h"
79 * PLD Revision 1.0 I/O Mapping
81 * 0x04 - 0x18 Timer 12-Bit
83 * PLD Revision 2.x I/O Mapping
85 * 0x04 - 0x14 Digital Input
86 * 0x18 - 0x25 Digital Output
87 * 0x28 - 0x44 Watchdog 8-Bit
88 * 0x48 - 0x64 Timer 12-Bit
90 #define APCI1564_EEPROM_REG 0x00
91 #define APCI1564_EEPROM_VCC_STATUS BIT(8)
92 #define APCI1564_EEPROM_TO_REV(x) (((x) >> 4) & 0xf)
93 #define APCI1564_EEPROM_DI BIT(3)
94 #define APCI1564_EEPROM_DO BIT(2)
95 #define APCI1564_EEPROM_CS BIT(1)
96 #define APCI1564_EEPROM_CLK BIT(0)
97 #define APCI1564_REV1_TIMER_IOBASE 0x04
98 #define APCI1564_REV2_MAIN_IOBASE 0x04
99 #define APCI1564_REV2_TIMER_IOBASE 0x48
104 * PLD Revision 1.0 I/O Mapping
105 * 0x00 - 0x10 Digital Input
106 * 0x14 - 0x20 Digital Output
107 * 0x24 - 0x3c Watchdog 8-Bit
109 * PLD Revision 2.x I/O Mapping
114 #define APCI1564_REV1_MAIN_IOBASE 0x00
117 * dev->iobase Register Map
118 * PLD Revision 1.0 - PCI BAR 1 + 0x00
119 * PLD Revision 2.x - PCI BAR 0 + 0x04
121 #define APCI1564_DI_REG 0x00
122 #define APCI1564_DI_INT_MODE1_REG 0x04
123 #define APCI1564_DI_INT_MODE2_REG 0x08
124 #define APCI1564_DI_INT_MODE_MASK 0x000ffff0 /* chans [19:4] */
125 #define APCI1564_DI_INT_STATUS_REG 0x0c
126 #define APCI1564_DI_IRQ_REG 0x10
127 #define APCI1564_DI_IRQ_ENA BIT(2)
128 #define APCI1564_DI_IRQ_MODE BIT(1) /* 1=AND, 0=OR */
129 #define APCI1564_DO_REG 0x14
130 #define APCI1564_DO_INT_CTRL_REG 0x18
131 #define APCI1564_DO_INT_CTRL_CC_INT_ENA BIT(1)
132 #define APCI1564_DO_INT_CTRL_VCC_INT_ENA BIT(0)
133 #define APCI1564_DO_INT_STATUS_REG 0x1c
134 #define APCI1564_DO_INT_STATUS_CC BIT(1)
135 #define APCI1564_DO_INT_STATUS_VCC BIT(0)
136 #define APCI1564_DO_IRQ_REG 0x20
137 #define APCI1564_DO_IRQ_INTR BIT(0)
138 #define APCI1564_WDOG_IOBASE 0x24
141 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
142 * PLD Revision 1.0 - PCI BAR 0 + 0x04
143 * PLD Revision 2.x - PCI BAR 0 + 0x48
147 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
148 * PLD Revision 2.x - PCI BAR 1 + 0x00
150 #define APCI1564_COUNTER(x) ((x) * 0x20)
153 * The dev->read_subdev is used to return the interrupt events along with
154 * the state of the interrupt capable inputs.
156 #define APCI1564_EVENT_COS BIT(31)
157 #define APCI1564_EVENT_TIMER BIT(30)
158 #define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */
159 #define APCI1564_EVENT_MASK 0xfff0000f /* all but [19:4] */
161 struct apci1564_private
{
162 unsigned long eeprom
; /* base address of EEPROM register */
163 unsigned long timer
; /* base address of 12-bit timer */
164 unsigned long counters
; /* base address of 32-bit counters */
165 unsigned int mode1
; /* rising-edge/high level channels */
166 unsigned int mode2
; /* falling-edge/low level channels */
167 unsigned int ctrl
; /* interrupt mode OR (edge) . AND (level) */
170 static int apci1564_reset(struct comedi_device
*dev
)
172 struct apci1564_private
*devpriv
= dev
->private;
174 /* Disable the input interrupts and reset status register */
175 outl(0x0, dev
->iobase
+ APCI1564_DI_IRQ_REG
);
176 inl(dev
->iobase
+ APCI1564_DI_INT_STATUS_REG
);
177 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE1_REG
);
178 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE2_REG
);
180 /* Reset the output channels and disable interrupts */
181 outl(0x0, dev
->iobase
+ APCI1564_DO_REG
);
182 outl(0x0, dev
->iobase
+ APCI1564_DO_INT_CTRL_REG
);
184 /* Reset the watchdog registers */
185 addi_watchdog_reset(dev
->iobase
+ APCI1564_WDOG_IOBASE
);
187 /* Reset the timer registers */
188 outl(0x0, devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
189 outl(0x0, devpriv
->timer
+ ADDI_TCW_RELOAD_REG
);
191 if (devpriv
->counters
) {
192 unsigned long iobase
= devpriv
->counters
+ ADDI_TCW_CTRL_REG
;
194 /* Reset the counter registers */
195 outl(0x0, iobase
+ APCI1564_COUNTER(0));
196 outl(0x0, iobase
+ APCI1564_COUNTER(1));
197 outl(0x0, iobase
+ APCI1564_COUNTER(2));
203 static irqreturn_t
apci1564_interrupt(int irq
, void *d
)
205 struct comedi_device
*dev
= d
;
206 struct apci1564_private
*devpriv
= dev
->private;
207 struct comedi_subdevice
*s
= dev
->read_subdev
;
212 s
->state
&= ~APCI1564_EVENT_MASK
;
214 status
= inl(dev
->iobase
+ APCI1564_DI_IRQ_REG
);
215 if (status
& APCI1564_DI_IRQ_ENA
) {
216 /* get the COS interrupt state and set the event flag */
217 s
->state
= inl(dev
->iobase
+ APCI1564_DI_INT_STATUS_REG
);
218 s
->state
&= APCI1564_DI_INT_MODE_MASK
;
219 s
->state
|= APCI1564_EVENT_COS
;
221 /* clear the interrupt */
222 outl(status
& ~APCI1564_DI_IRQ_ENA
,
223 dev
->iobase
+ APCI1564_DI_IRQ_REG
);
224 outl(status
, dev
->iobase
+ APCI1564_DI_IRQ_REG
);
227 status
= inl(devpriv
->timer
+ ADDI_TCW_IRQ_REG
);
228 if (status
& ADDI_TCW_IRQ
) {
229 s
->state
|= APCI1564_EVENT_TIMER
;
231 /* clear the interrupt */
232 ctrl
= inl(devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
233 outl(0x0, devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
234 outl(ctrl
, devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
237 if (devpriv
->counters
) {
238 for (chan
= 0; chan
< 3; chan
++) {
239 unsigned long iobase
;
241 iobase
= devpriv
->counters
+ APCI1564_COUNTER(chan
);
243 status
= inl(iobase
+ ADDI_TCW_IRQ_REG
);
244 if (status
& ADDI_TCW_IRQ
) {
245 s
->state
|= APCI1564_EVENT_COUNTER(chan
);
247 /* clear the interrupt */
248 ctrl
= inl(iobase
+ ADDI_TCW_CTRL_REG
);
249 outl(0x0, iobase
+ ADDI_TCW_CTRL_REG
);
250 outl(ctrl
, iobase
+ ADDI_TCW_CTRL_REG
);
255 if (s
->state
& APCI1564_EVENT_MASK
) {
256 comedi_buf_write_samples(s
, &s
->state
, 1);
257 comedi_handle_events(dev
, s
);
263 static int apci1564_di_insn_bits(struct comedi_device
*dev
,
264 struct comedi_subdevice
*s
,
265 struct comedi_insn
*insn
,
268 data
[1] = inl(dev
->iobase
+ APCI1564_DI_REG
);
273 static int apci1564_do_insn_bits(struct comedi_device
*dev
,
274 struct comedi_subdevice
*s
,
275 struct comedi_insn
*insn
,
278 s
->state
= inl(dev
->iobase
+ APCI1564_DO_REG
);
280 if (comedi_dio_update_state(s
, data
))
281 outl(s
->state
, dev
->iobase
+ APCI1564_DO_REG
);
288 static int apci1564_diag_insn_bits(struct comedi_device
*dev
,
289 struct comedi_subdevice
*s
,
290 struct comedi_insn
*insn
,
293 data
[1] = inl(dev
->iobase
+ APCI1564_DO_INT_STATUS_REG
) & 3;
299 * Change-Of-State (COS) interrupt configuration
301 * Channels 4 to 19 are interruptible. These channels can be configured
302 * to generate interrupts based on AND/OR logic for the desired channels.
305 * - reacts to rising or falling edges
306 * - interrupt is generated when any enabled channel
307 * meet the desired interrupt condition
310 * - reacts to changes in level of the selected inputs
311 * - interrupt is generated when all enabled channels
312 * meet the desired interrupt condition
313 * - after an interrupt, a change in level must occur on
314 * the selected inputs to release the IRQ logic
316 * The COS interrupt must be configured before it can be enabled.
318 * data[0] : INSN_CONFIG_DIGITAL_TRIG
319 * data[1] : trigger number (= 0)
320 * data[2] : configuration operation:
321 * COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
322 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
323 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
324 * data[3] : left-shift for data[4] and data[5]
325 * data[4] : rising-edge/high level channels
326 * data[5] : falling-edge/low level channels
328 static int apci1564_cos_insn_config(struct comedi_device
*dev
,
329 struct comedi_subdevice
*s
,
330 struct comedi_insn
*insn
,
333 struct apci1564_private
*devpriv
= dev
->private;
334 unsigned int shift
, oldmask
, himask
, lomask
;
337 case INSN_CONFIG_DIGITAL_TRIG
:
342 oldmask
= (1U << shift
) - 1;
343 himask
= data
[4] << shift
;
344 lomask
= data
[5] << shift
;
346 oldmask
= 0xffffffffu
;
351 case COMEDI_DIGITAL_TRIG_DISABLE
:
355 outl(0x0, dev
->iobase
+ APCI1564_DI_IRQ_REG
);
356 inl(dev
->iobase
+ APCI1564_DI_INT_STATUS_REG
);
357 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE1_REG
);
358 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE2_REG
);
360 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES
:
361 if (devpriv
->ctrl
!= APCI1564_DI_IRQ_ENA
) {
362 /* switching to 'OR' mode */
363 devpriv
->ctrl
= APCI1564_DI_IRQ_ENA
;
364 /* wipe old channels */
368 /* preserve unspecified channels */
369 devpriv
->mode1
&= oldmask
;
370 devpriv
->mode2
&= oldmask
;
372 /* configure specified channels */
373 devpriv
->mode1
|= himask
;
374 devpriv
->mode2
|= lomask
;
376 case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS
:
377 if (devpriv
->ctrl
!= (APCI1564_DI_IRQ_ENA
|
378 APCI1564_DI_IRQ_MODE
)) {
379 /* switching to 'AND' mode */
380 devpriv
->ctrl
= APCI1564_DI_IRQ_ENA
|
381 APCI1564_DI_IRQ_MODE
;
382 /* wipe old channels */
386 /* preserve unspecified channels */
387 devpriv
->mode1
&= oldmask
;
388 devpriv
->mode2
&= oldmask
;
390 /* configure specified channels */
391 devpriv
->mode1
|= himask
;
392 devpriv
->mode2
|= lomask
;
398 /* ensure the mode bits are in-range for channels [19:4] */
399 devpriv
->mode1
&= APCI1564_DI_INT_MODE_MASK
;
400 devpriv
->mode2
&= APCI1564_DI_INT_MODE_MASK
;
408 static int apci1564_cos_insn_bits(struct comedi_device
*dev
,
409 struct comedi_subdevice
*s
,
410 struct comedi_insn
*insn
,
418 static int apci1564_cos_cmdtest(struct comedi_device
*dev
,
419 struct comedi_subdevice
*s
,
420 struct comedi_cmd
*cmd
)
424 /* Step 1 : check if triggers are trivially valid */
426 err
|= comedi_check_trigger_src(&cmd
->start_src
, TRIG_NOW
);
427 err
|= comedi_check_trigger_src(&cmd
->scan_begin_src
, TRIG_EXT
);
428 err
|= comedi_check_trigger_src(&cmd
->convert_src
, TRIG_FOLLOW
);
429 err
|= comedi_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
430 err
|= comedi_check_trigger_src(&cmd
->stop_src
, TRIG_NONE
);
435 /* Step 2a : make sure trigger sources are unique */
436 /* Step 2b : and mutually compatible */
438 /* Step 3: check if arguments are trivially valid */
440 err
|= comedi_check_trigger_arg_is(&cmd
->start_arg
, 0);
441 err
|= comedi_check_trigger_arg_is(&cmd
->scan_begin_arg
, 0);
442 err
|= comedi_check_trigger_arg_is(&cmd
->convert_arg
, 0);
443 err
|= comedi_check_trigger_arg_is(&cmd
->scan_end_arg
,
445 err
|= comedi_check_trigger_arg_is(&cmd
->stop_arg
, 0);
450 /* Step 4: fix up any arguments */
452 /* Step 5: check channel list if it exists */
458 * Change-Of-State (COS) 'do_cmd' operation
460 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
462 static int apci1564_cos_cmd(struct comedi_device
*dev
,
463 struct comedi_subdevice
*s
)
465 struct apci1564_private
*devpriv
= dev
->private;
467 if (!devpriv
->ctrl
&& !(devpriv
->mode1
|| devpriv
->mode2
)) {
468 dev_warn(dev
->class_dev
,
469 "Interrupts disabled due to mode configuration!\n");
473 outl(devpriv
->mode1
, dev
->iobase
+ APCI1564_DI_INT_MODE1_REG
);
474 outl(devpriv
->mode2
, dev
->iobase
+ APCI1564_DI_INT_MODE2_REG
);
475 outl(devpriv
->ctrl
, dev
->iobase
+ APCI1564_DI_IRQ_REG
);
480 static int apci1564_cos_cancel(struct comedi_device
*dev
,
481 struct comedi_subdevice
*s
)
483 outl(0x0, dev
->iobase
+ APCI1564_DI_IRQ_REG
);
484 inl(dev
->iobase
+ APCI1564_DI_INT_STATUS_REG
);
485 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE1_REG
);
486 outl(0x0, dev
->iobase
+ APCI1564_DI_INT_MODE2_REG
);
491 static int apci1564_timer_insn_config(struct comedi_device
*dev
,
492 struct comedi_subdevice
*s
,
493 struct comedi_insn
*insn
,
496 struct apci1564_private
*devpriv
= dev
->private;
500 case INSN_CONFIG_ARM
:
501 if (data
[1] > s
->maxdata
)
503 outl(data
[1], devpriv
->timer
+ ADDI_TCW_RELOAD_REG
);
504 outl(ADDI_TCW_CTRL_IRQ_ENA
| ADDI_TCW_CTRL_TIMER_ENA
,
505 devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
507 case INSN_CONFIG_DISARM
:
508 outl(0x0, devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
510 case INSN_CONFIG_GET_COUNTER_STATUS
:
512 val
= inl(devpriv
->timer
+ ADDI_TCW_CTRL_REG
);
513 if (val
& ADDI_TCW_CTRL_IRQ_ENA
)
514 data
[1] |= COMEDI_COUNTER_ARMED
;
515 if (val
& ADDI_TCW_CTRL_TIMER_ENA
)
516 data
[1] |= COMEDI_COUNTER_COUNTING
;
517 val
= inl(devpriv
->timer
+ ADDI_TCW_STATUS_REG
);
518 if (val
& ADDI_TCW_STATUS_OVERFLOW
)
519 data
[1] |= COMEDI_COUNTER_TERMINAL_COUNT
;
520 data
[2] = COMEDI_COUNTER_ARMED
| COMEDI_COUNTER_COUNTING
|
521 COMEDI_COUNTER_TERMINAL_COUNT
;
523 case INSN_CONFIG_SET_CLOCK_SRC
:
524 if (data
[2] > s
->maxdata
)
526 outl(data
[1], devpriv
->timer
+ ADDI_TCW_TIMEBASE_REG
);
527 outl(data
[2], devpriv
->timer
+ ADDI_TCW_RELOAD_REG
);
529 case INSN_CONFIG_GET_CLOCK_SRC
:
530 data
[1] = inl(devpriv
->timer
+ ADDI_TCW_TIMEBASE_REG
);
531 data
[2] = inl(devpriv
->timer
+ ADDI_TCW_RELOAD_REG
);
540 static int apci1564_timer_insn_write(struct comedi_device
*dev
,
541 struct comedi_subdevice
*s
,
542 struct comedi_insn
*insn
,
545 struct apci1564_private
*devpriv
= dev
->private;
547 /* just write the last to the reload register */
549 unsigned int val
= data
[insn
->n
- 1];
551 outl(val
, devpriv
->timer
+ ADDI_TCW_RELOAD_REG
);
557 static int apci1564_timer_insn_read(struct comedi_device
*dev
,
558 struct comedi_subdevice
*s
,
559 struct comedi_insn
*insn
,
562 struct apci1564_private
*devpriv
= dev
->private;
565 /* return the actual value of the timer */
566 for (i
= 0; i
< insn
->n
; i
++)
567 data
[i
] = inl(devpriv
->timer
+ ADDI_TCW_VAL_REG
);
572 static int apci1564_counter_insn_config(struct comedi_device
*dev
,
573 struct comedi_subdevice
*s
,
574 struct comedi_insn
*insn
,
577 struct apci1564_private
*devpriv
= dev
->private;
578 unsigned int chan
= CR_CHAN(insn
->chanspec
);
579 unsigned long iobase
= devpriv
->counters
+ APCI1564_COUNTER(chan
);
583 case INSN_CONFIG_ARM
:
584 val
= inl(iobase
+ ADDI_TCW_CTRL_REG
);
585 val
|= ADDI_TCW_CTRL_IRQ_ENA
| ADDI_TCW_CTRL_CNTR_ENA
;
586 outl(data
[1], iobase
+ ADDI_TCW_RELOAD_REG
);
587 outl(val
, iobase
+ ADDI_TCW_CTRL_REG
);
589 case INSN_CONFIG_DISARM
:
590 val
= inl(iobase
+ ADDI_TCW_CTRL_REG
);
591 val
&= ~(ADDI_TCW_CTRL_IRQ_ENA
| ADDI_TCW_CTRL_CNTR_ENA
);
592 outl(val
, iobase
+ ADDI_TCW_CTRL_REG
);
594 case INSN_CONFIG_SET_COUNTER_MODE
:
596 * FIXME: The counter operation is not described in the
597 * datasheet. For now just write the raw data[1] value to
598 * the control register.
600 outl(data
[1], iobase
+ ADDI_TCW_CTRL_REG
);
602 case INSN_CONFIG_GET_COUNTER_STATUS
:
604 val
= inl(iobase
+ ADDI_TCW_CTRL_REG
);
605 if (val
& ADDI_TCW_CTRL_IRQ_ENA
)
606 data
[1] |= COMEDI_COUNTER_ARMED
;
607 if (val
& ADDI_TCW_CTRL_CNTR_ENA
)
608 data
[1] |= COMEDI_COUNTER_COUNTING
;
609 val
= inl(iobase
+ ADDI_TCW_STATUS_REG
);
610 if (val
& ADDI_TCW_STATUS_OVERFLOW
)
611 data
[1] |= COMEDI_COUNTER_TERMINAL_COUNT
;
612 data
[2] = COMEDI_COUNTER_ARMED
| COMEDI_COUNTER_COUNTING
|
613 COMEDI_COUNTER_TERMINAL_COUNT
;
622 static int apci1564_counter_insn_write(struct comedi_device
*dev
,
623 struct comedi_subdevice
*s
,
624 struct comedi_insn
*insn
,
627 struct apci1564_private
*devpriv
= dev
->private;
628 unsigned int chan
= CR_CHAN(insn
->chanspec
);
629 unsigned long iobase
= devpriv
->counters
+ APCI1564_COUNTER(chan
);
631 /* just write the last to the reload register */
633 unsigned int val
= data
[insn
->n
- 1];
635 outl(val
, iobase
+ ADDI_TCW_RELOAD_REG
);
641 static int apci1564_counter_insn_read(struct comedi_device
*dev
,
642 struct comedi_subdevice
*s
,
643 struct comedi_insn
*insn
,
646 struct apci1564_private
*devpriv
= dev
->private;
647 unsigned int chan
= CR_CHAN(insn
->chanspec
);
648 unsigned long iobase
= devpriv
->counters
+ APCI1564_COUNTER(chan
);
651 /* return the actual value of the counter */
652 for (i
= 0; i
< insn
->n
; i
++)
653 data
[i
] = inl(iobase
+ ADDI_TCW_VAL_REG
);
658 static int apci1564_auto_attach(struct comedi_device
*dev
,
659 unsigned long context_unused
)
661 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
662 struct apci1564_private
*devpriv
;
663 struct comedi_subdevice
*s
;
667 devpriv
= comedi_alloc_devpriv(dev
, sizeof(*devpriv
));
671 ret
= comedi_pci_enable(dev
);
675 /* read the EEPROM register and check the I/O map revision */
676 devpriv
->eeprom
= pci_resource_start(pcidev
, 0);
677 val
= inl(devpriv
->eeprom
+ APCI1564_EEPROM_REG
);
678 if (APCI1564_EEPROM_TO_REV(val
) == 0) {
679 /* PLD Revision 1.0 I/O Mapping */
680 dev
->iobase
= pci_resource_start(pcidev
, 1) +
681 APCI1564_REV1_MAIN_IOBASE
;
682 devpriv
->timer
= devpriv
->eeprom
+ APCI1564_REV1_TIMER_IOBASE
;
684 /* PLD Revision 2.x I/O Mapping */
685 dev
->iobase
= devpriv
->eeprom
+ APCI1564_REV2_MAIN_IOBASE
;
686 devpriv
->timer
= devpriv
->eeprom
+ APCI1564_REV2_TIMER_IOBASE
;
687 devpriv
->counters
= pci_resource_start(pcidev
, 1);
692 if (pcidev
->irq
> 0) {
693 ret
= request_irq(pcidev
->irq
, apci1564_interrupt
, IRQF_SHARED
,
694 dev
->board_name
, dev
);
696 dev
->irq
= pcidev
->irq
;
699 ret
= comedi_alloc_subdevices(dev
, 7);
703 /* Allocate and Initialise DI Subdevice Structures */
704 s
= &dev
->subdevices
[0];
705 s
->type
= COMEDI_SUBD_DI
;
706 s
->subdev_flags
= SDF_READABLE
;
709 s
->range_table
= &range_digital
;
710 s
->insn_bits
= apci1564_di_insn_bits
;
712 /* Allocate and Initialise DO Subdevice Structures */
713 s
= &dev
->subdevices
[1];
714 s
->type
= COMEDI_SUBD_DO
;
715 s
->subdev_flags
= SDF_WRITABLE
;
718 s
->range_table
= &range_digital
;
719 s
->insn_bits
= apci1564_do_insn_bits
;
721 /* Change-Of-State (COS) interrupt subdevice */
722 s
= &dev
->subdevices
[2];
724 dev
->read_subdev
= s
;
725 s
->type
= COMEDI_SUBD_DI
;
726 s
->subdev_flags
= SDF_READABLE
| SDF_CMD_READ
| SDF_LSAMPL
;
729 s
->range_table
= &range_digital
;
731 s
->insn_config
= apci1564_cos_insn_config
;
732 s
->insn_bits
= apci1564_cos_insn_bits
;
733 s
->do_cmdtest
= apci1564_cos_cmdtest
;
734 s
->do_cmd
= apci1564_cos_cmd
;
735 s
->cancel
= apci1564_cos_cancel
;
737 s
->type
= COMEDI_SUBD_UNUSED
;
740 /* Timer subdevice */
741 s
= &dev
->subdevices
[3];
742 s
->type
= COMEDI_SUBD_TIMER
;
743 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
;
746 s
->range_table
= &range_digital
;
747 s
->insn_config
= apci1564_timer_insn_config
;
748 s
->insn_write
= apci1564_timer_insn_write
;
749 s
->insn_read
= apci1564_timer_insn_read
;
751 /* Counter subdevice */
752 s
= &dev
->subdevices
[4];
753 if (devpriv
->counters
) {
754 s
->type
= COMEDI_SUBD_COUNTER
;
755 s
->subdev_flags
= SDF_WRITABLE
| SDF_READABLE
| SDF_LSAMPL
;
757 s
->maxdata
= 0xffffffff;
758 s
->range_table
= &range_digital
;
759 s
->insn_config
= apci1564_counter_insn_config
;
760 s
->insn_write
= apci1564_counter_insn_write
;
761 s
->insn_read
= apci1564_counter_insn_read
;
763 s
->type
= COMEDI_SUBD_UNUSED
;
766 /* Initialize the watchdog subdevice */
767 s
= &dev
->subdevices
[5];
768 ret
= addi_watchdog_init(s
, dev
->iobase
+ APCI1564_WDOG_IOBASE
);
772 /* Initialize the diagnostic status subdevice */
773 s
= &dev
->subdevices
[6];
774 s
->type
= COMEDI_SUBD_DI
;
775 s
->subdev_flags
= SDF_READABLE
;
778 s
->range_table
= &range_digital
;
779 s
->insn_bits
= apci1564_diag_insn_bits
;
784 static void apci1564_detach(struct comedi_device
*dev
)
788 comedi_pci_detach(dev
);
791 static struct comedi_driver apci1564_driver
= {
792 .driver_name
= "addi_apci_1564",
793 .module
= THIS_MODULE
,
794 .auto_attach
= apci1564_auto_attach
,
795 .detach
= apci1564_detach
,
798 static int apci1564_pci_probe(struct pci_dev
*dev
,
799 const struct pci_device_id
*id
)
801 return comedi_pci_auto_config(dev
, &apci1564_driver
, id
->driver_data
);
804 static const struct pci_device_id apci1564_pci_table
[] = {
805 { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA
, 0x1006) },
808 MODULE_DEVICE_TABLE(pci
, apci1564_pci_table
);
810 static struct pci_driver apci1564_pci_driver
= {
811 .name
= "addi_apci_1564",
812 .id_table
= apci1564_pci_table
,
813 .probe
= apci1564_pci_probe
,
814 .remove
= comedi_pci_auto_unconfig
,
816 module_comedi_pci_driver(apci1564_driver
, apci1564_pci_driver
);
818 MODULE_AUTHOR("Comedi https://www.comedi.org");
819 MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
820 MODULE_LICENSE("GPL");