drivers/staging/comedi/drivers/addi_tcw.h

   1 #ifndef _ADDI_TCW_H
   2 #define _ADDI_TCW_H
   3
   4 /*
   5  * Following are the generic definitions for the ADDI-DATA timer/counter/
   6  * watchdog (TCW) registers and bits. Some of the registers are not used
   7  * depending on the use of the TCW.
   8  */
   9
  10 #define ADDI_TCW_VAL_REG                0x00
  11
  12 #define ADDI_TCW_SYNC_REG               0x00
  13 #define ADDI_TCW_SYNC_CTR_TRIG          BIT(8)
  14 #define ADDI_TCW_SYNC_CTR_DIS           BIT(7)
  15 #define ADDI_TCW_SYNC_CTR_ENA           BIT(6)
  16 #define ADDI_TCW_SYNC_TIMER_TRIG        BIT(5)
  17 #define ADDI_TCW_SYNC_TIMER_DIS         BIT(4)
  18 #define ADDI_TCW_SYNC_TIMER_ENA         BIT(3)
  19 #define ADDI_TCW_SYNC_WDOG_TRIG         BIT(2)
  20 #define ADDI_TCW_SYNC_WDOG_DIS          BIT(1)
  21 #define ADDI_TCW_SYNC_WDOG_ENA          BIT(0)
  22
  23 #define ADDI_TCW_RELOAD_REG             0x04
  24
  25 #define ADDI_TCW_TIMEBASE_REG           0x08
  26
  27 #define ADDI_TCW_CTRL_REG               0x0c
  28 #define ADDI_TCW_CTRL_EXT_CLK_STATUS    BIT(21)
  29 #define ADDI_TCW_CTRL_CASCADE           BIT(20)
  30 #define ADDI_TCW_CTRL_CNTR_ENA          BIT(19)
  31 #define ADDI_TCW_CTRL_CNT_UP            BIT(18)
  32 #define ADDI_TCW_CTRL_EXT_CLK(x)        (((x) & 3) << 16)
  33 #define ADDI_TCW_CTRL_EXT_CLK_MASK      ADDI_TCW_CTRL_EXT_CLK(3)
  34 #define ADDI_TCW_CTRL_MODE(x)           (((x) & 7) << 13)
  35 #define ADDI_TCW_CTRL_MODE_MASK         ADDI_TCW_CTRL_MODE(7)
  36 #define ADDI_TCW_CTRL_OUT(x)            (((x) & 3) << 11)
  37 #define ADDI_TCW_CTRL_OUT_MASK          ADDI_TCW_CTRL_OUT(3)
  38 #define ADDI_TCW_CTRL_GATE              BIT(10)
  39 #define ADDI_TCW_CTRL_TRIG              BIT(9)
  40 #define ADDI_TCW_CTRL_EXT_GATE(x)       (((x) & 3) << 7)
  41 #define ADDI_TCW_CTRL_EXT_GATE_MASK     ADDI_TCW_CTRL_EXT_GATE(3)
  42 #define ADDI_TCW_CTRL_EXT_TRIG(x)       (((x) & 3) << 5)
  43 #define ADDI_TCW_CTRL_EXT_TRIG_MASK     ADDI_TCW_CTRL_EXT_TRIG(3)
  44 #define ADDI_TCW_CTRL_TIMER_ENA         BIT(4)
  45 #define ADDI_TCW_CTRL_RESET_ENA         BIT(3)
  46 #define ADDI_TCW_CTRL_WARN_ENA          BIT(2)
  47 #define ADDI_TCW_CTRL_IRQ_ENA           BIT(1)
  48 #define ADDI_TCW_CTRL_ENA               BIT(0)
  49
  50 #define ADDI_TCW_STATUS_REG             0x10
  51 #define ADDI_TCW_STATUS_SOFT_CLR        BIT(3)
  52 #define ADDI_TCW_STATUS_HARDWARE_TRIG   BIT(2)
  53 #define ADDI_TCW_STATUS_SOFT_TRIG       BIT(1)
  54 #define ADDI_TCW_STATUS_OVERFLOW        BIT(0)
  55
  56 #define ADDI_TCW_IRQ_REG                0x14
  57 #define ADDI_TCW_IRQ                    BIT(0)
  58
  59 #define ADDI_TCW_WARN_TIMEVAL_REG       0x18
  60
  61 #define ADDI_TCW_WARN_TIMEBASE_REG      0x1c
  62
  63 #endif