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staging: comedi: drivers: use comedi_fc.h cmdtest helpers
[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / comedi / drivers / gsc_hpdi.c
1 /*
2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26 ************************************************************************/
27
28 /*
29
30 Driver: gsc_hpdi
31 Description: General Standards Corporation High
32 Speed Parallel Digital Interface rs485 boards
33 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
34 Status: only receive mode works, transmit not supported
35 Updated: 2003-02-20
36 Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
37 PMC-HPDI32
38
39 Configuration options:
40 [0] - PCI bus of device (optional)
41 [1] - PCI slot of device (optional)
42
43 There are some additional hpdi models available from GSC for which
44 support could be added to this driver.
45
46 */
47
48 #include <linux/interrupt.h>
49 #include "../comedidev.h"
50 #include <linux/delay.h>
51
52 #include "plx9080.h"
53 #include "comedi_fc.h"
54
55 static void abort_dma(struct comedi_device *dev, unsigned int channel);
56 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
57 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
58 struct comedi_cmd *cmd);
59 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
60 static irqreturn_t handle_interrupt(int irq, void *d);
61 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
62
63 #undef HPDI_DEBUG /* disable debugging messages */
64 /* #define HPDI_DEBUG enable debugging code */
65
66 #ifdef HPDI_DEBUG
67 #define DEBUG_PRINT(format, args...) printk(format , ## args)
68 #else
69 #define DEBUG_PRINT(format, args...)
70 #endif
71
72 #define TIMER_BASE 50 /* 20MHz master clock */
73 #define DMA_BUFFER_SIZE 0x10000
74 #define NUM_DMA_BUFFERS 4
75 #define NUM_DMA_DESCRIPTORS 256
76
77 /* indices of base address regions */
78 enum base_address_regions {
79 PLX9080_BADDRINDEX = 0,
80 HPDI_BADDRINDEX = 2,
81 };
82
83 enum hpdi_registers {
84 FIRMWARE_REV_REG = 0x0,
85 BOARD_CONTROL_REG = 0x4,
86 BOARD_STATUS_REG = 0x8,
87 TX_PROG_ALMOST_REG = 0xc,
88 RX_PROG_ALMOST_REG = 0x10,
89 FEATURES_REG = 0x14,
90 FIFO_REG = 0x18,
91 TX_STATUS_COUNT_REG = 0x1c,
92 TX_LINE_VALID_COUNT_REG = 0x20,
93 TX_LINE_INVALID_COUNT_REG = 0x24,
94 RX_STATUS_COUNT_REG = 0x28,
95 RX_LINE_COUNT_REG = 0x2c,
96 INTERRUPT_CONTROL_REG = 0x30,
97 INTERRUPT_STATUS_REG = 0x34,
98 TX_CLOCK_DIVIDER_REG = 0x38,
99 TX_FIFO_SIZE_REG = 0x40,
100 RX_FIFO_SIZE_REG = 0x44,
101 TX_FIFO_WORDS_REG = 0x48,
102 RX_FIFO_WORDS_REG = 0x4c,
103 INTERRUPT_EDGE_LEVEL_REG = 0x50,
104 INTERRUPT_POLARITY_REG = 0x54,
105 };
106
107 int command_channel_valid(unsigned int channel)
108 {
109 if (channel == 0 || channel > 6) {
110 printk(KERN_WARNING
111 "gsc_hpdi: bug! invalid cable command channel\n");
112 return 0;
113 }
114 return 1;
115 }
116
117 /* bit definitions */
118
119 enum firmware_revision_bits {
120 FEATURES_REG_PRESENT_BIT = 0x8000,
121 };
122 int firmware_revision(uint32_t fwr_bits)
123 {
124 return fwr_bits & 0xff;
125 }
126
127 int pcb_revision(uint32_t fwr_bits)
128 {
129 return (fwr_bits >> 8) & 0xff;
130 }
131
132 int hpdi_subid(uint32_t fwr_bits)
133 {
134 return (fwr_bits >> 16) & 0xff;
135 }
136
137 enum board_control_bits {
138 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
139 TX_FIFO_RESET_BIT = 0x2,
140 RX_FIFO_RESET_BIT = 0x4,
141 TX_ENABLE_BIT = 0x10,
142 RX_ENABLE_BIT = 0x20,
143 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
144 /* for ch 0, ch 1 can only transmit (when present) */
145 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
146 START_TX_BIT = 0x10,
147 CABLE_THROTTLE_ENABLE_BIT = 0x20,
148 TEST_MODE_ENABLE_BIT = 0x80000000,
149 };
150 uint32_t command_discrete_output_bits(unsigned int channel, int output,
151 int output_value)
152 {
153 uint32_t bits = 0;
154
155 if (command_channel_valid(channel) == 0)
156 return 0;
157 if (output) {
158 bits |= 0x1 << (16 + channel);
159 if (output_value)
160 bits |= 0x1 << (24 + channel);
161 } else
162 bits |= 0x1 << (24 + channel);
163
164 return bits;
165 }
166
167 enum board_status_bits {
168 COMMAND_LINE_STATUS_MASK = 0x7f,
169 TX_IN_PROGRESS_BIT = 0x80,
170 TX_NOT_EMPTY_BIT = 0x100,
171 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
172 TX_NOT_ALMOST_FULL_BIT = 0x400,
173 TX_NOT_FULL_BIT = 0x800,
174 RX_NOT_EMPTY_BIT = 0x1000,
175 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
176 RX_NOT_ALMOST_FULL_BIT = 0x4000,
177 RX_NOT_FULL_BIT = 0x8000,
178 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
179 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
180 TX_OVERRUN_BIT = 0x200000,
181 RX_UNDERRUN_BIT = 0x400000,
182 RX_OVERRUN_BIT = 0x800000,
183 };
184
185 uint32_t almost_full_bits(unsigned int num_words)
186 {
187 /* XXX need to add or subtract one? */
188 return (num_words << 16) & 0xff0000;
189 }
190
191 uint32_t almost_empty_bits(unsigned int num_words)
192 {
193 return num_words & 0xffff;
194 }
195
196 unsigned int almost_full_num_words(uint32_t bits)
197 {
198 /* XXX need to add or subtract one? */
199 return (bits >> 16) & 0xffff;
200 }
201
202 unsigned int almost_empty_num_words(uint32_t bits)
203 {
204 return bits & 0xffff;
205 }
206
207 enum features_bits {
208 FIFO_SIZE_PRESENT_BIT = 0x1,
209 FIFO_WORDS_PRESENT_BIT = 0x2,
210 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
211 GPIO_SUPPORTED_BIT = 0x8,
212 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
213 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
214 };
215
216 enum interrupt_sources {
217 FRAME_VALID_START_INTR = 0,
218 FRAME_VALID_END_INTR = 1,
219 TX_FIFO_EMPTY_INTR = 8,
220 TX_FIFO_ALMOST_EMPTY_INTR = 9,
221 TX_FIFO_ALMOST_FULL_INTR = 10,
222 TX_FIFO_FULL_INTR = 11,
223 RX_EMPTY_INTR = 12,
224 RX_ALMOST_EMPTY_INTR = 13,
225 RX_ALMOST_FULL_INTR = 14,
226 RX_FULL_INTR = 15,
227 };
228 int command_intr_source(unsigned int channel)
229 {
230 if (command_channel_valid(channel) == 0)
231 channel = 1;
232 return channel + 1;
233 }
234
235 uint32_t intr_bit(int interrupt_source)
236 {
237 return 0x1 << interrupt_source;
238 }
239
240 uint32_t tx_clock_divisor_bits(unsigned int divisor)
241 {
242 return divisor & 0xff;
243 }
244
245 unsigned int fifo_size(uint32_t fifo_size_bits)
246 {
247 return fifo_size_bits & 0xfffff;
248 }
249
250 unsigned int fifo_words(uint32_t fifo_words_bits)
251 {
252 return fifo_words_bits & 0xfffff;
253 }
254
255 uint32_t intr_edge_bit(int interrupt_source)
256 {
257 return 0x1 << interrupt_source;
258 }
259
260 uint32_t intr_active_high_bit(int interrupt_source)
261 {
262 return 0x1 << interrupt_source;
263 }
264
265 struct hpdi_board {
266
267 char *name;
268 int device_id; /* pci device id */
269 int subdevice_id; /* pci subdevice id */
270 };
271
272 static const struct hpdi_board hpdi_boards[] = {
273 {
274 .name = "pci-hpdi32",
275 .device_id = PCI_DEVICE_ID_PLX_9080,
276 .subdevice_id = 0x2400,
277 },
278 #if 0
279 {
280 .name = "pxi-hpdi32",
281 .device_id = 0x9656,
282 .subdevice_id = 0x2705,
283 },
284 #endif
285 };
286
287 static inline struct hpdi_board *board(const struct comedi_device *dev)
288 {
289 return (struct hpdi_board *)dev->board_ptr;
290 }
291
292 struct hpdi_private {
293
294 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
295 /* base addresses (physical) */
296 resource_size_t plx9080_phys_iobase;
297 resource_size_t hpdi_phys_iobase;
298 /* base addresses (ioremapped) */
299 void __iomem *plx9080_iobase;
300 void __iomem *hpdi_iobase;
301 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
302 /* physical addresses of dma buffers */
303 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
304 /* array of dma descriptors read by plx9080, allocated to get proper
305 * alignment */
306 struct plx_dma_desc *dma_desc;
307 /* physical address of dma descriptor array */
308 dma_addr_t dma_desc_phys_addr;
309 unsigned int num_dma_descriptors;
310 /* pointer to start of buffers indexed by descriptor */
311 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
312 /* index of the dma descriptor that is currently being used */
313 volatile unsigned int dma_desc_index;
314 unsigned int tx_fifo_size;
315 unsigned int rx_fifo_size;
316 volatile unsigned long dio_count;
317 /* software copies of values written to hpdi registers */
318 volatile uint32_t bits[24];
319 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
320 volatile unsigned int block_size;
321 unsigned dio_config_output:1;
322 };
323
324 static inline struct hpdi_private *priv(struct comedi_device *dev)
325 {
326 return dev->private;
327 }
328
329 static int dio_config_insn(struct comedi_device *dev,
330 struct comedi_subdevice *s, struct comedi_insn *insn,
331 unsigned int *data)
332 {
333 switch (data[0]) {
334 case INSN_CONFIG_DIO_OUTPUT:
335 priv(dev)->dio_config_output = 1;
336 return insn->n;
337 break;
338 case INSN_CONFIG_DIO_INPUT:
339 priv(dev)->dio_config_output = 0;
340 return insn->n;
341 break;
342 case INSN_CONFIG_DIO_QUERY:
343 data[1] =
344 priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
345 return insn->n;
346 break;
347 case INSN_CONFIG_BLOCK_SIZE:
348 return dio_config_block_size(dev, data);
349 break;
350 default:
351 break;
352 }
353
354 return -EINVAL;
355 }
356
357 static void disable_plx_interrupts(struct comedi_device *dev)
358 {
359 writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
360 }
361
362 /* initialize plx9080 chip */
363 static void init_plx9080(struct comedi_device *dev)
364 {
365 uint32_t bits;
366 void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
367
368 /* plx9080 dump */
369 DEBUG_PRINT(" plx interrupt status 0x%x\n",
370 readl(plx_iobase + PLX_INTRCS_REG));
371 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
372 DEBUG_PRINT(" plx control reg 0x%x\n",
373 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
374
375 DEBUG_PRINT(" plx revision 0x%x\n",
376 readl(plx_iobase + PLX_REVISION_REG));
377 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
378 readl(plx_iobase + PLX_DMA0_MODE_REG));
379 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
380 readl(plx_iobase + PLX_DMA1_MODE_REG));
381 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
382 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
383 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
384 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
385 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
386 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
387 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
388 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
389 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
390 readb(plx_iobase + PLX_DMA0_CS_REG));
391 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
392 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
393 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
394 #ifdef __BIG_ENDIAN
395 bits = BIGEND_DMA0 | BIGEND_DMA1;
396 #else
397 bits = 0;
398 #endif
399 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
400
401 disable_plx_interrupts(dev);
402
403 abort_dma(dev, 0);
404 abort_dma(dev, 1);
405
406 /* configure dma0 mode */
407 bits = 0;
408 /* enable ready input */
409 bits |= PLX_DMA_EN_READYIN_BIT;
410 /* enable dma chaining */
411 bits |= PLX_EN_CHAIN_BIT;
412 /* enable interrupt on dma done
413 * (probably don't need this, since chain never finishes) */
414 bits |= PLX_EN_DMA_DONE_INTR_BIT;
415 /* don't increment local address during transfers
416 * (we are transferring from a fixed fifo register) */
417 bits |= PLX_LOCAL_ADDR_CONST_BIT;
418 /* route dma interrupt to pci bus */
419 bits |= PLX_DMA_INTR_PCI_BIT;
420 /* enable demand mode */
421 bits |= PLX_DEMAND_MODE_BIT;
422 /* enable local burst mode */
423 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
424 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
425 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
426 }
427
428 /* Allocate and initialize the subdevice structures.
429 */
430 static int setup_subdevices(struct comedi_device *dev)
431 {
432 struct comedi_subdevice *s;
433 int ret;
434
435 ret = comedi_alloc_subdevices(dev, 1);
436 if (ret)
437 return ret;
438
439 s = &dev->subdevices[0];
440 /* analog input subdevice */
441 dev->read_subdev = s;
442 /* dev->write_subdev = s; */
443 s->type = COMEDI_SUBD_DIO;
444 s->subdev_flags =
445 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
446 s->n_chan = 32;
447 s->len_chanlist = 32;
448 s->maxdata = 1;
449 s->range_table = &range_digital;
450 s->insn_config = dio_config_insn;
451 s->do_cmd = hpdi_cmd;
452 s->do_cmdtest = hpdi_cmd_test;
453 s->cancel = hpdi_cancel;
454
455 return 0;
456 }
457
458 static int init_hpdi(struct comedi_device *dev)
459 {
460 uint32_t plx_intcsr_bits;
461
462 writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
463 udelay(10);
464
465 writel(almost_empty_bits(32) | almost_full_bits(32),
466 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
467 writel(almost_empty_bits(32) | almost_full_bits(32),
468 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
469
470 priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
471 TX_FIFO_SIZE_REG));
472 priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
473 RX_FIFO_SIZE_REG));
474
475 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
476
477 /* enable interrupts */
478 plx_intcsr_bits =
479 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
480 ICS_DMA0_E;
481 writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
482
483 return 0;
484 }
485
486 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
487 static int setup_dma_descriptors(struct comedi_device *dev,
488 unsigned int transfer_size)
489 {
490 unsigned int buffer_index, buffer_offset;
491 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
492 PLX_XFER_LOCAL_TO_PCI;
493 unsigned int i;
494
495 if (transfer_size > DMA_BUFFER_SIZE)
496 transfer_size = DMA_BUFFER_SIZE;
497 transfer_size -= transfer_size % sizeof(uint32_t);
498 if (transfer_size == 0)
499 return -1;
500
501 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
502 DEBUG_PRINT(" descriptors at 0x%lx\n",
503 (unsigned long)priv(dev)->dma_desc_phys_addr);
504
505 buffer_offset = 0;
506 buffer_index = 0;
507 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
508 buffer_index < NUM_DMA_BUFFERS; i++) {
509 priv(dev)->dma_desc[i].pci_start_addr =
510 cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
511 buffer_offset);
512 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
513 priv(dev)->dma_desc[i].transfer_size =
514 cpu_to_le32(transfer_size);
515 priv(dev)->dma_desc[i].next =
516 cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
517 1) *
518 sizeof(priv(dev)->dma_desc[0])) | next_bits);
519
520 priv(dev)->desc_dio_buffer[i] =
521 priv(dev)->dio_buffer[buffer_index] +
522 (buffer_offset / sizeof(uint32_t));
523
524 buffer_offset += transfer_size;
525 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
526 buffer_offset = 0;
527 buffer_index++;
528 }
529
530 DEBUG_PRINT(" desc %i\n", i);
531 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
532 priv(dev)->desc_dio_buffer[i],
533 (unsigned long)priv(dev)->dma_desc[i].
534 pci_start_addr);
535 DEBUG_PRINT(" next 0x%lx\n",
536 (unsigned long)priv(dev)->dma_desc[i].next);
537 }
538 priv(dev)->num_dma_descriptors = i;
539 /* fix last descriptor to point back to first */
540 priv(dev)->dma_desc[i - 1].next =
541 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
542 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
543 (unsigned long)priv(dev)->dma_desc[i - 1].next);
544
545 priv(dev)->block_size = transfer_size;
546
547 return transfer_size;
548 }
549
550 static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
551 {
552 struct pci_dev *pcidev;
553 int i;
554 int retval;
555
556 printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
557
558 if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
559 return -ENOMEM;
560
561 pcidev = NULL;
562 for (i = 0; i < ARRAY_SIZE(hpdi_boards) &&
563 dev->board_ptr == NULL; i++) {
564 do {
565 pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
566 hpdi_boards[i].device_id,
567 PCI_VENDOR_ID_PLX,
568 hpdi_boards[i].subdevice_id,
569 pcidev);
570 /* was a particular bus/slot requested? */
571 if (it->options[0] || it->options[1]) {
572 /* are we on the wrong bus/slot? */
573 if (pcidev->bus->number != it->options[0] ||
574 PCI_SLOT(pcidev->devfn) != it->options[1])
575 continue;
576 }
577 if (pcidev) {
578 priv(dev)->hw_dev = pcidev;
579 dev->board_ptr = hpdi_boards + i;
580 break;
581 }
582 } while (pcidev != NULL);
583 }
584 if (dev->board_ptr == NULL) {
585 printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
586 return -EIO;
587 }
588
589 printk(KERN_WARNING
590 "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
591 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
592
593 if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
594 printk(KERN_WARNING
595 " failed enable PCI device and request regions\n");
596 return -EIO;
597 }
598 pci_set_master(pcidev);
599
600 /* Initialize dev->board_name */
601 dev->board_name = board(dev)->name;
602
603 priv(dev)->plx9080_phys_iobase =
604 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
605 priv(dev)->hpdi_phys_iobase =
606 pci_resource_start(pcidev, HPDI_BADDRINDEX);
607
608 /* remap, won't work with 2.0 kernels but who cares */
609 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
610 pci_resource_len(pcidev,
611 PLX9080_BADDRINDEX));
612 priv(dev)->hpdi_iobase =
613 ioremap(priv(dev)->hpdi_phys_iobase,
614 pci_resource_len(pcidev, HPDI_BADDRINDEX));
615 if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
616 printk(KERN_WARNING " failed to remap io memory\n");
617 return -ENOMEM;
618 }
619
620 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
621 DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
622
623 init_plx9080(dev);
624
625 /* get irq */
626 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
627 dev->driver->driver_name, dev)) {
628 printk(KERN_WARNING
629 " unable to allocate irq %u\n", pcidev->irq);
630 return -EINVAL;
631 }
632 dev->irq = pcidev->irq;
633
634 printk(KERN_WARNING " irq %u\n", dev->irq);
635
636 /* allocate pci dma buffers */
637 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
638 priv(dev)->dio_buffer[i] =
639 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
640 &priv(dev)->dio_buffer_phys_addr[i]);
641 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
642 priv(dev)->dio_buffer[i],
643 (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
644 }
645 /* allocate dma descriptors */
646 priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
647 sizeof(struct plx_dma_desc) *
648 NUM_DMA_DESCRIPTORS,
649 &priv(dev)->
650 dma_desc_phys_addr);
651 if (priv(dev)->dma_desc_phys_addr & 0xf) {
652 printk(KERN_WARNING
653 " dma descriptors not quad-word aligned (bug)\n");
654 return -EIO;
655 }
656
657 retval = setup_dma_descriptors(dev, 0x1000);
658 if (retval < 0)
659 return retval;
660
661 retval = setup_subdevices(dev);
662 if (retval < 0)
663 return retval;
664
665 return init_hpdi(dev);
666 }
667
668 static void hpdi_detach(struct comedi_device *dev)
669 {
670 unsigned int i;
671
672 if (dev->irq)
673 free_irq(dev->irq, dev);
674 if ((priv(dev)) && (priv(dev)->hw_dev)) {
675 if (priv(dev)->plx9080_iobase) {
676 disable_plx_interrupts(dev);
677 iounmap(priv(dev)->plx9080_iobase);
678 }
679 if (priv(dev)->hpdi_iobase)
680 iounmap(priv(dev)->hpdi_iobase);
681 /* free pci dma buffers */
682 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
683 if (priv(dev)->dio_buffer[i])
684 pci_free_consistent(priv(dev)->hw_dev,
685 DMA_BUFFER_SIZE,
686 priv(dev)->
687 dio_buffer[i],
688 priv
689 (dev)->dio_buffer_phys_addr
690 [i]);
691 }
692 /* free dma descriptors */
693 if (priv(dev)->dma_desc)
694 pci_free_consistent(priv(dev)->hw_dev,
695 sizeof(struct plx_dma_desc)
696 * NUM_DMA_DESCRIPTORS,
697 priv(dev)->dma_desc,
698 priv(dev)->
699 dma_desc_phys_addr);
700 if (priv(dev)->hpdi_phys_iobase)
701 comedi_pci_disable(priv(dev)->hw_dev);
702 pci_dev_put(priv(dev)->hw_dev);
703 }
704 }
705
706 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
707 {
708 unsigned int requested_block_size;
709 int retval;
710
711 requested_block_size = data[1];
712
713 retval = setup_dma_descriptors(dev, requested_block_size);
714 if (retval < 0)
715 return retval;
716
717 data[1] = retval;
718
719 return 2;
720 }
721
722 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
723 struct comedi_cmd *cmd)
724 {
725 int err = 0;
726 int i;
727
728 /* Step 1 : check if triggers are trivially valid */
729
730 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
731 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
732 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
733 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
734 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
735
736 if (err)
737 return 1;
738
739 /* Step 2a : make sure trigger sources are unique */
740
741 err |= cfc_check_trigger_is_unique(cmd->stop_src);
742
743 /* Step 2b : and mutually compatible */
744
745 if (err)
746 return 2;
747
748 /* step 3: make sure arguments are trivially compatible */
749
750 if (!cmd->chanlist_len) {
751 cmd->chanlist_len = 32;
752 err++;
753 }
754 if (cmd->scan_end_arg != cmd->chanlist_len) {
755 cmd->scan_end_arg = cmd->chanlist_len;
756 err++;
757 }
758
759 switch (cmd->stop_src) {
760 case TRIG_COUNT:
761 if (!cmd->stop_arg) {
762 cmd->stop_arg = 1;
763 err++;
764 }
765 break;
766 case TRIG_NONE:
767 if (cmd->stop_arg != 0) {
768 cmd->stop_arg = 0;
769 err++;
770 }
771 break;
772 default:
773 break;
774 }
775
776 if (err)
777 return 3;
778
779 /* step 4: fix up any arguments */
780
781 if (err)
782 return 4;
783
784 if (!cmd->chanlist)
785 return 0;
786
787 for (i = 1; i < cmd->chanlist_len; i++) {
788 if (CR_CHAN(cmd->chanlist[i]) != i) {
789 /* XXX could support 8 or 16 channels */
790 comedi_error(dev,
791 "chanlist must be ch 0 to 31 in order");
792 err++;
793 break;
794 }
795 }
796
797 if (err)
798 return 5;
799
800 return 0;
801 }
802
803 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
804 struct comedi_cmd *cmd)
805 {
806 if (priv(dev)->dio_config_output)
807 return -EINVAL;
808 else
809 return di_cmd_test(dev, s, cmd);
810 }
811
812 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
813 unsigned int offset)
814 {
815 writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
816 priv(dev)->hpdi_iobase + offset);
817 }
818
819 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
820 {
821 uint32_t bits;
822 unsigned long flags;
823 struct comedi_async *async = s->async;
824 struct comedi_cmd *cmd = &async->cmd;
825
826 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
827
828 DEBUG_PRINT("hpdi: in di_cmd\n");
829
830 abort_dma(dev, 0);
831
832 priv(dev)->dma_desc_index = 0;
833
834 /* These register are supposedly unused during chained dma,
835 * but I have found that left over values from last operation
836 * occasionally cause problems with transfer of first dma
837 * block. Initializing them to zero seems to fix the problem. */
838 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
839 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
840 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
841 /* give location of first dma descriptor */
842 bits =
843 priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
844 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
845 writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
846
847 /* spinlock for plx dma control/status reg */
848 spin_lock_irqsave(&dev->spinlock, flags);
849 /* enable dma transfer */
850 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
851 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
852 spin_unlock_irqrestore(&dev->spinlock, flags);
853
854 if (cmd->stop_src == TRIG_COUNT)
855 priv(dev)->dio_count = cmd->stop_arg;
856 else
857 priv(dev)->dio_count = 1;
858
859 /* clear over/under run status flags */
860 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
861 priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
862 /* enable interrupts */
863 writel(intr_bit(RX_FULL_INTR),
864 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
865
866 DEBUG_PRINT("hpdi: starting rx\n");
867 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
868
869 return 0;
870 }
871
872 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
873 {
874 if (priv(dev)->dio_config_output)
875 return -EINVAL;
876 else
877 return di_cmd(dev, s);
878 }
879
880 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
881 {
882 struct comedi_async *async = dev->read_subdev->async;
883 uint32_t next_transfer_addr;
884 int j;
885 int num_samples = 0;
886 void __iomem *pci_addr_reg;
887
888 if (channel)
889 pci_addr_reg =
890 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
891 else
892 pci_addr_reg =
893 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
894
895 /* loop until we have read all the full buffers */
896 j = 0;
897 for (next_transfer_addr = readl(pci_addr_reg);
898 (next_transfer_addr <
899 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
900 pci_start_addr)
901 || next_transfer_addr >=
902 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
903 pci_start_addr) + priv(dev)->block_size)
904 && j < priv(dev)->num_dma_descriptors; j++) {
905 /* transfer data from dma buffer to comedi buffer */
906 num_samples = priv(dev)->block_size / sizeof(uint32_t);
907 if (async->cmd.stop_src == TRIG_COUNT) {
908 if (num_samples > priv(dev)->dio_count)
909 num_samples = priv(dev)->dio_count;
910 priv(dev)->dio_count -= num_samples;
911 }
912 cfc_write_array_to_buffer(dev->read_subdev,
913 priv(dev)->desc_dio_buffer[priv(dev)->
914 dma_desc_index],
915 num_samples * sizeof(uint32_t));
916 priv(dev)->dma_desc_index++;
917 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
918
919 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
920 priv(dev)->dma_desc[priv(dev)->dma_desc_index].
921 next);
922 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
923 }
924 /* XXX check for buffer overrun somehow */
925 }
926
927 static irqreturn_t handle_interrupt(int irq, void *d)
928 {
929 struct comedi_device *dev = d;
930 struct comedi_subdevice *s = dev->read_subdev;
931 struct comedi_async *async = s->async;
932 uint32_t hpdi_intr_status, hpdi_board_status;
933 uint32_t plx_status;
934 uint32_t plx_bits;
935 uint8_t dma0_status, dma1_status;
936 unsigned long flags;
937
938 if (!dev->attached)
939 return IRQ_NONE;
940
941 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
942 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
943 return IRQ_NONE;
944
945 hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
946 hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
947
948 async->events = 0;
949
950 if (hpdi_intr_status) {
951 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
952 writel(hpdi_intr_status,
953 priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
954 }
955 /* spin lock makes sure no one else changes plx dma control reg */
956 spin_lock_irqsave(&dev->spinlock, flags);
957 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
958 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
959 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
960 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
961
962 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
963 if (dma0_status & PLX_DMA_EN_BIT)
964 drain_dma_buffers(dev, 0);
965 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
966 }
967 spin_unlock_irqrestore(&dev->spinlock, flags);
968
969 /* spin lock makes sure no one else changes plx dma control reg */
970 spin_lock_irqsave(&dev->spinlock, flags);
971 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
972 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
973 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
974 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
975 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
976
977 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
978 }
979 spin_unlock_irqrestore(&dev->spinlock, flags);
980
981 /* clear possible plx9080 interrupt sources */
982 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
983 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
984 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
985 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
986 }
987
988 if (hpdi_board_status & RX_OVERRUN_BIT) {
989 comedi_error(dev, "rx fifo overrun");
990 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
991 DEBUG_PRINT("dma0_status 0x%x\n",
992 (int)readb(priv(dev)->plx9080_iobase +
993 PLX_DMA0_CS_REG));
994 }
995
996 if (hpdi_board_status & RX_UNDERRUN_BIT) {
997 comedi_error(dev, "rx fifo underrun");
998 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
999 }
1000
1001 if (priv(dev)->dio_count == 0)
1002 async->events |= COMEDI_CB_EOA;
1003
1004 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1005 DEBUG_PRINT("plx status 0x%x\n", plx_status);
1006 if (async->events)
1007 DEBUG_PRINT(" events 0x%x\n", async->events);
1008
1009 cfc_handle_events(dev, s);
1010
1011 return IRQ_HANDLED;
1012 }
1013
1014 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1015 {
1016 unsigned long flags;
1017
1018 /* spinlock for plx dma control/status reg */
1019 spin_lock_irqsave(&dev->spinlock, flags);
1020
1021 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1022
1023 spin_unlock_irqrestore(&dev->spinlock, flags);
1024 }
1025
1026 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1027 {
1028 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1029
1030 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
1031
1032 abort_dma(dev, 0);
1033
1034 return 0;
1035 }
1036
1037 static struct comedi_driver gsc_hpdi_driver = {
1038 .driver_name = "gsc_hpdi",
1039 .module = THIS_MODULE,
1040 .attach = hpdi_attach,
1041 .detach = hpdi_detach,
1042 };
1043
1044 static int __devinit gsc_hpdi_pci_probe(struct pci_dev *dev,
1045 const struct pci_device_id *ent)
1046 {
1047 return comedi_pci_auto_config(dev, &gsc_hpdi_driver);
1048 }
1049
1050 static void __devexit gsc_hpdi_pci_remove(struct pci_dev *dev)
1051 {
1052 comedi_pci_auto_unconfig(dev);
1053 }
1054
1055 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
1056 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
1057 0x2400, 0, 0, 0},
1058 { 0 }
1059 };
1060 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
1061
1062 static struct pci_driver gsc_hpdi_pci_driver = {
1063 .name = "gsc_hpdi",
1064 .id_table = gsc_hpdi_pci_table,
1065 .probe = gsc_hpdi_pci_probe,
1066 .remove = __devexit_p(gsc_hpdi_pci_remove)
1067 };
1068 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
1069
1070 MODULE_AUTHOR("Comedi http://www.comedi.org");
1071 MODULE_DESCRIPTION("Comedi low-level driver");
1072 MODULE_LICENSE("GPL");
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