2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Description: Meilhaus ME-4000 series boards
26 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
27 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
28 Updated: Mon, 18 Mar 2002 15:34:01 -0800
29 Status: broken (no support for loading firmware)
38 Configuration Options: not applicable, uses PCI auto config
40 The firmware required by these boards is available in the
41 comedi_nonfree_firmware tarball available from
42 http://www.comedi.org. However, the driver's support for
43 loading the firmware through comedi_config is currently
48 #include <linux/pci.h>
49 #include <linux/delay.h>
50 #include <linux/interrupt.h>
51 #include <linux/list.h>
52 #include <linux/spinlock.h>
54 #include "../comedidev.h"
56 #include "comedi_fc.h"
60 /* file removed due to GPL incompatibility */
61 #include "me4000_fw.h"
64 #define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650
65 #define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660
66 #define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661
67 #define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662
68 #define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663
69 #define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670
70 #define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671
71 #define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672
72 #define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673
73 #define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680
74 #define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681
75 #define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682
76 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683
79 * ME4000 Register map and bit defines
81 #define ME4000_AO_CHAN(x) ((x) * 0x18)
83 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
84 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
85 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
86 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
87 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
88 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
89 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
90 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
91 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
92 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
93 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
94 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
95 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
96 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
97 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
98 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
99 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
100 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
101 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
102 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
103 #define ME4000_AI_CTRL_REG 0x74
104 #define ME4000_AI_STATUS_REG 0x74
105 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
106 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
107 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
108 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
109 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
110 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
111 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
112 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
113 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
114 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
115 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
116 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
117 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
118 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
119 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
120 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
121 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
122 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
123 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
124 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
125 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
126 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
127 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
128 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
129 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
130 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
131 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
132 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
133 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
134 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
135 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
136 #define ME4000_AI_CHANNEL_LIST_REG 0x78
137 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
138 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
139 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
140 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
141 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
142 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
143 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
144 #define ME4000_AI_DATA_REG 0x7c
145 #define ME4000_AI_CHAN_TIMER_REG 0x80
146 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
147 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
148 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
149 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
150 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
151 #define ME4000_AI_START_REG 0x98
152 #define ME4000_IRQ_STATUS_REG 0x9c
153 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
154 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
155 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
156 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
157 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
158 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
159 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
160 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
161 #define ME4000_DIO_PORT_0_REG 0xa0
162 #define ME4000_DIO_PORT_1_REG 0xa4
163 #define ME4000_DIO_PORT_2_REG 0xa8
164 #define ME4000_DIO_PORT_3_REG 0xac
165 #define ME4000_DIO_DIR_REG 0xb0
166 #define ME4000_AO_LOADSETREG_XX 0xb4
167 #define ME4000_DIO_CTRL_REG 0xb8
168 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
169 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
170 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
171 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
172 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
173 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
174 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
175 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
176 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
177 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
178 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
179 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
180 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
181 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
182 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
183 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
184 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
187 * PLX Register map and bit defines
189 #define PLX_INTCSR 0x4c
190 #define PLX_INTCSR_LOCAL_INT1_EN (1 << 0)
191 #define PLX_INTCSR_LOCAL_INT1_POL (1 << 1)
192 #define PLX_INTCSR_LOCAL_INT1_STATE (1 << 2)
193 #define PLX_INTCSR_LOCAL_INT2_EN (1 << 3)
194 #define PLX_INTCSR_LOCAL_INT2_POL (1 << 4)
195 #define PLX_INTCSR_LOCAL_INT2_STATE (1 << 5)
196 #define PLX_INTCSR_PCI_INT_EN (1 << 6)
197 #define PLX_INTCSR_SOFT_INT (1 << 7)
199 #define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
200 #define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
201 #define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
202 #define PLX_ICR_BIT_EEPROM_READ (1 << 27)
203 #define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
204 #define PLX_ICR_MASK_EEPROM (0x1f << 24)
206 #define EEPROM_DELAY 1
208 #define ME4000_AI_FIFO_COUNT 2048
210 #define ME4000_AI_MIN_TICKS 66
211 #define ME4000_AI_MIN_SAMPLE_TIME 2000
212 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
214 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
217 unsigned long plx_regbase
;
218 unsigned long timer_regbase
;
220 unsigned int ao_readback
[4];
223 struct me4000_board
{
225 unsigned short device_id
;
236 static const struct me4000_board me4000_boards
[] = {
239 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4650
,
244 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4660
,
251 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4660I
,
258 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4660S
,
266 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4660IS
,
274 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4670
,
283 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4670I
,
292 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4670S
,
302 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4670IS
,
312 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4680
,
322 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4680I
,
332 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4680S
,
343 .device_id
= PCI_DEVICE_ID_MEILHAUS_ME4680IS
,
355 static const struct comedi_lrange me4000_ai_range
= {
365 #define FIRMWARE_NOT_AVAILABLE 1
366 #if FIRMWARE_NOT_AVAILABLE
367 extern unsigned char *xilinx_firm
;
370 static int xilinx_download(struct comedi_device
*dev
)
372 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
373 struct me4000_info
*info
= dev
->private;
374 unsigned long xilinx_iobase
= pci_resource_start(pcidev
, 5);
376 wait_queue_head_t queue
;
383 init_waitqueue_head(&queue
);
386 * Set PLX local interrupt 2 polarity to high.
387 * Interrupt is thrown by init pin of xilinx.
389 outl(0x10, info
->plx_regbase
+ PLX_INTCSR
);
391 /* Set /CS and /WRITE of the Xilinx */
392 value
= inl(info
->plx_regbase
+ PLX_ICR
);
394 outl(value
, info
->plx_regbase
+ PLX_ICR
);
396 /* Init Xilinx with CS1 */
397 inb(xilinx_iobase
+ 0xC8);
399 /* Wait until /INIT pin is set */
401 if (!(inl(info
->plx_regbase
+ PLX_INTCSR
) & 0x20)) {
402 dev_err(dev
->class_dev
, "Can't init Xilinx\n");
406 /* Reset /CS and /WRITE of the Xilinx */
407 value
= inl(info
->plx_regbase
+ PLX_ICR
);
409 outl(value
, info
->plx_regbase
+ PLX_ICR
);
410 if (FIRMWARE_NOT_AVAILABLE
) {
411 dev_err(dev
->class_dev
,
412 "xilinx firmware unavailable due to licensing, aborting");
415 /* Download Xilinx firmware */
416 size
= (xilinx_firm
[0] << 24) + (xilinx_firm
[1] << 16) +
417 (xilinx_firm
[2] << 8) + xilinx_firm
[3];
420 for (idx
= 0; idx
< size
; idx
++) {
421 outb(xilinx_firm
[16 + idx
], xilinx_iobase
);
424 /* Check if BUSY flag is low */
425 if (inl(info
->plx_regbase
+ PLX_ICR
) & 0x20) {
426 dev_err(dev
->class_dev
,
427 "Xilinx is still busy (idx = %d)\n",
434 /* If done flag is high download was successful */
435 if (inl(info
->plx_regbase
+ PLX_ICR
) & 0x4) {
437 dev_err(dev
->class_dev
, "DONE flag is not set\n");
438 dev_err(dev
->class_dev
, "Download not successful\n");
442 /* Set /CS and /WRITE */
443 value
= inl(info
->plx_regbase
+ PLX_ICR
);
445 outl(value
, info
->plx_regbase
+ PLX_ICR
);
450 static void me4000_reset(struct comedi_device
*dev
)
452 struct me4000_info
*info
= dev
->private;
456 /* Make a hardware reset */
457 val
= inl(info
->plx_regbase
+ PLX_ICR
);
459 outl(val
, info
->plx_regbase
+ PLX_ICR
);
461 outl(val
, info
->plx_regbase
+ PLX_ICR
);
463 /* 0x8000 to the DACs means an output voltage of 0V */
464 for (chan
= 0; chan
< 4; chan
++)
465 outl(0x8000, dev
->iobase
+ ME4000_AO_SINGLE_REG(chan
));
467 /* Set both stop bits in the analog input control register */
468 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
| ME4000_AI_CTRL_BIT_STOP
,
469 dev
->iobase
+ ME4000_AI_CTRL_REG
);
471 /* Set both stop bits in the analog output control register */
472 val
= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP
| ME4000_AO_CTRL_BIT_STOP
;
473 for (chan
= 0; chan
< 4; chan
++)
474 outl(val
, dev
->iobase
+ ME4000_AO_CTRL_REG(chan
));
476 /* Enable interrupts on the PLX */
477 outl(0x43, info
->plx_regbase
+ PLX_INTCSR
);
479 /* Set the adustment register for AO demux */
480 outl(ME4000_AO_DEMUX_ADJUST_VALUE
,
481 dev
->iobase
+ ME4000_AO_DEMUX_ADJUST_REG
);
484 * Set digital I/O direction for port 0
485 * to output on isolated versions
487 if (!(inl(dev
->iobase
+ ME4000_DIO_DIR_REG
) & 0x1))
488 outl(0x1, dev
->iobase
+ ME4000_DIO_CTRL_REG
);
491 /*=============================================================================
493 ===========================================================================*/
495 static int me4000_ai_insn_read(struct comedi_device
*dev
,
496 struct comedi_subdevice
*subdevice
,
497 struct comedi_insn
*insn
, unsigned int *data
)
499 const struct me4000_board
*thisboard
= comedi_board(dev
);
500 int chan
= CR_CHAN(insn
->chanspec
);
501 int rang
= CR_RANGE(insn
->chanspec
);
502 int aref
= CR_AREF(insn
->chanspec
);
504 unsigned long entry
= 0;
510 } else if (insn
->n
> 1) {
511 dev_err(dev
->class_dev
, "Invalid instruction length %d\n",
518 entry
|= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5
;
521 entry
|= ME4000_AI_LIST_RANGE_UNIPOLAR_10
;
524 entry
|= ME4000_AI_LIST_RANGE_BIPOLAR_2_5
;
527 entry
|= ME4000_AI_LIST_RANGE_BIPOLAR_10
;
530 dev_err(dev
->class_dev
, "Invalid range specified\n");
537 if (chan
>= thisboard
->ai_nchan
) {
538 dev_err(dev
->class_dev
,
539 "Analog input is not available\n");
542 entry
|= ME4000_AI_LIST_INPUT_SINGLE_ENDED
| chan
;
546 if (rang
== 0 || rang
== 1) {
547 dev_err(dev
->class_dev
,
548 "Range must be bipolar when aref = diff\n");
552 if (chan
>= thisboard
->ai_diff_nchan
) {
553 dev_err(dev
->class_dev
,
554 "Analog input is not available\n");
557 entry
|= ME4000_AI_LIST_INPUT_DIFFERENTIAL
| chan
;
560 dev_err(dev
->class_dev
, "Invalid aref specified\n");
564 entry
|= ME4000_AI_LIST_LAST_ENTRY
;
566 /* Clear channel list, data fifo and both stop bits */
567 tmp
= inl(dev
->iobase
+ ME4000_AI_CTRL_REG
);
568 tmp
&= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO
|
569 ME4000_AI_CTRL_BIT_DATA_FIFO
|
570 ME4000_AI_CTRL_BIT_STOP
| ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
);
571 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
573 /* Set the acquisition mode to single */
574 tmp
&= ~(ME4000_AI_CTRL_BIT_MODE_0
| ME4000_AI_CTRL_BIT_MODE_1
|
575 ME4000_AI_CTRL_BIT_MODE_2
);
576 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
578 /* Enable channel list and data fifo */
579 tmp
|= ME4000_AI_CTRL_BIT_CHANNEL_FIFO
| ME4000_AI_CTRL_BIT_DATA_FIFO
;
580 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
582 /* Generate channel list entry */
583 outl(entry
, dev
->iobase
+ ME4000_AI_CHANNEL_LIST_REG
);
585 /* Set the timer to maximum sample rate */
586 outl(ME4000_AI_MIN_TICKS
, dev
->iobase
+ ME4000_AI_CHAN_TIMER_REG
);
587 outl(ME4000_AI_MIN_TICKS
, dev
->iobase
+ ME4000_AI_CHAN_PRE_TIMER_REG
);
589 /* Start conversion by dummy read */
590 inl(dev
->iobase
+ ME4000_AI_START_REG
);
592 /* Wait until ready */
594 if (!(inl(dev
->iobase
+ ME4000_AI_STATUS_REG
) &
595 ME4000_AI_STATUS_BIT_EF_DATA
)) {
596 dev_err(dev
->class_dev
, "Value not available after wait\n");
600 /* Read value from data fifo */
601 lval
= inl(dev
->iobase
+ ME4000_AI_DATA_REG
) & 0xFFFF;
602 data
[0] = lval
^ 0x8000;
607 static int me4000_ai_cancel(struct comedi_device
*dev
,
608 struct comedi_subdevice
*s
)
612 /* Stop any running conversion */
613 tmp
= inl(dev
->iobase
+ ME4000_AI_CTRL_REG
);
614 tmp
&= ~(ME4000_AI_CTRL_BIT_STOP
| ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
);
615 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
617 /* Clear the control register */
618 outl(0x0, dev
->iobase
+ ME4000_AI_CTRL_REG
);
623 static int ai_check_chanlist(struct comedi_device
*dev
,
624 struct comedi_subdevice
*s
, struct comedi_cmd
*cmd
)
626 const struct me4000_board
*thisboard
= comedi_board(dev
);
630 /* Check whether a channel list is available */
631 if (!cmd
->chanlist_len
) {
632 dev_err(dev
->class_dev
, "No channel list available\n");
636 /* Check the channel list size */
637 if (cmd
->chanlist_len
> ME4000_AI_CHANNEL_LIST_COUNT
) {
638 dev_err(dev
->class_dev
, "Channel list is to large\n");
642 /* Check the pointer */
643 if (!cmd
->chanlist
) {
644 dev_err(dev
->class_dev
, "NULL pointer to channel list\n");
648 /* Check whether aref is equal for all entries */
649 aref
= CR_AREF(cmd
->chanlist
[0]);
650 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
651 if (CR_AREF(cmd
->chanlist
[i
]) != aref
) {
652 dev_err(dev
->class_dev
,
653 "Mode is not equal for all entries\n");
658 /* Check whether channels are available for this ending */
659 if (aref
== SDF_DIFF
) {
660 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
661 if (CR_CHAN(cmd
->chanlist
[i
]) >=
662 thisboard
->ai_diff_nchan
) {
663 dev_err(dev
->class_dev
,
664 "Channel number to high\n");
669 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
670 if (CR_CHAN(cmd
->chanlist
[i
]) >= thisboard
->ai_nchan
) {
671 dev_err(dev
->class_dev
,
672 "Channel number to high\n");
678 /* Check if bipolar is set for all entries when in differential mode */
679 if (aref
== SDF_DIFF
) {
680 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
681 if (CR_RANGE(cmd
->chanlist
[i
]) != 1 &&
682 CR_RANGE(cmd
->chanlist
[i
]) != 2) {
683 dev_err(dev
->class_dev
,
684 "Bipolar is not selected in differential mode\n");
693 static int ai_round_cmd_args(struct comedi_device
*dev
,
694 struct comedi_subdevice
*s
,
695 struct comedi_cmd
*cmd
,
696 unsigned int *init_ticks
,
697 unsigned int *scan_ticks
, unsigned int *chan_ticks
)
706 if (cmd
->start_arg
) {
707 *init_ticks
= (cmd
->start_arg
* 33) / 1000;
708 rest
= (cmd
->start_arg
* 33) % 1000;
710 if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_NEAREST
) {
713 } else if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_UP
) {
719 if (cmd
->scan_begin_arg
) {
720 *scan_ticks
= (cmd
->scan_begin_arg
* 33) / 1000;
721 rest
= (cmd
->scan_begin_arg
* 33) % 1000;
723 if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_NEAREST
) {
726 } else if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_UP
) {
732 if (cmd
->convert_arg
) {
733 *chan_ticks
= (cmd
->convert_arg
* 33) / 1000;
734 rest
= (cmd
->convert_arg
* 33) % 1000;
736 if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_NEAREST
) {
739 } else if ((cmd
->flags
& TRIG_ROUND_MASK
) == TRIG_ROUND_UP
) {
748 static void ai_write_timer(struct comedi_device
*dev
,
749 unsigned int init_ticks
,
750 unsigned int scan_ticks
, unsigned int chan_ticks
)
752 outl(init_ticks
- 1, dev
->iobase
+ ME4000_AI_SCAN_PRE_TIMER_LOW_REG
);
753 outl(0x0, dev
->iobase
+ ME4000_AI_SCAN_PRE_TIMER_HIGH_REG
);
756 outl(scan_ticks
- 1, dev
->iobase
+ ME4000_AI_SCAN_TIMER_LOW_REG
);
757 outl(0x0, dev
->iobase
+ ME4000_AI_SCAN_TIMER_HIGH_REG
);
760 outl(chan_ticks
- 1, dev
->iobase
+ ME4000_AI_CHAN_PRE_TIMER_REG
);
761 outl(chan_ticks
- 1, dev
->iobase
+ ME4000_AI_CHAN_TIMER_REG
);
764 static int ai_write_chanlist(struct comedi_device
*dev
,
765 struct comedi_subdevice
*s
, struct comedi_cmd
*cmd
)
773 for (i
= 0; i
< cmd
->chanlist_len
; i
++) {
774 chan
= CR_CHAN(cmd
->chanlist
[i
]);
775 rang
= CR_RANGE(cmd
->chanlist
[i
]);
776 aref
= CR_AREF(cmd
->chanlist
[i
]);
781 entry
|= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5
;
783 entry
|= ME4000_AI_LIST_RANGE_UNIPOLAR_10
;
785 entry
|= ME4000_AI_LIST_RANGE_BIPOLAR_2_5
;
787 entry
|= ME4000_AI_LIST_RANGE_BIPOLAR_10
;
789 if (aref
== SDF_DIFF
)
790 entry
|= ME4000_AI_LIST_INPUT_DIFFERENTIAL
;
792 entry
|= ME4000_AI_LIST_INPUT_SINGLE_ENDED
;
794 outl(entry
, dev
->iobase
+ ME4000_AI_CHANNEL_LIST_REG
);
800 static int ai_prepare(struct comedi_device
*dev
,
801 struct comedi_subdevice
*s
,
802 struct comedi_cmd
*cmd
,
803 unsigned int init_ticks
,
804 unsigned int scan_ticks
, unsigned int chan_ticks
)
807 unsigned long tmp
= 0;
809 /* Write timer arguments */
810 ai_write_timer(dev
, init_ticks
, scan_ticks
, chan_ticks
);
812 /* Reset control register */
813 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
816 if ((cmd
->start_src
== TRIG_EXT
&&
817 cmd
->scan_begin_src
== TRIG_TIMER
&&
818 cmd
->convert_src
== TRIG_TIMER
) ||
819 (cmd
->start_src
== TRIG_EXT
&&
820 cmd
->scan_begin_src
== TRIG_FOLLOW
&&
821 cmd
->convert_src
== TRIG_TIMER
)) {
822 tmp
= ME4000_AI_CTRL_BIT_MODE_1
|
823 ME4000_AI_CTRL_BIT_CHANNEL_FIFO
|
824 ME4000_AI_CTRL_BIT_DATA_FIFO
;
825 } else if (cmd
->start_src
== TRIG_EXT
&&
826 cmd
->scan_begin_src
== TRIG_EXT
&&
827 cmd
->convert_src
== TRIG_TIMER
) {
828 tmp
= ME4000_AI_CTRL_BIT_MODE_2
|
829 ME4000_AI_CTRL_BIT_CHANNEL_FIFO
|
830 ME4000_AI_CTRL_BIT_DATA_FIFO
;
831 } else if (cmd
->start_src
== TRIG_EXT
&&
832 cmd
->scan_begin_src
== TRIG_EXT
&&
833 cmd
->convert_src
== TRIG_EXT
) {
834 tmp
= ME4000_AI_CTRL_BIT_MODE_0
|
835 ME4000_AI_CTRL_BIT_MODE_1
|
836 ME4000_AI_CTRL_BIT_CHANNEL_FIFO
|
837 ME4000_AI_CTRL_BIT_DATA_FIFO
;
839 tmp
= ME4000_AI_CTRL_BIT_MODE_0
|
840 ME4000_AI_CTRL_BIT_CHANNEL_FIFO
|
841 ME4000_AI_CTRL_BIT_DATA_FIFO
;
845 if (cmd
->stop_src
== TRIG_COUNT
) {
846 outl(cmd
->chanlist_len
* cmd
->stop_arg
,
847 dev
->iobase
+ ME4000_AI_SAMPLE_COUNTER_REG
);
848 tmp
|= ME4000_AI_CTRL_BIT_HF_IRQ
| ME4000_AI_CTRL_BIT_SC_IRQ
;
849 } else if (cmd
->stop_src
== TRIG_NONE
&&
850 cmd
->scan_end_src
== TRIG_COUNT
) {
851 outl(cmd
->scan_end_arg
,
852 dev
->iobase
+ ME4000_AI_SAMPLE_COUNTER_REG
);
853 tmp
|= ME4000_AI_CTRL_BIT_HF_IRQ
| ME4000_AI_CTRL_BIT_SC_IRQ
;
855 tmp
|= ME4000_AI_CTRL_BIT_HF_IRQ
;
858 /* Write the setup to the control register */
859 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
861 /* Write the channel list */
862 ai_write_chanlist(dev
, s
, cmd
);
867 static int me4000_ai_do_cmd(struct comedi_device
*dev
,
868 struct comedi_subdevice
*s
)
871 unsigned int init_ticks
= 0;
872 unsigned int scan_ticks
= 0;
873 unsigned int chan_ticks
= 0;
874 struct comedi_cmd
*cmd
= &s
->async
->cmd
;
876 /* Reset the analog input */
877 err
= me4000_ai_cancel(dev
, s
);
881 /* Round the timer arguments */
882 err
= ai_round_cmd_args(dev
,
883 s
, cmd
, &init_ticks
, &scan_ticks
, &chan_ticks
);
887 /* Prepare the AI for acquisition */
888 err
= ai_prepare(dev
, s
, cmd
, init_ticks
, scan_ticks
, chan_ticks
);
892 /* Start acquistion by dummy read */
893 inl(dev
->iobase
+ ME4000_AI_START_REG
);
898 static int me4000_ai_do_cmd_test(struct comedi_device
*dev
,
899 struct comedi_subdevice
*s
,
900 struct comedi_cmd
*cmd
)
903 unsigned int init_ticks
;
904 unsigned int chan_ticks
;
905 unsigned int scan_ticks
;
908 /* Only rounding flags are implemented */
909 cmd
->flags
&= TRIG_ROUND_NEAREST
| TRIG_ROUND_UP
| TRIG_ROUND_DOWN
;
911 /* Round the timer arguments */
912 ai_round_cmd_args(dev
, s
, cmd
, &init_ticks
, &scan_ticks
, &chan_ticks
);
914 /* Step 1 : check if triggers are trivially valid */
916 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_NOW
| TRIG_EXT
);
917 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
,
918 TRIG_FOLLOW
| TRIG_TIMER
| TRIG_EXT
);
919 err
|= cfc_check_trigger_src(&cmd
->convert_src
, TRIG_TIMER
| TRIG_EXT
);
920 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
,
921 TRIG_NONE
| TRIG_COUNT
);
922 err
|= cfc_check_trigger_src(&cmd
->stop_src
, TRIG_NONE
| TRIG_COUNT
);
927 /* Step 2a : make sure trigger sources are unique */
929 err
|= cfc_check_trigger_is_unique(cmd
->start_src
);
930 err
|= cfc_check_trigger_is_unique(cmd
->scan_begin_src
);
931 err
|= cfc_check_trigger_is_unique(cmd
->convert_src
);
932 err
|= cfc_check_trigger_is_unique(cmd
->scan_end_src
);
933 err
|= cfc_check_trigger_is_unique(cmd
->stop_src
);
935 /* Step 2b : and mutually compatible */
937 if (cmd
->start_src
== TRIG_NOW
&&
938 cmd
->scan_begin_src
== TRIG_TIMER
&&
939 cmd
->convert_src
== TRIG_TIMER
) {
940 } else if (cmd
->start_src
== TRIG_NOW
&&
941 cmd
->scan_begin_src
== TRIG_FOLLOW
&&
942 cmd
->convert_src
== TRIG_TIMER
) {
943 } else if (cmd
->start_src
== TRIG_EXT
&&
944 cmd
->scan_begin_src
== TRIG_TIMER
&&
945 cmd
->convert_src
== TRIG_TIMER
) {
946 } else if (cmd
->start_src
== TRIG_EXT
&&
947 cmd
->scan_begin_src
== TRIG_FOLLOW
&&
948 cmd
->convert_src
== TRIG_TIMER
) {
949 } else if (cmd
->start_src
== TRIG_EXT
&&
950 cmd
->scan_begin_src
== TRIG_EXT
&&
951 cmd
->convert_src
== TRIG_TIMER
) {
952 } else if (cmd
->start_src
== TRIG_EXT
&&
953 cmd
->scan_begin_src
== TRIG_EXT
&&
954 cmd
->convert_src
== TRIG_EXT
) {
959 if (cmd
->stop_src
== TRIG_NONE
&& cmd
->scan_end_src
== TRIG_NONE
) {
960 } else if (cmd
->stop_src
== TRIG_COUNT
&&
961 cmd
->scan_end_src
== TRIG_NONE
) {
962 } else if (cmd
->stop_src
== TRIG_NONE
&&
963 cmd
->scan_end_src
== TRIG_COUNT
) {
964 } else if (cmd
->stop_src
== TRIG_COUNT
&&
965 cmd
->scan_end_src
== TRIG_COUNT
) {
973 /* Step 3: check if arguments are trivially valid */
975 if (cmd
->chanlist_len
< 1) {
976 cmd
->chanlist_len
= 1;
979 if (init_ticks
< 66) {
980 cmd
->start_arg
= 2000;
983 if (scan_ticks
&& scan_ticks
< 67) {
984 cmd
->scan_begin_arg
= 2031;
987 if (chan_ticks
< 66) {
988 cmd
->convert_arg
= 2000;
996 * Stage 4. Check for argument conflicts.
998 if (cmd
->start_src
== TRIG_NOW
&&
999 cmd
->scan_begin_src
== TRIG_TIMER
&&
1000 cmd
->convert_src
== TRIG_TIMER
) {
1002 /* Check timer arguments */
1003 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1004 dev_err(dev
->class_dev
, "Invalid start arg\n");
1005 cmd
->start_arg
= 2000; /* 66 ticks at least */
1008 if (chan_ticks
< ME4000_AI_MIN_TICKS
) {
1009 dev_err(dev
->class_dev
, "Invalid convert arg\n");
1010 cmd
->convert_arg
= 2000; /* 66 ticks at least */
1013 if (scan_ticks
<= cmd
->chanlist_len
* chan_ticks
) {
1014 dev_err(dev
->class_dev
, "Invalid scan end arg\n");
1016 /* At least one tick more */
1017 cmd
->scan_end_arg
= 2000 * cmd
->chanlist_len
+ 31;
1020 } else if (cmd
->start_src
== TRIG_NOW
&&
1021 cmd
->scan_begin_src
== TRIG_FOLLOW
&&
1022 cmd
->convert_src
== TRIG_TIMER
) {
1024 /* Check timer arguments */
1025 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1026 dev_err(dev
->class_dev
, "Invalid start arg\n");
1027 cmd
->start_arg
= 2000; /* 66 ticks at least */
1030 if (chan_ticks
< ME4000_AI_MIN_TICKS
) {
1031 dev_err(dev
->class_dev
, "Invalid convert arg\n");
1032 cmd
->convert_arg
= 2000; /* 66 ticks at least */
1035 } else if (cmd
->start_src
== TRIG_EXT
&&
1036 cmd
->scan_begin_src
== TRIG_TIMER
&&
1037 cmd
->convert_src
== TRIG_TIMER
) {
1039 /* Check timer arguments */
1040 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1041 dev_err(dev
->class_dev
, "Invalid start arg\n");
1042 cmd
->start_arg
= 2000; /* 66 ticks at least */
1045 if (chan_ticks
< ME4000_AI_MIN_TICKS
) {
1046 dev_err(dev
->class_dev
, "Invalid convert arg\n");
1047 cmd
->convert_arg
= 2000; /* 66 ticks at least */
1050 if (scan_ticks
<= cmd
->chanlist_len
* chan_ticks
) {
1051 dev_err(dev
->class_dev
, "Invalid scan end arg\n");
1053 /* At least one tick more */
1054 cmd
->scan_end_arg
= 2000 * cmd
->chanlist_len
+ 31;
1057 } else if (cmd
->start_src
== TRIG_EXT
&&
1058 cmd
->scan_begin_src
== TRIG_FOLLOW
&&
1059 cmd
->convert_src
== TRIG_TIMER
) {
1061 /* Check timer arguments */
1062 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1063 dev_err(dev
->class_dev
, "Invalid start arg\n");
1064 cmd
->start_arg
= 2000; /* 66 ticks at least */
1067 if (chan_ticks
< ME4000_AI_MIN_TICKS
) {
1068 dev_err(dev
->class_dev
, "Invalid convert arg\n");
1069 cmd
->convert_arg
= 2000; /* 66 ticks at least */
1072 } else if (cmd
->start_src
== TRIG_EXT
&&
1073 cmd
->scan_begin_src
== TRIG_EXT
&&
1074 cmd
->convert_src
== TRIG_TIMER
) {
1076 /* Check timer arguments */
1077 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1078 dev_err(dev
->class_dev
, "Invalid start arg\n");
1079 cmd
->start_arg
= 2000; /* 66 ticks at least */
1082 if (chan_ticks
< ME4000_AI_MIN_TICKS
) {
1083 dev_err(dev
->class_dev
, "Invalid convert arg\n");
1084 cmd
->convert_arg
= 2000; /* 66 ticks at least */
1087 } else if (cmd
->start_src
== TRIG_EXT
&&
1088 cmd
->scan_begin_src
== TRIG_EXT
&&
1089 cmd
->convert_src
== TRIG_EXT
) {
1091 /* Check timer arguments */
1092 if (init_ticks
< ME4000_AI_MIN_TICKS
) {
1093 dev_err(dev
->class_dev
, "Invalid start arg\n");
1094 cmd
->start_arg
= 2000; /* 66 ticks at least */
1098 if (cmd
->stop_src
== TRIG_COUNT
) {
1099 if (cmd
->stop_arg
== 0) {
1100 dev_err(dev
->class_dev
, "Invalid stop arg\n");
1105 if (cmd
->scan_end_src
== TRIG_COUNT
) {
1106 if (cmd
->scan_end_arg
== 0) {
1107 dev_err(dev
->class_dev
, "Invalid scan end arg\n");
1108 cmd
->scan_end_arg
= 1;
1117 * Stage 5. Check the channel list.
1119 if (ai_check_chanlist(dev
, s
, cmd
))
1125 static irqreturn_t
me4000_ai_isr(int irq
, void *dev_id
)
1128 struct comedi_device
*dev
= dev_id
;
1129 struct comedi_subdevice
*s
= &dev
->subdevices
[0];
1137 /* Reset all events */
1138 s
->async
->events
= 0;
1140 /* Check if irq number is right */
1141 if (irq
!= dev
->irq
) {
1142 dev_err(dev
->class_dev
, "Incorrect interrupt num: %d\n", irq
);
1146 if (inl(dev
->iobase
+ ME4000_IRQ_STATUS_REG
) &
1147 ME4000_IRQ_STATUS_BIT_AI_HF
) {
1148 /* Read status register to find out what happened */
1149 tmp
= inl(dev
->iobase
+ ME4000_AI_CTRL_REG
);
1151 if (!(tmp
& ME4000_AI_STATUS_BIT_FF_DATA
) &&
1152 !(tmp
& ME4000_AI_STATUS_BIT_HF_DATA
) &&
1153 (tmp
& ME4000_AI_STATUS_BIT_EF_DATA
)) {
1154 c
= ME4000_AI_FIFO_COUNT
;
1157 * FIFO overflow, so stop conversion
1158 * and disable all interrupts
1160 tmp
|= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
;
1161 tmp
&= ~(ME4000_AI_CTRL_BIT_HF_IRQ
|
1162 ME4000_AI_CTRL_BIT_SC_IRQ
);
1163 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1165 s
->async
->events
|= COMEDI_CB_ERROR
| COMEDI_CB_EOA
;
1167 dev_err(dev
->class_dev
, "FIFO overflow\n");
1168 } else if ((tmp
& ME4000_AI_STATUS_BIT_FF_DATA
)
1169 && !(tmp
& ME4000_AI_STATUS_BIT_HF_DATA
)
1170 && (tmp
& ME4000_AI_STATUS_BIT_EF_DATA
)) {
1171 s
->async
->events
|= COMEDI_CB_BLOCK
;
1173 c
= ME4000_AI_FIFO_COUNT
/ 2;
1175 dev_err(dev
->class_dev
,
1176 "Can't determine state of fifo\n");
1180 * Undefined state, so stop conversion
1181 * and disable all interrupts
1183 tmp
|= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
;
1184 tmp
&= ~(ME4000_AI_CTRL_BIT_HF_IRQ
|
1185 ME4000_AI_CTRL_BIT_SC_IRQ
);
1186 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1188 s
->async
->events
|= COMEDI_CB_ERROR
| COMEDI_CB_EOA
;
1190 dev_err(dev
->class_dev
, "Undefined FIFO state\n");
1193 for (i
= 0; i
< c
; i
++) {
1194 /* Read value from data fifo */
1195 lval
= inl(dev
->iobase
+ ME4000_AI_DATA_REG
) & 0xFFFF;
1198 if (!comedi_buf_put(s
->async
, lval
)) {
1200 * Buffer overflow, so stop conversion
1201 * and disable all interrupts
1203 tmp
|= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
;
1204 tmp
&= ~(ME4000_AI_CTRL_BIT_HF_IRQ
|
1205 ME4000_AI_CTRL_BIT_SC_IRQ
);
1206 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1208 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1210 dev_err(dev
->class_dev
, "Buffer overflow\n");
1216 /* Work is done, so reset the interrupt */
1217 tmp
|= ME4000_AI_CTRL_BIT_HF_IRQ_RESET
;
1218 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1219 tmp
&= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET
;
1220 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1223 if (inl(dev
->iobase
+ ME4000_IRQ_STATUS_REG
) &
1224 ME4000_IRQ_STATUS_BIT_SC
) {
1225 s
->async
->events
|= COMEDI_CB_BLOCK
| COMEDI_CB_EOA
;
1228 * Acquisition is complete, so stop
1229 * conversion and disable all interrupts
1231 tmp
= inl(dev
->iobase
+ ME4000_AI_CTRL_REG
);
1232 tmp
|= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP
;
1233 tmp
&= ~(ME4000_AI_CTRL_BIT_HF_IRQ
| ME4000_AI_CTRL_BIT_SC_IRQ
);
1234 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1236 /* Poll data until fifo empty */
1237 while (inl(dev
->iobase
+ ME4000_AI_CTRL_REG
) &
1238 ME4000_AI_STATUS_BIT_EF_DATA
) {
1239 /* Read value from data fifo */
1240 lval
= inl(dev
->iobase
+ ME4000_AI_DATA_REG
) & 0xFFFF;
1243 if (!comedi_buf_put(s
->async
, lval
)) {
1244 dev_err(dev
->class_dev
, "Buffer overflow\n");
1245 s
->async
->events
|= COMEDI_CB_OVERFLOW
;
1250 /* Work is done, so reset the interrupt */
1251 tmp
|= ME4000_AI_CTRL_BIT_SC_IRQ_RESET
;
1252 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1253 tmp
&= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET
;
1254 outl(tmp
, dev
->iobase
+ ME4000_AI_CTRL_REG
);
1257 if (s
->async
->events
)
1258 comedi_event(dev
, s
);
1263 /*=============================================================================
1264 Analog output section
1265 ===========================================================================*/
1267 static int me4000_ao_insn_write(struct comedi_device
*dev
,
1268 struct comedi_subdevice
*s
,
1269 struct comedi_insn
*insn
, unsigned int *data
)
1271 const struct me4000_board
*thisboard
= comedi_board(dev
);
1272 struct me4000_info
*info
= dev
->private;
1273 int chan
= CR_CHAN(insn
->chanspec
);
1274 int rang
= CR_RANGE(insn
->chanspec
);
1275 int aref
= CR_AREF(insn
->chanspec
);
1280 } else if (insn
->n
> 1) {
1281 dev_err(dev
->class_dev
, "Invalid instruction length %d\n",
1286 if (chan
>= thisboard
->ao_nchan
) {
1287 dev_err(dev
->class_dev
, "Invalid channel %d\n", insn
->n
);
1292 dev_err(dev
->class_dev
, "Invalid range %d\n", insn
->n
);
1296 if (aref
!= AREF_GROUND
&& aref
!= AREF_COMMON
) {
1297 dev_err(dev
->class_dev
, "Invalid aref %d\n", insn
->n
);
1301 /* Stop any running conversion */
1302 tmp
= inl(dev
->iobase
+ ME4000_AO_CTRL_REG(chan
));
1303 tmp
|= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP
;
1304 outl(tmp
, dev
->iobase
+ ME4000_AO_CTRL_REG(chan
));
1306 /* Clear control register and set to single mode */
1307 outl(0x0, dev
->iobase
+ ME4000_AO_CTRL_REG(chan
));
1309 /* Write data value */
1310 outl(data
[0], dev
->iobase
+ ME4000_AO_SINGLE_REG(chan
));
1312 /* Store in the mirror */
1313 info
->ao_readback
[chan
] = data
[0];
1318 static int me4000_ao_insn_read(struct comedi_device
*dev
,
1319 struct comedi_subdevice
*s
,
1320 struct comedi_insn
*insn
, unsigned int *data
)
1322 struct me4000_info
*info
= dev
->private;
1323 int chan
= CR_CHAN(insn
->chanspec
);
1327 } else if (insn
->n
> 1) {
1328 dev_err(dev
->class_dev
, "Invalid instruction length\n");
1332 data
[0] = info
->ao_readback
[chan
];
1337 /*=============================================================================
1339 ===========================================================================*/
1341 static int me4000_dio_insn_bits(struct comedi_device
*dev
,
1342 struct comedi_subdevice
*s
,
1343 struct comedi_insn
*insn
, unsigned int *data
)
1346 * The insn data consists of a mask in data[0] and the new data
1347 * in data[1]. The mask defines which bits we are concerning about.
1348 * The new data must be anded with the mask.
1349 * Each channel corresponds to a bit.
1352 /* Check if requested ports are configured for output */
1353 if ((s
->io_bits
& data
[0]) != data
[0])
1356 s
->state
&= ~data
[0];
1357 s
->state
|= data
[0] & data
[1];
1359 /* Write out the new digital output lines */
1360 outl((s
->state
>> 0) & 0xFF,
1361 dev
->iobase
+ ME4000_DIO_PORT_0_REG
);
1362 outl((s
->state
>> 8) & 0xFF,
1363 dev
->iobase
+ ME4000_DIO_PORT_1_REG
);
1364 outl((s
->state
>> 16) & 0xFF,
1365 dev
->iobase
+ ME4000_DIO_PORT_2_REG
);
1366 outl((s
->state
>> 24) & 0xFF,
1367 dev
->iobase
+ ME4000_DIO_PORT_3_REG
);
1370 /* On return, data[1] contains the value of
1371 the digital input and output lines. */
1372 data
[1] = ((inl(dev
->iobase
+ ME4000_DIO_PORT_0_REG
) & 0xFF) << 0) |
1373 ((inl(dev
->iobase
+ ME4000_DIO_PORT_1_REG
) & 0xFF) << 8) |
1374 ((inl(dev
->iobase
+ ME4000_DIO_PORT_2_REG
) & 0xFF) << 16) |
1375 ((inl(dev
->iobase
+ ME4000_DIO_PORT_3_REG
) & 0xFF) << 24);
1380 static int me4000_dio_insn_config(struct comedi_device
*dev
,
1381 struct comedi_subdevice
*s
,
1382 struct comedi_insn
*insn
, unsigned int *data
)
1385 int chan
= CR_CHAN(insn
->chanspec
);
1390 case INSN_CONFIG_DIO_QUERY
:
1392 (s
->io_bits
& (1 << chan
)) ? COMEDI_OUTPUT
: COMEDI_INPUT
;
1394 case INSN_CONFIG_DIO_INPUT
:
1395 case INSN_CONFIG_DIO_OUTPUT
:
1400 * The input or output configuration of each digital line is
1401 * configured by a special insn_config instruction. chanspec
1402 * contains the channel to be changed, and data[0] contains the
1403 * value INSN_CONFIG_DIO_INPUT or INSN_CONFIG_DIO_OUTPUT.
1404 * On the ME-4000 it is only possible to switch port wise (8 bit)
1407 tmp
= inl(dev
->iobase
+ ME4000_DIO_CTRL_REG
);
1409 if (data
[0] == INSN_CONFIG_DIO_OUTPUT
) {
1412 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_0
|
1413 ME4000_DIO_CTRL_BIT_MODE_1
);
1414 tmp
|= ME4000_DIO_CTRL_BIT_MODE_0
;
1415 } else if (chan
< 16) {
1417 * Chech for optoisolated ME-4000 version.
1418 * If one the first port is a fixed output
1419 * port and the second is a fixed input port.
1421 if (!inl(dev
->iobase
+ ME4000_DIO_DIR_REG
))
1424 s
->io_bits
|= 0xFF00;
1425 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_2
|
1426 ME4000_DIO_CTRL_BIT_MODE_3
);
1427 tmp
|= ME4000_DIO_CTRL_BIT_MODE_2
;
1428 } else if (chan
< 24) {
1429 s
->io_bits
|= 0xFF0000;
1430 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_4
|
1431 ME4000_DIO_CTRL_BIT_MODE_5
);
1432 tmp
|= ME4000_DIO_CTRL_BIT_MODE_4
;
1433 } else if (chan
< 32) {
1434 s
->io_bits
|= 0xFF000000;
1435 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_6
|
1436 ME4000_DIO_CTRL_BIT_MODE_7
);
1437 tmp
|= ME4000_DIO_CTRL_BIT_MODE_6
;
1444 * Chech for optoisolated ME-4000 version.
1445 * If one the first port is a fixed output
1446 * port and the second is a fixed input port.
1448 if (!inl(dev
->iobase
+ ME4000_DIO_DIR_REG
))
1451 s
->io_bits
&= ~0xFF;
1452 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_0
|
1453 ME4000_DIO_CTRL_BIT_MODE_1
);
1454 } else if (chan
< 16) {
1455 s
->io_bits
&= ~0xFF00;
1456 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_2
|
1457 ME4000_DIO_CTRL_BIT_MODE_3
);
1458 } else if (chan
< 24) {
1459 s
->io_bits
&= ~0xFF0000;
1460 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_4
|
1461 ME4000_DIO_CTRL_BIT_MODE_5
);
1462 } else if (chan
< 32) {
1463 s
->io_bits
&= ~0xFF000000;
1464 tmp
&= ~(ME4000_DIO_CTRL_BIT_MODE_6
|
1465 ME4000_DIO_CTRL_BIT_MODE_7
);
1471 outl(tmp
, dev
->iobase
+ ME4000_DIO_CTRL_REG
);
1476 /*=============================================================================
1478 ===========================================================================*/
1480 static int me4000_cnt_insn_config(struct comedi_device
*dev
,
1481 struct comedi_subdevice
*s
,
1482 struct comedi_insn
*insn
,
1485 struct me4000_info
*info
= dev
->private;
1493 err
= i8254_load(info
->timer_regbase
, 0, insn
->chanspec
, 0,
1494 I8254_MODE0
| I8254_BINARY
);
1498 case GPCT_SET_OPERATION
:
1502 err
= i8254_set_mode(info
->timer_regbase
, 0, insn
->chanspec
,
1503 (data
[1] << 1) | I8254_BINARY
);
1514 static int me4000_cnt_insn_read(struct comedi_device
*dev
,
1515 struct comedi_subdevice
*s
,
1516 struct comedi_insn
*insn
, unsigned int *data
)
1518 struct me4000_info
*info
= dev
->private;
1524 dev_err(dev
->class_dev
, "Invalid instruction length %d\n",
1529 data
[0] = i8254_read(info
->timer_regbase
, 0, insn
->chanspec
);
1534 static int me4000_cnt_insn_write(struct comedi_device
*dev
,
1535 struct comedi_subdevice
*s
,
1536 struct comedi_insn
*insn
, unsigned int *data
)
1538 struct me4000_info
*info
= dev
->private;
1542 } else if (insn
->n
> 1) {
1543 dev_err(dev
->class_dev
, "Invalid instruction length %d\n",
1548 i8254_write(info
->timer_regbase
, 0, insn
->chanspec
, data
[0]);
1553 static const void *me4000_find_boardinfo(struct comedi_device
*dev
,
1554 struct pci_dev
*pcidev
)
1556 const struct me4000_board
*thisboard
;
1559 for (i
= 0; i
< ARRAY_SIZE(me4000_boards
); i
++) {
1560 thisboard
= &me4000_boards
[i
];
1561 if (thisboard
->device_id
== pcidev
->device
)
1567 static int me4000_auto_attach(struct comedi_device
*dev
,
1568 unsigned long context_unused
)
1570 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1571 const struct me4000_board
*thisboard
;
1572 struct me4000_info
*info
;
1573 struct comedi_subdevice
*s
;
1576 thisboard
= me4000_find_boardinfo(dev
, pcidev
);
1579 dev
->board_ptr
= thisboard
;
1580 dev
->board_name
= thisboard
->name
;
1582 info
= kzalloc(sizeof(*info
), GFP_KERNEL
);
1585 dev
->private = info
;
1587 result
= comedi_pci_enable(pcidev
, dev
->board_name
);
1591 info
->plx_regbase
= pci_resource_start(pcidev
, 1);
1592 dev
->iobase
= pci_resource_start(pcidev
, 2);
1593 info
->timer_regbase
= pci_resource_start(pcidev
, 3);
1594 if (!info
->plx_regbase
|| !dev
->iobase
|| !info
->timer_regbase
)
1597 result
= xilinx_download(dev
);
1603 result
= comedi_alloc_subdevices(dev
, 4);
1607 /*=========================================================================
1608 Analog input subdevice
1609 ========================================================================*/
1611 s
= &dev
->subdevices
[0];
1613 if (thisboard
->ai_nchan
) {
1614 s
->type
= COMEDI_SUBD_AI
;
1616 SDF_READABLE
| SDF_COMMON
| SDF_GROUND
| SDF_DIFF
;
1617 s
->n_chan
= thisboard
->ai_nchan
;
1618 s
->maxdata
= 0xFFFF; /* 16 bit ADC */
1619 s
->len_chanlist
= ME4000_AI_CHANNEL_LIST_COUNT
;
1620 s
->range_table
= &me4000_ai_range
;
1621 s
->insn_read
= me4000_ai_insn_read
;
1623 if (pcidev
->irq
> 0) {
1624 if (request_irq(pcidev
->irq
, me4000_ai_isr
,
1625 IRQF_SHARED
, dev
->board_name
, dev
)) {
1626 dev_warn(dev
->class_dev
,
1627 "request_irq failed\n");
1629 dev
->read_subdev
= s
;
1630 s
->subdev_flags
|= SDF_CMD_READ
;
1631 s
->cancel
= me4000_ai_cancel
;
1632 s
->do_cmdtest
= me4000_ai_do_cmd_test
;
1633 s
->do_cmd
= me4000_ai_do_cmd
;
1635 dev
->irq
= pcidev
->irq
;
1638 dev_warn(dev
->class_dev
, "No interrupt available\n");
1641 s
->type
= COMEDI_SUBD_UNUSED
;
1644 /*=========================================================================
1645 Analog output subdevice
1646 ========================================================================*/
1648 s
= &dev
->subdevices
[1];
1650 if (thisboard
->ao_nchan
) {
1651 s
->type
= COMEDI_SUBD_AO
;
1652 s
->subdev_flags
= SDF_WRITEABLE
| SDF_COMMON
| SDF_GROUND
;
1653 s
->n_chan
= thisboard
->ao_nchan
;
1654 s
->maxdata
= 0xFFFF; /* 16 bit DAC */
1655 s
->range_table
= &range_bipolar10
;
1656 s
->insn_write
= me4000_ao_insn_write
;
1657 s
->insn_read
= me4000_ao_insn_read
;
1659 s
->type
= COMEDI_SUBD_UNUSED
;
1662 /*=========================================================================
1663 Digital I/O subdevice
1664 ========================================================================*/
1666 s
= &dev
->subdevices
[2];
1668 if (thisboard
->dio_nchan
) {
1669 s
->type
= COMEDI_SUBD_DIO
;
1670 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
1671 s
->n_chan
= thisboard
->dio_nchan
;
1673 s
->range_table
= &range_digital
;
1674 s
->insn_bits
= me4000_dio_insn_bits
;
1675 s
->insn_config
= me4000_dio_insn_config
;
1677 s
->type
= COMEDI_SUBD_UNUSED
;
1681 * Check for optoisolated ME-4000 version. If one the first
1682 * port is a fixed output port and the second is a fixed input port.
1684 if (!inl(dev
->iobase
+ ME4000_DIO_DIR_REG
)) {
1686 outl(ME4000_DIO_CTRL_BIT_MODE_0
,
1687 dev
->iobase
+ ME4000_DIO_DIR_REG
);
1690 /*=========================================================================
1692 ========================================================================*/
1694 s
= &dev
->subdevices
[3];
1696 if (thisboard
->has_counter
) {
1697 s
->type
= COMEDI_SUBD_COUNTER
;
1698 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
1700 s
->maxdata
= 0xFFFF; /* 16 bit counters */
1701 s
->insn_read
= me4000_cnt_insn_read
;
1702 s
->insn_write
= me4000_cnt_insn_write
;
1703 s
->insn_config
= me4000_cnt_insn_config
;
1705 s
->type
= COMEDI_SUBD_UNUSED
;
1711 static void me4000_detach(struct comedi_device
*dev
)
1713 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1716 free_irq(dev
->irq
, dev
);
1720 comedi_pci_disable(pcidev
);
1725 static struct comedi_driver me4000_driver
= {
1726 .driver_name
= "me4000",
1727 .module
= THIS_MODULE
,
1728 .auto_attach
= me4000_auto_attach
,
1729 .detach
= me4000_detach
,
1732 static int me4000_pci_probe(struct pci_dev
*dev
,
1733 const struct pci_device_id
*ent
)
1735 return comedi_pci_auto_config(dev
, &me4000_driver
);
1738 static DEFINE_PCI_DEVICE_TABLE(me4000_pci_table
) = {
1739 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4650
)},
1740 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4660
)},
1741 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4660I
)},
1742 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4660S
)},
1743 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4660IS
)},
1744 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4670
)},
1745 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4670I
)},
1746 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4670S
)},
1747 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4670IS
)},
1748 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4680
)},
1749 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4680I
)},
1750 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4680S
)},
1751 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS
, PCI_DEVICE_ID_MEILHAUS_ME4680IS
)},
1754 MODULE_DEVICE_TABLE(pci
, me4000_pci_table
);
1756 static struct pci_driver me4000_pci_driver
= {
1758 .id_table
= me4000_pci_table
,
1759 .probe
= me4000_pci_probe
,
1760 .remove
= comedi_pci_auto_unconfig
,
1762 module_comedi_pci_driver(me4000_driver
, me4000_pci_driver
);
1764 MODULE_AUTHOR("Comedi http://www.comedi.org");
1765 MODULE_DESCRIPTION("Comedi low-level driver");
1766 MODULE_LICENSE("GPL");