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[mirror_ubuntu-eoan-kernel.git] / drivers / staging / comedi / drivers / ni_65xx.c
1 /*
2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
4
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20 */
21 /*
22 Driver: ni_65xx
23 Description: National Instruments 65xx static dio boards
24 Author: Jon Grierson <jd@renko.co.uk>,
25 Frank Mori Hess <fmhess@users.sourceforge.net>
26 Status: testing
27 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
28 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
29 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
30 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
31 Updated: Wed Oct 18 08:59:11 EDT 2006
32
33 Based on the PCI-6527 driver by ds.
34 The interrupt subdevice (subdevice 3) is probably broken for all boards
35 except maybe the 6514.
36
37 */
38
39 /*
40 Manuals (available from ftp://ftp.natinst.com/support/manuals)
41
42 370106b.pdf 6514 Register Level Programmer Manual
43
44 */
45
46 #define DEBUG 1
47 #define DEBUG_FLAGS
48
49 #include <linux/module.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52
53 #include "../comedidev.h"
54
55 #include "comedi_fc.h"
56 #include "mite.h"
57
58 #define NI6514_DIO_SIZE 4096
59 #define NI6514_MITE_SIZE 4096
60
61 #define NI_65XX_MAX_NUM_PORTS 12
62 static const unsigned ni_65xx_channels_per_port = 8;
63 static const unsigned ni_65xx_port_offset = 0x10;
64
65 static inline unsigned Port_Data(unsigned port)
66 {
67 return 0x40 + port * ni_65xx_port_offset;
68 }
69
70 static inline unsigned Port_Select(unsigned port)
71 {
72 return 0x41 + port * ni_65xx_port_offset;
73 }
74
75 static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
76 {
77 return 0x42 + port * ni_65xx_port_offset;
78 }
79
80 static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
81 {
82 return 0x43 + port * ni_65xx_port_offset;
83 }
84
85 static inline unsigned Filter_Enable(unsigned port)
86 {
87 return 0x44 + port * ni_65xx_port_offset;
88 }
89
90 #define ID_Register 0x00
91
92 #define Clear_Register 0x01
93 #define ClrEdge 0x08
94 #define ClrOverflow 0x04
95
96 #define Filter_Interval 0x08
97
98 #define Change_Status 0x02
99 #define MasterInterruptStatus 0x04
100 #define Overflow 0x02
101 #define EdgeStatus 0x01
102
103 #define Master_Interrupt_Control 0x03
104 #define FallingEdgeIntEnable 0x10
105 #define RisingEdgeIntEnable 0x08
106 #define MasterInterruptEnable 0x04
107 #define OverflowIntEnable 0x02
108 #define EdgeIntEnable 0x01
109
110 enum ni_65xx_boardid {
111 BOARD_PCI6509,
112 BOARD_PXI6509,
113 BOARD_PCI6510,
114 BOARD_PCI6511,
115 BOARD_PXI6511,
116 BOARD_PCI6512,
117 BOARD_PXI6512,
118 BOARD_PCI6513,
119 BOARD_PXI6513,
120 BOARD_PCI6514,
121 BOARD_PXI6514,
122 BOARD_PCI6515,
123 BOARD_PXI6515,
124 BOARD_PCI6516,
125 BOARD_PCI6517,
126 BOARD_PCI6518,
127 BOARD_PCI6519,
128 BOARD_PCI6520,
129 BOARD_PCI6521,
130 BOARD_PXI6521,
131 BOARD_PCI6528,
132 BOARD_PXI6528,
133 };
134
135 struct ni_65xx_board {
136 const char *name;
137 unsigned num_dio_ports;
138 unsigned num_di_ports;
139 unsigned num_do_ports;
140 unsigned invert_outputs:1;
141 };
142
143 static const struct ni_65xx_board ni_65xx_boards[] = {
144 [BOARD_PCI6509] = {
145 .name = "pci-6509",
146 .num_dio_ports = 12,
147 },
148 [BOARD_PXI6509] = {
149 .name = "pxi-6509",
150 .num_dio_ports = 12,
151 },
152 [BOARD_PCI6510] = {
153 .name = "pci-6510",
154 .num_di_ports = 4,
155 },
156 [BOARD_PCI6511] = {
157 .name = "pci-6511",
158 .num_di_ports = 8,
159 },
160 [BOARD_PXI6511] = {
161 .name = "pxi-6511",
162 .num_di_ports = 8,
163 },
164 [BOARD_PCI6512] = {
165 .name = "pci-6512",
166 .num_do_ports = 8,
167 },
168 [BOARD_PXI6512] = {
169 .name = "pxi-6512",
170 .num_do_ports = 8,
171 },
172 [BOARD_PCI6513] = {
173 .name = "pci-6513",
174 .num_do_ports = 8,
175 .invert_outputs = 1,
176 },
177 [BOARD_PXI6513] = {
178 .name = "pxi-6513",
179 .num_do_ports = 8,
180 .invert_outputs = 1,
181 },
182 [BOARD_PCI6514] = {
183 .name = "pci-6514",
184 .num_di_ports = 4,
185 .num_do_ports = 4,
186 .invert_outputs = 1,
187 },
188 [BOARD_PXI6514] = {
189 .name = "pxi-6514",
190 .num_di_ports = 4,
191 .num_do_ports = 4,
192 .invert_outputs = 1,
193 },
194 [BOARD_PCI6515] = {
195 .name = "pci-6515",
196 .num_di_ports = 4,
197 .num_do_ports = 4,
198 .invert_outputs = 1,
199 },
200 [BOARD_PXI6515] = {
201 .name = "pxi-6515",
202 .num_di_ports = 4,
203 .num_do_ports = 4,
204 .invert_outputs = 1,
205 },
206 [BOARD_PCI6516] = {
207 .name = "pci-6516",
208 .num_do_ports = 4,
209 .invert_outputs = 1,
210 },
211 [BOARD_PCI6517] = {
212 .name = "pci-6517",
213 .num_do_ports = 4,
214 .invert_outputs = 1,
215 },
216 [BOARD_PCI6518] = {
217 .name = "pci-6518",
218 .num_di_ports = 2,
219 .num_do_ports = 2,
220 .invert_outputs = 1,
221 },
222 [BOARD_PCI6519] = {
223 .name = "pci-6519",
224 .num_di_ports = 2,
225 .num_do_ports = 2,
226 .invert_outputs = 1,
227 },
228 [BOARD_PCI6520] = {
229 .name = "pci-6520",
230 .num_di_ports = 1,
231 .num_do_ports = 1,
232 },
233 [BOARD_PCI6521] = {
234 .name = "pci-6521",
235 .num_di_ports = 1,
236 .num_do_ports = 1,
237 },
238 [BOARD_PXI6521] = {
239 .name = "pxi-6521",
240 .num_di_ports = 1,
241 .num_do_ports = 1,
242 },
243 [BOARD_PCI6528] = {
244 .name = "pci-6528",
245 .num_di_ports = 3,
246 .num_do_ports = 3,
247 },
248 [BOARD_PXI6528] = {
249 .name = "pxi-6528",
250 .num_di_ports = 3,
251 .num_do_ports = 3,
252 },
253 };
254
255 static inline unsigned ni_65xx_port_by_channel(unsigned channel)
256 {
257 return channel / ni_65xx_channels_per_port;
258 }
259
260 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
261 *board)
262 {
263 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
264 }
265
266 struct ni_65xx_private {
267 struct mite_struct *mite;
268 unsigned int filter_interval;
269 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
270 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
271 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
272 };
273
274 struct ni_65xx_subdevice_private {
275 unsigned base_port;
276 };
277
278 static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
279 *subdev)
280 {
281 return subdev->private;
282 }
283
284 static int ni_65xx_config_filter(struct comedi_device *dev,
285 struct comedi_subdevice *s,
286 struct comedi_insn *insn, unsigned int *data)
287 {
288 struct ni_65xx_private *devpriv = dev->private;
289 const unsigned chan = CR_CHAN(insn->chanspec);
290 const unsigned port =
291 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
292
293 if (data[0] != INSN_CONFIG_FILTER)
294 return -EINVAL;
295 if (data[1]) {
296 static const unsigned filter_resolution_ns = 200;
297 static const unsigned max_filter_interval = 0xfffff;
298 unsigned interval =
299 (data[1] +
300 (filter_resolution_ns / 2)) / filter_resolution_ns;
301 if (interval > max_filter_interval)
302 interval = max_filter_interval;
303 data[1] = interval * filter_resolution_ns;
304
305 if (interval != devpriv->filter_interval) {
306 writeb(interval,
307 devpriv->mite->daq_io_addr +
308 Filter_Interval);
309 devpriv->filter_interval = interval;
310 }
311
312 devpriv->filter_enable[port] |=
313 1 << (chan % ni_65xx_channels_per_port);
314 } else {
315 devpriv->filter_enable[port] &=
316 ~(1 << (chan % ni_65xx_channels_per_port));
317 }
318
319 writeb(devpriv->filter_enable[port],
320 devpriv->mite->daq_io_addr + Filter_Enable(port));
321
322 return 2;
323 }
324
325 static int ni_65xx_dio_insn_config(struct comedi_device *dev,
326 struct comedi_subdevice *s,
327 struct comedi_insn *insn, unsigned int *data)
328 {
329 struct ni_65xx_private *devpriv = dev->private;
330 unsigned port;
331
332 if (insn->n < 1)
333 return -EINVAL;
334 port = sprivate(s)->base_port +
335 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
336 switch (data[0]) {
337 case INSN_CONFIG_FILTER:
338 return ni_65xx_config_filter(dev, s, insn, data);
339 break;
340 case INSN_CONFIG_DIO_OUTPUT:
341 if (s->type != COMEDI_SUBD_DIO)
342 return -EINVAL;
343 devpriv->dio_direction[port] = COMEDI_OUTPUT;
344 writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
345 return 1;
346 break;
347 case INSN_CONFIG_DIO_INPUT:
348 if (s->type != COMEDI_SUBD_DIO)
349 return -EINVAL;
350 devpriv->dio_direction[port] = COMEDI_INPUT;
351 writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
352 return 1;
353 break;
354 case INSN_CONFIG_DIO_QUERY:
355 if (s->type != COMEDI_SUBD_DIO)
356 return -EINVAL;
357 data[1] = devpriv->dio_direction[port];
358 return insn->n;
359 break;
360 default:
361 break;
362 }
363 return -EINVAL;
364 }
365
366 static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
367 struct comedi_subdevice *s,
368 struct comedi_insn *insn, unsigned int *data)
369 {
370 const struct ni_65xx_board *board = comedi_board(dev);
371 struct ni_65xx_private *devpriv = dev->private;
372 unsigned base_bitfield_channel;
373 const unsigned max_ports_per_bitfield = 5;
374 unsigned read_bits = 0;
375 unsigned j;
376
377 base_bitfield_channel = CR_CHAN(insn->chanspec);
378 for (j = 0; j < max_ports_per_bitfield; ++j) {
379 const unsigned port_offset =
380 ni_65xx_port_by_channel(base_bitfield_channel) + j;
381 const unsigned port =
382 sprivate(s)->base_port + port_offset;
383 unsigned base_port_channel;
384 unsigned port_mask, port_data, port_read_bits;
385 int bitshift;
386 if (port >= ni_65xx_total_num_ports(board))
387 break;
388 base_port_channel = port_offset * ni_65xx_channels_per_port;
389 port_mask = data[0];
390 port_data = data[1];
391 bitshift = base_port_channel - base_bitfield_channel;
392 if (bitshift >= 32 || bitshift <= -32)
393 break;
394 if (bitshift > 0) {
395 port_mask >>= bitshift;
396 port_data >>= bitshift;
397 } else {
398 port_mask <<= -bitshift;
399 port_data <<= -bitshift;
400 }
401 port_mask &= 0xff;
402 port_data &= 0xff;
403 if (port_mask) {
404 unsigned bits;
405 devpriv->output_bits[port] &= ~port_mask;
406 devpriv->output_bits[port] |=
407 port_data & port_mask;
408 bits = devpriv->output_bits[port];
409 if (board->invert_outputs)
410 bits = ~bits;
411 writeb(bits,
412 devpriv->mite->daq_io_addr +
413 Port_Data(port));
414 }
415 port_read_bits =
416 readb(devpriv->mite->daq_io_addr + Port_Data(port));
417 if (s->type == COMEDI_SUBD_DO && board->invert_outputs) {
418 /* Outputs inverted, so invert value read back from
419 * DO subdevice. (Does not apply to boards with DIO
420 * subdevice.) */
421 port_read_bits ^= 0xFF;
422 }
423 if (bitshift > 0)
424 port_read_bits <<= bitshift;
425 else
426 port_read_bits >>= -bitshift;
427
428 read_bits |= port_read_bits;
429 }
430 data[1] = read_bits;
431 return insn->n;
432 }
433
434 static irqreturn_t ni_65xx_interrupt(int irq, void *d)
435 {
436 struct comedi_device *dev = d;
437 struct ni_65xx_private *devpriv = dev->private;
438 struct comedi_subdevice *s = &dev->subdevices[2];
439 unsigned int status;
440
441 status = readb(devpriv->mite->daq_io_addr + Change_Status);
442 if ((status & MasterInterruptStatus) == 0)
443 return IRQ_NONE;
444 if ((status & EdgeStatus) == 0)
445 return IRQ_NONE;
446
447 writeb(ClrEdge | ClrOverflow,
448 devpriv->mite->daq_io_addr + Clear_Register);
449
450 comedi_buf_put(s->async, 0);
451 s->async->events |= COMEDI_CB_EOS;
452 comedi_event(dev, s);
453 return IRQ_HANDLED;
454 }
455
456 static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
457 struct comedi_subdevice *s,
458 struct comedi_cmd *cmd)
459 {
460 int err = 0;
461
462 /* Step 1 : check if triggers are trivially valid */
463
464 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
465 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
466 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
467 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
468 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
469
470 if (err)
471 return 1;
472
473 /* Step 2a : make sure trigger sources are unique */
474 /* Step 2b : and mutually compatible */
475
476 if (err)
477 return 2;
478
479 /* Step 3: check if arguments are trivially valid */
480
481 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
482 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
483 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
484 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
485 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
486
487 if (err)
488 return 3;
489
490 /* step 4: fix up any arguments */
491
492 if (err)
493 return 4;
494
495 return 0;
496 }
497
498 static int ni_65xx_intr_cmd(struct comedi_device *dev,
499 struct comedi_subdevice *s)
500 {
501 struct ni_65xx_private *devpriv = dev->private;
502 /* struct comedi_cmd *cmd = &s->async->cmd; */
503
504 writeb(ClrEdge | ClrOverflow,
505 devpriv->mite->daq_io_addr + Clear_Register);
506 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
507 MasterInterruptEnable | EdgeIntEnable,
508 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
509
510 return 0;
511 }
512
513 static int ni_65xx_intr_cancel(struct comedi_device *dev,
514 struct comedi_subdevice *s)
515 {
516 struct ni_65xx_private *devpriv = dev->private;
517
518 writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
519
520 return 0;
521 }
522
523 static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
524 struct comedi_subdevice *s,
525 struct comedi_insn *insn, unsigned int *data)
526 {
527 data[1] = 0;
528 return insn->n;
529 }
530
531 static int ni_65xx_intr_insn_config(struct comedi_device *dev,
532 struct comedi_subdevice *s,
533 struct comedi_insn *insn,
534 unsigned int *data)
535 {
536 struct ni_65xx_private *devpriv = dev->private;
537
538 if (insn->n < 1)
539 return -EINVAL;
540 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
541 return -EINVAL;
542
543 writeb(data[1],
544 devpriv->mite->daq_io_addr +
545 Rising_Edge_Detection_Enable(0));
546 writeb(data[1] >> 8,
547 devpriv->mite->daq_io_addr +
548 Rising_Edge_Detection_Enable(0x10));
549 writeb(data[1] >> 16,
550 devpriv->mite->daq_io_addr +
551 Rising_Edge_Detection_Enable(0x20));
552 writeb(data[1] >> 24,
553 devpriv->mite->daq_io_addr +
554 Rising_Edge_Detection_Enable(0x30));
555
556 writeb(data[2],
557 devpriv->mite->daq_io_addr +
558 Falling_Edge_Detection_Enable(0));
559 writeb(data[2] >> 8,
560 devpriv->mite->daq_io_addr +
561 Falling_Edge_Detection_Enable(0x10));
562 writeb(data[2] >> 16,
563 devpriv->mite->daq_io_addr +
564 Falling_Edge_Detection_Enable(0x20));
565 writeb(data[2] >> 24,
566 devpriv->mite->daq_io_addr +
567 Falling_Edge_Detection_Enable(0x30));
568
569 return 2;
570 }
571
572 static int ni_65xx_auto_attach(struct comedi_device *dev,
573 unsigned long context)
574 {
575 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
576 const struct ni_65xx_board *board = NULL;
577 struct ni_65xx_private *devpriv;
578 struct ni_65xx_subdevice_private *spriv;
579 struct comedi_subdevice *s;
580 unsigned i;
581 int ret;
582
583 if (context < ARRAY_SIZE(ni_65xx_boards))
584 board = &ni_65xx_boards[context];
585 if (!board)
586 return -ENODEV;
587 dev->board_ptr = board;
588 dev->board_name = board->name;
589
590 ret = comedi_pci_enable(dev);
591 if (ret)
592 return ret;
593
594 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
595 if (!devpriv)
596 return -ENOMEM;
597
598 devpriv->mite = mite_alloc(pcidev);
599 if (!devpriv->mite)
600 return -ENOMEM;
601
602 ret = mite_setup(devpriv->mite);
603 if (ret < 0) {
604 dev_warn(dev->class_dev, "error setting up mite\n");
605 return ret;
606 }
607
608 dev->irq = mite_irq(devpriv->mite);
609 dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
610 readb(devpriv->mite->daq_io_addr + ID_Register));
611
612 ret = comedi_alloc_subdevices(dev, 4);
613 if (ret)
614 return ret;
615
616 s = &dev->subdevices[0];
617 if (board->num_di_ports) {
618 s->type = COMEDI_SUBD_DI;
619 s->subdev_flags = SDF_READABLE;
620 s->n_chan =
621 board->num_di_ports * ni_65xx_channels_per_port;
622 s->range_table = &range_digital;
623 s->maxdata = 1;
624 s->insn_config = ni_65xx_dio_insn_config;
625 s->insn_bits = ni_65xx_dio_insn_bits;
626 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
627 if (!spriv)
628 return -ENOMEM;
629 spriv->base_port = 0;
630 } else {
631 s->type = COMEDI_SUBD_UNUSED;
632 }
633
634 s = &dev->subdevices[1];
635 if (board->num_do_ports) {
636 s->type = COMEDI_SUBD_DO;
637 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
638 s->n_chan =
639 board->num_do_ports * ni_65xx_channels_per_port;
640 s->range_table = &range_digital;
641 s->maxdata = 1;
642 s->insn_bits = ni_65xx_dio_insn_bits;
643 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
644 if (!spriv)
645 return -ENOMEM;
646 spriv->base_port = board->num_di_ports;
647 } else {
648 s->type = COMEDI_SUBD_UNUSED;
649 }
650
651 s = &dev->subdevices[2];
652 if (board->num_dio_ports) {
653 s->type = COMEDI_SUBD_DIO;
654 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
655 s->n_chan =
656 board->num_dio_ports * ni_65xx_channels_per_port;
657 s->range_table = &range_digital;
658 s->maxdata = 1;
659 s->insn_config = ni_65xx_dio_insn_config;
660 s->insn_bits = ni_65xx_dio_insn_bits;
661 spriv = comedi_alloc_spriv(s, sizeof(*spriv));
662 if (!spriv)
663 return -ENOMEM;
664 spriv->base_port = 0;
665 for (i = 0; i < board->num_dio_ports; ++i) {
666 /* configure all ports for input */
667 writeb(0x1,
668 devpriv->mite->daq_io_addr +
669 Port_Select(i));
670 }
671 } else {
672 s->type = COMEDI_SUBD_UNUSED;
673 }
674
675 s = &dev->subdevices[3];
676 dev->read_subdev = s;
677 s->type = COMEDI_SUBD_DI;
678 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
679 s->n_chan = 1;
680 s->range_table = &range_unknown;
681 s->maxdata = 1;
682 s->do_cmdtest = ni_65xx_intr_cmdtest;
683 s->do_cmd = ni_65xx_intr_cmd;
684 s->cancel = ni_65xx_intr_cancel;
685 s->insn_bits = ni_65xx_intr_insn_bits;
686 s->insn_config = ni_65xx_intr_insn_config;
687
688 for (i = 0; i < ni_65xx_total_num_ports(board); ++i) {
689 writeb(0x00,
690 devpriv->mite->daq_io_addr + Filter_Enable(i));
691 if (board->invert_outputs)
692 writeb(0x01,
693 devpriv->mite->daq_io_addr + Port_Data(i));
694 else
695 writeb(0x00,
696 devpriv->mite->daq_io_addr + Port_Data(i));
697 }
698 writeb(ClrEdge | ClrOverflow,
699 devpriv->mite->daq_io_addr + Clear_Register);
700 writeb(0x00,
701 devpriv->mite->daq_io_addr + Master_Interrupt_Control);
702
703 /* Set filter interval to 0 (32bit reg) */
704 writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
705
706 ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
707 "ni_65xx", dev);
708 if (ret < 0) {
709 dev->irq = 0;
710 dev_warn(dev->class_dev, "irq not available\n");
711 }
712
713 return 0;
714 }
715
716 static void ni_65xx_detach(struct comedi_device *dev)
717 {
718 struct ni_65xx_private *devpriv = dev->private;
719
720 if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
721 writeb(0x00,
722 devpriv->mite->daq_io_addr +
723 Master_Interrupt_Control);
724 }
725 if (dev->irq)
726 free_irq(dev->irq, dev);
727 if (devpriv) {
728 if (devpriv->mite) {
729 mite_unsetup(devpriv->mite);
730 mite_free(devpriv->mite);
731 }
732 }
733 comedi_pci_disable(dev);
734 }
735
736 static struct comedi_driver ni_65xx_driver = {
737 .driver_name = "ni_65xx",
738 .module = THIS_MODULE,
739 .auto_attach = ni_65xx_auto_attach,
740 .detach = ni_65xx_detach,
741 };
742
743 static int ni_65xx_pci_probe(struct pci_dev *dev,
744 const struct pci_device_id *id)
745 {
746 return comedi_pci_auto_config(dev, &ni_65xx_driver, id->driver_data);
747 }
748
749 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
750 { PCI_VDEVICE(NI, 0x1710), BOARD_PXI6509 },
751 { PCI_VDEVICE(NI, 0x7085), BOARD_PCI6509 },
752 { PCI_VDEVICE(NI, 0x7086), BOARD_PXI6528 },
753 { PCI_VDEVICE(NI, 0x7087), BOARD_PCI6515 },
754 { PCI_VDEVICE(NI, 0x7088), BOARD_PCI6514 },
755 { PCI_VDEVICE(NI, 0x70a9), BOARD_PCI6528 },
756 { PCI_VDEVICE(NI, 0x70c3), BOARD_PCI6511 },
757 { PCI_VDEVICE(NI, 0x70c8), BOARD_PCI6513 },
758 { PCI_VDEVICE(NI, 0x70c9), BOARD_PXI6515 },
759 { PCI_VDEVICE(NI, 0x70cc), BOARD_PCI6512 },
760 { PCI_VDEVICE(NI, 0x70cd), BOARD_PXI6514 },
761 { PCI_VDEVICE(NI, 0x70d1), BOARD_PXI6513 },
762 { PCI_VDEVICE(NI, 0x70d2), BOARD_PXI6512 },
763 { PCI_VDEVICE(NI, 0x70d3), BOARD_PXI6511 },
764 { PCI_VDEVICE(NI, 0x7124), BOARD_PCI6510 },
765 { PCI_VDEVICE(NI, 0x7125), BOARD_PCI6516 },
766 { PCI_VDEVICE(NI, 0x7126), BOARD_PCI6517 },
767 { PCI_VDEVICE(NI, 0x7127), BOARD_PCI6518 },
768 { PCI_VDEVICE(NI, 0x7128), BOARD_PCI6519 },
769 { PCI_VDEVICE(NI, 0x718b), BOARD_PCI6521 },
770 { PCI_VDEVICE(NI, 0x718c), BOARD_PXI6521 },
771 { PCI_VDEVICE(NI, 0x71c5), BOARD_PCI6520 },
772 { 0 }
773 };
774 MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
775
776 static struct pci_driver ni_65xx_pci_driver = {
777 .name = "ni_65xx",
778 .id_table = ni_65xx_pci_table,
779 .probe = ni_65xx_pci_probe,
780 .remove = comedi_pci_auto_unconfig,
781 };
782 module_comedi_pci_driver(ni_65xx_driver, ni_65xx_pci_driver);
783
784 MODULE_AUTHOR("Comedi http://www.comedi.org");
785 MODULE_DESCRIPTION("Comedi low-level driver");
786 MODULE_LICENSE("GPL");
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