2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: National Instruments 65xx static dio boards
29 Author: Jon Grierson <jd@renko.co.uk>,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
32 Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510,
33 PCI-6511, PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514,
34 PXI-6514, PCI-6515, PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519,
35 PCI-6520, PCI-6521, PXI-6521, PCI-6528, PXI-6528
36 Updated: Wed Oct 18 08:59:11 EDT 2006
38 Based on the PCI-6527 driver by ds.
39 The interrupt subdevice (subdevice 3) is probably broken for all boards
40 except maybe the 6514.
45 Manuals (available from ftp://ftp.natinst.com/support/manuals)
47 370106b.pdf 6514 Register Level Programmer Manual
54 #include <linux/pci.h>
55 #include <linux/interrupt.h>
56 #include <linux/slab.h>
58 #include "../comedidev.h"
60 #include "comedi_fc.h"
63 #define NI6514_DIO_SIZE 4096
64 #define NI6514_MITE_SIZE 4096
66 #define NI_65XX_MAX_NUM_PORTS 12
67 static const unsigned ni_65xx_channels_per_port
= 8;
68 static const unsigned ni_65xx_port_offset
= 0x10;
70 static inline unsigned Port_Data(unsigned port
)
72 return 0x40 + port
* ni_65xx_port_offset
;
75 static inline unsigned Port_Select(unsigned port
)
77 return 0x41 + port
* ni_65xx_port_offset
;
80 static inline unsigned Rising_Edge_Detection_Enable(unsigned port
)
82 return 0x42 + port
* ni_65xx_port_offset
;
85 static inline unsigned Falling_Edge_Detection_Enable(unsigned port
)
87 return 0x43 + port
* ni_65xx_port_offset
;
90 static inline unsigned Filter_Enable(unsigned port
)
92 return 0x44 + port
* ni_65xx_port_offset
;
95 #define ID_Register 0x00
97 #define Clear_Register 0x01
99 #define ClrOverflow 0x04
101 #define Filter_Interval 0x08
103 #define Change_Status 0x02
104 #define MasterInterruptStatus 0x04
105 #define Overflow 0x02
106 #define EdgeStatus 0x01
108 #define Master_Interrupt_Control 0x03
109 #define FallingEdgeIntEnable 0x10
110 #define RisingEdgeIntEnable 0x08
111 #define MasterInterruptEnable 0x04
112 #define OverflowIntEnable 0x02
113 #define EdgeIntEnable 0x01
115 enum ni_65xx_boardid
{
140 struct ni_65xx_board
{
142 unsigned num_dio_ports
;
143 unsigned num_di_ports
;
144 unsigned num_do_ports
;
145 unsigned invert_outputs
:1;
148 static const struct ni_65xx_board ni_65xx_boards
[] = {
260 static inline unsigned ni_65xx_port_by_channel(unsigned channel
)
262 return channel
/ ni_65xx_channels_per_port
;
265 static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
268 return board
->num_dio_ports
+ board
->num_di_ports
+ board
->num_do_ports
;
271 struct ni_65xx_private
{
272 struct mite_struct
*mite
;
273 unsigned int filter_interval
;
274 unsigned short filter_enable
[NI_65XX_MAX_NUM_PORTS
];
275 unsigned short output_bits
[NI_65XX_MAX_NUM_PORTS
];
276 unsigned short dio_direction
[NI_65XX_MAX_NUM_PORTS
];
279 struct ni_65xx_subdevice_private
{
283 static inline struct ni_65xx_subdevice_private
*sprivate(struct comedi_subdevice
286 return subdev
->private;
289 static struct ni_65xx_subdevice_private
*ni_65xx_alloc_subdevice_private(void)
291 struct ni_65xx_subdevice_private
*subdev_private
=
292 kzalloc(sizeof(struct ni_65xx_subdevice_private
), GFP_KERNEL
);
293 if (subdev_private
== NULL
)
295 return subdev_private
;
298 static int ni_65xx_config_filter(struct comedi_device
*dev
,
299 struct comedi_subdevice
*s
,
300 struct comedi_insn
*insn
, unsigned int *data
)
302 struct ni_65xx_private
*devpriv
= dev
->private;
303 const unsigned chan
= CR_CHAN(insn
->chanspec
);
304 const unsigned port
=
305 sprivate(s
)->base_port
+ ni_65xx_port_by_channel(chan
);
307 if (data
[0] != INSN_CONFIG_FILTER
)
310 static const unsigned filter_resolution_ns
= 200;
311 static const unsigned max_filter_interval
= 0xfffff;
314 (filter_resolution_ns
/ 2)) / filter_resolution_ns
;
315 if (interval
> max_filter_interval
)
316 interval
= max_filter_interval
;
317 data
[1] = interval
* filter_resolution_ns
;
319 if (interval
!= devpriv
->filter_interval
) {
321 devpriv
->mite
->daq_io_addr
+
323 devpriv
->filter_interval
= interval
;
326 devpriv
->filter_enable
[port
] |=
327 1 << (chan
% ni_65xx_channels_per_port
);
329 devpriv
->filter_enable
[port
] &=
330 ~(1 << (chan
% ni_65xx_channels_per_port
));
333 writeb(devpriv
->filter_enable
[port
],
334 devpriv
->mite
->daq_io_addr
+ Filter_Enable(port
));
339 static int ni_65xx_dio_insn_config(struct comedi_device
*dev
,
340 struct comedi_subdevice
*s
,
341 struct comedi_insn
*insn
, unsigned int *data
)
343 struct ni_65xx_private
*devpriv
= dev
->private;
348 port
= sprivate(s
)->base_port
+
349 ni_65xx_port_by_channel(CR_CHAN(insn
->chanspec
));
351 case INSN_CONFIG_FILTER
:
352 return ni_65xx_config_filter(dev
, s
, insn
, data
);
354 case INSN_CONFIG_DIO_OUTPUT
:
355 if (s
->type
!= COMEDI_SUBD_DIO
)
357 devpriv
->dio_direction
[port
] = COMEDI_OUTPUT
;
358 writeb(0, devpriv
->mite
->daq_io_addr
+ Port_Select(port
));
361 case INSN_CONFIG_DIO_INPUT
:
362 if (s
->type
!= COMEDI_SUBD_DIO
)
364 devpriv
->dio_direction
[port
] = COMEDI_INPUT
;
365 writeb(1, devpriv
->mite
->daq_io_addr
+ Port_Select(port
));
368 case INSN_CONFIG_DIO_QUERY
:
369 if (s
->type
!= COMEDI_SUBD_DIO
)
371 data
[1] = devpriv
->dio_direction
[port
];
380 static int ni_65xx_dio_insn_bits(struct comedi_device
*dev
,
381 struct comedi_subdevice
*s
,
382 struct comedi_insn
*insn
, unsigned int *data
)
384 const struct ni_65xx_board
*board
= comedi_board(dev
);
385 struct ni_65xx_private
*devpriv
= dev
->private;
386 unsigned base_bitfield_channel
;
387 const unsigned max_ports_per_bitfield
= 5;
388 unsigned read_bits
= 0;
391 base_bitfield_channel
= CR_CHAN(insn
->chanspec
);
392 for (j
= 0; j
< max_ports_per_bitfield
; ++j
) {
393 const unsigned port_offset
=
394 ni_65xx_port_by_channel(base_bitfield_channel
) + j
;
395 const unsigned port
=
396 sprivate(s
)->base_port
+ port_offset
;
397 unsigned base_port_channel
;
398 unsigned port_mask
, port_data
, port_read_bits
;
400 if (port
>= ni_65xx_total_num_ports(board
))
402 base_port_channel
= port_offset
* ni_65xx_channels_per_port
;
405 bitshift
= base_port_channel
- base_bitfield_channel
;
406 if (bitshift
>= 32 || bitshift
<= -32)
409 port_mask
>>= bitshift
;
410 port_data
>>= bitshift
;
412 port_mask
<<= -bitshift
;
413 port_data
<<= -bitshift
;
419 devpriv
->output_bits
[port
] &= ~port_mask
;
420 devpriv
->output_bits
[port
] |=
421 port_data
& port_mask
;
422 bits
= devpriv
->output_bits
[port
];
423 if (board
->invert_outputs
)
426 devpriv
->mite
->daq_io_addr
+
430 readb(devpriv
->mite
->daq_io_addr
+ Port_Data(port
));
431 if (s
->type
== COMEDI_SUBD_DO
&& board
->invert_outputs
) {
432 /* Outputs inverted, so invert value read back from
433 * DO subdevice. (Does not apply to boards with DIO
435 port_read_bits
^= 0xFF;
438 port_read_bits
<<= bitshift
;
440 port_read_bits
>>= -bitshift
;
442 read_bits
|= port_read_bits
;
448 static irqreturn_t
ni_65xx_interrupt(int irq
, void *d
)
450 struct comedi_device
*dev
= d
;
451 struct ni_65xx_private
*devpriv
= dev
->private;
452 struct comedi_subdevice
*s
= &dev
->subdevices
[2];
455 status
= readb(devpriv
->mite
->daq_io_addr
+ Change_Status
);
456 if ((status
& MasterInterruptStatus
) == 0)
458 if ((status
& EdgeStatus
) == 0)
461 writeb(ClrEdge
| ClrOverflow
,
462 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
464 comedi_buf_put(s
->async
, 0);
465 s
->async
->events
|= COMEDI_CB_EOS
;
466 comedi_event(dev
, s
);
470 static int ni_65xx_intr_cmdtest(struct comedi_device
*dev
,
471 struct comedi_subdevice
*s
,
472 struct comedi_cmd
*cmd
)
476 /* Step 1 : check if triggers are trivially valid */
478 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_NOW
);
479 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
, TRIG_OTHER
);
480 err
|= cfc_check_trigger_src(&cmd
->convert_src
, TRIG_FOLLOW
);
481 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
482 err
|= cfc_check_trigger_src(&cmd
->stop_src
, TRIG_COUNT
);
487 /* Step 2a : make sure trigger sources are unique */
488 /* Step 2b : and mutually compatible */
493 /* Step 3: check if arguments are trivially valid */
495 err
|= cfc_check_trigger_arg_is(&cmd
->start_arg
, 0);
496 err
|= cfc_check_trigger_arg_is(&cmd
->scan_begin_arg
, 0);
497 err
|= cfc_check_trigger_arg_is(&cmd
->convert_arg
, 0);
498 err
|= cfc_check_trigger_arg_is(&cmd
->scan_end_arg
, 1);
499 err
|= cfc_check_trigger_arg_is(&cmd
->stop_arg
, 0);
504 /* step 4: fix up any arguments */
512 static int ni_65xx_intr_cmd(struct comedi_device
*dev
,
513 struct comedi_subdevice
*s
)
515 struct ni_65xx_private
*devpriv
= dev
->private;
516 /* struct comedi_cmd *cmd = &s->async->cmd; */
518 writeb(ClrEdge
| ClrOverflow
,
519 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
520 writeb(FallingEdgeIntEnable
| RisingEdgeIntEnable
|
521 MasterInterruptEnable
| EdgeIntEnable
,
522 devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
527 static int ni_65xx_intr_cancel(struct comedi_device
*dev
,
528 struct comedi_subdevice
*s
)
530 struct ni_65xx_private
*devpriv
= dev
->private;
532 writeb(0x00, devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
537 static int ni_65xx_intr_insn_bits(struct comedi_device
*dev
,
538 struct comedi_subdevice
*s
,
539 struct comedi_insn
*insn
, unsigned int *data
)
545 static int ni_65xx_intr_insn_config(struct comedi_device
*dev
,
546 struct comedi_subdevice
*s
,
547 struct comedi_insn
*insn
,
550 struct ni_65xx_private
*devpriv
= dev
->private;
554 if (data
[0] != INSN_CONFIG_CHANGE_NOTIFY
)
558 devpriv
->mite
->daq_io_addr
+
559 Rising_Edge_Detection_Enable(0));
561 devpriv
->mite
->daq_io_addr
+
562 Rising_Edge_Detection_Enable(0x10));
563 writeb(data
[1] >> 16,
564 devpriv
->mite
->daq_io_addr
+
565 Rising_Edge_Detection_Enable(0x20));
566 writeb(data
[1] >> 24,
567 devpriv
->mite
->daq_io_addr
+
568 Rising_Edge_Detection_Enable(0x30));
571 devpriv
->mite
->daq_io_addr
+
572 Falling_Edge_Detection_Enable(0));
574 devpriv
->mite
->daq_io_addr
+
575 Falling_Edge_Detection_Enable(0x10));
576 writeb(data
[2] >> 16,
577 devpriv
->mite
->daq_io_addr
+
578 Falling_Edge_Detection_Enable(0x20));
579 writeb(data
[2] >> 24,
580 devpriv
->mite
->daq_io_addr
+
581 Falling_Edge_Detection_Enable(0x30));
586 static int ni_65xx_auto_attach(struct comedi_device
*dev
,
587 unsigned long context
)
589 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
590 const struct ni_65xx_board
*board
= NULL
;
591 struct ni_65xx_private
*devpriv
;
592 struct comedi_subdevice
*s
;
596 if (context
< ARRAY_SIZE(ni_65xx_boards
))
597 board
= &ni_65xx_boards
[context
];
600 dev
->board_ptr
= board
;
601 dev
->board_name
= board
->name
;
603 ret
= comedi_pci_enable(dev
);
607 devpriv
= kzalloc(sizeof(*devpriv
), GFP_KERNEL
);
610 dev
->private = devpriv
;
612 devpriv
->mite
= mite_alloc(pcidev
);
616 ret
= mite_setup(devpriv
->mite
);
618 dev_warn(dev
->class_dev
, "error setting up mite\n");
622 dev
->irq
= mite_irq(devpriv
->mite
);
623 dev_info(dev
->class_dev
, "board: %s, ID=0x%02x", dev
->board_name
,
624 readb(devpriv
->mite
->daq_io_addr
+ ID_Register
));
626 ret
= comedi_alloc_subdevices(dev
, 4);
630 s
= &dev
->subdevices
[0];
631 if (board
->num_di_ports
) {
632 s
->type
= COMEDI_SUBD_DI
;
633 s
->subdev_flags
= SDF_READABLE
;
635 board
->num_di_ports
* ni_65xx_channels_per_port
;
636 s
->range_table
= &range_digital
;
638 s
->insn_config
= ni_65xx_dio_insn_config
;
639 s
->insn_bits
= ni_65xx_dio_insn_bits
;
640 s
->private = ni_65xx_alloc_subdevice_private();
641 if (s
->private == NULL
)
643 sprivate(s
)->base_port
= 0;
645 s
->type
= COMEDI_SUBD_UNUSED
;
648 s
= &dev
->subdevices
[1];
649 if (board
->num_do_ports
) {
650 s
->type
= COMEDI_SUBD_DO
;
651 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
653 board
->num_do_ports
* ni_65xx_channels_per_port
;
654 s
->range_table
= &range_digital
;
656 s
->insn_bits
= ni_65xx_dio_insn_bits
;
657 s
->private = ni_65xx_alloc_subdevice_private();
658 if (s
->private == NULL
)
660 sprivate(s
)->base_port
= board
->num_di_ports
;
662 s
->type
= COMEDI_SUBD_UNUSED
;
665 s
= &dev
->subdevices
[2];
666 if (board
->num_dio_ports
) {
667 s
->type
= COMEDI_SUBD_DIO
;
668 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
670 board
->num_dio_ports
* ni_65xx_channels_per_port
;
671 s
->range_table
= &range_digital
;
673 s
->insn_config
= ni_65xx_dio_insn_config
;
674 s
->insn_bits
= ni_65xx_dio_insn_bits
;
675 s
->private = ni_65xx_alloc_subdevice_private();
676 if (s
->private == NULL
)
678 sprivate(s
)->base_port
= 0;
679 for (i
= 0; i
< board
->num_dio_ports
; ++i
) {
680 /* configure all ports for input */
682 devpriv
->mite
->daq_io_addr
+
686 s
->type
= COMEDI_SUBD_UNUSED
;
689 s
= &dev
->subdevices
[3];
690 dev
->read_subdev
= s
;
691 s
->type
= COMEDI_SUBD_DI
;
692 s
->subdev_flags
= SDF_READABLE
| SDF_CMD_READ
;
694 s
->range_table
= &range_unknown
;
696 s
->do_cmdtest
= ni_65xx_intr_cmdtest
;
697 s
->do_cmd
= ni_65xx_intr_cmd
;
698 s
->cancel
= ni_65xx_intr_cancel
;
699 s
->insn_bits
= ni_65xx_intr_insn_bits
;
700 s
->insn_config
= ni_65xx_intr_insn_config
;
702 for (i
= 0; i
< ni_65xx_total_num_ports(board
); ++i
) {
704 devpriv
->mite
->daq_io_addr
+ Filter_Enable(i
));
705 if (board
->invert_outputs
)
707 devpriv
->mite
->daq_io_addr
+ Port_Data(i
));
710 devpriv
->mite
->daq_io_addr
+ Port_Data(i
));
712 writeb(ClrEdge
| ClrOverflow
,
713 devpriv
->mite
->daq_io_addr
+ Clear_Register
);
715 devpriv
->mite
->daq_io_addr
+ Master_Interrupt_Control
);
717 /* Set filter interval to 0 (32bit reg) */
718 writeb(0x00000000, devpriv
->mite
->daq_io_addr
+ Filter_Interval
);
720 ret
= request_irq(dev
->irq
, ni_65xx_interrupt
, IRQF_SHARED
,
724 dev_warn(dev
->class_dev
, "irq not available\n");
730 static void ni_65xx_detach(struct comedi_device
*dev
)
732 struct ni_65xx_private
*devpriv
= dev
->private;
735 if (devpriv
&& devpriv
->mite
&& devpriv
->mite
->daq_io_addr
) {
737 devpriv
->mite
->daq_io_addr
+
738 Master_Interrupt_Control
);
741 free_irq(dev
->irq
, dev
);
742 for (i
= 0; i
< dev
->n_subdevices
; ++i
)
743 comedi_spriv_free(dev
, i
);
746 mite_unsetup(devpriv
->mite
);
747 mite_free(devpriv
->mite
);
750 comedi_pci_disable(dev
);
753 static struct comedi_driver ni_65xx_driver
= {
754 .driver_name
= "ni_65xx",
755 .module
= THIS_MODULE
,
756 .auto_attach
= ni_65xx_auto_attach
,
757 .detach
= ni_65xx_detach
,
760 static int ni_65xx_pci_probe(struct pci_dev
*dev
,
761 const struct pci_device_id
*id
)
763 return comedi_pci_auto_config(dev
, &ni_65xx_driver
, id
->driver_data
);
766 static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table
) = {
767 { PCI_VDEVICE(NI
, 0x1710), BOARD_PXI6509
},
768 { PCI_VDEVICE(NI
, 0x7085), BOARD_PCI6509
},
769 { PCI_VDEVICE(NI
, 0x7086), BOARD_PXI6528
},
770 { PCI_VDEVICE(NI
, 0x7087), BOARD_PCI6515
},
771 { PCI_VDEVICE(NI
, 0x7088), BOARD_PCI6514
},
772 { PCI_VDEVICE(NI
, 0x70a9), BOARD_PCI6528
},
773 { PCI_VDEVICE(NI
, 0x70c3), BOARD_PCI6511
},
774 { PCI_VDEVICE(NI
, 0x70c8), BOARD_PCI6513
},
775 { PCI_VDEVICE(NI
, 0x70c9), BOARD_PXI6515
},
776 { PCI_VDEVICE(NI
, 0x70cc), BOARD_PCI6512
},
777 { PCI_VDEVICE(NI
, 0x70cd), BOARD_PXI6514
},
778 { PCI_VDEVICE(NI
, 0x70d1), BOARD_PXI6513
},
779 { PCI_VDEVICE(NI
, 0x70d2), BOARD_PXI6512
},
780 { PCI_VDEVICE(NI
, 0x70d3), BOARD_PXI6511
},
781 { PCI_VDEVICE(NI
, 0x7124), BOARD_PCI6510
},
782 { PCI_VDEVICE(NI
, 0x7125), BOARD_PCI6516
},
783 { PCI_VDEVICE(NI
, 0x7126), BOARD_PCI6517
},
784 { PCI_VDEVICE(NI
, 0x7127), BOARD_PCI6518
},
785 { PCI_VDEVICE(NI
, 0x7128), BOARD_PCI6519
},
786 { PCI_VDEVICE(NI
, 0x718b), BOARD_PCI6521
},
787 { PCI_VDEVICE(NI
, 0x718c), BOARD_PXI6521
},
788 { PCI_VDEVICE(NI
, 0x71c5), BOARD_PCI6520
},
791 MODULE_DEVICE_TABLE(pci
, ni_65xx_pci_table
);
793 static struct pci_driver ni_65xx_pci_driver
= {
795 .id_table
= ni_65xx_pci_table
,
796 .probe
= ni_65xx_pci_probe
,
797 .remove
= comedi_pci_auto_unconfig
,
799 module_comedi_pci_driver(ni_65xx_driver
, ni_65xx_pci_driver
);
801 MODULE_AUTHOR("Comedi http://www.comedi.org");
802 MODULE_DESCRIPTION("Comedi low-level driver");
803 MODULE_LICENSE("GPL");