2 * Hardware driver for NI 660x devices
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 * Description: National Instruments 660x counter/timer boards
18 * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
19 * PXI-6608, PCI-6624, PXI-6624
20 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
21 * Herman.Bruyninckx@mech.kuleuven.ac.be,
22 * Wim.Meeussen@mech.kuleuven.ac.be,
23 * Klaas.Gadeyne@mech.kuleuven.ac.be,
24 * Frank Mori Hess <fmhess@users.sourceforge.net>
25 * Updated: Mon, 16 Jan 2017 14:00:43 +0000
26 * Status: experimental
28 * Encoders work. PulseGeneration (both single pulse and pulse train)
29 * works. Buffered commands work for input but not output.
32 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
33 * DAQ 6601/6602 User Manual (NI 322137B-01)
36 #include <linux/module.h>
37 #include <linux/interrupt.h>
39 #include "../comedi_pci.h"
44 /* See Register-Level Programmer Manual page 3.1 */
45 enum ni_660x_register
{
46 /* see enum ni_gpct_register */
47 NI660X_STC_DIO_PARALLEL_INPUT
= NITIO_NUM_REGS
,
48 NI660X_STC_DIO_OUTPUT
,
49 NI660X_STC_DIO_CONTROL
,
50 NI660X_STC_DIO_SERIAL_INPUT
,
54 NI660X_GLOBAL_INT_STATUS
,
56 NI660X_GLOBAL_INT_CFG
,
80 #define NI660X_CLK_CFG_COUNTER_SWAP BIT(21)
82 #define NI660X_GLOBAL_INT_COUNTER0 BIT(8)
83 #define NI660X_GLOBAL_INT_COUNTER1 BIT(9)
84 #define NI660X_GLOBAL_INT_COUNTER2 BIT(10)
85 #define NI660X_GLOBAL_INT_COUNTER3 BIT(11)
86 #define NI660X_GLOBAL_INT_CASCADE BIT(29)
87 #define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30)
88 #define NI660X_GLOBAL_INT_GLOBAL BIT(31)
90 #define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c)))
91 #define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
92 #define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
93 #define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80)
95 #define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2))
96 #define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
97 #define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
98 #define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12))
99 #define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7)
101 struct ni_660x_register_data
{
102 int offset
; /* Offset from base address from GPCT chip */
103 char size
; /* 2 or 4 bytes */
106 static const struct ni_660x_register_data ni_660x_reg_data
[NI660X_NUM_REGS
] = {
107 [NITIO_G0_INT_ACK
] = { 0x004, 2 }, /* write */
108 [NITIO_G0_STATUS
] = { 0x004, 2 }, /* read */
109 [NITIO_G1_INT_ACK
] = { 0x006, 2 }, /* write */
110 [NITIO_G1_STATUS
] = { 0x006, 2 }, /* read */
111 [NITIO_G01_STATUS
] = { 0x008, 2 }, /* read */
112 [NITIO_G0_CMD
] = { 0x00c, 2 }, /* write */
113 [NI660X_STC_DIO_PARALLEL_INPUT
] = { 0x00e, 2 }, /* read */
114 [NITIO_G1_CMD
] = { 0x00e, 2 }, /* write */
115 [NITIO_G0_HW_SAVE
] = { 0x010, 4 }, /* read */
116 [NITIO_G1_HW_SAVE
] = { 0x014, 4 }, /* read */
117 [NI660X_STC_DIO_OUTPUT
] = { 0x014, 2 }, /* write */
118 [NI660X_STC_DIO_CONTROL
] = { 0x016, 2 }, /* write */
119 [NITIO_G0_SW_SAVE
] = { 0x018, 4 }, /* read */
120 [NITIO_G1_SW_SAVE
] = { 0x01c, 4 }, /* read */
121 [NITIO_G0_MODE
] = { 0x034, 2 }, /* write */
122 [NITIO_G01_STATUS1
] = { 0x036, 2 }, /* read */
123 [NITIO_G1_MODE
] = { 0x036, 2 }, /* write */
124 [NI660X_STC_DIO_SERIAL_INPUT
] = { 0x038, 2 }, /* read */
125 [NITIO_G0_LOADA
] = { 0x038, 4 }, /* write */
126 [NITIO_G01_STATUS2
] = { 0x03a, 2 }, /* read */
127 [NITIO_G0_LOADB
] = { 0x03c, 4 }, /* write */
128 [NITIO_G1_LOADA
] = { 0x040, 4 }, /* write */
129 [NITIO_G1_LOADB
] = { 0x044, 4 }, /* write */
130 [NITIO_G0_INPUT_SEL
] = { 0x048, 2 }, /* write */
131 [NITIO_G1_INPUT_SEL
] = { 0x04a, 2 }, /* write */
132 [NITIO_G0_AUTO_INC
] = { 0x088, 2 }, /* write */
133 [NITIO_G1_AUTO_INC
] = { 0x08a, 2 }, /* write */
134 [NITIO_G01_RESET
] = { 0x090, 2 }, /* write */
135 [NITIO_G0_INT_ENA
] = { 0x092, 2 }, /* write */
136 [NITIO_G1_INT_ENA
] = { 0x096, 2 }, /* write */
137 [NITIO_G0_CNT_MODE
] = { 0x0b0, 2 }, /* write */
138 [NITIO_G1_CNT_MODE
] = { 0x0b2, 2 }, /* write */
139 [NITIO_G0_GATE2
] = { 0x0b4, 2 }, /* write */
140 [NITIO_G1_GATE2
] = { 0x0b6, 2 }, /* write */
141 [NITIO_G0_DMA_CFG
] = { 0x0b8, 2 }, /* write */
142 [NITIO_G0_DMA_STATUS
] = { 0x0b8, 2 }, /* read */
143 [NITIO_G1_DMA_CFG
] = { 0x0ba, 2 }, /* write */
144 [NITIO_G1_DMA_STATUS
] = { 0x0ba, 2 }, /* read */
145 [NITIO_G2_INT_ACK
] = { 0x104, 2 }, /* write */
146 [NITIO_G2_STATUS
] = { 0x104, 2 }, /* read */
147 [NITIO_G3_INT_ACK
] = { 0x106, 2 }, /* write */
148 [NITIO_G3_STATUS
] = { 0x106, 2 }, /* read */
149 [NITIO_G23_STATUS
] = { 0x108, 2 }, /* read */
150 [NITIO_G2_CMD
] = { 0x10c, 2 }, /* write */
151 [NITIO_G3_CMD
] = { 0x10e, 2 }, /* write */
152 [NITIO_G2_HW_SAVE
] = { 0x110, 4 }, /* read */
153 [NITIO_G3_HW_SAVE
] = { 0x114, 4 }, /* read */
154 [NITIO_G2_SW_SAVE
] = { 0x118, 4 }, /* read */
155 [NITIO_G3_SW_SAVE
] = { 0x11c, 4 }, /* read */
156 [NITIO_G2_MODE
] = { 0x134, 2 }, /* write */
157 [NITIO_G23_STATUS1
] = { 0x136, 2 }, /* read */
158 [NITIO_G3_MODE
] = { 0x136, 2 }, /* write */
159 [NITIO_G2_LOADA
] = { 0x138, 4 }, /* write */
160 [NITIO_G23_STATUS2
] = { 0x13a, 2 }, /* read */
161 [NITIO_G2_LOADB
] = { 0x13c, 4 }, /* write */
162 [NITIO_G3_LOADA
] = { 0x140, 4 }, /* write */
163 [NITIO_G3_LOADB
] = { 0x144, 4 }, /* write */
164 [NITIO_G2_INPUT_SEL
] = { 0x148, 2 }, /* write */
165 [NITIO_G3_INPUT_SEL
] = { 0x14a, 2 }, /* write */
166 [NITIO_G2_AUTO_INC
] = { 0x188, 2 }, /* write */
167 [NITIO_G3_AUTO_INC
] = { 0x18a, 2 }, /* write */
168 [NITIO_G23_RESET
] = { 0x190, 2 }, /* write */
169 [NITIO_G2_INT_ENA
] = { 0x192, 2 }, /* write */
170 [NITIO_G3_INT_ENA
] = { 0x196, 2 }, /* write */
171 [NITIO_G2_CNT_MODE
] = { 0x1b0, 2 }, /* write */
172 [NITIO_G3_CNT_MODE
] = { 0x1b2, 2 }, /* write */
173 [NITIO_G2_GATE2
] = { 0x1b4, 2 }, /* write */
174 [NITIO_G3_GATE2
] = { 0x1b6, 2 }, /* write */
175 [NITIO_G2_DMA_CFG
] = { 0x1b8, 2 }, /* write */
176 [NITIO_G2_DMA_STATUS
] = { 0x1b8, 2 }, /* read */
177 [NITIO_G3_DMA_CFG
] = { 0x1ba, 2 }, /* write */
178 [NITIO_G3_DMA_STATUS
] = { 0x1ba, 2 }, /* read */
179 [NI660X_DIO32_INPUT
] = { 0x414, 4 }, /* read */
180 [NI660X_DIO32_OUTPUT
] = { 0x510, 4 }, /* write */
181 [NI660X_CLK_CFG
] = { 0x73c, 4 }, /* write */
182 [NI660X_GLOBAL_INT_STATUS
] = { 0x754, 4 }, /* read */
183 [NI660X_DMA_CFG
] = { 0x76c, 4 }, /* write */
184 [NI660X_GLOBAL_INT_CFG
] = { 0x770, 4 }, /* write */
185 [NI660X_IO_CFG_0_1
] = { 0x77c, 2 }, /* read/write */
186 [NI660X_IO_CFG_2_3
] = { 0x77e, 2 }, /* read/write */
187 [NI660X_IO_CFG_4_5
] = { 0x780, 2 }, /* read/write */
188 [NI660X_IO_CFG_6_7
] = { 0x782, 2 }, /* read/write */
189 [NI660X_IO_CFG_8_9
] = { 0x784, 2 }, /* read/write */
190 [NI660X_IO_CFG_10_11
] = { 0x786, 2 }, /* read/write */
191 [NI660X_IO_CFG_12_13
] = { 0x788, 2 }, /* read/write */
192 [NI660X_IO_CFG_14_15
] = { 0x78a, 2 }, /* read/write */
193 [NI660X_IO_CFG_16_17
] = { 0x78c, 2 }, /* read/write */
194 [NI660X_IO_CFG_18_19
] = { 0x78e, 2 }, /* read/write */
195 [NI660X_IO_CFG_20_21
] = { 0x790, 2 }, /* read/write */
196 [NI660X_IO_CFG_22_23
] = { 0x792, 2 }, /* read/write */
197 [NI660X_IO_CFG_24_25
] = { 0x794, 2 }, /* read/write */
198 [NI660X_IO_CFG_26_27
] = { 0x796, 2 }, /* read/write */
199 [NI660X_IO_CFG_28_29
] = { 0x798, 2 }, /* read/write */
200 [NI660X_IO_CFG_30_31
] = { 0x79a, 2 }, /* read/write */
201 [NI660X_IO_CFG_32_33
] = { 0x79c, 2 }, /* read/write */
202 [NI660X_IO_CFG_34_35
] = { 0x79e, 2 }, /* read/write */
203 [NI660X_IO_CFG_36_37
] = { 0x7a0, 2 }, /* read/write */
204 [NI660X_IO_CFG_38_39
] = { 0x7a2, 2 } /* read/write */
207 #define NI660X_CHIP_OFFSET 0x800
209 enum ni_660x_boardid
{
218 struct ni_660x_board
{
220 unsigned int n_chips
; /* total number of TIO chips */
223 static const struct ni_660x_board ni_660x_boards
[] = {
250 #define NI660X_NUM_PFI_CHANNELS 40
252 /* there are only up to 3 dma channels, but the register layout allows for 4 */
253 #define NI660X_MAX_DMA_CHANNEL 4
255 #define NI660X_COUNTERS_PER_CHIP 4
256 #define NI660X_MAX_CHIPS 2
257 #define NI660X_MAX_COUNTERS (NI660X_MAX_CHIPS * \
258 NI660X_COUNTERS_PER_CHIP)
260 struct ni_660x_private
{
262 struct ni_gpct_device
*counter_dev
;
263 struct mite_ring
*ring
[NI660X_MAX_CHIPS
][NI660X_COUNTERS_PER_CHIP
];
264 /* protects mite channel request/release */
265 spinlock_t mite_channel_lock
;
266 /* prevents races between interrupt and comedi_poll */
267 spinlock_t interrupt_lock
;
268 unsigned int dma_cfg
[NI660X_MAX_CHIPS
];
269 unsigned int io_cfg
[NI660X_NUM_PFI_CHANNELS
];
273 static void ni_660x_write(struct comedi_device
*dev
, unsigned int chip
,
274 unsigned int bits
, unsigned int reg
)
276 unsigned int addr
= (chip
* NI660X_CHIP_OFFSET
) +
277 ni_660x_reg_data
[reg
].offset
;
279 if (ni_660x_reg_data
[reg
].size
== 2)
280 writew(bits
, dev
->mmio
+ addr
);
282 writel(bits
, dev
->mmio
+ addr
);
285 static unsigned int ni_660x_read(struct comedi_device
*dev
,
286 unsigned int chip
, unsigned int reg
)
288 unsigned int addr
= (chip
* NI660X_CHIP_OFFSET
) +
289 ni_660x_reg_data
[reg
].offset
;
291 if (ni_660x_reg_data
[reg
].size
== 2)
292 return readw(dev
->mmio
+ addr
);
293 return readl(dev
->mmio
+ addr
);
296 static void ni_660x_gpct_write(struct ni_gpct
*counter
, unsigned int bits
,
297 enum ni_gpct_register reg
)
299 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
301 ni_660x_write(dev
, counter
->chip_index
, bits
, reg
);
304 static unsigned int ni_660x_gpct_read(struct ni_gpct
*counter
,
305 enum ni_gpct_register reg
)
307 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
309 return ni_660x_read(dev
, counter
->chip_index
, reg
);
312 static inline void ni_660x_set_dma_channel(struct comedi_device
*dev
,
313 unsigned int mite_channel
,
314 struct ni_gpct
*counter
)
316 struct ni_660x_private
*devpriv
= dev
->private;
317 unsigned int chip
= counter
->chip_index
;
319 devpriv
->dma_cfg
[chip
] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel
);
320 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL(mite_channel
,
321 counter
->counter_index
);
322 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
] |
323 NI660X_DMA_CFG_RESET(mite_channel
),
328 static inline void ni_660x_unset_dma_channel(struct comedi_device
*dev
,
329 unsigned int mite_channel
,
330 struct ni_gpct
*counter
)
332 struct ni_660x_private
*devpriv
= dev
->private;
333 unsigned int chip
= counter
->chip_index
;
335 devpriv
->dma_cfg
[chip
] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel
);
336 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL_NONE(mite_channel
);
337 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
], NI660X_DMA_CFG
);
341 static int ni_660x_request_mite_channel(struct comedi_device
*dev
,
342 struct ni_gpct
*counter
,
343 enum comedi_io_direction direction
)
345 struct ni_660x_private
*devpriv
= dev
->private;
346 struct mite_ring
*ring
;
347 struct mite_channel
*mite_chan
;
350 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
351 ring
= devpriv
->ring
[counter
->chip_index
][counter
->counter_index
];
352 mite_chan
= mite_request_channel(devpriv
->mite
, ring
);
354 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
355 dev_err(dev
->class_dev
,
356 "failed to reserve mite dma channel for counter\n");
359 mite_chan
->dir
= direction
;
360 ni_tio_set_mite_channel(counter
, mite_chan
);
361 ni_660x_set_dma_channel(dev
, mite_chan
->channel
, counter
);
362 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
366 static void ni_660x_release_mite_channel(struct comedi_device
*dev
,
367 struct ni_gpct
*counter
)
369 struct ni_660x_private
*devpriv
= dev
->private;
372 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
373 if (counter
->mite_chan
) {
374 struct mite_channel
*mite_chan
= counter
->mite_chan
;
376 ni_660x_unset_dma_channel(dev
, mite_chan
->channel
, counter
);
377 ni_tio_set_mite_channel(counter
, NULL
);
378 mite_release_channel(mite_chan
);
380 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
383 static int ni_660x_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
385 struct ni_gpct
*counter
= s
->private;
388 retval
= ni_660x_request_mite_channel(dev
, counter
, COMEDI_INPUT
);
390 dev_err(dev
->class_dev
,
391 "no dma channel available for use by counter\n");
394 ni_tio_acknowledge(counter
);
396 return ni_tio_cmd(dev
, s
);
399 static int ni_660x_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
401 struct ni_gpct
*counter
= s
->private;
404 retval
= ni_tio_cancel(counter
);
405 ni_660x_release_mite_channel(dev
, counter
);
409 static void set_tio_counterswap(struct comedi_device
*dev
, int chip
)
411 unsigned int bits
= 0;
414 * See P. 3.5 of the Register-Level Programming manual.
415 * The CounterSwap bit has to be set on the second chip,
416 * otherwise it will try to use the same pins as the
420 bits
= NI660X_CLK_CFG_COUNTER_SWAP
;
422 ni_660x_write(dev
, chip
, bits
, NI660X_CLK_CFG
);
425 static void ni_660x_handle_gpct_interrupt(struct comedi_device
*dev
,
426 struct comedi_subdevice
*s
)
428 struct ni_gpct
*counter
= s
->private;
430 ni_tio_handle_interrupt(counter
, s
);
431 comedi_handle_events(dev
, s
);
434 static irqreturn_t
ni_660x_interrupt(int irq
, void *d
)
436 struct comedi_device
*dev
= d
;
437 struct ni_660x_private
*devpriv
= dev
->private;
438 struct comedi_subdevice
*s
;
444 /* make sure dev->attached is checked before doing anything else */
447 /* lock to avoid race with comedi_poll */
448 spin_lock_irqsave(&devpriv
->interrupt_lock
, flags
);
449 for (i
= 0; i
< dev
->n_subdevices
; ++i
) {
450 s
= &dev
->subdevices
[i
];
451 if (s
->type
== COMEDI_SUBD_COUNTER
)
452 ni_660x_handle_gpct_interrupt(dev
, s
);
454 spin_unlock_irqrestore(&devpriv
->interrupt_lock
, flags
);
458 static int ni_660x_input_poll(struct comedi_device
*dev
,
459 struct comedi_subdevice
*s
)
461 struct ni_660x_private
*devpriv
= dev
->private;
462 struct ni_gpct
*counter
= s
->private;
465 /* lock to avoid race with comedi_poll */
466 spin_lock_irqsave(&devpriv
->interrupt_lock
, flags
);
467 mite_sync_dma(counter
->mite_chan
, s
);
468 spin_unlock_irqrestore(&devpriv
->interrupt_lock
, flags
);
469 return comedi_buf_read_n_available(s
);
472 static int ni_660x_buf_change(struct comedi_device
*dev
,
473 struct comedi_subdevice
*s
)
475 struct ni_660x_private
*devpriv
= dev
->private;
476 struct ni_gpct
*counter
= s
->private;
477 struct mite_ring
*ring
;
480 ring
= devpriv
->ring
[counter
->chip_index
][counter
->counter_index
];
481 ret
= mite_buf_change(ring
, s
);
488 static int ni_660x_allocate_private(struct comedi_device
*dev
)
490 struct ni_660x_private
*devpriv
;
493 devpriv
= comedi_alloc_devpriv(dev
, sizeof(*devpriv
));
497 spin_lock_init(&devpriv
->mite_channel_lock
);
498 spin_lock_init(&devpriv
->interrupt_lock
);
499 for (i
= 0; i
< NI660X_NUM_PFI_CHANNELS
; ++i
)
500 devpriv
->io_cfg
[i
] = NI_660X_PFI_OUTPUT_COUNTER
;
505 static int ni_660x_alloc_mite_rings(struct comedi_device
*dev
)
507 const struct ni_660x_board
*board
= dev
->board_ptr
;
508 struct ni_660x_private
*devpriv
= dev
->private;
512 for (i
= 0; i
< board
->n_chips
; ++i
) {
513 for (j
= 0; j
< NI660X_COUNTERS_PER_CHIP
; ++j
) {
514 devpriv
->ring
[i
][j
] = mite_alloc_ring(devpriv
->mite
);
515 if (!devpriv
->ring
[i
][j
])
522 static void ni_660x_free_mite_rings(struct comedi_device
*dev
)
524 const struct ni_660x_board
*board
= dev
->board_ptr
;
525 struct ni_660x_private
*devpriv
= dev
->private;
529 for (i
= 0; i
< board
->n_chips
; ++i
) {
530 for (j
= 0; j
< NI660X_COUNTERS_PER_CHIP
; ++j
)
531 mite_free_ring(devpriv
->ring
[i
][j
]);
535 static int ni_660x_dio_insn_bits(struct comedi_device
*dev
,
536 struct comedi_subdevice
*s
,
537 struct comedi_insn
*insn
,
540 unsigned int shift
= CR_CHAN(insn
->chanspec
);
541 unsigned int mask
= data
[0] << shift
;
542 unsigned int bits
= data
[1] << shift
;
545 * There are 40 channels in this subdevice but only 32 are usable
546 * as DIO. The shift adjusts the mask/bits to account for the base
547 * channel in insn->chanspec. The state update can then be handled
548 * normally for the 32 usable channels.
552 s
->state
|= (bits
& mask
);
553 ni_660x_write(dev
, 0, s
->state
, NI660X_DIO32_OUTPUT
);
557 * Return the input channels, shifted back to account for the base
560 data
[1] = ni_660x_read(dev
, 0, NI660X_DIO32_INPUT
) >> shift
;
565 static void ni_660x_select_pfi_output(struct comedi_device
*dev
,
566 unsigned int chan
, unsigned int out_sel
)
568 const struct ni_660x_board
*board
= dev
->board_ptr
;
569 unsigned int active_chip
= 0;
570 unsigned int idle_chip
= 0;
573 if (board
->n_chips
> 1) {
574 if (out_sel
== NI_660X_PFI_OUTPUT_COUNTER
&&
575 chan
>= 8 && chan
<= 23) {
576 /* counters 4-7 pfi channels */
580 /* counters 0-3 pfi channels */
586 if (idle_chip
!= active_chip
) {
587 /* set the pfi channel to high-z on the inactive chip */
588 bits
= ni_660x_read(dev
, idle_chip
, NI660X_IO_CFG(chan
));
589 bits
&= ~NI660X_IO_CFG_OUT_SEL_MASK(chan
);
590 bits
|= NI660X_IO_CFG_OUT_SEL(chan
, 0); /* high-z */
591 ni_660x_write(dev
, idle_chip
, bits
, NI660X_IO_CFG(chan
));
594 /* set the pfi channel output on the active chip */
595 bits
= ni_660x_read(dev
, active_chip
, NI660X_IO_CFG(chan
));
596 bits
&= ~NI660X_IO_CFG_OUT_SEL_MASK(chan
);
597 bits
|= NI660X_IO_CFG_OUT_SEL(chan
, out_sel
);
598 ni_660x_write(dev
, active_chip
, bits
, NI660X_IO_CFG(chan
));
601 static int ni_660x_set_pfi_routing(struct comedi_device
*dev
,
602 unsigned int chan
, unsigned int source
)
604 struct ni_660x_private
*devpriv
= dev
->private;
607 case NI_660X_PFI_OUTPUT_COUNTER
:
611 case NI_660X_PFI_OUTPUT_DIO
:
619 devpriv
->io_cfg
[chan
] = source
;
620 if (devpriv
->io_dir
& (1ULL << chan
))
621 ni_660x_select_pfi_output(dev
, chan
, devpriv
->io_cfg
[chan
]);
625 static int ni_660x_dio_insn_config(struct comedi_device
*dev
,
626 struct comedi_subdevice
*s
,
627 struct comedi_insn
*insn
,
630 struct ni_660x_private
*devpriv
= dev
->private;
631 unsigned int chan
= CR_CHAN(insn
->chanspec
);
632 u64 bit
= 1ULL << chan
;
637 case INSN_CONFIG_DIO_OUTPUT
:
638 devpriv
->io_dir
|= bit
;
639 ni_660x_select_pfi_output(dev
, chan
, devpriv
->io_cfg
[chan
]);
642 case INSN_CONFIG_DIO_INPUT
:
643 devpriv
->io_dir
&= ~bit
;
644 ni_660x_select_pfi_output(dev
, chan
, 0); /* high-z */
647 case INSN_CONFIG_DIO_QUERY
:
648 data
[1] = (devpriv
->io_dir
& bit
) ? COMEDI_OUTPUT
652 case INSN_CONFIG_SET_ROUTING
:
653 ret
= ni_660x_set_pfi_routing(dev
, chan
, data
[1]);
658 case INSN_CONFIG_GET_ROUTING
:
659 data
[1] = devpriv
->io_cfg
[chan
];
662 case INSN_CONFIG_FILTER
:
663 val
= ni_660x_read(dev
, 0, NI660X_IO_CFG(chan
));
664 val
&= ~NI660X_IO_CFG_IN_SEL_MASK(chan
);
665 val
|= NI660X_IO_CFG_IN_SEL(chan
, data
[1]);
666 ni_660x_write(dev
, 0, val
, NI660X_IO_CFG(chan
));
676 static void ni_660x_init_tio_chips(struct comedi_device
*dev
,
677 unsigned int n_chips
)
679 struct ni_660x_private
*devpriv
= dev
->private;
684 * We use the ioconfig registers to control dio direction, so zero
685 * output enables in stc dio control reg.
687 ni_660x_write(dev
, 0, 0, NI660X_STC_DIO_CONTROL
);
689 for (chip
= 0; chip
< n_chips
; ++chip
) {
690 /* init dma configuration register */
691 devpriv
->dma_cfg
[chip
] = 0;
692 for (chan
= 0; chan
< NI660X_MAX_DMA_CHANNEL
; ++chan
)
693 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL_NONE(chan
);
694 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
],
697 /* init ioconfig registers */
698 for (chan
= 0; chan
< NI660X_NUM_PFI_CHANNELS
; ++chan
)
699 ni_660x_write(dev
, chip
, 0, NI660X_IO_CFG(chan
));
703 static int ni_660x_auto_attach(struct comedi_device
*dev
,
704 unsigned long context
)
706 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
707 const struct ni_660x_board
*board
= NULL
;
708 struct ni_660x_private
*devpriv
;
709 struct comedi_subdevice
*s
;
710 struct ni_gpct_device
*gpct_dev
;
711 unsigned int n_counters
;
715 unsigned int global_interrupt_config_bits
;
717 if (context
< ARRAY_SIZE(ni_660x_boards
))
718 board
= &ni_660x_boards
[context
];
721 dev
->board_ptr
= board
;
722 dev
->board_name
= board
->name
;
724 ret
= comedi_pci_enable(dev
);
728 ret
= ni_660x_allocate_private(dev
);
731 devpriv
= dev
->private;
733 devpriv
->mite
= mite_attach(dev
, true); /* use win1 */
737 ret
= ni_660x_alloc_mite_rings(dev
);
741 ni_660x_init_tio_chips(dev
, board
->n_chips
);
743 n_counters
= board
->n_chips
* NI660X_COUNTERS_PER_CHIP
;
744 gpct_dev
= ni_gpct_device_construct(dev
,
747 ni_gpct_variant_660x
,
751 devpriv
->counter_dev
= gpct_dev
;
753 ret
= comedi_alloc_subdevices(dev
, 2 + NI660X_MAX_COUNTERS
);
759 s
= &dev
->subdevices
[subdev
++];
760 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
761 s
->type
= COMEDI_SUBD_UNUSED
;
764 * Digital I/O subdevice
766 * There are 40 channels but only the first 32 can be digital I/Os.
767 * The last 8 are dedicated to counters 0 and 1.
769 * Counter 0-3 signals are from the first TIO chip.
770 * Counter 4-7 signals are from the second TIO chip.
773 * PFI Chan DIO Chan Counter Signal
774 * ------- -------- --------------
816 s
= &dev
->subdevices
[subdev
++];
817 s
->type
= COMEDI_SUBD_DIO
;
818 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
819 s
->n_chan
= NI660X_NUM_PFI_CHANNELS
;
821 s
->range_table
= &range_digital
;
822 s
->insn_bits
= ni_660x_dio_insn_bits
;
823 s
->insn_config
= ni_660x_dio_insn_config
;
826 * Default the DIO channels as:
827 * chan 0-7: DIO inputs
828 * chan 8-39: counter signal inputs
830 for (i
= 0; i
< s
->n_chan
; ++i
) {
831 unsigned int source
= (i
< 8) ? NI_660X_PFI_OUTPUT_DIO
832 : NI_660X_PFI_OUTPUT_COUNTER
;
834 ni_660x_set_pfi_routing(dev
, i
, source
);
835 ni_660x_select_pfi_output(dev
, i
, 0); /* high-z */
838 /* Counter subdevices (4 NI TIO General Purpose Counters per chip) */
839 for (i
= 0; i
< NI660X_MAX_COUNTERS
; ++i
) {
840 s
= &dev
->subdevices
[subdev
++];
841 if (i
< n_counters
) {
842 struct ni_gpct
*counter
= &gpct_dev
->counters
[i
];
844 counter
->chip_index
= i
/ NI660X_COUNTERS_PER_CHIP
;
845 counter
->counter_index
= i
% NI660X_COUNTERS_PER_CHIP
;
847 s
->type
= COMEDI_SUBD_COUNTER
;
848 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
|
849 SDF_LSAMPL
| SDF_CMD_READ
;
851 s
->maxdata
= 0xffffffff;
852 s
->insn_read
= ni_tio_insn_read
;
853 s
->insn_write
= ni_tio_insn_write
;
854 s
->insn_config
= ni_tio_insn_config
;
856 s
->do_cmd
= ni_660x_cmd
;
857 s
->do_cmdtest
= ni_tio_cmdtest
;
858 s
->cancel
= ni_660x_cancel
;
859 s
->poll
= ni_660x_input_poll
;
860 s
->buf_change
= ni_660x_buf_change
;
861 s
->async_dma_dir
= DMA_BIDIRECTIONAL
;
862 s
->private = counter
;
864 ni_tio_init_counter(counter
);
866 s
->type
= COMEDI_SUBD_UNUSED
;
871 * To be safe, set counterswap bits on tio chips after all the counter
872 * outputs have been set to high impedance mode.
874 for (i
= 0; i
< board
->n_chips
; ++i
)
875 set_tio_counterswap(dev
, i
);
877 ret
= request_irq(pcidev
->irq
, ni_660x_interrupt
, IRQF_SHARED
,
878 dev
->board_name
, dev
);
880 dev_warn(dev
->class_dev
, " irq not available\n");
883 dev
->irq
= pcidev
->irq
;
884 global_interrupt_config_bits
= NI660X_GLOBAL_INT_GLOBAL
;
885 if (board
->n_chips
> 1)
886 global_interrupt_config_bits
|= NI660X_GLOBAL_INT_CASCADE
;
887 ni_660x_write(dev
, 0, global_interrupt_config_bits
,
888 NI660X_GLOBAL_INT_CFG
);
893 static void ni_660x_detach(struct comedi_device
*dev
)
895 struct ni_660x_private
*devpriv
= dev
->private;
898 ni_660x_write(dev
, 0, 0, NI660X_GLOBAL_INT_CFG
);
899 free_irq(dev
->irq
, dev
);
902 ni_gpct_device_destroy(devpriv
->counter_dev
);
903 ni_660x_free_mite_rings(dev
);
904 mite_detach(devpriv
->mite
);
908 comedi_pci_disable(dev
);
911 static struct comedi_driver ni_660x_driver
= {
912 .driver_name
= "ni_660x",
913 .module
= THIS_MODULE
,
914 .auto_attach
= ni_660x_auto_attach
,
915 .detach
= ni_660x_detach
,
918 static int ni_660x_pci_probe(struct pci_dev
*dev
,
919 const struct pci_device_id
*id
)
921 return comedi_pci_auto_config(dev
, &ni_660x_driver
, id
->driver_data
);
924 static const struct pci_device_id ni_660x_pci_table
[] = {
925 { PCI_VDEVICE(NI
, 0x1310), BOARD_PCI6602
},
926 { PCI_VDEVICE(NI
, 0x1360), BOARD_PXI6602
},
927 { PCI_VDEVICE(NI
, 0x2c60), BOARD_PCI6601
},
928 { PCI_VDEVICE(NI
, 0x2cc0), BOARD_PXI6608
},
929 { PCI_VDEVICE(NI
, 0x1e30), BOARD_PCI6624
},
930 { PCI_VDEVICE(NI
, 0x1e40), BOARD_PXI6624
},
933 MODULE_DEVICE_TABLE(pci
, ni_660x_pci_table
);
935 static struct pci_driver ni_660x_pci_driver
= {
937 .id_table
= ni_660x_pci_table
,
938 .probe
= ni_660x_pci_probe
,
939 .remove
= comedi_pci_auto_unconfig
,
941 module_comedi_pci_driver(ni_660x_driver
, ni_660x_pci_driver
);
943 MODULE_AUTHOR("Comedi http://www.comedi.org");
944 MODULE_DESCRIPTION("Comedi driver for NI 660x counter/timer boards");
945 MODULE_LICENSE("GPL");