1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for NI 660x devices
8 * Description: National Instruments 660x counter/timer boards
9 * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
10 * PCI-6608, PXI-6608, PCI-6624, PXI-6624
11 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
12 * Herman.Bruyninckx@mech.kuleuven.ac.be,
13 * Wim.Meeussen@mech.kuleuven.ac.be,
14 * Klaas.Gadeyne@mech.kuleuven.ac.be,
15 * Frank Mori Hess <fmhess@users.sourceforge.net>
16 * Updated: Mon, 16 Jan 2017 14:00:43 +0000
17 * Status: experimental
19 * Encoders work. PulseGeneration (both single pulse and pulse train)
20 * works. Buffered commands work for input but not output.
23 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
24 * DAQ 6601/6602 User Manual (NI 322137B-01)
27 #include <linux/module.h>
28 #include <linux/interrupt.h>
30 #include "../comedi_pci.h"
34 #include "ni_routes.h"
36 /* See Register-Level Programmer Manual page 3.1 */
37 enum ni_660x_register
{
38 /* see enum ni_gpct_register */
39 NI660X_STC_DIO_PARALLEL_INPUT
= NITIO_NUM_REGS
,
40 NI660X_STC_DIO_OUTPUT
,
41 NI660X_STC_DIO_CONTROL
,
42 NI660X_STC_DIO_SERIAL_INPUT
,
46 NI660X_GLOBAL_INT_STATUS
,
48 NI660X_GLOBAL_INT_CFG
,
72 #define NI660X_CLK_CFG_COUNTER_SWAP BIT(21)
74 #define NI660X_GLOBAL_INT_COUNTER0 BIT(8)
75 #define NI660X_GLOBAL_INT_COUNTER1 BIT(9)
76 #define NI660X_GLOBAL_INT_COUNTER2 BIT(10)
77 #define NI660X_GLOBAL_INT_COUNTER3 BIT(11)
78 #define NI660X_GLOBAL_INT_CASCADE BIT(29)
79 #define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30)
80 #define NI660X_GLOBAL_INT_GLOBAL BIT(31)
82 #define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c)))
83 #define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
84 #define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
85 #define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80)
87 #define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2))
88 #define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
89 #define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
90 #define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12))
91 #define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7)
93 struct ni_660x_register_data
{
94 int offset
; /* Offset from base address from GPCT chip */
95 char size
; /* 2 or 4 bytes */
98 static const struct ni_660x_register_data ni_660x_reg_data
[NI660X_NUM_REGS
] = {
99 [NITIO_G0_INT_ACK
] = { 0x004, 2 }, /* write */
100 [NITIO_G0_STATUS
] = { 0x004, 2 }, /* read */
101 [NITIO_G1_INT_ACK
] = { 0x006, 2 }, /* write */
102 [NITIO_G1_STATUS
] = { 0x006, 2 }, /* read */
103 [NITIO_G01_STATUS
] = { 0x008, 2 }, /* read */
104 [NITIO_G0_CMD
] = { 0x00c, 2 }, /* write */
105 [NI660X_STC_DIO_PARALLEL_INPUT
] = { 0x00e, 2 }, /* read */
106 [NITIO_G1_CMD
] = { 0x00e, 2 }, /* write */
107 [NITIO_G0_HW_SAVE
] = { 0x010, 4 }, /* read */
108 [NITIO_G1_HW_SAVE
] = { 0x014, 4 }, /* read */
109 [NI660X_STC_DIO_OUTPUT
] = { 0x014, 2 }, /* write */
110 [NI660X_STC_DIO_CONTROL
] = { 0x016, 2 }, /* write */
111 [NITIO_G0_SW_SAVE
] = { 0x018, 4 }, /* read */
112 [NITIO_G1_SW_SAVE
] = { 0x01c, 4 }, /* read */
113 [NITIO_G0_MODE
] = { 0x034, 2 }, /* write */
114 [NITIO_G01_STATUS1
] = { 0x036, 2 }, /* read */
115 [NITIO_G1_MODE
] = { 0x036, 2 }, /* write */
116 [NI660X_STC_DIO_SERIAL_INPUT
] = { 0x038, 2 }, /* read */
117 [NITIO_G0_LOADA
] = { 0x038, 4 }, /* write */
118 [NITIO_G01_STATUS2
] = { 0x03a, 2 }, /* read */
119 [NITIO_G0_LOADB
] = { 0x03c, 4 }, /* write */
120 [NITIO_G1_LOADA
] = { 0x040, 4 }, /* write */
121 [NITIO_G1_LOADB
] = { 0x044, 4 }, /* write */
122 [NITIO_G0_INPUT_SEL
] = { 0x048, 2 }, /* write */
123 [NITIO_G1_INPUT_SEL
] = { 0x04a, 2 }, /* write */
124 [NITIO_G0_AUTO_INC
] = { 0x088, 2 }, /* write */
125 [NITIO_G1_AUTO_INC
] = { 0x08a, 2 }, /* write */
126 [NITIO_G01_RESET
] = { 0x090, 2 }, /* write */
127 [NITIO_G0_INT_ENA
] = { 0x092, 2 }, /* write */
128 [NITIO_G1_INT_ENA
] = { 0x096, 2 }, /* write */
129 [NITIO_G0_CNT_MODE
] = { 0x0b0, 2 }, /* write */
130 [NITIO_G1_CNT_MODE
] = { 0x0b2, 2 }, /* write */
131 [NITIO_G0_GATE2
] = { 0x0b4, 2 }, /* write */
132 [NITIO_G1_GATE2
] = { 0x0b6, 2 }, /* write */
133 [NITIO_G0_DMA_CFG
] = { 0x0b8, 2 }, /* write */
134 [NITIO_G0_DMA_STATUS
] = { 0x0b8, 2 }, /* read */
135 [NITIO_G1_DMA_CFG
] = { 0x0ba, 2 }, /* write */
136 [NITIO_G1_DMA_STATUS
] = { 0x0ba, 2 }, /* read */
137 [NITIO_G2_INT_ACK
] = { 0x104, 2 }, /* write */
138 [NITIO_G2_STATUS
] = { 0x104, 2 }, /* read */
139 [NITIO_G3_INT_ACK
] = { 0x106, 2 }, /* write */
140 [NITIO_G3_STATUS
] = { 0x106, 2 }, /* read */
141 [NITIO_G23_STATUS
] = { 0x108, 2 }, /* read */
142 [NITIO_G2_CMD
] = { 0x10c, 2 }, /* write */
143 [NITIO_G3_CMD
] = { 0x10e, 2 }, /* write */
144 [NITIO_G2_HW_SAVE
] = { 0x110, 4 }, /* read */
145 [NITIO_G3_HW_SAVE
] = { 0x114, 4 }, /* read */
146 [NITIO_G2_SW_SAVE
] = { 0x118, 4 }, /* read */
147 [NITIO_G3_SW_SAVE
] = { 0x11c, 4 }, /* read */
148 [NITIO_G2_MODE
] = { 0x134, 2 }, /* write */
149 [NITIO_G23_STATUS1
] = { 0x136, 2 }, /* read */
150 [NITIO_G3_MODE
] = { 0x136, 2 }, /* write */
151 [NITIO_G2_LOADA
] = { 0x138, 4 }, /* write */
152 [NITIO_G23_STATUS2
] = { 0x13a, 2 }, /* read */
153 [NITIO_G2_LOADB
] = { 0x13c, 4 }, /* write */
154 [NITIO_G3_LOADA
] = { 0x140, 4 }, /* write */
155 [NITIO_G3_LOADB
] = { 0x144, 4 }, /* write */
156 [NITIO_G2_INPUT_SEL
] = { 0x148, 2 }, /* write */
157 [NITIO_G3_INPUT_SEL
] = { 0x14a, 2 }, /* write */
158 [NITIO_G2_AUTO_INC
] = { 0x188, 2 }, /* write */
159 [NITIO_G3_AUTO_INC
] = { 0x18a, 2 }, /* write */
160 [NITIO_G23_RESET
] = { 0x190, 2 }, /* write */
161 [NITIO_G2_INT_ENA
] = { 0x192, 2 }, /* write */
162 [NITIO_G3_INT_ENA
] = { 0x196, 2 }, /* write */
163 [NITIO_G2_CNT_MODE
] = { 0x1b0, 2 }, /* write */
164 [NITIO_G3_CNT_MODE
] = { 0x1b2, 2 }, /* write */
165 [NITIO_G2_GATE2
] = { 0x1b4, 2 }, /* write */
166 [NITIO_G3_GATE2
] = { 0x1b6, 2 }, /* write */
167 [NITIO_G2_DMA_CFG
] = { 0x1b8, 2 }, /* write */
168 [NITIO_G2_DMA_STATUS
] = { 0x1b8, 2 }, /* read */
169 [NITIO_G3_DMA_CFG
] = { 0x1ba, 2 }, /* write */
170 [NITIO_G3_DMA_STATUS
] = { 0x1ba, 2 }, /* read */
171 [NI660X_DIO32_INPUT
] = { 0x414, 4 }, /* read */
172 [NI660X_DIO32_OUTPUT
] = { 0x510, 4 }, /* write */
173 [NI660X_CLK_CFG
] = { 0x73c, 4 }, /* write */
174 [NI660X_GLOBAL_INT_STATUS
] = { 0x754, 4 }, /* read */
175 [NI660X_DMA_CFG
] = { 0x76c, 4 }, /* write */
176 [NI660X_GLOBAL_INT_CFG
] = { 0x770, 4 }, /* write */
177 [NI660X_IO_CFG_0_1
] = { 0x77c, 2 }, /* read/write */
178 [NI660X_IO_CFG_2_3
] = { 0x77e, 2 }, /* read/write */
179 [NI660X_IO_CFG_4_5
] = { 0x780, 2 }, /* read/write */
180 [NI660X_IO_CFG_6_7
] = { 0x782, 2 }, /* read/write */
181 [NI660X_IO_CFG_8_9
] = { 0x784, 2 }, /* read/write */
182 [NI660X_IO_CFG_10_11
] = { 0x786, 2 }, /* read/write */
183 [NI660X_IO_CFG_12_13
] = { 0x788, 2 }, /* read/write */
184 [NI660X_IO_CFG_14_15
] = { 0x78a, 2 }, /* read/write */
185 [NI660X_IO_CFG_16_17
] = { 0x78c, 2 }, /* read/write */
186 [NI660X_IO_CFG_18_19
] = { 0x78e, 2 }, /* read/write */
187 [NI660X_IO_CFG_20_21
] = { 0x790, 2 }, /* read/write */
188 [NI660X_IO_CFG_22_23
] = { 0x792, 2 }, /* read/write */
189 [NI660X_IO_CFG_24_25
] = { 0x794, 2 }, /* read/write */
190 [NI660X_IO_CFG_26_27
] = { 0x796, 2 }, /* read/write */
191 [NI660X_IO_CFG_28_29
] = { 0x798, 2 }, /* read/write */
192 [NI660X_IO_CFG_30_31
] = { 0x79a, 2 }, /* read/write */
193 [NI660X_IO_CFG_32_33
] = { 0x79c, 2 }, /* read/write */
194 [NI660X_IO_CFG_34_35
] = { 0x79e, 2 }, /* read/write */
195 [NI660X_IO_CFG_36_37
] = { 0x7a0, 2 }, /* read/write */
196 [NI660X_IO_CFG_38_39
] = { 0x7a2, 2 } /* read/write */
199 #define NI660X_CHIP_OFFSET 0x800
201 enum ni_660x_boardid
{
211 struct ni_660x_board
{
213 unsigned int n_chips
; /* total number of TIO chips */
216 static const struct ni_660x_board ni_660x_boards
[] = {
247 #define NI660X_NUM_PFI_CHANNELS 40
249 /* there are only up to 3 dma channels, but the register layout allows for 4 */
250 #define NI660X_MAX_DMA_CHANNEL 4
252 #define NI660X_COUNTERS_PER_CHIP 4
253 #define NI660X_MAX_CHIPS 2
254 #define NI660X_MAX_COUNTERS (NI660X_MAX_CHIPS * \
255 NI660X_COUNTERS_PER_CHIP)
257 struct ni_660x_private
{
259 struct ni_gpct_device
*counter_dev
;
260 struct mite_ring
*ring
[NI660X_MAX_CHIPS
][NI660X_COUNTERS_PER_CHIP
];
261 /* protects mite channel request/release */
262 spinlock_t mite_channel_lock
;
263 /* prevents races between interrupt and comedi_poll */
264 spinlock_t interrupt_lock
;
265 unsigned int dma_cfg
[NI660X_MAX_CHIPS
];
266 unsigned int io_cfg
[NI660X_NUM_PFI_CHANNELS
];
268 struct ni_route_tables routing_tables
;
271 static void ni_660x_write(struct comedi_device
*dev
, unsigned int chip
,
272 unsigned int bits
, unsigned int reg
)
274 unsigned int addr
= (chip
* NI660X_CHIP_OFFSET
) +
275 ni_660x_reg_data
[reg
].offset
;
277 if (ni_660x_reg_data
[reg
].size
== 2)
278 writew(bits
, dev
->mmio
+ addr
);
280 writel(bits
, dev
->mmio
+ addr
);
283 static unsigned int ni_660x_read(struct comedi_device
*dev
,
284 unsigned int chip
, unsigned int reg
)
286 unsigned int addr
= (chip
* NI660X_CHIP_OFFSET
) +
287 ni_660x_reg_data
[reg
].offset
;
289 if (ni_660x_reg_data
[reg
].size
== 2)
290 return readw(dev
->mmio
+ addr
);
291 return readl(dev
->mmio
+ addr
);
294 static void ni_660x_gpct_write(struct ni_gpct
*counter
, unsigned int bits
,
295 enum ni_gpct_register reg
)
297 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
299 ni_660x_write(dev
, counter
->chip_index
, bits
, reg
);
302 static unsigned int ni_660x_gpct_read(struct ni_gpct
*counter
,
303 enum ni_gpct_register reg
)
305 struct comedi_device
*dev
= counter
->counter_dev
->dev
;
307 return ni_660x_read(dev
, counter
->chip_index
, reg
);
310 static inline void ni_660x_set_dma_channel(struct comedi_device
*dev
,
311 unsigned int mite_channel
,
312 struct ni_gpct
*counter
)
314 struct ni_660x_private
*devpriv
= dev
->private;
315 unsigned int chip
= counter
->chip_index
;
317 devpriv
->dma_cfg
[chip
] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel
);
318 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL(mite_channel
,
319 counter
->counter_index
);
320 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
] |
321 NI660X_DMA_CFG_RESET(mite_channel
),
325 static inline void ni_660x_unset_dma_channel(struct comedi_device
*dev
,
326 unsigned int mite_channel
,
327 struct ni_gpct
*counter
)
329 struct ni_660x_private
*devpriv
= dev
->private;
330 unsigned int chip
= counter
->chip_index
;
332 devpriv
->dma_cfg
[chip
] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel
);
333 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL_NONE(mite_channel
);
334 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
], NI660X_DMA_CFG
);
337 static int ni_660x_request_mite_channel(struct comedi_device
*dev
,
338 struct ni_gpct
*counter
,
339 enum comedi_io_direction direction
)
341 struct ni_660x_private
*devpriv
= dev
->private;
342 struct mite_ring
*ring
;
343 struct mite_channel
*mite_chan
;
346 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
347 ring
= devpriv
->ring
[counter
->chip_index
][counter
->counter_index
];
348 mite_chan
= mite_request_channel(devpriv
->mite
, ring
);
350 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
351 dev_err(dev
->class_dev
,
352 "failed to reserve mite dma channel for counter\n");
355 mite_chan
->dir
= direction
;
356 ni_tio_set_mite_channel(counter
, mite_chan
);
357 ni_660x_set_dma_channel(dev
, mite_chan
->channel
, counter
);
358 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
362 static void ni_660x_release_mite_channel(struct comedi_device
*dev
,
363 struct ni_gpct
*counter
)
365 struct ni_660x_private
*devpriv
= dev
->private;
368 spin_lock_irqsave(&devpriv
->mite_channel_lock
, flags
);
369 if (counter
->mite_chan
) {
370 struct mite_channel
*mite_chan
= counter
->mite_chan
;
372 ni_660x_unset_dma_channel(dev
, mite_chan
->channel
, counter
);
373 ni_tio_set_mite_channel(counter
, NULL
);
374 mite_release_channel(mite_chan
);
376 spin_unlock_irqrestore(&devpriv
->mite_channel_lock
, flags
);
379 static int ni_660x_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
381 struct ni_gpct
*counter
= s
->private;
384 retval
= ni_660x_request_mite_channel(dev
, counter
, COMEDI_INPUT
);
386 dev_err(dev
->class_dev
,
387 "no dma channel available for use by counter\n");
390 ni_tio_acknowledge(counter
);
392 return ni_tio_cmd(dev
, s
);
395 static int ni_660x_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
397 struct ni_gpct
*counter
= s
->private;
400 retval
= ni_tio_cancel(counter
);
401 ni_660x_release_mite_channel(dev
, counter
);
405 static void set_tio_counterswap(struct comedi_device
*dev
, int chip
)
407 unsigned int bits
= 0;
410 * See P. 3.5 of the Register-Level Programming manual.
411 * The CounterSwap bit has to be set on the second chip,
412 * otherwise it will try to use the same pins as the
416 bits
= NI660X_CLK_CFG_COUNTER_SWAP
;
418 ni_660x_write(dev
, chip
, bits
, NI660X_CLK_CFG
);
421 static void ni_660x_handle_gpct_interrupt(struct comedi_device
*dev
,
422 struct comedi_subdevice
*s
)
424 struct ni_gpct
*counter
= s
->private;
426 ni_tio_handle_interrupt(counter
, s
);
427 comedi_handle_events(dev
, s
);
430 static irqreturn_t
ni_660x_interrupt(int irq
, void *d
)
432 struct comedi_device
*dev
= d
;
433 struct ni_660x_private
*devpriv
= dev
->private;
434 struct comedi_subdevice
*s
;
440 /* make sure dev->attached is checked before doing anything else */
443 /* lock to avoid race with comedi_poll */
444 spin_lock_irqsave(&devpriv
->interrupt_lock
, flags
);
445 for (i
= 0; i
< dev
->n_subdevices
; ++i
) {
446 s
= &dev
->subdevices
[i
];
447 if (s
->type
== COMEDI_SUBD_COUNTER
)
448 ni_660x_handle_gpct_interrupt(dev
, s
);
450 spin_unlock_irqrestore(&devpriv
->interrupt_lock
, flags
);
454 static int ni_660x_input_poll(struct comedi_device
*dev
,
455 struct comedi_subdevice
*s
)
457 struct ni_660x_private
*devpriv
= dev
->private;
458 struct ni_gpct
*counter
= s
->private;
461 /* lock to avoid race with comedi_poll */
462 spin_lock_irqsave(&devpriv
->interrupt_lock
, flags
);
463 mite_sync_dma(counter
->mite_chan
, s
);
464 spin_unlock_irqrestore(&devpriv
->interrupt_lock
, flags
);
465 return comedi_buf_read_n_available(s
);
468 static int ni_660x_buf_change(struct comedi_device
*dev
,
469 struct comedi_subdevice
*s
)
471 struct ni_660x_private
*devpriv
= dev
->private;
472 struct ni_gpct
*counter
= s
->private;
473 struct mite_ring
*ring
;
476 ring
= devpriv
->ring
[counter
->chip_index
][counter
->counter_index
];
477 ret
= mite_buf_change(ring
, s
);
484 static int ni_660x_allocate_private(struct comedi_device
*dev
)
486 struct ni_660x_private
*devpriv
;
489 devpriv
= comedi_alloc_devpriv(dev
, sizeof(*devpriv
));
493 spin_lock_init(&devpriv
->mite_channel_lock
);
494 spin_lock_init(&devpriv
->interrupt_lock
);
495 for (i
= 0; i
< NI660X_NUM_PFI_CHANNELS
; ++i
)
496 devpriv
->io_cfg
[i
] = NI_660X_PFI_OUTPUT_COUNTER
;
501 static int ni_660x_alloc_mite_rings(struct comedi_device
*dev
)
503 const struct ni_660x_board
*board
= dev
->board_ptr
;
504 struct ni_660x_private
*devpriv
= dev
->private;
508 for (i
= 0; i
< board
->n_chips
; ++i
) {
509 for (j
= 0; j
< NI660X_COUNTERS_PER_CHIP
; ++j
) {
510 devpriv
->ring
[i
][j
] = mite_alloc_ring(devpriv
->mite
);
511 if (!devpriv
->ring
[i
][j
])
518 static void ni_660x_free_mite_rings(struct comedi_device
*dev
)
520 const struct ni_660x_board
*board
= dev
->board_ptr
;
521 struct ni_660x_private
*devpriv
= dev
->private;
525 for (i
= 0; i
< board
->n_chips
; ++i
) {
526 for (j
= 0; j
< NI660X_COUNTERS_PER_CHIP
; ++j
)
527 mite_free_ring(devpriv
->ring
[i
][j
]);
531 static int ni_660x_dio_insn_bits(struct comedi_device
*dev
,
532 struct comedi_subdevice
*s
,
533 struct comedi_insn
*insn
,
536 unsigned int shift
= CR_CHAN(insn
->chanspec
);
537 unsigned int mask
= data
[0] << shift
;
538 unsigned int bits
= data
[1] << shift
;
541 * There are 40 channels in this subdevice but only 32 are usable
542 * as DIO. The shift adjusts the mask/bits to account for the base
543 * channel in insn->chanspec. The state update can then be handled
544 * normally for the 32 usable channels.
548 s
->state
|= (bits
& mask
);
549 ni_660x_write(dev
, 0, s
->state
, NI660X_DIO32_OUTPUT
);
553 * Return the input channels, shifted back to account for the base
556 data
[1] = ni_660x_read(dev
, 0, NI660X_DIO32_INPUT
) >> shift
;
561 static void ni_660x_select_pfi_output(struct comedi_device
*dev
,
562 unsigned int chan
, unsigned int out_sel
)
564 const struct ni_660x_board
*board
= dev
->board_ptr
;
565 unsigned int active_chip
= 0;
566 unsigned int idle_chip
= 0;
569 if (chan
>= NI_PFI(0))
570 /* allow new and old names of pfi channels to work. */
573 if (board
->n_chips
> 1) {
574 if (out_sel
== NI_660X_PFI_OUTPUT_COUNTER
&&
575 chan
>= 8 && chan
<= 23) {
576 /* counters 4-7 pfi channels */
580 /* counters 0-3 pfi channels */
586 if (idle_chip
!= active_chip
) {
587 /* set the pfi channel to high-z on the inactive chip */
588 bits
= ni_660x_read(dev
, idle_chip
, NI660X_IO_CFG(chan
));
589 bits
&= ~NI660X_IO_CFG_OUT_SEL_MASK(chan
);
590 bits
|= NI660X_IO_CFG_OUT_SEL(chan
, 0); /* high-z */
591 ni_660x_write(dev
, idle_chip
, bits
, NI660X_IO_CFG(chan
));
594 /* set the pfi channel output on the active chip */
595 bits
= ni_660x_read(dev
, active_chip
, NI660X_IO_CFG(chan
));
596 bits
&= ~NI660X_IO_CFG_OUT_SEL_MASK(chan
);
597 bits
|= NI660X_IO_CFG_OUT_SEL(chan
, out_sel
);
598 ni_660x_write(dev
, active_chip
, bits
, NI660X_IO_CFG(chan
));
601 static void ni_660x_set_pfi_direction(struct comedi_device
*dev
,
603 unsigned int direction
)
605 struct ni_660x_private
*devpriv
= dev
->private;
608 if (chan
>= NI_PFI(0))
609 /* allow new and old names of pfi channels to work. */
614 if (direction
== COMEDI_OUTPUT
) {
615 devpriv
->io_dir
|= bit
;
616 /* reset the output to currently assigned output value */
617 ni_660x_select_pfi_output(dev
, chan
, devpriv
->io_cfg
[chan
]);
619 devpriv
->io_dir
&= ~bit
;
620 /* set pin to high-z; do not change currently assigned route */
621 ni_660x_select_pfi_output(dev
, chan
, 0);
625 static unsigned int ni_660x_get_pfi_direction(struct comedi_device
*dev
,
628 struct ni_660x_private
*devpriv
= dev
->private;
631 if (chan
>= NI_PFI(0))
632 /* allow new and old names of pfi channels to work. */
637 return (devpriv
->io_dir
& bit
) ? COMEDI_OUTPUT
: COMEDI_INPUT
;
640 static int ni_660x_set_pfi_routing(struct comedi_device
*dev
,
641 unsigned int chan
, unsigned int source
)
643 struct ni_660x_private
*devpriv
= dev
->private;
645 if (chan
>= NI_PFI(0))
646 /* allow new and old names of pfi channels to work. */
650 case NI_660X_PFI_OUTPUT_COUNTER
:
654 case NI_660X_PFI_OUTPUT_DIO
:
662 devpriv
->io_cfg
[chan
] = source
;
663 if (ni_660x_get_pfi_direction(dev
, chan
) == COMEDI_OUTPUT
)
664 ni_660x_select_pfi_output(dev
, chan
, devpriv
->io_cfg
[chan
]);
668 static int ni_660x_get_pfi_routing(struct comedi_device
*dev
, unsigned int chan
)
670 struct ni_660x_private
*devpriv
= dev
->private;
672 if (chan
>= NI_PFI(0))
673 /* allow new and old names of pfi channels to work. */
676 return devpriv
->io_cfg
[chan
];
679 static void ni_660x_set_pfi_filter(struct comedi_device
*dev
,
680 unsigned int chan
, unsigned int value
)
684 if (chan
>= NI_PFI(0))
685 /* allow new and old names of pfi channels to work. */
688 val
= ni_660x_read(dev
, 0, NI660X_IO_CFG(chan
));
689 val
&= ~NI660X_IO_CFG_IN_SEL_MASK(chan
);
690 val
|= NI660X_IO_CFG_IN_SEL(chan
, value
);
691 ni_660x_write(dev
, 0, val
, NI660X_IO_CFG(chan
));
694 static int ni_660x_dio_insn_config(struct comedi_device
*dev
,
695 struct comedi_subdevice
*s
,
696 struct comedi_insn
*insn
,
699 unsigned int chan
= CR_CHAN(insn
->chanspec
);
703 case INSN_CONFIG_DIO_OUTPUT
:
704 ni_660x_set_pfi_direction(dev
, chan
, COMEDI_OUTPUT
);
707 case INSN_CONFIG_DIO_INPUT
:
708 ni_660x_set_pfi_direction(dev
, chan
, COMEDI_INPUT
);
711 case INSN_CONFIG_DIO_QUERY
:
712 data
[1] = ni_660x_get_pfi_direction(dev
, chan
);
715 case INSN_CONFIG_SET_ROUTING
:
716 ret
= ni_660x_set_pfi_routing(dev
, chan
, data
[1]);
721 case INSN_CONFIG_GET_ROUTING
:
722 data
[1] = ni_660x_get_pfi_routing(dev
, chan
);
725 case INSN_CONFIG_FILTER
:
726 ni_660x_set_pfi_filter(dev
, chan
, data
[1]);
736 static unsigned int _ni_get_valid_routes(struct comedi_device
*dev
,
737 unsigned int n_pairs
,
738 unsigned int *pair_data
)
740 struct ni_660x_private
*devpriv
= dev
->private;
742 return ni_get_valid_routes(&devpriv
->routing_tables
, n_pairs
,
747 * Retrieves the current source of the output selector for the given
748 * destination. If the terminal for the destination is not already configured
749 * as an output, this function returns -EINVAL as error.
751 * Return: The register value of the destination output selector;
752 * -EINVAL if terminal is not configured for output.
754 static inline int get_output_select_source(int dest
, struct comedi_device
*dev
)
756 struct ni_660x_private
*devpriv
= dev
->private;
759 if (channel_is_pfi(dest
)) {
760 if (ni_660x_get_pfi_direction(dev
, dest
) == COMEDI_OUTPUT
)
761 reg
= ni_660x_get_pfi_routing(dev
, dest
);
762 } else if (channel_is_rtsi(dest
)) {
763 dev_dbg(dev
->class_dev
,
764 "%s: unhandled rtsi destination (%d) queried\n",
767 * The following can be enabled when RTSI routing info is
768 * determined (not currently documented):
769 * if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
770 * reg = ni_get_rtsi_routing(dev, dest);
772 * if (reg == NI_RTSI_OUTPUT_RGOUT0) {
773 * dest = NI_RGOUT0; ** prepare for lookup below **
774 * reg = get_rgout0_reg(dev);
775 * } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
776 * reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
777 * const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
779 * dest = NI_RTSI_BRD(i); ** prepare for lookup **
780 * reg = get_ith_rtsi_brd_reg(i, dev);
784 } else if (channel_is_ctr(dest
)) {
785 reg
= ni_tio_get_routing(devpriv
->counter_dev
, dest
);
787 dev_dbg(dev
->class_dev
,
788 "%s: unhandled destination (%d) queried\n",
793 return ni_find_route_source(CR_CHAN(reg
), dest
,
794 &devpriv
->routing_tables
);
801 * Return: -1 if not connectible;
802 * 0 if connectible and not connected;
803 * 1 if connectible and connected.
805 static inline int test_route(unsigned int src
, unsigned int dest
,
806 struct comedi_device
*dev
)
808 struct ni_660x_private
*devpriv
= dev
->private;
809 s8 reg
= ni_route_to_register(CR_CHAN(src
), dest
,
810 &devpriv
->routing_tables
);
814 if (get_output_select_source(dest
, dev
) != CR_CHAN(src
))
819 /* Connect the actual route. */
820 static inline int connect_route(unsigned int src
, unsigned int dest
,
821 struct comedi_device
*dev
)
823 struct ni_660x_private
*devpriv
= dev
->private;
824 s8 reg
= ni_route_to_register(CR_CHAN(src
), dest
,
825 &devpriv
->routing_tables
);
829 /* route is not valid */
832 current_src
= get_output_select_source(dest
, dev
);
833 if (current_src
== CR_CHAN(src
))
835 if (current_src
>= 0)
836 /* destination mux is already busy. complain, don't overwrite */
839 /* The route is valid and available. Now connect... */
840 if (channel_is_pfi(CR_CHAN(dest
))) {
842 * set routing and then direction so that the output does not
843 * first get generated with the wrong pin
845 ni_660x_set_pfi_routing(dev
, dest
, reg
);
846 ni_660x_set_pfi_direction(dev
, dest
, COMEDI_OUTPUT
);
847 } else if (channel_is_rtsi(CR_CHAN(dest
))) {
848 dev_dbg(dev
->class_dev
, "%s: unhandled rtsi destination (%d)\n",
852 * The following can be enabled when RTSI routing info is
853 * determined (not currently documented):
854 * if (reg == NI_RTSI_OUTPUT_RGOUT0) {
855 * int ret = incr_rgout0_src_use(src, dev);
859 * } else if (ni_rtsi_route_requires_mux(reg)) {
860 * ** Attempt to allocate and route (src->brd) **
861 * int brd = incr_rtsi_brd_src_use(src, dev);
866 * ** Now lookup the register value for (brd->dest) **
867 * reg = ni_lookup_route_register(brd, CR_CHAN(dest),
868 * &devpriv->routing_tables);
871 * ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
872 * ni_set_rtsi_routing(dev, dest, reg);
874 } else if (channel_is_ctr(CR_CHAN(dest
))) {
876 * we are adding back the channel modifier info to set
877 * invert/edge info passed by the user
879 ni_tio_set_routing(devpriv
->counter_dev
, dest
,
880 reg
| (src
& ~CR_CHAN(-1)));
887 static inline int disconnect_route(unsigned int src
, unsigned int dest
,
888 struct comedi_device
*dev
)
890 struct ni_660x_private
*devpriv
= dev
->private;
891 s8 reg
= ni_route_to_register(CR_CHAN(src
), CR_CHAN(dest
),
892 &devpriv
->routing_tables
);
895 /* route is not valid */
897 if (get_output_select_source(dest
, dev
) != CR_CHAN(src
))
898 /* cannot disconnect something not connected */
901 /* The route is valid and is connected. Now disconnect... */
902 if (channel_is_pfi(CR_CHAN(dest
))) {
903 unsigned int source
= ((CR_CHAN(dest
) - NI_PFI(0)) < 8)
904 ? NI_660X_PFI_OUTPUT_DIO
905 : NI_660X_PFI_OUTPUT_COUNTER
;
907 /* set the pfi to high impedance, and disconnect */
908 ni_660x_set_pfi_direction(dev
, dest
, COMEDI_INPUT
);
909 ni_660x_set_pfi_routing(dev
, dest
, source
);
910 } else if (channel_is_rtsi(CR_CHAN(dest
))) {
911 dev_dbg(dev
->class_dev
, "%s: unhandled rtsi destination (%d)\n",
915 * The following can be enabled when RTSI routing info is
916 * determined (not currently documented):
917 * if (reg == NI_RTSI_OUTPUT_RGOUT0) {
918 * int ret = decr_rgout0_src_use(src, dev);
922 * } else if (ni_rtsi_route_requires_mux(reg)) {
923 * ** find which RTSI_BRD line is source for rtsi pin **
924 * int brd = ni_find_route_source(
925 * ni_get_rtsi_routing(dev, dest), CR_CHAN(dest),
926 * &devpriv->routing_tables);
931 * ** decrement/disconnect RTSI_BRD line from source **
932 * decr_rtsi_brd_src_use(src, brd, dev);
935 * ** set rtsi output selector to default state **
936 * reg = default_rtsi_routing[CR_CHAN(dest) - TRIGGER_LINE(0)];
937 * ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
938 * ni_set_rtsi_routing(dev, dest, reg);
940 } else if (channel_is_ctr(CR_CHAN(dest
))) {
941 ni_tio_unset_routing(devpriv
->counter_dev
, dest
);
948 static int ni_global_insn_config(struct comedi_device
*dev
,
949 struct comedi_insn
*insn
,
953 case INSN_DEVICE_CONFIG_TEST_ROUTE
:
954 data
[0] = test_route(data
[1], data
[2], dev
);
956 case INSN_DEVICE_CONFIG_CONNECT_ROUTE
:
957 return connect_route(data
[1], data
[2], dev
);
958 case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE
:
959 return disconnect_route(data
[1], data
[2], dev
);
961 * This case is already handled one level up.
962 * case INSN_DEVICE_CONFIG_GET_ROUTES:
970 static void ni_660x_init_tio_chips(struct comedi_device
*dev
,
971 unsigned int n_chips
)
973 struct ni_660x_private
*devpriv
= dev
->private;
978 * We use the ioconfig registers to control dio direction, so zero
979 * output enables in stc dio control reg.
981 ni_660x_write(dev
, 0, 0, NI660X_STC_DIO_CONTROL
);
983 for (chip
= 0; chip
< n_chips
; ++chip
) {
984 /* init dma configuration register */
985 devpriv
->dma_cfg
[chip
] = 0;
986 for (chan
= 0; chan
< NI660X_MAX_DMA_CHANNEL
; ++chan
)
987 devpriv
->dma_cfg
[chip
] |= NI660X_DMA_CFG_SEL_NONE(chan
);
988 ni_660x_write(dev
, chip
, devpriv
->dma_cfg
[chip
],
991 /* init ioconfig registers */
992 for (chan
= 0; chan
< NI660X_NUM_PFI_CHANNELS
; ++chan
)
993 ni_660x_write(dev
, chip
, 0, NI660X_IO_CFG(chan
));
997 static int ni_660x_auto_attach(struct comedi_device
*dev
,
998 unsigned long context
)
1000 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1001 const struct ni_660x_board
*board
= NULL
;
1002 struct ni_660x_private
*devpriv
;
1003 struct comedi_subdevice
*s
;
1004 struct ni_gpct_device
*gpct_dev
;
1005 unsigned int n_counters
;
1009 unsigned int global_interrupt_config_bits
;
1011 if (context
< ARRAY_SIZE(ni_660x_boards
))
1012 board
= &ni_660x_boards
[context
];
1015 dev
->board_ptr
= board
;
1016 dev
->board_name
= board
->name
;
1018 ret
= comedi_pci_enable(dev
);
1022 ret
= ni_660x_allocate_private(dev
);
1025 devpriv
= dev
->private;
1027 devpriv
->mite
= mite_attach(dev
, true); /* use win1 */
1031 ret
= ni_660x_alloc_mite_rings(dev
);
1035 ni_660x_init_tio_chips(dev
, board
->n_chips
);
1037 /* prepare the device for globally-named routes. */
1038 if (ni_assign_device_routes("ni_660x", board
->name
, NULL
,
1039 &devpriv
->routing_tables
) < 0) {
1040 dev_warn(dev
->class_dev
, "%s: %s device has no signal routing table.\n",
1041 __func__
, board
->name
);
1042 dev_warn(dev
->class_dev
, "%s: High level NI signal names will not be available for this %s board.\n",
1043 __func__
, board
->name
);
1046 * only(?) assign insn_device_config if we have global names for
1049 dev
->insn_device_config
= ni_global_insn_config
;
1050 dev
->get_valid_routes
= _ni_get_valid_routes
;
1053 n_counters
= board
->n_chips
* NI660X_COUNTERS_PER_CHIP
;
1054 gpct_dev
= ni_gpct_device_construct(dev
,
1057 ni_gpct_variant_660x
,
1059 NI660X_COUNTERS_PER_CHIP
,
1060 &devpriv
->routing_tables
);
1063 devpriv
->counter_dev
= gpct_dev
;
1065 ret
= comedi_alloc_subdevices(dev
, 2 + NI660X_MAX_COUNTERS
);
1071 s
= &dev
->subdevices
[subdev
++];
1072 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1073 s
->type
= COMEDI_SUBD_UNUSED
;
1076 * Digital I/O subdevice
1078 * There are 40 channels but only the first 32 can be digital I/Os.
1079 * The last 8 are dedicated to counters 0 and 1.
1081 * Counter 0-3 signals are from the first TIO chip.
1082 * Counter 4-7 signals are from the second TIO chip.
1085 * PFI Chan DIO Chan Counter Signal
1086 * ------- -------- --------------
1098 * 11 11 CTR 7 SOURCE
1102 * 15 15 CTR 6 SOURCE
1106 * 19 19 CTR 5 SOURCE
1110 * 23 23 CTR 4 SOURCE
1114 * 27 27 CTR 3 SOURCE
1118 * 31 31 CTR 2 SOURCE
1128 s
= &dev
->subdevices
[subdev
++];
1129 s
->type
= COMEDI_SUBD_DIO
;
1130 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
1131 s
->n_chan
= NI660X_NUM_PFI_CHANNELS
;
1133 s
->range_table
= &range_digital
;
1134 s
->insn_bits
= ni_660x_dio_insn_bits
;
1135 s
->insn_config
= ni_660x_dio_insn_config
;
1138 * Default the DIO channels as:
1139 * chan 0-7: DIO inputs
1140 * chan 8-39: counter signal inputs
1142 for (i
= 0; i
< s
->n_chan
; ++i
) {
1143 unsigned int source
= (i
< 8) ? NI_660X_PFI_OUTPUT_DIO
1144 : NI_660X_PFI_OUTPUT_COUNTER
;
1146 ni_660x_set_pfi_routing(dev
, i
, source
);
1147 ni_660x_set_pfi_direction(dev
, i
, COMEDI_INPUT
);/* high-z */
1150 /* Counter subdevices (4 NI TIO General Purpose Counters per chip) */
1151 for (i
= 0; i
< NI660X_MAX_COUNTERS
; ++i
) {
1152 s
= &dev
->subdevices
[subdev
++];
1153 if (i
< n_counters
) {
1154 struct ni_gpct
*counter
= &gpct_dev
->counters
[i
];
1156 s
->type
= COMEDI_SUBD_COUNTER
;
1157 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
|
1158 SDF_LSAMPL
| SDF_CMD_READ
;
1160 s
->maxdata
= 0xffffffff;
1161 s
->insn_read
= ni_tio_insn_read
;
1162 s
->insn_write
= ni_tio_insn_write
;
1163 s
->insn_config
= ni_tio_insn_config
;
1164 s
->len_chanlist
= 1;
1165 s
->do_cmd
= ni_660x_cmd
;
1166 s
->do_cmdtest
= ni_tio_cmdtest
;
1167 s
->cancel
= ni_660x_cancel
;
1168 s
->poll
= ni_660x_input_poll
;
1169 s
->buf_change
= ni_660x_buf_change
;
1170 s
->async_dma_dir
= DMA_BIDIRECTIONAL
;
1171 s
->private = counter
;
1173 ni_tio_init_counter(counter
);
1175 s
->type
= COMEDI_SUBD_UNUSED
;
1180 * To be safe, set counterswap bits on tio chips after all the counter
1181 * outputs have been set to high impedance mode.
1183 for (i
= 0; i
< board
->n_chips
; ++i
)
1184 set_tio_counterswap(dev
, i
);
1186 ret
= request_irq(pcidev
->irq
, ni_660x_interrupt
, IRQF_SHARED
,
1187 dev
->board_name
, dev
);
1189 dev_warn(dev
->class_dev
, " irq not available\n");
1192 dev
->irq
= pcidev
->irq
;
1193 global_interrupt_config_bits
= NI660X_GLOBAL_INT_GLOBAL
;
1194 if (board
->n_chips
> 1)
1195 global_interrupt_config_bits
|= NI660X_GLOBAL_INT_CASCADE
;
1196 ni_660x_write(dev
, 0, global_interrupt_config_bits
,
1197 NI660X_GLOBAL_INT_CFG
);
1202 static void ni_660x_detach(struct comedi_device
*dev
)
1204 struct ni_660x_private
*devpriv
= dev
->private;
1207 ni_660x_write(dev
, 0, 0, NI660X_GLOBAL_INT_CFG
);
1208 free_irq(dev
->irq
, dev
);
1211 ni_gpct_device_destroy(devpriv
->counter_dev
);
1212 ni_660x_free_mite_rings(dev
);
1213 mite_detach(devpriv
->mite
);
1217 comedi_pci_disable(dev
);
1220 static struct comedi_driver ni_660x_driver
= {
1221 .driver_name
= "ni_660x",
1222 .module
= THIS_MODULE
,
1223 .auto_attach
= ni_660x_auto_attach
,
1224 .detach
= ni_660x_detach
,
1227 static int ni_660x_pci_probe(struct pci_dev
*dev
,
1228 const struct pci_device_id
*id
)
1230 return comedi_pci_auto_config(dev
, &ni_660x_driver
, id
->driver_data
);
1233 static const struct pci_device_id ni_660x_pci_table
[] = {
1234 { PCI_VDEVICE(NI
, 0x1310), BOARD_PCI6602
},
1235 { PCI_VDEVICE(NI
, 0x1360), BOARD_PXI6602
},
1236 { PCI_VDEVICE(NI
, 0x2c60), BOARD_PCI6601
},
1237 { PCI_VDEVICE(NI
, 0x2db0), BOARD_PCI6608
},
1238 { PCI_VDEVICE(NI
, 0x2cc0), BOARD_PXI6608
},
1239 { PCI_VDEVICE(NI
, 0x1e30), BOARD_PCI6624
},
1240 { PCI_VDEVICE(NI
, 0x1e40), BOARD_PXI6624
},
1243 MODULE_DEVICE_TABLE(pci
, ni_660x_pci_table
);
1245 static struct pci_driver ni_660x_pci_driver
= {
1247 .id_table
= ni_660x_pci_table
,
1248 .probe
= ni_660x_pci_probe
,
1249 .remove
= comedi_pci_auto_unconfig
,
1251 module_comedi_pci_driver(ni_660x_driver
, ni_660x_pci_driver
);
1253 MODULE_AUTHOR("Comedi https://www.comedi.org");
1254 MODULE_DESCRIPTION("Comedi driver for NI 660x counter/timer boards");
1255 MODULE_LICENSE("GPL");