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Merge branch 'stable/for-linus-4.11' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / ni_660x.c
1 /*
2 * Hardware driver for NI 660x devices
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 /*
16 * Driver: ni_660x
17 * Description: National Instruments 660x counter/timer boards
18 * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
19 * PXI-6608, PCI-6624, PXI-6624
20 * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
21 * Herman.Bruyninckx@mech.kuleuven.ac.be,
22 * Wim.Meeussen@mech.kuleuven.ac.be,
23 * Klaas.Gadeyne@mech.kuleuven.ac.be,
24 * Frank Mori Hess <fmhess@users.sourceforge.net>
25 * Updated: Mon, 16 Jan 2017 14:00:43 +0000
26 * Status: experimental
27 *
28 * Encoders work. PulseGeneration (both single pulse and pulse train)
29 * works. Buffered commands work for input but not output.
30 *
31 * References:
32 * DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
33 * DAQ 6601/6602 User Manual (NI 322137B-01)
34 */
35
36 #include <linux/module.h>
37 #include <linux/interrupt.h>
38
39 #include "../comedi_pci.h"
40
41 #include "mite.h"
42 #include "ni_tio.h"
43
44 /* See Register-Level Programmer Manual page 3.1 */
45 enum ni_660x_register {
46 /* see enum ni_gpct_register */
47 NI660X_STC_DIO_PARALLEL_INPUT = NITIO_NUM_REGS,
48 NI660X_STC_DIO_OUTPUT,
49 NI660X_STC_DIO_CONTROL,
50 NI660X_STC_DIO_SERIAL_INPUT,
51 NI660X_DIO32_INPUT,
52 NI660X_DIO32_OUTPUT,
53 NI660X_CLK_CFG,
54 NI660X_GLOBAL_INT_STATUS,
55 NI660X_DMA_CFG,
56 NI660X_GLOBAL_INT_CFG,
57 NI660X_IO_CFG_0_1,
58 NI660X_IO_CFG_2_3,
59 NI660X_IO_CFG_4_5,
60 NI660X_IO_CFG_6_7,
61 NI660X_IO_CFG_8_9,
62 NI660X_IO_CFG_10_11,
63 NI660X_IO_CFG_12_13,
64 NI660X_IO_CFG_14_15,
65 NI660X_IO_CFG_16_17,
66 NI660X_IO_CFG_18_19,
67 NI660X_IO_CFG_20_21,
68 NI660X_IO_CFG_22_23,
69 NI660X_IO_CFG_24_25,
70 NI660X_IO_CFG_26_27,
71 NI660X_IO_CFG_28_29,
72 NI660X_IO_CFG_30_31,
73 NI660X_IO_CFG_32_33,
74 NI660X_IO_CFG_34_35,
75 NI660X_IO_CFG_36_37,
76 NI660X_IO_CFG_38_39,
77 NI660X_NUM_REGS,
78 };
79
80 #define NI660X_CLK_CFG_COUNTER_SWAP BIT(21)
81
82 #define NI660X_GLOBAL_INT_COUNTER0 BIT(8)
83 #define NI660X_GLOBAL_INT_COUNTER1 BIT(9)
84 #define NI660X_GLOBAL_INT_COUNTER2 BIT(10)
85 #define NI660X_GLOBAL_INT_COUNTER3 BIT(11)
86 #define NI660X_GLOBAL_INT_CASCADE BIT(29)
87 #define NI660X_GLOBAL_INT_GLOBAL_POL BIT(30)
88 #define NI660X_GLOBAL_INT_GLOBAL BIT(31)
89
90 #define NI660X_DMA_CFG_SEL(_c, _s) (((_s) & 0x1f) << (8 * (_c)))
91 #define NI660X_DMA_CFG_SEL_MASK(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
92 #define NI660X_DMA_CFG_SEL_NONE(_c) NI660X_DMA_CFG_SEL((_c), 0x1f)
93 #define NI660X_DMA_CFG_RESET(_c) NI660X_DMA_CFG_SEL((_c), 0x80)
94
95 #define NI660X_IO_CFG(x) (NI660X_IO_CFG_0_1 + ((x) / 2))
96 #define NI660X_IO_CFG_OUT_SEL(_c, _s) (((_s) & 0x3) << (((_c) % 2) ? 0 : 8))
97 #define NI660X_IO_CFG_OUT_SEL_MASK(_c) NI660X_IO_CFG_OUT_SEL((_c), 0x3)
98 #define NI660X_IO_CFG_IN_SEL(_c, _s) (((_s) & 0x7) << (((_c) % 2) ? 4 : 12))
99 #define NI660X_IO_CFG_IN_SEL_MASK(_c) NI660X_IO_CFG_IN_SEL((_c), 0x7)
100
101 struct ni_660x_register_data {
102 int offset; /* Offset from base address from GPCT chip */
103 char size; /* 2 or 4 bytes */
104 };
105
106 static const struct ni_660x_register_data ni_660x_reg_data[NI660X_NUM_REGS] = {
107 [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */
108 [NITIO_G0_STATUS] = { 0x004, 2 }, /* read */
109 [NITIO_G1_INT_ACK] = { 0x006, 2 }, /* write */
110 [NITIO_G1_STATUS] = { 0x006, 2 }, /* read */
111 [NITIO_G01_STATUS] = { 0x008, 2 }, /* read */
112 [NITIO_G0_CMD] = { 0x00c, 2 }, /* write */
113 [NI660X_STC_DIO_PARALLEL_INPUT] = { 0x00e, 2 }, /* read */
114 [NITIO_G1_CMD] = { 0x00e, 2 }, /* write */
115 [NITIO_G0_HW_SAVE] = { 0x010, 4 }, /* read */
116 [NITIO_G1_HW_SAVE] = { 0x014, 4 }, /* read */
117 [NI660X_STC_DIO_OUTPUT] = { 0x014, 2 }, /* write */
118 [NI660X_STC_DIO_CONTROL] = { 0x016, 2 }, /* write */
119 [NITIO_G0_SW_SAVE] = { 0x018, 4 }, /* read */
120 [NITIO_G1_SW_SAVE] = { 0x01c, 4 }, /* read */
121 [NITIO_G0_MODE] = { 0x034, 2 }, /* write */
122 [NITIO_G01_STATUS1] = { 0x036, 2 }, /* read */
123 [NITIO_G1_MODE] = { 0x036, 2 }, /* write */
124 [NI660X_STC_DIO_SERIAL_INPUT] = { 0x038, 2 }, /* read */
125 [NITIO_G0_LOADA] = { 0x038, 4 }, /* write */
126 [NITIO_G01_STATUS2] = { 0x03a, 2 }, /* read */
127 [NITIO_G0_LOADB] = { 0x03c, 4 }, /* write */
128 [NITIO_G1_LOADA] = { 0x040, 4 }, /* write */
129 [NITIO_G1_LOADB] = { 0x044, 4 }, /* write */
130 [NITIO_G0_INPUT_SEL] = { 0x048, 2 }, /* write */
131 [NITIO_G1_INPUT_SEL] = { 0x04a, 2 }, /* write */
132 [NITIO_G0_AUTO_INC] = { 0x088, 2 }, /* write */
133 [NITIO_G1_AUTO_INC] = { 0x08a, 2 }, /* write */
134 [NITIO_G01_RESET] = { 0x090, 2 }, /* write */
135 [NITIO_G0_INT_ENA] = { 0x092, 2 }, /* write */
136 [NITIO_G1_INT_ENA] = { 0x096, 2 }, /* write */
137 [NITIO_G0_CNT_MODE] = { 0x0b0, 2 }, /* write */
138 [NITIO_G1_CNT_MODE] = { 0x0b2, 2 }, /* write */
139 [NITIO_G0_GATE2] = { 0x0b4, 2 }, /* write */
140 [NITIO_G1_GATE2] = { 0x0b6, 2 }, /* write */
141 [NITIO_G0_DMA_CFG] = { 0x0b8, 2 }, /* write */
142 [NITIO_G0_DMA_STATUS] = { 0x0b8, 2 }, /* read */
143 [NITIO_G1_DMA_CFG] = { 0x0ba, 2 }, /* write */
144 [NITIO_G1_DMA_STATUS] = { 0x0ba, 2 }, /* read */
145 [NITIO_G2_INT_ACK] = { 0x104, 2 }, /* write */
146 [NITIO_G2_STATUS] = { 0x104, 2 }, /* read */
147 [NITIO_G3_INT_ACK] = { 0x106, 2 }, /* write */
148 [NITIO_G3_STATUS] = { 0x106, 2 }, /* read */
149 [NITIO_G23_STATUS] = { 0x108, 2 }, /* read */
150 [NITIO_G2_CMD] = { 0x10c, 2 }, /* write */
151 [NITIO_G3_CMD] = { 0x10e, 2 }, /* write */
152 [NITIO_G2_HW_SAVE] = { 0x110, 4 }, /* read */
153 [NITIO_G3_HW_SAVE] = { 0x114, 4 }, /* read */
154 [NITIO_G2_SW_SAVE] = { 0x118, 4 }, /* read */
155 [NITIO_G3_SW_SAVE] = { 0x11c, 4 }, /* read */
156 [NITIO_G2_MODE] = { 0x134, 2 }, /* write */
157 [NITIO_G23_STATUS1] = { 0x136, 2 }, /* read */
158 [NITIO_G3_MODE] = { 0x136, 2 }, /* write */
159 [NITIO_G2_LOADA] = { 0x138, 4 }, /* write */
160 [NITIO_G23_STATUS2] = { 0x13a, 2 }, /* read */
161 [NITIO_G2_LOADB] = { 0x13c, 4 }, /* write */
162 [NITIO_G3_LOADA] = { 0x140, 4 }, /* write */
163 [NITIO_G3_LOADB] = { 0x144, 4 }, /* write */
164 [NITIO_G2_INPUT_SEL] = { 0x148, 2 }, /* write */
165 [NITIO_G3_INPUT_SEL] = { 0x14a, 2 }, /* write */
166 [NITIO_G2_AUTO_INC] = { 0x188, 2 }, /* write */
167 [NITIO_G3_AUTO_INC] = { 0x18a, 2 }, /* write */
168 [NITIO_G23_RESET] = { 0x190, 2 }, /* write */
169 [NITIO_G2_INT_ENA] = { 0x192, 2 }, /* write */
170 [NITIO_G3_INT_ENA] = { 0x196, 2 }, /* write */
171 [NITIO_G2_CNT_MODE] = { 0x1b0, 2 }, /* write */
172 [NITIO_G3_CNT_MODE] = { 0x1b2, 2 }, /* write */
173 [NITIO_G2_GATE2] = { 0x1b4, 2 }, /* write */
174 [NITIO_G3_GATE2] = { 0x1b6, 2 }, /* write */
175 [NITIO_G2_DMA_CFG] = { 0x1b8, 2 }, /* write */
176 [NITIO_G2_DMA_STATUS] = { 0x1b8, 2 }, /* read */
177 [NITIO_G3_DMA_CFG] = { 0x1ba, 2 }, /* write */
178 [NITIO_G3_DMA_STATUS] = { 0x1ba, 2 }, /* read */
179 [NI660X_DIO32_INPUT] = { 0x414, 4 }, /* read */
180 [NI660X_DIO32_OUTPUT] = { 0x510, 4 }, /* write */
181 [NI660X_CLK_CFG] = { 0x73c, 4 }, /* write */
182 [NI660X_GLOBAL_INT_STATUS] = { 0x754, 4 }, /* read */
183 [NI660X_DMA_CFG] = { 0x76c, 4 }, /* write */
184 [NI660X_GLOBAL_INT_CFG] = { 0x770, 4 }, /* write */
185 [NI660X_IO_CFG_0_1] = { 0x77c, 2 }, /* read/write */
186 [NI660X_IO_CFG_2_3] = { 0x77e, 2 }, /* read/write */
187 [NI660X_IO_CFG_4_5] = { 0x780, 2 }, /* read/write */
188 [NI660X_IO_CFG_6_7] = { 0x782, 2 }, /* read/write */
189 [NI660X_IO_CFG_8_9] = { 0x784, 2 }, /* read/write */
190 [NI660X_IO_CFG_10_11] = { 0x786, 2 }, /* read/write */
191 [NI660X_IO_CFG_12_13] = { 0x788, 2 }, /* read/write */
192 [NI660X_IO_CFG_14_15] = { 0x78a, 2 }, /* read/write */
193 [NI660X_IO_CFG_16_17] = { 0x78c, 2 }, /* read/write */
194 [NI660X_IO_CFG_18_19] = { 0x78e, 2 }, /* read/write */
195 [NI660X_IO_CFG_20_21] = { 0x790, 2 }, /* read/write */
196 [NI660X_IO_CFG_22_23] = { 0x792, 2 }, /* read/write */
197 [NI660X_IO_CFG_24_25] = { 0x794, 2 }, /* read/write */
198 [NI660X_IO_CFG_26_27] = { 0x796, 2 }, /* read/write */
199 [NI660X_IO_CFG_28_29] = { 0x798, 2 }, /* read/write */
200 [NI660X_IO_CFG_30_31] = { 0x79a, 2 }, /* read/write */
201 [NI660X_IO_CFG_32_33] = { 0x79c, 2 }, /* read/write */
202 [NI660X_IO_CFG_34_35] = { 0x79e, 2 }, /* read/write */
203 [NI660X_IO_CFG_36_37] = { 0x7a0, 2 }, /* read/write */
204 [NI660X_IO_CFG_38_39] = { 0x7a2, 2 } /* read/write */
205 };
206
207 #define NI660X_CHIP_OFFSET 0x800
208
209 enum ni_660x_boardid {
210 BOARD_PCI6601,
211 BOARD_PCI6602,
212 BOARD_PXI6602,
213 BOARD_PXI6608,
214 BOARD_PCI6624,
215 BOARD_PXI6624
216 };
217
218 struct ni_660x_board {
219 const char *name;
220 unsigned int n_chips; /* total number of TIO chips */
221 };
222
223 static const struct ni_660x_board ni_660x_boards[] = {
224 [BOARD_PCI6601] = {
225 .name = "PCI-6601",
226 .n_chips = 1,
227 },
228 [BOARD_PCI6602] = {
229 .name = "PCI-6602",
230 .n_chips = 2,
231 },
232 [BOARD_PXI6602] = {
233 .name = "PXI-6602",
234 .n_chips = 2,
235 },
236 [BOARD_PXI6608] = {
237 .name = "PXI-6608",
238 .n_chips = 2,
239 },
240 [BOARD_PCI6624] = {
241 .name = "PCI-6624",
242 .n_chips = 2,
243 },
244 [BOARD_PXI6624] = {
245 .name = "PXI-6624",
246 .n_chips = 2,
247 },
248 };
249
250 #define NI660X_NUM_PFI_CHANNELS 40
251
252 /* there are only up to 3 dma channels, but the register layout allows for 4 */
253 #define NI660X_MAX_DMA_CHANNEL 4
254
255 #define NI660X_COUNTERS_PER_CHIP 4
256 #define NI660X_MAX_CHIPS 2
257 #define NI660X_MAX_COUNTERS (NI660X_MAX_CHIPS * \
258 NI660X_COUNTERS_PER_CHIP)
259
260 struct ni_660x_private {
261 struct mite *mite;
262 struct ni_gpct_device *counter_dev;
263 struct mite_ring *ring[NI660X_MAX_CHIPS][NI660X_COUNTERS_PER_CHIP];
264 /* protects mite channel request/release */
265 spinlock_t mite_channel_lock;
266 /* prevents races between interrupt and comedi_poll */
267 spinlock_t interrupt_lock;
268 unsigned int dma_cfg[NI660X_MAX_CHIPS];
269 unsigned int io_cfg[NI660X_NUM_PFI_CHANNELS];
270 u64 io_dir;
271 };
272
273 static void ni_660x_write(struct comedi_device *dev, unsigned int chip,
274 unsigned int bits, unsigned int reg)
275 {
276 unsigned int addr = (chip * NI660X_CHIP_OFFSET) +
277 ni_660x_reg_data[reg].offset;
278
279 if (ni_660x_reg_data[reg].size == 2)
280 writew(bits, dev->mmio + addr);
281 else
282 writel(bits, dev->mmio + addr);
283 }
284
285 static unsigned int ni_660x_read(struct comedi_device *dev,
286 unsigned int chip, unsigned int reg)
287 {
288 unsigned int addr = (chip * NI660X_CHIP_OFFSET) +
289 ni_660x_reg_data[reg].offset;
290
291 if (ni_660x_reg_data[reg].size == 2)
292 return readw(dev->mmio + addr);
293 return readl(dev->mmio + addr);
294 }
295
296 static void ni_660x_gpct_write(struct ni_gpct *counter, unsigned int bits,
297 enum ni_gpct_register reg)
298 {
299 struct comedi_device *dev = counter->counter_dev->dev;
300
301 ni_660x_write(dev, counter->chip_index, bits, reg);
302 }
303
304 static unsigned int ni_660x_gpct_read(struct ni_gpct *counter,
305 enum ni_gpct_register reg)
306 {
307 struct comedi_device *dev = counter->counter_dev->dev;
308
309 return ni_660x_read(dev, counter->chip_index, reg);
310 }
311
312 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
313 unsigned int mite_channel,
314 struct ni_gpct *counter)
315 {
316 struct ni_660x_private *devpriv = dev->private;
317 unsigned int chip = counter->chip_index;
318
319 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
320 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL(mite_channel,
321 counter->counter_index);
322 ni_660x_write(dev, chip, devpriv->dma_cfg[chip] |
323 NI660X_DMA_CFG_RESET(mite_channel),
324 NI660X_DMA_CFG);
325 mmiowb();
326 }
327
328 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
329 unsigned int mite_channel,
330 struct ni_gpct *counter)
331 {
332 struct ni_660x_private *devpriv = dev->private;
333 unsigned int chip = counter->chip_index;
334
335 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
336 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(mite_channel);
337 ni_660x_write(dev, chip, devpriv->dma_cfg[chip], NI660X_DMA_CFG);
338 mmiowb();
339 }
340
341 static int ni_660x_request_mite_channel(struct comedi_device *dev,
342 struct ni_gpct *counter,
343 enum comedi_io_direction direction)
344 {
345 struct ni_660x_private *devpriv = dev->private;
346 struct mite_ring *ring;
347 struct mite_channel *mite_chan;
348 unsigned long flags;
349
350 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
351 ring = devpriv->ring[counter->chip_index][counter->counter_index];
352 mite_chan = mite_request_channel(devpriv->mite, ring);
353 if (!mite_chan) {
354 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
355 dev_err(dev->class_dev,
356 "failed to reserve mite dma channel for counter\n");
357 return -EBUSY;
358 }
359 mite_chan->dir = direction;
360 ni_tio_set_mite_channel(counter, mite_chan);
361 ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
362 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
363 return 0;
364 }
365
366 static void ni_660x_release_mite_channel(struct comedi_device *dev,
367 struct ni_gpct *counter)
368 {
369 struct ni_660x_private *devpriv = dev->private;
370 unsigned long flags;
371
372 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
373 if (counter->mite_chan) {
374 struct mite_channel *mite_chan = counter->mite_chan;
375
376 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
377 ni_tio_set_mite_channel(counter, NULL);
378 mite_release_channel(mite_chan);
379 }
380 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
381 }
382
383 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
384 {
385 struct ni_gpct *counter = s->private;
386 int retval;
387
388 retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
389 if (retval) {
390 dev_err(dev->class_dev,
391 "no dma channel available for use by counter\n");
392 return retval;
393 }
394 ni_tio_acknowledge(counter);
395
396 return ni_tio_cmd(dev, s);
397 }
398
399 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
400 {
401 struct ni_gpct *counter = s->private;
402 int retval;
403
404 retval = ni_tio_cancel(counter);
405 ni_660x_release_mite_channel(dev, counter);
406 return retval;
407 }
408
409 static void set_tio_counterswap(struct comedi_device *dev, int chip)
410 {
411 unsigned int bits = 0;
412
413 /*
414 * See P. 3.5 of the Register-Level Programming manual.
415 * The CounterSwap bit has to be set on the second chip,
416 * otherwise it will try to use the same pins as the
417 * first chip.
418 */
419 if (chip)
420 bits = NI660X_CLK_CFG_COUNTER_SWAP;
421
422 ni_660x_write(dev, chip, bits, NI660X_CLK_CFG);
423 }
424
425 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
426 struct comedi_subdevice *s)
427 {
428 struct ni_gpct *counter = s->private;
429
430 ni_tio_handle_interrupt(counter, s);
431 comedi_handle_events(dev, s);
432 }
433
434 static irqreturn_t ni_660x_interrupt(int irq, void *d)
435 {
436 struct comedi_device *dev = d;
437 struct ni_660x_private *devpriv = dev->private;
438 struct comedi_subdevice *s;
439 unsigned int i;
440 unsigned long flags;
441
442 if (!dev->attached)
443 return IRQ_NONE;
444 /* make sure dev->attached is checked before doing anything else */
445 smp_mb();
446
447 /* lock to avoid race with comedi_poll */
448 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
449 for (i = 0; i < dev->n_subdevices; ++i) {
450 s = &dev->subdevices[i];
451 if (s->type == COMEDI_SUBD_COUNTER)
452 ni_660x_handle_gpct_interrupt(dev, s);
453 }
454 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
455 return IRQ_HANDLED;
456 }
457
458 static int ni_660x_input_poll(struct comedi_device *dev,
459 struct comedi_subdevice *s)
460 {
461 struct ni_660x_private *devpriv = dev->private;
462 struct ni_gpct *counter = s->private;
463 unsigned long flags;
464
465 /* lock to avoid race with comedi_poll */
466 spin_lock_irqsave(&devpriv->interrupt_lock, flags);
467 mite_sync_dma(counter->mite_chan, s);
468 spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
469 return comedi_buf_read_n_available(s);
470 }
471
472 static int ni_660x_buf_change(struct comedi_device *dev,
473 struct comedi_subdevice *s)
474 {
475 struct ni_660x_private *devpriv = dev->private;
476 struct ni_gpct *counter = s->private;
477 struct mite_ring *ring;
478 int ret;
479
480 ring = devpriv->ring[counter->chip_index][counter->counter_index];
481 ret = mite_buf_change(ring, s);
482 if (ret < 0)
483 return ret;
484
485 return 0;
486 }
487
488 static int ni_660x_allocate_private(struct comedi_device *dev)
489 {
490 struct ni_660x_private *devpriv;
491 unsigned int i;
492
493 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
494 if (!devpriv)
495 return -ENOMEM;
496
497 spin_lock_init(&devpriv->mite_channel_lock);
498 spin_lock_init(&devpriv->interrupt_lock);
499 for (i = 0; i < NI660X_NUM_PFI_CHANNELS; ++i)
500 devpriv->io_cfg[i] = NI_660X_PFI_OUTPUT_COUNTER;
501
502 return 0;
503 }
504
505 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
506 {
507 const struct ni_660x_board *board = dev->board_ptr;
508 struct ni_660x_private *devpriv = dev->private;
509 unsigned int i;
510 unsigned int j;
511
512 for (i = 0; i < board->n_chips; ++i) {
513 for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j) {
514 devpriv->ring[i][j] = mite_alloc_ring(devpriv->mite);
515 if (!devpriv->ring[i][j])
516 return -ENOMEM;
517 }
518 }
519 return 0;
520 }
521
522 static void ni_660x_free_mite_rings(struct comedi_device *dev)
523 {
524 const struct ni_660x_board *board = dev->board_ptr;
525 struct ni_660x_private *devpriv = dev->private;
526 unsigned int i;
527 unsigned int j;
528
529 for (i = 0; i < board->n_chips; ++i) {
530 for (j = 0; j < NI660X_COUNTERS_PER_CHIP; ++j)
531 mite_free_ring(devpriv->ring[i][j]);
532 }
533 }
534
535 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
536 struct comedi_subdevice *s,
537 struct comedi_insn *insn,
538 unsigned int *data)
539 {
540 unsigned int shift = CR_CHAN(insn->chanspec);
541 unsigned int mask = data[0] << shift;
542 unsigned int bits = data[1] << shift;
543
544 /*
545 * There are 40 channels in this subdevice but only 32 are usable
546 * as DIO. The shift adjusts the mask/bits to account for the base
547 * channel in insn->chanspec. The state update can then be handled
548 * normally for the 32 usable channels.
549 */
550 if (mask) {
551 s->state &= ~mask;
552 s->state |= (bits & mask);
553 ni_660x_write(dev, 0, s->state, NI660X_DIO32_OUTPUT);
554 }
555
556 /*
557 * Return the input channels, shifted back to account for the base
558 * channel.
559 */
560 data[1] = ni_660x_read(dev, 0, NI660X_DIO32_INPUT) >> shift;
561
562 return insn->n;
563 }
564
565 static void ni_660x_select_pfi_output(struct comedi_device *dev,
566 unsigned int chan, unsigned int out_sel)
567 {
568 const struct ni_660x_board *board = dev->board_ptr;
569 unsigned int active_chip = 0;
570 unsigned int idle_chip = 0;
571 unsigned int bits;
572
573 if (board->n_chips > 1) {
574 if (out_sel == NI_660X_PFI_OUTPUT_COUNTER &&
575 chan >= 8 && chan <= 23) {
576 /* counters 4-7 pfi channels */
577 active_chip = 1;
578 idle_chip = 0;
579 } else {
580 /* counters 0-3 pfi channels */
581 active_chip = 0;
582 idle_chip = 1;
583 }
584 }
585
586 if (idle_chip != active_chip) {
587 /* set the pfi channel to high-z on the inactive chip */
588 bits = ni_660x_read(dev, idle_chip, NI660X_IO_CFG(chan));
589 bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan);
590 bits |= NI660X_IO_CFG_OUT_SEL(chan, 0); /* high-z */
591 ni_660x_write(dev, idle_chip, bits, NI660X_IO_CFG(chan));
592 }
593
594 /* set the pfi channel output on the active chip */
595 bits = ni_660x_read(dev, active_chip, NI660X_IO_CFG(chan));
596 bits &= ~NI660X_IO_CFG_OUT_SEL_MASK(chan);
597 bits |= NI660X_IO_CFG_OUT_SEL(chan, out_sel);
598 ni_660x_write(dev, active_chip, bits, NI660X_IO_CFG(chan));
599 }
600
601 static int ni_660x_set_pfi_routing(struct comedi_device *dev,
602 unsigned int chan, unsigned int source)
603 {
604 struct ni_660x_private *devpriv = dev->private;
605
606 switch (source) {
607 case NI_660X_PFI_OUTPUT_COUNTER:
608 if (chan < 8)
609 return -EINVAL;
610 break;
611 case NI_660X_PFI_OUTPUT_DIO:
612 if (chan > 31)
613 return -EINVAL;
614 default:
615 return -EINVAL;
616 }
617
618 devpriv->io_cfg[chan] = source;
619 if (devpriv->io_dir & (1ULL << chan))
620 ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]);
621 return 0;
622 }
623
624 static int ni_660x_dio_insn_config(struct comedi_device *dev,
625 struct comedi_subdevice *s,
626 struct comedi_insn *insn,
627 unsigned int *data)
628 {
629 struct ni_660x_private *devpriv = dev->private;
630 unsigned int chan = CR_CHAN(insn->chanspec);
631 u64 bit = 1ULL << chan;
632 unsigned int val;
633 int ret;
634
635 switch (data[0]) {
636 case INSN_CONFIG_DIO_OUTPUT:
637 devpriv->io_dir |= bit;
638 ni_660x_select_pfi_output(dev, chan, devpriv->io_cfg[chan]);
639 break;
640
641 case INSN_CONFIG_DIO_INPUT:
642 devpriv->io_dir &= ~bit;
643 ni_660x_select_pfi_output(dev, chan, 0); /* high-z */
644 break;
645
646 case INSN_CONFIG_DIO_QUERY:
647 data[1] = (devpriv->io_dir & bit) ? COMEDI_OUTPUT
648 : COMEDI_INPUT;
649 break;
650
651 case INSN_CONFIG_SET_ROUTING:
652 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
653 if (ret)
654 return ret;
655 break;
656
657 case INSN_CONFIG_GET_ROUTING:
658 data[1] = devpriv->io_cfg[chan];
659 break;
660
661 case INSN_CONFIG_FILTER:
662 val = ni_660x_read(dev, 0, NI660X_IO_CFG(chan));
663 val &= ~NI660X_IO_CFG_IN_SEL_MASK(chan);
664 val |= NI660X_IO_CFG_IN_SEL(chan, data[1]);
665 ni_660x_write(dev, 0, val, NI660X_IO_CFG(chan));
666 break;
667
668 default:
669 return -EINVAL;
670 }
671
672 return insn->n;
673 }
674
675 static void ni_660x_init_tio_chips(struct comedi_device *dev,
676 unsigned int n_chips)
677 {
678 struct ni_660x_private *devpriv = dev->private;
679 unsigned int chip;
680 unsigned int chan;
681
682 /*
683 * We use the ioconfig registers to control dio direction, so zero
684 * output enables in stc dio control reg.
685 */
686 ni_660x_write(dev, 0, 0, NI660X_STC_DIO_CONTROL);
687
688 for (chip = 0; chip < n_chips; ++chip) {
689 /* init dma configuration register */
690 devpriv->dma_cfg[chip] = 0;
691 for (chan = 0; chan < NI660X_MAX_DMA_CHANNEL; ++chan)
692 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(chan);
693 ni_660x_write(dev, chip, devpriv->dma_cfg[chip],
694 NI660X_DMA_CFG);
695
696 /* init ioconfig registers */
697 for (chan = 0; chan < NI660X_NUM_PFI_CHANNELS; ++chan)
698 ni_660x_write(dev, chip, 0, NI660X_IO_CFG(chan));
699 }
700 }
701
702 static int ni_660x_auto_attach(struct comedi_device *dev,
703 unsigned long context)
704 {
705 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
706 const struct ni_660x_board *board = NULL;
707 struct ni_660x_private *devpriv;
708 struct comedi_subdevice *s;
709 struct ni_gpct_device *gpct_dev;
710 unsigned int n_counters;
711 int subdev;
712 int ret;
713 unsigned int i;
714 unsigned int global_interrupt_config_bits;
715
716 if (context < ARRAY_SIZE(ni_660x_boards))
717 board = &ni_660x_boards[context];
718 if (!board)
719 return -ENODEV;
720 dev->board_ptr = board;
721 dev->board_name = board->name;
722
723 ret = comedi_pci_enable(dev);
724 if (ret)
725 return ret;
726
727 ret = ni_660x_allocate_private(dev);
728 if (ret < 0)
729 return ret;
730 devpriv = dev->private;
731
732 devpriv->mite = mite_attach(dev, true); /* use win1 */
733 if (!devpriv->mite)
734 return -ENOMEM;
735
736 ret = ni_660x_alloc_mite_rings(dev);
737 if (ret < 0)
738 return ret;
739
740 ni_660x_init_tio_chips(dev, board->n_chips);
741
742 n_counters = board->n_chips * NI660X_COUNTERS_PER_CHIP;
743 gpct_dev = ni_gpct_device_construct(dev,
744 ni_660x_gpct_write,
745 ni_660x_gpct_read,
746 ni_gpct_variant_660x,
747 n_counters);
748 if (!gpct_dev)
749 return -ENOMEM;
750 devpriv->counter_dev = gpct_dev;
751
752 ret = comedi_alloc_subdevices(dev, 2 + NI660X_MAX_COUNTERS);
753 if (ret)
754 return ret;
755
756 subdev = 0;
757
758 s = &dev->subdevices[subdev++];
759 /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
760 s->type = COMEDI_SUBD_UNUSED;
761
762 /*
763 * Digital I/O subdevice
764 *
765 * There are 40 channels but only the first 32 can be digital I/Os.
766 * The last 8 are dedicated to counters 0 and 1.
767 *
768 * Counter 0-3 signals are from the first TIO chip.
769 * Counter 4-7 signals are from the second TIO chip.
770 *
771 * Comedi External
772 * PFI Chan DIO Chan Counter Signal
773 * ------- -------- --------------
774 * 0 0
775 * 1 1
776 * 2 2
777 * 3 3
778 * 4 4
779 * 5 5
780 * 6 6
781 * 7 7
782 * 8 8 CTR 7 OUT
783 * 9 9 CTR 7 AUX
784 * 10 10 CTR 7 GATE
785 * 11 11 CTR 7 SOURCE
786 * 12 12 CTR 6 OUT
787 * 13 13 CTR 6 AUX
788 * 14 14 CTR 6 GATE
789 * 15 15 CTR 6 SOURCE
790 * 16 16 CTR 5 OUT
791 * 17 17 CTR 5 AUX
792 * 18 18 CTR 5 GATE
793 * 19 19 CTR 5 SOURCE
794 * 20 20 CTR 4 OUT
795 * 21 21 CTR 4 AUX
796 * 22 22 CTR 4 GATE
797 * 23 23 CTR 4 SOURCE
798 * 24 24 CTR 3 OUT
799 * 25 25 CTR 3 AUX
800 * 26 26 CTR 3 GATE
801 * 27 27 CTR 3 SOURCE
802 * 28 28 CTR 2 OUT
803 * 29 29 CTR 2 AUX
804 * 30 30 CTR 2 GATE
805 * 31 31 CTR 2 SOURCE
806 * 32 CTR 1 OUT
807 * 33 CTR 1 AUX
808 * 34 CTR 1 GATE
809 * 35 CTR 1 SOURCE
810 * 36 CTR 0 OUT
811 * 37 CTR 0 AUX
812 * 38 CTR 0 GATE
813 * 39 CTR 0 SOURCE
814 */
815 s = &dev->subdevices[subdev++];
816 s->type = COMEDI_SUBD_DIO;
817 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
818 s->n_chan = NI660X_NUM_PFI_CHANNELS;
819 s->maxdata = 1;
820 s->range_table = &range_digital;
821 s->insn_bits = ni_660x_dio_insn_bits;
822 s->insn_config = ni_660x_dio_insn_config;
823
824 /*
825 * Default the DIO channels as:
826 * chan 0-7: DIO inputs
827 * chan 8-39: counter signal inputs
828 */
829 for (i = 0; i < s->n_chan; ++i) {
830 unsigned int source = (i < 8) ? NI_660X_PFI_OUTPUT_DIO
831 : NI_660X_PFI_OUTPUT_COUNTER;
832
833 ni_660x_set_pfi_routing(dev, i, source);
834 ni_660x_select_pfi_output(dev, i, 0); /* high-z */
835 }
836
837 /* Counter subdevices (4 NI TIO General Purpose Counters per chip) */
838 for (i = 0; i < NI660X_MAX_COUNTERS; ++i) {
839 s = &dev->subdevices[subdev++];
840 if (i < n_counters) {
841 struct ni_gpct *counter = &gpct_dev->counters[i];
842
843 counter->chip_index = i / NI660X_COUNTERS_PER_CHIP;
844 counter->counter_index = i % NI660X_COUNTERS_PER_CHIP;
845
846 s->type = COMEDI_SUBD_COUNTER;
847 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
848 SDF_LSAMPL | SDF_CMD_READ;
849 s->n_chan = 3;
850 s->maxdata = 0xffffffff;
851 s->insn_read = ni_tio_insn_read;
852 s->insn_write = ni_tio_insn_write;
853 s->insn_config = ni_tio_insn_config;
854 s->len_chanlist = 1;
855 s->do_cmd = ni_660x_cmd;
856 s->do_cmdtest = ni_tio_cmdtest;
857 s->cancel = ni_660x_cancel;
858 s->poll = ni_660x_input_poll;
859 s->buf_change = ni_660x_buf_change;
860 s->async_dma_dir = DMA_BIDIRECTIONAL;
861 s->private = counter;
862
863 ni_tio_init_counter(counter);
864 } else {
865 s->type = COMEDI_SUBD_UNUSED;
866 }
867 }
868
869 /*
870 * To be safe, set counterswap bits on tio chips after all the counter
871 * outputs have been set to high impedance mode.
872 */
873 for (i = 0; i < board->n_chips; ++i)
874 set_tio_counterswap(dev, i);
875
876 ret = request_irq(pcidev->irq, ni_660x_interrupt, IRQF_SHARED,
877 dev->board_name, dev);
878 if (ret < 0) {
879 dev_warn(dev->class_dev, " irq not available\n");
880 return ret;
881 }
882 dev->irq = pcidev->irq;
883 global_interrupt_config_bits = NI660X_GLOBAL_INT_GLOBAL;
884 if (board->n_chips > 1)
885 global_interrupt_config_bits |= NI660X_GLOBAL_INT_CASCADE;
886 ni_660x_write(dev, 0, global_interrupt_config_bits,
887 NI660X_GLOBAL_INT_CFG);
888
889 return 0;
890 }
891
892 static void ni_660x_detach(struct comedi_device *dev)
893 {
894 struct ni_660x_private *devpriv = dev->private;
895
896 if (dev->irq) {
897 ni_660x_write(dev, 0, 0, NI660X_GLOBAL_INT_CFG);
898 free_irq(dev->irq, dev);
899 }
900 if (devpriv) {
901 ni_gpct_device_destroy(devpriv->counter_dev);
902 ni_660x_free_mite_rings(dev);
903 mite_detach(devpriv->mite);
904 }
905 if (dev->mmio)
906 iounmap(dev->mmio);
907 comedi_pci_disable(dev);
908 }
909
910 static struct comedi_driver ni_660x_driver = {
911 .driver_name = "ni_660x",
912 .module = THIS_MODULE,
913 .auto_attach = ni_660x_auto_attach,
914 .detach = ni_660x_detach,
915 };
916
917 static int ni_660x_pci_probe(struct pci_dev *dev,
918 const struct pci_device_id *id)
919 {
920 return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data);
921 }
922
923 static const struct pci_device_id ni_660x_pci_table[] = {
924 { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 },
925 { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 },
926 { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 },
927 { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 },
928 { PCI_VDEVICE(NI, 0x1e30), BOARD_PCI6624 },
929 { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 },
930 { 0 }
931 };
932 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
933
934 static struct pci_driver ni_660x_pci_driver = {
935 .name = "ni_660x",
936 .id_table = ni_660x_pci_table,
937 .probe = ni_660x_pci_probe,
938 .remove = comedi_pci_auto_unconfig,
939 };
940 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
941
942 MODULE_AUTHOR("Comedi http://www.comedi.org");
943 MODULE_DESCRIPTION("Comedi driver for NI 660x counter/timer boards");
944 MODULE_LICENSE("GPL");
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