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[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / comedi / drivers / ni_atmio16d.c
1 /*
2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 */
21 /*
22 Driver: ni_atmio16d
23 Description: National Instruments AT-MIO-16D
24 Author: Chris R. Baugher <baugher@enteract.com>
25 Status: unknown
26 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
27 */
28 /*
29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
31 * handling code from his driver as an example for this one.
32 *
33 * Chris Baugher
34 * 5/1/2000
35 *
36 */
37
38 #include "../comedidev.h"
39
40 #include <linux/ioport.h>
41
42 #include "8255.h"
43
44 /* Configuration and Status Registers */
45 #define COM_REG_1 0x00 /* wo 16 */
46 #define STAT_REG 0x00 /* ro 16 */
47 #define COM_REG_2 0x02 /* wo 16 */
48 /* Event Strobe Registers */
49 #define START_CONVERT_REG 0x08 /* wo 16 */
50 #define START_DAQ_REG 0x0A /* wo 16 */
51 #define AD_CLEAR_REG 0x0C /* wo 16 */
52 #define EXT_STROBE_REG 0x0E /* wo 16 */
53 /* Analog Output Registers */
54 #define DAC0_REG 0x10 /* wo 16 */
55 #define DAC1_REG 0x12 /* wo 16 */
56 #define INT2CLR_REG 0x14 /* wo 16 */
57 /* Analog Input Registers */
58 #define MUX_CNTR_REG 0x04 /* wo 16 */
59 #define MUX_GAIN_REG 0x06 /* wo 16 */
60 #define AD_FIFO_REG 0x16 /* ro 16 */
61 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
62 /* AM9513A Counter/Timer Registers */
63 #define AM9513A_DATA_REG 0x18 /* rw 16 */
64 #define AM9513A_COM_REG 0x1A /* wo 16 */
65 #define AM9513A_STAT_REG 0x1A /* ro 16 */
66 /* MIO-16 Digital I/O Registers */
67 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
68 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
69 /* RTSI Switch Registers */
70 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
71 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
72 /* DIO-24 Registers */
73 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
74 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
75 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
76 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
77
78 /* Command Register bits */
79 #define COMREG1_2SCADC 0x0001
80 #define COMREG1_1632CNT 0x0002
81 #define COMREG1_SCANEN 0x0008
82 #define COMREG1_DAQEN 0x0010
83 #define COMREG1_DMAEN 0x0020
84 #define COMREG1_CONVINTEN 0x0080
85 #define COMREG2_SCN2 0x0010
86 #define COMREG2_INTEN 0x0080
87 #define COMREG2_DOUTEN0 0x0100
88 #define COMREG2_DOUTEN1 0x0200
89 /* Status Register bits */
90 #define STAT_AD_OVERRUN 0x0100
91 #define STAT_AD_OVERFLOW 0x0200
92 #define STAT_AD_DAQPROG 0x0800
93 #define STAT_AD_CONVAVAIL 0x2000
94 #define STAT_AD_DAQSTOPINT 0x4000
95 /* AM9513A Counter/Timer defines */
96 #define CLOCK_1_MHZ 0x8B25
97 #define CLOCK_100_KHZ 0x8C25
98 #define CLOCK_10_KHZ 0x8D25
99 #define CLOCK_1_KHZ 0x8E25
100 #define CLOCK_100_HZ 0x8F25
101 /* Other miscellaneous defines */
102 #define ATMIO16D_SIZE 32 /* bus address range */
103 #define devpriv ((struct atmio16d_private *)dev->private)
104 #define ATMIO16D_TIMEOUT 10
105
106 struct atmio16_board_t {
107
108 const char *name;
109 int has_8255;
110 };
111
112 static const struct atmio16_board_t atmio16_boards[] = {
113 {
114 name: "atmio16",
115 has_8255:0,
116 },
117 {
118 name: "atmio16d",
119 has_8255:1,
120 },
121 };
122
123 #define n_atmio16_boards sizeof(atmio16_boards)/sizeof(atmio16_boards[0])
124
125 #define boardtype ((const struct atmio16_board_t *)dev->board_ptr)
126
127 /* function prototypes */
128 static int atmio16d_attach(struct comedi_device * dev, struct comedi_devconfig * it);
129 static int atmio16d_detach(struct comedi_device * dev);
130 static irqreturn_t atmio16d_interrupt(int irq, void *d);
131 static int atmio16d_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
132 struct comedi_cmd * cmd);
133 static int atmio16d_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
134 static int atmio16d_ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
135 static void reset_counters(struct comedi_device * dev);
136 static void reset_atmio16d(struct comedi_device * dev);
137
138 /* main driver struct */
139 static struct comedi_driver driver_atmio16d = {
140 driver_name:"atmio16",
141 module:THIS_MODULE,
142 attach:atmio16d_attach,
143 detach:atmio16d_detach,
144 board_name:&atmio16_boards[0].name,
145 num_names:n_atmio16_boards,
146 offset:sizeof(struct atmio16_board_t),
147 };
148
149 COMEDI_INITCLEANUP(driver_atmio16d);
150
151 /* range structs */
152 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
153 BIP_RANGE(10),
154 BIP_RANGE(1),
155 BIP_RANGE(0.1),
156 BIP_RANGE(0.02)
157 }
158 };
159
160 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
161 BIP_RANGE(5),
162 BIP_RANGE(0.5),
163 BIP_RANGE(0.05),
164 BIP_RANGE(0.01)
165 }
166 };
167
168 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
169 UNI_RANGE(10),
170 UNI_RANGE(1),
171 UNI_RANGE(0.1),
172 UNI_RANGE(0.02)
173 }
174 };
175
176 /* private data struct */
177 struct atmio16d_private {
178 enum { adc_diff, adc_singleended } adc_mux;
179 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
180 enum { adc_2comp, adc_straight } adc_coding;
181 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
182 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
183 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
184 const struct comedi_lrange *ao_range_type_list[2];
185 unsigned int ao_readback[2];
186 unsigned int com_reg_1_state; /* current state of command register 1 */
187 unsigned int com_reg_2_state; /* current state of command register 2 */
188 };
189
190 static void reset_counters(struct comedi_device * dev)
191 {
192 /* Counter 2 */
193 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
194 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
195 outw(0x4, dev->iobase + AM9513A_DATA_REG);
196 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
197 outw(0x3, dev->iobase + AM9513A_DATA_REG);
198 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
199 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
200 /* Counter 3 */
201 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
202 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
203 outw(0x4, dev->iobase + AM9513A_DATA_REG);
204 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
205 outw(0x3, dev->iobase + AM9513A_DATA_REG);
206 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
207 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
208 /* Counter 4 */
209 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
210 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
211 outw(0x4, dev->iobase + AM9513A_DATA_REG);
212 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
213 outw(0x3, dev->iobase + AM9513A_DATA_REG);
214 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
215 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
216 /* Counter 5 */
217 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
218 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
219 outw(0x4, dev->iobase + AM9513A_DATA_REG);
220 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
221 outw(0x3, dev->iobase + AM9513A_DATA_REG);
222 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
223 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
224
225 outw(0, dev->iobase + AD_CLEAR_REG);
226 }
227
228 static void reset_atmio16d(struct comedi_device * dev)
229 {
230 int i;
231
232 /* now we need to initialize the board */
233 outw(0, dev->iobase + COM_REG_1);
234 outw(0, dev->iobase + COM_REG_2);
235 outw(0, dev->iobase + MUX_GAIN_REG);
236 /* init AM9513A timer */
237 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
238 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
239 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
240 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
241 for (i = 1; i <= 5; ++i) {
242 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
243 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
244 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
245 outw(0x3, dev->iobase + AM9513A_DATA_REG);
246 }
247 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
248 /* timer init done */
249 outw(0, dev->iobase + AD_CLEAR_REG);
250 outw(0, dev->iobase + INT2CLR_REG);
251 /* select straight binary mode for Analog Input */
252 devpriv->com_reg_1_state |= 1;
253 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
254 devpriv->adc_coding = adc_straight;
255 /* zero the analog outputs */
256 outw(2048, dev->iobase + DAC0_REG);
257 outw(2048, dev->iobase + DAC1_REG);
258 }
259
260 static irqreturn_t atmio16d_interrupt(int irq, void *d)
261 {
262 struct comedi_device *dev = d;
263 struct comedi_subdevice *s = dev->subdevices + 0;
264
265 /* printk("atmio16d_interrupt!\n"); */
266
267 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
268
269 comedi_event(dev, s);
270 return IRQ_HANDLED;
271 }
272
273 static int atmio16d_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
274 struct comedi_cmd * cmd)
275 {
276 int err = 0, tmp;
277 #ifdef DEBUG1
278 printk("atmio16d_ai_cmdtest\n");
279 #endif
280 /* make sure triggers are valid */
281 tmp = cmd->start_src;
282 cmd->start_src &= TRIG_NOW;
283 if (!cmd->start_src || tmp != cmd->start_src)
284 err++;
285
286 tmp = cmd->scan_begin_src;
287 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER;
288 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
289 err++;
290
291 tmp = cmd->convert_src;
292 cmd->convert_src &= TRIG_TIMER;
293 if (!cmd->convert_src || tmp != cmd->convert_src)
294 err++;
295
296 tmp = cmd->scan_end_src;
297 cmd->scan_end_src &= TRIG_COUNT;
298 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
299 err++;
300
301 tmp = cmd->stop_src;
302 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
303 if (!cmd->stop_src || tmp != cmd->stop_src)
304 err++;
305
306 if (err)
307 return 1;
308
309 /* step 2: make sure trigger sources are unique and mutually compatible */
310 /* note that mutual compatiblity is not an issue here */
311 if (cmd->scan_begin_src != TRIG_FOLLOW &&
312 cmd->scan_begin_src != TRIG_EXT &&
313 cmd->scan_begin_src != TRIG_TIMER)
314 err++;
315 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
316 err++;
317
318 if (err)
319 return 2;
320
321 /* step 3: make sure arguments are trivially compatible */
322
323 if (cmd->start_arg != 0) {
324 cmd->start_arg = 0;
325 err++;
326 }
327 if (cmd->scan_begin_src == TRIG_FOLLOW) {
328 /* internal trigger */
329 if (cmd->scan_begin_arg != 0) {
330 cmd->scan_begin_arg = 0;
331 err++;
332 }
333 } else {
334 #if 0
335 /* external trigger */
336 /* should be level/edge, hi/lo specification here */
337 if (cmd->scan_begin_arg != 0) {
338 cmd->scan_begin_arg = 0;
339 err++;
340 }
341 #endif
342 }
343
344 if (cmd->convert_arg < 10000) {
345 cmd->convert_arg = 10000;
346 err++;
347 }
348 #if 0
349 if (cmd->convert_arg > SLOWEST_TIMER) {
350 cmd->convert_arg = SLOWEST_TIMER;
351 err++;
352 }
353 #endif
354 if (cmd->scan_end_arg != cmd->chanlist_len) {
355 cmd->scan_end_arg = cmd->chanlist_len;
356 err++;
357 }
358 if (cmd->stop_src == TRIG_COUNT) {
359 /* any count is allowed */
360 } else {
361 /* TRIG_NONE */
362 if (cmd->stop_arg != 0) {
363 cmd->stop_arg = 0;
364 err++;
365 }
366 }
367
368 if (err)
369 return 3;
370
371 return 0;
372 }
373
374 static int atmio16d_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
375 {
376 struct comedi_cmd *cmd = &s->async->cmd;
377 unsigned int timer, base_clock;
378 unsigned int sample_count, tmp, chan, gain;
379 int i;
380 #ifdef DEBUG1
381 printk("atmio16d_ai_cmd\n");
382 #endif
383 /* This is slowly becoming a working command interface. *
384 * It is still uber-experimental */
385
386 reset_counters(dev);
387 s->async->cur_chan = 0;
388
389 /* check if scanning multiple channels */
390 if (cmd->chanlist_len < 2) {
391 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
392 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
393 } else {
394 devpriv->com_reg_1_state |= COMREG1_SCANEN;
395 devpriv->com_reg_2_state |= COMREG2_SCN2;
396 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
397 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
398 }
399
400 /* Setup the Mux-Gain Counter */
401 for (i = 0; i < cmd->chanlist_len; ++i) {
402 chan = CR_CHAN(cmd->chanlist[i]);
403 gain = CR_RANGE(cmd->chanlist[i]);
404 outw(i, dev->iobase + MUX_CNTR_REG);
405 tmp = chan | (gain << 6);
406 if (i == cmd->scan_end_arg - 1)
407 tmp |= 0x0010; /* set LASTONE bit */
408 outw(tmp, dev->iobase + MUX_GAIN_REG);
409 }
410
411 /* Now program the sample interval timer */
412 /* Figure out which clock to use then get an
413 * appropriate timer value */
414 if (cmd->convert_arg < 65536000) {
415 base_clock = CLOCK_1_MHZ;
416 timer = cmd->convert_arg / 1000;
417 } else if (cmd->convert_arg < 655360000) {
418 base_clock = CLOCK_100_KHZ;
419 timer = cmd->convert_arg / 10000;
420 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */ ) {
421 base_clock = CLOCK_10_KHZ;
422 timer = cmd->convert_arg / 100000;
423 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */ ) {
424 base_clock = CLOCK_1_KHZ;
425 timer = cmd->convert_arg / 1000000;
426 }
427 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
428 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
429 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
430 outw(0x2, dev->iobase + AM9513A_DATA_REG);
431 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
432 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
433 outw(timer, dev->iobase + AM9513A_DATA_REG);
434 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
435
436 /* Now figure out how many samples to get */
437 /* and program the sample counter */
438 sample_count = cmd->stop_arg * cmd->scan_end_arg;
439 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
440 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
441 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
442 if (sample_count < 65536) {
443 /* use only Counter 4 */
444 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
445 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
446 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
447 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
448 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
449 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
450 } else {
451 /* Counter 4 and 5 are needed */
452 if ((tmp = sample_count & 0xFFFF)) {
453 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
454 } else {
455 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
456 }
457 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
458 outw(0, dev->iobase + AM9513A_DATA_REG);
459 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
460 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
461 outw(0x25, dev->iobase + AM9513A_DATA_REG);
462 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
463 tmp = sample_count & 0xFFFF;
464 if ((tmp == 0) || (tmp == 1)) {
465 outw((sample_count >> 16) & 0xFFFF,
466 dev->iobase + AM9513A_DATA_REG);
467 } else {
468 outw(((sample_count >> 16) & 0xFFFF) + 1,
469 dev->iobase + AM9513A_DATA_REG);
470 }
471 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
472 devpriv->com_reg_1_state |= COMREG1_1632CNT;
473 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
474 }
475
476 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
477 /* Figure out which clock to use then get an
478 * appropriate timer value */
479 if (cmd->chanlist_len > 1) {
480 if (cmd->scan_begin_arg < 65536000) {
481 base_clock = CLOCK_1_MHZ;
482 timer = cmd->scan_begin_arg / 1000;
483 } else if (cmd->scan_begin_arg < 655360000) {
484 base_clock = CLOCK_100_KHZ;
485 timer = cmd->scan_begin_arg / 10000;
486 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */ ) {
487 base_clock = CLOCK_10_KHZ;
488 timer = cmd->scan_begin_arg / 100000;
489 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */ ) {
490 base_clock = CLOCK_1_KHZ;
491 timer = cmd->scan_begin_arg / 1000000;
492 }
493 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
494 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
495 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
496 outw(0x2, dev->iobase + AM9513A_DATA_REG);
497 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
498 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
499 outw(timer, dev->iobase + AM9513A_DATA_REG);
500 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
501 }
502
503 /* Clear the A/D FIFO and reset the MUX counter */
504 outw(0, dev->iobase + AD_CLEAR_REG);
505 outw(0, dev->iobase + MUX_CNTR_REG);
506 outw(0, dev->iobase + INT2CLR_REG);
507 /* enable this acquisition operation */
508 devpriv->com_reg_1_state |= COMREG1_DAQEN;
509 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
510 /* enable interrupts for conversion completion */
511 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
512 devpriv->com_reg_2_state |= COMREG2_INTEN;
513 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
514 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
515 /* apply a trigger. this starts the counters! */
516 outw(0, dev->iobase + START_DAQ_REG);
517
518 return 0;
519 }
520
521 /* This will cancel a running acquisition operation */
522 static int atmio16d_ai_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
523 {
524 reset_atmio16d(dev);
525
526 return 0;
527 }
528
529 /* Mode 0 is used to get a single conversion on demand */
530 static int atmio16d_ai_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
531 struct comedi_insn * insn, unsigned int * data)
532 {
533 int i, t;
534 int chan;
535 int gain;
536 int status;
537
538 #ifdef DEBUG1
539 printk("atmio16d_ai_insn_read\n");
540 #endif
541 chan = CR_CHAN(insn->chanspec);
542 gain = CR_RANGE(insn->chanspec);
543
544 /* reset the Analog input circuitry */
545 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
546 /* reset the Analog Input MUX Counter to 0 */
547 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
548
549 /* set the Input MUX gain */
550 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
551
552 for (i = 0; i < insn->n; i++) {
553 /* start the conversion */
554 outw(0, dev->iobase + START_CONVERT_REG);
555 /* wait for it to finish */
556 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
557 /* check conversion status */
558 status = inw(dev->iobase + STAT_REG);
559 #ifdef DEBUG1
560 printk("status=%x\n", status);
561 #endif
562 if (status & STAT_AD_CONVAVAIL) {
563 /* read the data now */
564 data[i] = inw(dev->iobase + AD_FIFO_REG);
565 /* change to two's complement if need be */
566 if (devpriv->adc_coding == adc_2comp) {
567 data[i] ^= 0x800;
568 }
569 break;
570 }
571 if (status & STAT_AD_OVERFLOW) {
572 printk("atmio16d: a/d FIFO overflow\n");
573 outw(0, dev->iobase + AD_CLEAR_REG);
574
575 return -ETIME;
576 }
577 }
578 /* end waiting, now check if it timed out */
579 if (t == ATMIO16D_TIMEOUT) {
580 rt_printk("atmio16d: timeout\n");
581
582 return -ETIME;
583 }
584 }
585
586 return i;
587 }
588
589 static int atmio16d_ao_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
590 struct comedi_insn * insn, unsigned int * data)
591 {
592 int i;
593 #ifdef DEBUG1
594 printk("atmio16d_ao_insn_read\n");
595 #endif
596
597 for (i = 0; i < insn->n; i++) {
598 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
599 }
600
601 return i;
602 }
603
604 static int atmio16d_ao_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
605 struct comedi_insn * insn, unsigned int * data)
606 {
607 int i;
608 int chan;
609 int d;
610 #ifdef DEBUG1
611 printk("atmio16d_ao_insn_write\n");
612 #endif
613
614 chan = CR_CHAN(insn->chanspec);
615
616 for (i = 0; i < insn->n; i++) {
617 d = data[i];
618 switch (chan) {
619 case 0:
620 if (devpriv->dac0_coding == dac_2comp) {
621 d ^= 0x800;
622 }
623 outw(d, dev->iobase + DAC0_REG);
624 break;
625 case 1:
626 if (devpriv->dac1_coding == dac_2comp) {
627 d ^= 0x800;
628 }
629 outw(d, dev->iobase + DAC1_REG);
630 break;
631 default:
632 return -EINVAL;
633 }
634 devpriv->ao_readback[chan] = data[i];
635 }
636 return i;
637 }
638
639 static int atmio16d_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
640 struct comedi_insn * insn, unsigned int * data)
641 {
642 if (insn->n != 2)
643 return -EINVAL;
644
645 if (data[0]) {
646 s->state &= ~data[0];
647 s->state |= (data[0] | data[1]);
648 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
649 }
650 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
651
652 return 2;
653 }
654
655 static int atmio16d_dio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
656 struct comedi_insn * insn, unsigned int * data)
657 {
658 int i;
659 int mask;
660
661 for (i = 0; i < insn->n; i++) {
662 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
663 s->io_bits &= ~mask;
664 if (data[i])
665 s->io_bits |= mask;
666 }
667 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
668 if (s->io_bits & 0x0f)
669 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
670 if (s->io_bits & 0xf0)
671 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
672 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
673
674 return i;
675 }
676
677 /*
678 options[0] - I/O port
679 options[1] - MIO irq
680 0 == no irq
681 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
682 options[2] - DIO irq
683 0 == no irq
684 N == irq N {3,4,5,6,7,9}
685 options[3] - DMA1 channel
686 0 == no DMA
687 N == DMA N {5,6,7}
688 options[4] - DMA2 channel
689 0 == no DMA
690 N == DMA N {5,6,7}
691
692 options[5] - a/d mux
693 0=differential, 1=single
694 options[6] - a/d range
695 0=bipolar10, 1=bipolar5, 2=unipolar10
696
697 options[7] - dac0 range
698 0=bipolar, 1=unipolar
699 options[8] - dac0 reference
700 0=internal, 1=external
701 options[9] - dac0 coding
702 0=2's comp, 1=straight binary
703
704 options[10] - dac1 range
705 options[11] - dac1 reference
706 options[12] - dac1 coding
707 */
708
709 static int atmio16d_attach(struct comedi_device * dev, struct comedi_devconfig * it)
710 {
711 unsigned int irq;
712 unsigned long iobase;
713 int ret;
714
715 struct comedi_subdevice *s;
716
717 /* make sure the address range is free and allocate it */
718 iobase = it->options[0];
719 printk("comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase);
720 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) {
721 printk("I/O port conflict\n");
722 return -EIO;
723 }
724 dev->iobase = iobase;
725
726 /* board name */
727 dev->board_name = boardtype->name;
728
729 if ((ret = alloc_subdevices(dev, 4)) < 0)
730 return ret;
731 if ((ret = alloc_private(dev, sizeof(struct atmio16d_private))) < 0)
732 return ret;
733
734 /* reset the atmio16d hardware */
735 reset_atmio16d(dev);
736
737 /* check if our interrupt is available and get it */
738 irq = it->options[1];
739 if (irq) {
740 if ((ret = comedi_request_irq(irq, atmio16d_interrupt,
741 0, "atmio16d", dev)) < 0) {
742 printk("failed to allocate irq %u\n", irq);
743 return ret;
744 }
745 dev->irq = irq;
746 printk("( irq = %u )\n", irq);
747 } else {
748 printk("( no irq )");
749 }
750
751 /* set device options */
752 devpriv->adc_mux = it->options[5];
753 devpriv->adc_range = it->options[6];
754
755 devpriv->dac0_range = it->options[7];
756 devpriv->dac0_reference = it->options[8];
757 devpriv->dac0_coding = it->options[9];
758 devpriv->dac1_range = it->options[10];
759 devpriv->dac1_reference = it->options[11];
760 devpriv->dac1_coding = it->options[12];
761
762 /* setup sub-devices */
763 s = dev->subdevices + 0;
764 dev->read_subdev = s;
765 /* ai subdevice */
766 s->type = COMEDI_SUBD_AI;
767 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
768 s->n_chan = (devpriv->adc_mux ? 16 : 8);
769 s->len_chanlist = 16;
770 s->insn_read = atmio16d_ai_insn_read;
771 s->do_cmdtest = atmio16d_ai_cmdtest;
772 s->do_cmd = atmio16d_ai_cmd;
773 s->cancel = atmio16d_ai_cancel;
774 s->maxdata = 0xfff; /* 4095 decimal */
775 switch (devpriv->adc_range) {
776 case adc_bipolar10:
777 s->range_table = &range_atmio16d_ai_10_bipolar;
778 break;
779 case adc_bipolar5:
780 s->range_table = &range_atmio16d_ai_5_bipolar;
781 break;
782 case adc_unipolar10:
783 s->range_table = &range_atmio16d_ai_unipolar;
784 break;
785 }
786
787 /* ao subdevice */
788 s++;
789 s->type = COMEDI_SUBD_AO;
790 s->subdev_flags = SDF_WRITABLE;
791 s->n_chan = 2;
792 s->insn_read = atmio16d_ao_insn_read;
793 s->insn_write = atmio16d_ao_insn_write;
794 s->maxdata = 0xfff; /* 4095 decimal */
795 s->range_table_list = devpriv->ao_range_type_list;
796 switch (devpriv->dac0_range) {
797 case dac_bipolar:
798 devpriv->ao_range_type_list[0] = &range_bipolar10;
799 break;
800 case dac_unipolar:
801 devpriv->ao_range_type_list[0] = &range_unipolar10;
802 break;
803 }
804 switch (devpriv->dac1_range) {
805 case dac_bipolar:
806 devpriv->ao_range_type_list[1] = &range_bipolar10;
807 break;
808 case dac_unipolar:
809 devpriv->ao_range_type_list[1] = &range_unipolar10;
810 break;
811 }
812
813 /* Digital I/O */
814 s++;
815 s->type = COMEDI_SUBD_DIO;
816 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
817 s->n_chan = 8;
818 s->insn_bits = atmio16d_dio_insn_bits;
819 s->insn_config = atmio16d_dio_insn_config;
820 s->maxdata = 1;
821 s->range_table = &range_digital;
822
823 /* 8255 subdevice */
824 s++;
825 if (boardtype->has_8255) {
826 subdev_8255_init(dev, s, NULL, dev->iobase);
827 } else {
828 s->type = COMEDI_SUBD_UNUSED;
829 }
830
831 /* don't yet know how to deal with counter/timers */
832 #if 0
833 s++;
834 /* do */
835 s->type = COMEDI_SUBD_TIMER;
836 s->n_chan = 0;
837 s->maxdata = 0
838 #endif
839 printk("\n");
840
841 return 0;
842 }
843
844 static int atmio16d_detach(struct comedi_device * dev)
845 {
846 printk("comedi%d: atmio16d: remove\n", dev->minor);
847
848 if (dev->subdevices && boardtype->has_8255)
849 subdev_8255_cleanup(dev, dev->subdevices + 3);
850
851 if (dev->irq)
852 comedi_free_irq(dev->irq, dev);
853
854 reset_atmio16d(dev);
855
856 if (dev->iobase)
857 release_region(dev->iobase, ATMIO16D_SIZE);
858
859 return 0;
860 }
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