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1 /*
2 * comedi/drivers/ni_labpc.c
3 * Driver for National Instruments Lab-PC series boards and compatibles
4 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 /*
18 * Driver: ni_labpc
19 * Description: National Instruments Lab-PC (& compatibles)
20 * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200]
21 * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai]
22 * (National Instruments) Lab-PC+ [lab-pc+]
23 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
24 * Status: works
25 *
26 * Configuration options - ISA boards:
27 * [0] - I/O port base address
28 * [1] - IRQ (optional, required for timed or externally triggered
29 * conversions)
30 * [2] - DMA channel (optional)
31 *
32 * Tested with lab-pc-1200. For the older Lab-PC+, not all input
33 * ranges and analog references will work, the available ranges/arefs
34 * will depend on how you have configured the jumpers on your board
35 * (see your owner's manual).
36 *
37 * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards
38 * has not yet been added to the driver, mainly due to the fact that
39 * I don't know the device id numbers. If you have one of these boards,
40 * please file a bug report at http://comedi.org/ so I can get the
41 * necessary information from you.
42 *
43 * The 1200 series boards have onboard calibration dacs for correcting
44 * analog input/output offsets and gains. The proper settings for these
45 * caldacs are stored on the board's eeprom. To read the caldac values
46 * from the eeprom and store them into a file that can be then be used
47 * by comedilib, use the comedi_calibrate program.
48 *
49 * The Lab-pc+ has quirky chanlist requirements when scanning multiple
50 * channels. Multiple channel scan sequence must start at highest channel,
51 * then decrement down to channel 0. The rest of the cards can scan down
52 * like lab-pc+ or scan up from channel zero. Chanlists consisting of all
53 * one channel are also legal, and allow you to pace conversions in bursts.
54 *
55 * NI manuals:
56 * 341309a (labpc-1200 register manual)
57 * 320502b (lab-pc+)
58 */
59
60 #include <linux/interrupt.h>
61 #include <linux/slab.h>
62 #include <linux/io.h>
63 #include <linux/delay.h>
64
65 #include "../comedidev.h"
66
67 #include <asm/dma.h>
68
69 #include "8253.h"
70 #include "8255.h"
71 #include "comedi_fc.h"
72 #include "ni_labpc.h"
73
74 /*
75 * Register map (all registers are 8-bit)
76 */
77 #define STAT1_REG 0x00 /* R: Status 1 reg */
78 #define STAT1_DAVAIL (1 << 0)
79 #define STAT1_OVERRUN (1 << 1)
80 #define STAT1_OVERFLOW (1 << 2)
81 #define STAT1_CNTINT (1 << 3)
82 #define STAT1_GATA0 (1 << 5)
83 #define STAT1_EXTGATA0 (1 << 6)
84 #define CMD1_REG 0x00 /* W: Command 1 reg */
85 #define CMD1_MA(x) (((x) & 0x7) << 0)
86 #define CMD1_TWOSCMP (1 << 3)
87 #define CMD1_GAIN(x) (((x) & 0x7) << 4)
88 #define CMD1_SCANEN (1 << 7)
89 #define CMD2_REG 0x01 /* W: Command 2 reg */
90 #define CMD2_PRETRIG (1 << 0)
91 #define CMD2_HWTRIG (1 << 1)
92 #define CMD2_SWTRIG (1 << 2)
93 #define CMD2_TBSEL (1 << 3)
94 #define CMD2_2SDAC0 (1 << 4)
95 #define CMD2_2SDAC1 (1 << 5)
96 #define CMD2_LDAC(x) (1 << (6 + (x)))
97 #define CMD3_REG 0x02 /* W: Command 3 reg */
98 #define CMD3_DMAEN (1 << 0)
99 #define CMD3_DIOINTEN (1 << 1)
100 #define CMD3_DMATCINTEN (1 << 2)
101 #define CMD3_CNTINTEN (1 << 3)
102 #define CMD3_ERRINTEN (1 << 4)
103 #define CMD3_FIFOINTEN (1 << 5)
104 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
105 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
106 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
107 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */
108 #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */
109 #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */
110 #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */
111 #define CMD6_REG 0x0e /* W: Command 6 reg */
112 #define CMD6_NRSE (1 << 0)
113 #define CMD6_ADCUNI (1 << 1)
114 #define CMD6_DACUNI(x) (1 << (2 + (x)))
115 #define CMD6_HFINTEN (1 << 5)
116 #define CMD6_DQINTEN (1 << 6)
117 #define CMD6_SCANUP (1 << 7)
118 #define CMD4_REG 0x0f /* W: Command 3 reg */
119 #define CMD4_INTSCAN (1 << 0)
120 #define CMD4_EOIRCV (1 << 1)
121 #define CMD4_ECLKDRV (1 << 2)
122 #define CMD4_SEDIFF (1 << 3)
123 #define CMD4_ECLKRCV (1 << 4)
124 #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */
125 #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */
126 #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */
127 #define CMD5_REG 0x1c /* W: Command 5 reg */
128 #define CMD5_WRTPRT (1 << 2)
129 #define CMD5_DITHEREN (1 << 3)
130 #define CMD5_CALDACLD (1 << 4)
131 #define CMD5_SCLK (1 << 5)
132 #define CMD5_SDATA (1 << 6)
133 #define CMD5_EEPROMCS (1 << 7)
134 #define STAT2_REG 0x1d /* R: Status 2 reg */
135 #define STAT2_PROMOUT (1 << 0)
136 #define STAT2_OUTA1 (1 << 1)
137 #define STAT2_FIFONHF (1 << 2)
138 #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */
139 #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */
140
141 #define LABPC_SIZE 0x20 /* size of ISA io region */
142 #define LABPC_TIMER_BASE 500 /* 2 MHz master clock */
143 #define LABPC_ADC_TIMEOUT 1000
144
145 enum scan_mode {
146 MODE_SINGLE_CHAN,
147 MODE_SINGLE_CHAN_INTERVAL,
148 MODE_MULT_CHAN_UP,
149 MODE_MULT_CHAN_DOWN,
150 };
151
152 static const struct comedi_lrange range_labpc_plus_ai = {
153 16, {
154 BIP_RANGE(5),
155 BIP_RANGE(4),
156 BIP_RANGE(2.5),
157 BIP_RANGE(1),
158 BIP_RANGE(0.5),
159 BIP_RANGE(0.25),
160 BIP_RANGE(0.1),
161 BIP_RANGE(0.05),
162 UNI_RANGE(10),
163 UNI_RANGE(8),
164 UNI_RANGE(5),
165 UNI_RANGE(2),
166 UNI_RANGE(1),
167 UNI_RANGE(0.5),
168 UNI_RANGE(0.2),
169 UNI_RANGE(0.1)
170 }
171 };
172
173 static const struct comedi_lrange range_labpc_1200_ai = {
174 14, {
175 BIP_RANGE(5),
176 BIP_RANGE(2.5),
177 BIP_RANGE(1),
178 BIP_RANGE(0.5),
179 BIP_RANGE(0.25),
180 BIP_RANGE(0.1),
181 BIP_RANGE(0.05),
182 UNI_RANGE(10),
183 UNI_RANGE(5),
184 UNI_RANGE(2),
185 UNI_RANGE(1),
186 UNI_RANGE(0.5),
187 UNI_RANGE(0.2),
188 UNI_RANGE(0.1)
189 }
190 };
191
192 static const struct comedi_lrange range_labpc_ao = {
193 2, {
194 BIP_RANGE(5),
195 UNI_RANGE(10)
196 }
197 };
198
199 /* functions that do inb/outb and readb/writeb so we can use
200 * function pointers to decide which to use */
201 static inline unsigned int labpc_inb(unsigned long address)
202 {
203 return inb(address);
204 }
205
206 static inline void labpc_outb(unsigned int byte, unsigned long address)
207 {
208 outb(byte, address);
209 }
210
211 static inline unsigned int labpc_readb(unsigned long address)
212 {
213 return readb((void __iomem *)address);
214 }
215
216 static inline void labpc_writeb(unsigned int byte, unsigned long address)
217 {
218 writeb(byte, (void __iomem *)address);
219 }
220
221 #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA)
222 static const struct labpc_boardinfo labpc_boards[] = {
223 {
224 .name = "lab-pc-1200",
225 .ai_speed = 10000,
226 .ai_scan_up = 1,
227 .has_ao = 1,
228 .is_labpc1200 = 1,
229 }, {
230 .name = "lab-pc-1200ai",
231 .ai_speed = 10000,
232 .ai_scan_up = 1,
233 .is_labpc1200 = 1,
234 }, {
235 .name = "lab-pc+",
236 .ai_speed = 12000,
237 .has_ao = 1,
238 },
239 };
240 #endif
241
242 /* size in bytes of dma buffer */
243 static const int dma_buffer_size = 0xff00;
244 /* 2 bytes per sample */
245 static const int sample_size = 2;
246
247 static int labpc_counter_load(struct comedi_device *dev,
248 unsigned long base_address,
249 unsigned int counter_number,
250 unsigned int count, unsigned int mode)
251 {
252 const struct labpc_boardinfo *board = comedi_board(dev);
253
254 if (board->has_mmio)
255 return i8254_mm_load((void __iomem *)base_address, 0,
256 counter_number, count, mode);
257 else
258 return i8254_load(base_address, 0, counter_number, count, mode);
259 }
260
261 static int labpc_counter_set_mode(struct comedi_device *dev,
262 unsigned long base_address,
263 unsigned int counter_number,
264 unsigned int mode)
265 {
266 const struct labpc_boardinfo *board = comedi_board(dev);
267
268 if (board->has_mmio)
269 return i8254_mm_set_mode((void __iomem *)base_address, 0,
270 counter_number, mode);
271 else
272 return i8254_set_mode(base_address, 0, counter_number, mode);
273 }
274
275 static bool labpc_range_is_unipolar(struct comedi_subdevice *s,
276 unsigned int range)
277 {
278 return s->range_table->range[range].min >= 0;
279 }
280
281 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
282 {
283 struct labpc_private *devpriv = dev->private;
284 unsigned long flags;
285
286 spin_lock_irqsave(&dev->spinlock, flags);
287 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG);
288 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
289 spin_unlock_irqrestore(&dev->spinlock, flags);
290
291 devpriv->cmd3 = 0;
292 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
293
294 return 0;
295 }
296
297 static void labpc_ai_set_chan_and_gain(struct comedi_device *dev,
298 enum scan_mode mode,
299 unsigned int chan,
300 unsigned int range,
301 unsigned int aref)
302 {
303 const struct labpc_boardinfo *board = comedi_board(dev);
304 struct labpc_private *devpriv = dev->private;
305
306 if (board->is_labpc1200) {
307 /*
308 * The LabPC-1200 boards do not have a gain
309 * of '0x10'. Skip the range values that would
310 * result in this gain.
311 */
312 range += (range > 0) + (range > 7);
313 }
314
315 /* munge channel bits for differential/scan disabled mode */
316 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) &&
317 aref == AREF_DIFF)
318 chan *= 2;
319 devpriv->cmd1 = CMD1_MA(chan);
320 devpriv->cmd1 |= CMD1_GAIN(range);
321
322 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
323 }
324
325 static void labpc_setup_cmd6_reg(struct comedi_device *dev,
326 struct comedi_subdevice *s,
327 enum scan_mode mode,
328 enum transfer_type xfer,
329 unsigned int range,
330 unsigned int aref,
331 bool ena_intr)
332 {
333 const struct labpc_boardinfo *board = comedi_board(dev);
334 struct labpc_private *devpriv = dev->private;
335
336 if (!board->is_labpc1200)
337 return;
338
339 /* reference inputs to ground or common? */
340 if (aref != AREF_GROUND)
341 devpriv->cmd6 |= CMD6_NRSE;
342 else
343 devpriv->cmd6 &= ~CMD6_NRSE;
344
345 /* bipolar or unipolar range? */
346 if (labpc_range_is_unipolar(s, range))
347 devpriv->cmd6 |= CMD6_ADCUNI;
348 else
349 devpriv->cmd6 &= ~CMD6_ADCUNI;
350
351 /* interrupt on fifo half full? */
352 if (xfer == fifo_half_full_transfer)
353 devpriv->cmd6 |= CMD6_HFINTEN;
354 else
355 devpriv->cmd6 &= ~CMD6_HFINTEN;
356
357 /* enable interrupt on counter a1 terminal count? */
358 if (ena_intr)
359 devpriv->cmd6 |= CMD6_DQINTEN;
360 else
361 devpriv->cmd6 &= ~CMD6_DQINTEN;
362
363 /* are we scanning up or down through channels? */
364 if (mode == MODE_MULT_CHAN_UP)
365 devpriv->cmd6 |= CMD6_SCANUP;
366 else
367 devpriv->cmd6 &= ~CMD6_SCANUP;
368
369 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
370 }
371
372 static unsigned int labpc_read_adc_fifo(struct comedi_device *dev)
373 {
374 struct labpc_private *devpriv = dev->private;
375 unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
376 unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
377
378 return (msb << 8) | lsb;
379 }
380
381 static void labpc_clear_adc_fifo(struct comedi_device *dev)
382 {
383 struct labpc_private *devpriv = dev->private;
384
385 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
386 labpc_read_adc_fifo(dev);
387 }
388
389 static int labpc_ai_wait_for_data(struct comedi_device *dev,
390 int timeout)
391 {
392 struct labpc_private *devpriv = dev->private;
393 int i;
394
395 for (i = 0; i < timeout; i++) {
396 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
397 if (devpriv->stat1 & STAT1_DAVAIL)
398 return 0;
399 udelay(1);
400 }
401 return -ETIME;
402 }
403
404 static int labpc_ai_insn_read(struct comedi_device *dev,
405 struct comedi_subdevice *s,
406 struct comedi_insn *insn,
407 unsigned int *data)
408 {
409 struct labpc_private *devpriv = dev->private;
410 unsigned int chan = CR_CHAN(insn->chanspec);
411 unsigned int range = CR_RANGE(insn->chanspec);
412 unsigned int aref = CR_AREF(insn->chanspec);
413 int ret;
414 int i;
415
416 /* disable timed conversions, interrupt generation and dma */
417 labpc_cancel(dev, s);
418
419 labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref);
420
421 labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer,
422 range, aref, false);
423
424 /* setup cmd4 register */
425 devpriv->cmd4 = 0;
426 devpriv->cmd4 |= CMD4_ECLKRCV;
427 /* single-ended/differential */
428 if (aref == AREF_DIFF)
429 devpriv->cmd4 |= CMD4_SEDIFF;
430 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
431
432 /* initialize pacer counter to prevent any problems */
433 ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG,
434 0, I8254_MODE2);
435 if (ret)
436 return ret;
437
438 labpc_clear_adc_fifo(dev);
439
440 for (i = 0; i < insn->n; i++) {
441 /* trigger conversion */
442 devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG);
443
444 ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT);
445 if (ret)
446 return ret;
447
448 data[i] = labpc_read_adc_fifo(dev);
449 }
450
451 return insn->n;
452 }
453
454 #ifdef CONFIG_ISA_DMA_API
455 /* utility function that suggests a dma transfer size in bytes */
456 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
457 {
458 unsigned int size;
459 unsigned int freq;
460
461 if (cmd->convert_src == TRIG_TIMER)
462 freq = 1000000000 / cmd->convert_arg;
463 /* return some default value */
464 else
465 freq = 0xffffffff;
466
467 /* make buffer fill in no more than 1/3 second */
468 size = (freq / 3) * sample_size;
469
470 /* set a minimum and maximum size allowed */
471 if (size > dma_buffer_size)
472 size = dma_buffer_size - dma_buffer_size % sample_size;
473 else if (size < sample_size)
474 size = sample_size;
475
476 return size;
477 }
478 #endif
479
480 static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd,
481 enum scan_mode mode)
482 {
483 if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW)
484 return true;
485
486 return false;
487 }
488
489 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
490 enum scan_mode mode)
491 {
492 if (cmd->convert_src != TRIG_TIMER)
493 return 0;
494
495 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
496 return cmd->scan_begin_arg;
497
498 return cmd->convert_arg;
499 }
500
501 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
502 enum scan_mode mode, unsigned int ns)
503 {
504 if (cmd->convert_src != TRIG_TIMER)
505 return;
506
507 if (mode == MODE_SINGLE_CHAN &&
508 cmd->scan_begin_src == TRIG_TIMER) {
509 cmd->scan_begin_arg = ns;
510 if (cmd->convert_arg > cmd->scan_begin_arg)
511 cmd->convert_arg = cmd->scan_begin_arg;
512 } else
513 cmd->convert_arg = ns;
514 }
515
516 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
517 enum scan_mode mode)
518 {
519 if (cmd->scan_begin_src != TRIG_TIMER)
520 return 0;
521
522 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
523 return 0;
524
525 return cmd->scan_begin_arg;
526 }
527
528 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
529 enum scan_mode mode, unsigned int ns)
530 {
531 if (cmd->scan_begin_src != TRIG_TIMER)
532 return;
533
534 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
535 return;
536
537 cmd->scan_begin_arg = ns;
538 }
539
540 /* figures out what counter values to use based on command */
541 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
542 enum scan_mode mode)
543 {
544 struct labpc_private *devpriv = dev->private;
545 /* max value for 16 bit counter in mode 2 */
546 const int max_counter_value = 0x10000;
547 /* min value for 16 bit counter in mode 2 */
548 const int min_counter_value = 2;
549 unsigned int base_period;
550 unsigned int scan_period;
551 unsigned int convert_period;
552
553 /*
554 * if both convert and scan triggers are TRIG_TIMER, then they
555 * both rely on counter b0
556 */
557 convert_period = labpc_ai_convert_period(cmd, mode);
558 scan_period = labpc_ai_scan_period(cmd, mode);
559 if (convert_period && scan_period) {
560 /*
561 * pick the lowest b0 divisor value we can (for maximum input
562 * clock speed on convert and scan counters)
563 */
564 devpriv->divisor_b0 = (scan_period - 1) /
565 (LABPC_TIMER_BASE * max_counter_value) + 1;
566 if (devpriv->divisor_b0 < min_counter_value)
567 devpriv->divisor_b0 = min_counter_value;
568 if (devpriv->divisor_b0 > max_counter_value)
569 devpriv->divisor_b0 = max_counter_value;
570
571 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
572
573 /* set a0 for conversion frequency and b1 for scan frequency */
574 switch (cmd->flags & TRIG_ROUND_MASK) {
575 default:
576 case TRIG_ROUND_NEAREST:
577 devpriv->divisor_a0 =
578 (convert_period + (base_period / 2)) / base_period;
579 devpriv->divisor_b1 =
580 (scan_period + (base_period / 2)) / base_period;
581 break;
582 case TRIG_ROUND_UP:
583 devpriv->divisor_a0 =
584 (convert_period + (base_period - 1)) / base_period;
585 devpriv->divisor_b1 =
586 (scan_period + (base_period - 1)) / base_period;
587 break;
588 case TRIG_ROUND_DOWN:
589 devpriv->divisor_a0 = convert_period / base_period;
590 devpriv->divisor_b1 = scan_period / base_period;
591 break;
592 }
593 /* make sure a0 and b1 values are acceptable */
594 if (devpriv->divisor_a0 < min_counter_value)
595 devpriv->divisor_a0 = min_counter_value;
596 if (devpriv->divisor_a0 > max_counter_value)
597 devpriv->divisor_a0 = max_counter_value;
598 if (devpriv->divisor_b1 < min_counter_value)
599 devpriv->divisor_b1 = min_counter_value;
600 if (devpriv->divisor_b1 > max_counter_value)
601 devpriv->divisor_b1 = max_counter_value;
602 /* write corrected timings to command */
603 labpc_set_ai_convert_period(cmd, mode,
604 base_period * devpriv->divisor_a0);
605 labpc_set_ai_scan_period(cmd, mode,
606 base_period * devpriv->divisor_b1);
607 /*
608 * if only one TRIG_TIMER is used, we can employ the generic
609 * cascaded timing functions
610 */
611 } else if (scan_period) {
612 /*
613 * calculate cascaded counter values
614 * that give desired scan timing
615 */
616 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
617 &(devpriv->divisor_b1),
618 &(devpriv->divisor_b0),
619 &scan_period,
620 cmd->flags & TRIG_ROUND_MASK);
621 labpc_set_ai_scan_period(cmd, mode, scan_period);
622 } else if (convert_period) {
623 /*
624 * calculate cascaded counter values
625 * that give desired conversion timing
626 */
627 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
628 &(devpriv->divisor_a0),
629 &(devpriv->divisor_b0),
630 &convert_period,
631 cmd->flags & TRIG_ROUND_MASK);
632 labpc_set_ai_convert_period(cmd, mode, convert_period);
633 }
634 }
635
636 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
637 {
638 if (cmd->chanlist_len == 1)
639 return MODE_SINGLE_CHAN;
640
641 /* chanlist may be NULL during cmdtest. */
642 if (cmd->chanlist == NULL)
643 return MODE_MULT_CHAN_UP;
644
645 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
646 return MODE_SINGLE_CHAN_INTERVAL;
647
648 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
649 return MODE_MULT_CHAN_UP;
650
651 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
652 return MODE_MULT_CHAN_DOWN;
653
654 pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
655 return 0;
656 }
657
658 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
659 const struct comedi_cmd *cmd,
660 enum scan_mode mode)
661 {
662 int channel, range, aref, i;
663
664 if (cmd->chanlist == NULL)
665 return 0;
666
667 if (mode == MODE_SINGLE_CHAN)
668 return 0;
669
670 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
671 if (cmd->chanlist_len > 0xff) {
672 comedi_error(dev,
673 "ni_labpc: chanlist too long for single channel interval mode\n");
674 return 1;
675 }
676 }
677
678 channel = CR_CHAN(cmd->chanlist[0]);
679 range = CR_RANGE(cmd->chanlist[0]);
680 aref = CR_AREF(cmd->chanlist[0]);
681
682 for (i = 0; i < cmd->chanlist_len; i++) {
683
684 switch (mode) {
685 case MODE_SINGLE_CHAN_INTERVAL:
686 if (CR_CHAN(cmd->chanlist[i]) != channel) {
687 comedi_error(dev,
688 "channel scanning order specified in chanlist is not supported by hardware.\n");
689 return 1;
690 }
691 break;
692 case MODE_MULT_CHAN_UP:
693 if (CR_CHAN(cmd->chanlist[i]) != i) {
694 comedi_error(dev,
695 "channel scanning order specified in chanlist is not supported by hardware.\n");
696 return 1;
697 }
698 break;
699 case MODE_MULT_CHAN_DOWN:
700 if (CR_CHAN(cmd->chanlist[i]) !=
701 cmd->chanlist_len - i - 1) {
702 comedi_error(dev,
703 "channel scanning order specified in chanlist is not supported by hardware.\n");
704 return 1;
705 }
706 break;
707 default:
708 dev_err(dev->class_dev,
709 "ni_labpc: bug! in chanlist check\n");
710 return 1;
711 break;
712 }
713
714 if (CR_RANGE(cmd->chanlist[i]) != range) {
715 comedi_error(dev,
716 "entries in chanlist must all have the same range\n");
717 return 1;
718 }
719
720 if (CR_AREF(cmd->chanlist[i]) != aref) {
721 comedi_error(dev,
722 "entries in chanlist must all have the same reference\n");
723 return 1;
724 }
725 }
726
727 return 0;
728 }
729
730 static int labpc_ai_cmdtest(struct comedi_device *dev,
731 struct comedi_subdevice *s, struct comedi_cmd *cmd)
732 {
733 const struct labpc_boardinfo *board = comedi_board(dev);
734 int err = 0;
735 int tmp, tmp2;
736 unsigned int stop_mask;
737 enum scan_mode mode;
738
739 /* Step 1 : check if triggers are trivially valid */
740
741 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
742 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
743 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
744 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
745 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
746
747 stop_mask = TRIG_COUNT | TRIG_NONE;
748 if (board->is_labpc1200)
749 stop_mask |= TRIG_EXT;
750 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
751
752 if (err)
753 return 1;
754
755 /* Step 2a : make sure trigger sources are unique */
756
757 err |= cfc_check_trigger_is_unique(cmd->start_src);
758 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
759 err |= cfc_check_trigger_is_unique(cmd->convert_src);
760 err |= cfc_check_trigger_is_unique(cmd->stop_src);
761
762 /* Step 2b : and mutually compatible */
763
764 /* can't have external stop and start triggers at once */
765 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
766 err++;
767
768 if (err)
769 return 2;
770
771 /* Step 3: check if arguments are trivially valid */
772
773 if (cmd->start_arg == TRIG_NOW)
774 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
775
776 if (!cmd->chanlist_len)
777 err |= -EINVAL;
778 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
779
780 if (cmd->convert_src == TRIG_TIMER)
781 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
782 board->ai_speed);
783
784 /* make sure scan timing is not too fast */
785 if (cmd->scan_begin_src == TRIG_TIMER) {
786 if (cmd->convert_src == TRIG_TIMER)
787 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
788 cmd->convert_arg * cmd->chanlist_len);
789 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
790 board->ai_speed * cmd->chanlist_len);
791 }
792
793 switch (cmd->stop_src) {
794 case TRIG_COUNT:
795 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
796 break;
797 case TRIG_NONE:
798 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
799 break;
800 /*
801 * TRIG_EXT doesn't care since it doesn't
802 * trigger off a numbered channel
803 */
804 default:
805 break;
806 }
807
808 if (err)
809 return 3;
810
811 /* step 4: fix up any arguments */
812
813 tmp = cmd->convert_arg;
814 tmp2 = cmd->scan_begin_arg;
815 mode = labpc_ai_scan_mode(cmd);
816 labpc_adc_timing(dev, cmd, mode);
817 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
818 err++;
819
820 if (err)
821 return 4;
822
823 if (labpc_ai_chanlist_invalid(dev, cmd, mode))
824 return 5;
825
826 return 0;
827 }
828
829 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
830 {
831 const struct labpc_boardinfo *board = comedi_board(dev);
832 struct labpc_private *devpriv = dev->private;
833 struct comedi_async *async = s->async;
834 struct comedi_cmd *cmd = &async->cmd;
835 enum scan_mode mode = labpc_ai_scan_mode(cmd);
836 unsigned int chanspec = (mode == MODE_MULT_CHAN_UP)
837 ? cmd->chanlist[cmd->chanlist_len - 1]
838 : cmd->chanlist[0];
839 unsigned int chan = CR_CHAN(chanspec);
840 unsigned int range = CR_RANGE(chanspec);
841 unsigned int aref = CR_AREF(chanspec);
842 enum transfer_type xfer;
843 unsigned long flags;
844 int ret;
845
846 /* make sure board is disabled before setting up acquisition */
847 labpc_cancel(dev, s);
848
849 /* initialize software conversion count */
850 if (cmd->stop_src == TRIG_COUNT)
851 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
852
853 /* setup hardware conversion counter */
854 if (cmd->stop_src == TRIG_EXT) {
855 /*
856 * load counter a1 with count of 3
857 * (pc+ manual says this is minimum allowed) using mode 0
858 */
859 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
860 1, 3, I8254_MODE0);
861 } else {
862 /* just put counter a1 in mode 0 to set its output low */
863 ret = labpc_counter_set_mode(dev,
864 dev->iobase + COUNTER_A_BASE_REG,
865 1, I8254_MODE0);
866 }
867 if (ret) {
868 comedi_error(dev, "error loading counter a1");
869 return ret;
870 }
871
872 #ifdef CONFIG_ISA_DMA_API
873 /* figure out what method we will use to transfer data */
874 if (devpriv->dma_chan && /* need a dma channel allocated */
875 /*
876 * dma unsafe at RT priority,
877 * and too much setup time for TRIG_WAKE_EOS for
878 */
879 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0) {
880 xfer = isa_dma_transfer;
881 /* pc-plus has no fifo-half full interrupt */
882 } else
883 #endif
884 if (board->is_labpc1200 &&
885 /* wake-end-of-scan should interrupt on fifo not empty */
886 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
887 /* make sure we are taking more than just a few points */
888 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
889 xfer = fifo_half_full_transfer;
890 } else
891 xfer = fifo_not_empty_transfer;
892 devpriv->current_transfer = xfer;
893
894 labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref);
895
896 labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref,
897 (cmd->stop_src == TRIG_EXT));
898
899 /* manual says to set scan enable bit on second pass */
900 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
901 devpriv->cmd1 |= CMD1_SCANEN;
902 /* need a brief delay before enabling scan, or scan
903 * list will get screwed when you switch
904 * between scan up to scan down mode - dunno why */
905 udelay(1);
906 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
907 }
908
909 devpriv->write_byte(cmd->chanlist_len,
910 dev->iobase + INTERVAL_COUNT_REG);
911 /* load count */
912 devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG);
913
914 if (cmd->convert_src == TRIG_TIMER ||
915 cmd->scan_begin_src == TRIG_TIMER) {
916 /* set up pacing */
917 labpc_adc_timing(dev, cmd, mode);
918 /* load counter b0 in mode 3 */
919 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
920 0, devpriv->divisor_b0, I8254_MODE3);
921 if (ret < 0) {
922 comedi_error(dev, "error loading counter b0");
923 return -1;
924 }
925 }
926 /* set up conversion pacing */
927 if (labpc_ai_convert_period(cmd, mode)) {
928 /* load counter a0 in mode 2 */
929 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
930 0, devpriv->divisor_a0, I8254_MODE2);
931 } else {
932 /* initialize pacer counter to prevent any problems */
933 ret = labpc_counter_set_mode(dev,
934 dev->iobase + COUNTER_A_BASE_REG,
935 0, I8254_MODE2);
936 }
937 if (ret) {
938 comedi_error(dev, "error loading counter a0");
939 return ret;
940 }
941
942 /* set up scan pacing */
943 if (labpc_ai_scan_period(cmd, mode)) {
944 /* load counter b1 in mode 2 */
945 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
946 1, devpriv->divisor_b1, I8254_MODE2);
947 if (ret < 0) {
948 comedi_error(dev, "error loading counter b1");
949 return -1;
950 }
951 }
952
953 labpc_clear_adc_fifo(dev);
954
955 #ifdef CONFIG_ISA_DMA_API
956 /* set up dma transfer */
957 if (xfer == isa_dma_transfer) {
958 unsigned long irq_flags;
959
960 irq_flags = claim_dma_lock();
961 disable_dma(devpriv->dma_chan);
962 /* clear flip-flop to make sure 2-byte registers for
963 * count and address get set correctly */
964 clear_dma_ff(devpriv->dma_chan);
965 set_dma_addr(devpriv->dma_chan, devpriv->dma_addr);
966 /* set appropriate size of transfer */
967 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
968 if (cmd->stop_src == TRIG_COUNT &&
969 devpriv->count * sample_size < devpriv->dma_transfer_size) {
970 devpriv->dma_transfer_size =
971 devpriv->count * sample_size;
972 }
973 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
974 enable_dma(devpriv->dma_chan);
975 release_dma_lock(irq_flags);
976 /* enable board's dma */
977 devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN);
978 } else
979 devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN);
980 #endif
981
982 /* enable error interrupts */
983 devpriv->cmd3 |= CMD3_ERRINTEN;
984 /* enable fifo not empty interrupt? */
985 if (xfer == fifo_not_empty_transfer)
986 devpriv->cmd3 |= CMD3_FIFOINTEN;
987 else
988 devpriv->cmd3 &= ~CMD3_FIFOINTEN;
989 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
990
991 /* setup any external triggering/pacing (cmd4 register) */
992 devpriv->cmd4 = 0;
993 if (cmd->convert_src != TRIG_EXT)
994 devpriv->cmd4 |= CMD4_ECLKRCV;
995 /* XXX should discard first scan when using interval scanning
996 * since manual says it is not synced with scan clock */
997 if (!labpc_use_continuous_mode(cmd, mode)) {
998 devpriv->cmd4 |= CMD4_INTSCAN;
999 if (cmd->scan_begin_src == TRIG_EXT)
1000 devpriv->cmd4 |= CMD4_EOIRCV;
1001 }
1002 /* single-ended/differential */
1003 if (aref == AREF_DIFF)
1004 devpriv->cmd4 |= CMD4_SEDIFF;
1005 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
1006
1007 /* startup acquisition */
1008
1009 spin_lock_irqsave(&dev->spinlock, flags);
1010
1011 /* use 2 cascaded counters for pacing */
1012 devpriv->cmd2 |= CMD2_TBSEL;
1013
1014 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG);
1015 if (cmd->start_src == TRIG_EXT)
1016 devpriv->cmd2 |= CMD2_HWTRIG;
1017 else
1018 devpriv->cmd2 |= CMD2_SWTRIG;
1019 if (cmd->stop_src == TRIG_EXT)
1020 devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG);
1021
1022 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1023
1024 spin_unlock_irqrestore(&dev->spinlock, flags);
1025
1026 return 0;
1027 }
1028
1029 #ifdef CONFIG_ISA_DMA_API
1030 static void labpc_drain_dma(struct comedi_device *dev)
1031 {
1032 struct labpc_private *devpriv = dev->private;
1033 struct comedi_subdevice *s = dev->read_subdev;
1034 struct comedi_async *async = s->async;
1035 int status;
1036 unsigned long flags;
1037 unsigned int max_points, num_points, residue, leftover;
1038 int i;
1039
1040 status = devpriv->stat1;
1041
1042 flags = claim_dma_lock();
1043 disable_dma(devpriv->dma_chan);
1044 /* clear flip-flop to make sure 2-byte registers for
1045 * count and address get set correctly */
1046 clear_dma_ff(devpriv->dma_chan);
1047
1048 /* figure out how many points to read */
1049 max_points = devpriv->dma_transfer_size / sample_size;
1050 /* residue is the number of points left to be done on the dma
1051 * transfer. It should always be zero at this point unless
1052 * the stop_src is set to external triggering.
1053 */
1054 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1055 num_points = max_points - residue;
1056 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1057 num_points = devpriv->count;
1058
1059 /* figure out how many points will be stored next time */
1060 leftover = 0;
1061 if (async->cmd.stop_src != TRIG_COUNT) {
1062 leftover = devpriv->dma_transfer_size / sample_size;
1063 } else if (devpriv->count > num_points) {
1064 leftover = devpriv->count - num_points;
1065 if (leftover > max_points)
1066 leftover = max_points;
1067 }
1068
1069 /* write data to comedi buffer */
1070 for (i = 0; i < num_points; i++)
1071 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1072
1073 if (async->cmd.stop_src == TRIG_COUNT)
1074 devpriv->count -= num_points;
1075
1076 /* set address and count for next transfer */
1077 set_dma_addr(devpriv->dma_chan, devpriv->dma_addr);
1078 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1079 release_dma_lock(flags);
1080
1081 async->events |= COMEDI_CB_BLOCK;
1082 }
1083
1084 static void handle_isa_dma(struct comedi_device *dev)
1085 {
1086 struct labpc_private *devpriv = dev->private;
1087
1088 labpc_drain_dma(dev);
1089
1090 enable_dma(devpriv->dma_chan);
1091
1092 /* clear dma tc interrupt */
1093 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1094 }
1095 #endif
1096
1097 /* read all available samples from ai fifo */
1098 static int labpc_drain_fifo(struct comedi_device *dev)
1099 {
1100 struct labpc_private *devpriv = dev->private;
1101 short data;
1102 struct comedi_async *async = dev->read_subdev->async;
1103 const int timeout = 10000;
1104 unsigned int i;
1105
1106 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1107
1108 for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout;
1109 i++) {
1110 /* quit if we have all the data we want */
1111 if (async->cmd.stop_src == TRIG_COUNT) {
1112 if (devpriv->count == 0)
1113 break;
1114 devpriv->count--;
1115 }
1116 data = labpc_read_adc_fifo(dev);
1117 cfc_write_to_buffer(dev->read_subdev, data);
1118 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1119 }
1120 if (i == timeout) {
1121 comedi_error(dev, "ai timeout, fifo never empties");
1122 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1123 return -1;
1124 }
1125
1126 return 0;
1127 }
1128
1129 /* makes sure all data acquired by board is transferred to comedi (used
1130 * when acquisition is terminated by stop_src == TRIG_EXT). */
1131 static void labpc_drain_dregs(struct comedi_device *dev)
1132 {
1133 #ifdef CONFIG_ISA_DMA_API
1134 struct labpc_private *devpriv = dev->private;
1135
1136 if (devpriv->current_transfer == isa_dma_transfer)
1137 labpc_drain_dma(dev);
1138 #endif
1139
1140 labpc_drain_fifo(dev);
1141 }
1142
1143 /* interrupt service routine */
1144 static irqreturn_t labpc_interrupt(int irq, void *d)
1145 {
1146 struct comedi_device *dev = d;
1147 const struct labpc_boardinfo *board = comedi_board(dev);
1148 struct labpc_private *devpriv = dev->private;
1149 struct comedi_subdevice *s = dev->read_subdev;
1150 struct comedi_async *async;
1151 struct comedi_cmd *cmd;
1152
1153 if (!dev->attached) {
1154 comedi_error(dev, "premature interrupt");
1155 return IRQ_HANDLED;
1156 }
1157
1158 async = s->async;
1159 cmd = &async->cmd;
1160 async->events = 0;
1161
1162 /* read board status */
1163 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG);
1164 if (board->is_labpc1200)
1165 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG);
1166
1167 if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW |
1168 STAT1_OVERRUN | STAT1_DAVAIL)) == 0
1169 && (devpriv->stat2 & STAT2_OUTA1) == 0
1170 && (devpriv->stat2 & STAT2_FIFONHF)) {
1171 return IRQ_NONE;
1172 }
1173
1174 if (devpriv->stat1 & STAT1_OVERRUN) {
1175 /* clear error interrupt */
1176 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
1177 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1178 comedi_event(dev, s);
1179 comedi_error(dev, "overrun");
1180 return IRQ_HANDLED;
1181 }
1182
1183 #ifdef CONFIG_ISA_DMA_API
1184 if (devpriv->current_transfer == isa_dma_transfer) {
1185 /*
1186 * if a dma terminal count of external stop trigger
1187 * has occurred
1188 */
1189 if (devpriv->stat1 & STAT1_GATA0 ||
1190 (board->is_labpc1200 && devpriv->stat2 & STAT2_OUTA1)) {
1191 handle_isa_dma(dev);
1192 }
1193 } else
1194 #endif
1195 labpc_drain_fifo(dev);
1196
1197 if (devpriv->stat1 & STAT1_CNTINT) {
1198 comedi_error(dev, "handled timer interrupt?");
1199 /* clear it */
1200 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1201 }
1202
1203 if (devpriv->stat1 & STAT1_OVERFLOW) {
1204 /* clear error interrupt */
1205 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG);
1206 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1207 comedi_event(dev, s);
1208 comedi_error(dev, "overflow");
1209 return IRQ_HANDLED;
1210 }
1211 /* handle external stop trigger */
1212 if (cmd->stop_src == TRIG_EXT) {
1213 if (devpriv->stat2 & STAT2_OUTA1) {
1214 labpc_drain_dregs(dev);
1215 labpc_cancel(dev, s);
1216 async->events |= COMEDI_CB_EOA;
1217 }
1218 }
1219
1220 /* TRIG_COUNT end of acquisition */
1221 if (cmd->stop_src == TRIG_COUNT) {
1222 if (devpriv->count == 0) {
1223 labpc_cancel(dev, s);
1224 async->events |= COMEDI_CB_EOA;
1225 }
1226 }
1227
1228 comedi_event(dev, s);
1229 return IRQ_HANDLED;
1230 }
1231
1232 static int labpc_ao_insn_write(struct comedi_device *dev,
1233 struct comedi_subdevice *s,
1234 struct comedi_insn *insn,
1235 unsigned int *data)
1236 {
1237 const struct labpc_boardinfo *board = comedi_board(dev);
1238 struct labpc_private *devpriv = dev->private;
1239 int channel, range;
1240 unsigned long flags;
1241 int lsb, msb;
1242
1243 channel = CR_CHAN(insn->chanspec);
1244
1245 /* turn off pacing of analog output channel */
1246 /* note: hardware bug in daqcard-1200 means pacing cannot
1247 * be independently enabled/disabled for its the two channels */
1248 spin_lock_irqsave(&dev->spinlock, flags);
1249 devpriv->cmd2 &= ~CMD2_LDAC(channel);
1250 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1251 spin_unlock_irqrestore(&dev->spinlock, flags);
1252
1253 /* set range */
1254 if (board->is_labpc1200) {
1255 range = CR_RANGE(insn->chanspec);
1256 if (labpc_range_is_unipolar(s, range))
1257 devpriv->cmd6 |= CMD6_DACUNI(channel);
1258 else
1259 devpriv->cmd6 &= ~CMD6_DACUNI(channel);
1260 /* write to register */
1261 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
1262 }
1263 /* send data */
1264 lsb = data[0] & 0xff;
1265 msb = (data[0] >> 8) & 0xff;
1266 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1267 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1268
1269 /* remember value for readback */
1270 devpriv->ao_value[channel] = data[0];
1271
1272 return 1;
1273 }
1274
1275 static int labpc_ao_insn_read(struct comedi_device *dev,
1276 struct comedi_subdevice *s,
1277 struct comedi_insn *insn,
1278 unsigned int *data)
1279 {
1280 struct labpc_private *devpriv = dev->private;
1281
1282 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1283
1284 return 1;
1285 }
1286
1287 static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase)
1288 {
1289 if (dir) {
1290 writeb(data, (void __iomem *)(iobase + port));
1291 return 0;
1292 } else {
1293 return readb((void __iomem *)(iobase + port));
1294 }
1295 }
1296
1297 /* lowlevel write to eeprom/dac */
1298 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1299 unsigned int value_width)
1300 {
1301 struct labpc_private *devpriv = dev->private;
1302 int i;
1303
1304 for (i = 1; i <= value_width; i++) {
1305 /* clear serial clock */
1306 devpriv->cmd5 &= ~CMD5_SCLK;
1307 /* send bits most significant bit first */
1308 if (value & (1 << (value_width - i)))
1309 devpriv->cmd5 |= CMD5_SDATA;
1310 else
1311 devpriv->cmd5 &= ~CMD5_SDATA;
1312 udelay(1);
1313 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1314 /* set clock to load bit */
1315 devpriv->cmd5 |= CMD5_SCLK;
1316 udelay(1);
1317 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1318 }
1319 }
1320
1321 /* lowlevel read from eeprom */
1322 static unsigned int labpc_serial_in(struct comedi_device *dev)
1323 {
1324 struct labpc_private *devpriv = dev->private;
1325 unsigned int value = 0;
1326 int i;
1327 const int value_width = 8; /* number of bits wide values are */
1328
1329 for (i = 1; i <= value_width; i++) {
1330 /* set serial clock */
1331 devpriv->cmd5 |= CMD5_SCLK;
1332 udelay(1);
1333 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1334 /* clear clock bit */
1335 devpriv->cmd5 &= ~CMD5_SCLK;
1336 udelay(1);
1337 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1338 /* read bits most significant bit first */
1339 udelay(1);
1340 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG);
1341 if (devpriv->stat2 & STAT2_PROMOUT)
1342 value |= 1 << (value_width - i);
1343 }
1344
1345 return value;
1346 }
1347
1348 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1349 unsigned int address)
1350 {
1351 struct labpc_private *devpriv = dev->private;
1352 unsigned int value;
1353 /* bits to tell eeprom to expect a read */
1354 const int read_instruction = 0x3;
1355 /* 8 bit write lengths to eeprom */
1356 const int write_length = 8;
1357
1358 /* enable read/write to eeprom */
1359 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1360 udelay(1);
1361 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1362 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1363 udelay(1);
1364 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1365
1366 /* send read instruction */
1367 labpc_serial_out(dev, read_instruction, write_length);
1368 /* send 8 bit address to read from */
1369 labpc_serial_out(dev, address, write_length);
1370 /* read result */
1371 value = labpc_serial_in(dev);
1372
1373 /* disable read/write to eeprom */
1374 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1375 udelay(1);
1376 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1377
1378 return value;
1379 }
1380
1381 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
1382 {
1383 struct labpc_private *devpriv = dev->private;
1384 unsigned int value;
1385 const int read_status_instruction = 0x5;
1386 const int write_length = 8; /* 8 bit write lengths to eeprom */
1387
1388 /* enable read/write to eeprom */
1389 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1390 udelay(1);
1391 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1392 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1393 udelay(1);
1394 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1395
1396 /* send read status instruction */
1397 labpc_serial_out(dev, read_status_instruction, write_length);
1398 /* read result */
1399 value = labpc_serial_in(dev);
1400
1401 /* disable read/write to eeprom */
1402 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1403 udelay(1);
1404 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1405
1406 return value;
1407 }
1408
1409 static int labpc_eeprom_write(struct comedi_device *dev,
1410 unsigned int address, unsigned int value)
1411 {
1412 struct labpc_private *devpriv = dev->private;
1413 const int write_enable_instruction = 0x6;
1414 const int write_instruction = 0x2;
1415 const int write_length = 8; /* 8 bit write lengths to eeprom */
1416 const int write_in_progress_bit = 0x1;
1417 const int timeout = 10000;
1418 int i;
1419
1420 /* make sure there isn't already a write in progress */
1421 for (i = 0; i < timeout; i++) {
1422 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1423 0)
1424 break;
1425 }
1426 if (i == timeout) {
1427 comedi_error(dev, "eeprom write timed out");
1428 return -ETIME;
1429 }
1430 /* update software copy of eeprom */
1431 devpriv->eeprom_data[address] = value;
1432
1433 /* enable read/write to eeprom */
1434 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1435 udelay(1);
1436 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1437 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT);
1438 udelay(1);
1439 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1440
1441 /* send write_enable instruction */
1442 labpc_serial_out(dev, write_enable_instruction, write_length);
1443 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1444 udelay(1);
1445 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1446
1447 /* send write instruction */
1448 devpriv->cmd5 |= CMD5_EEPROMCS;
1449 udelay(1);
1450 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1451 labpc_serial_out(dev, write_instruction, write_length);
1452 /* send 8 bit address to write to */
1453 labpc_serial_out(dev, address, write_length);
1454 /* write value */
1455 labpc_serial_out(dev, value, write_length);
1456 devpriv->cmd5 &= ~CMD5_EEPROMCS;
1457 udelay(1);
1458 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1459
1460 /* disable read/write to eeprom */
1461 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT);
1462 udelay(1);
1463 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1464
1465 return 0;
1466 }
1467
1468 /* writes to 8 bit calibration dacs */
1469 static void write_caldac(struct comedi_device *dev, unsigned int channel,
1470 unsigned int value)
1471 {
1472 struct labpc_private *devpriv = dev->private;
1473
1474 if (value == devpriv->caldac[channel])
1475 return;
1476 devpriv->caldac[channel] = value;
1477
1478 /* clear caldac load bit and make sure we don't write to eeprom */
1479 devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT);
1480 udelay(1);
1481 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1482
1483 /* write 4 bit channel */
1484 labpc_serial_out(dev, channel, 4);
1485 /* write 8 bit caldac value */
1486 labpc_serial_out(dev, value, 8);
1487
1488 /* set and clear caldac bit to load caldac value */
1489 devpriv->cmd5 |= CMD5_CALDACLD;
1490 udelay(1);
1491 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1492 devpriv->cmd5 &= ~CMD5_CALDACLD;
1493 udelay(1);
1494 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1495 }
1496
1497 static int labpc_calib_insn_write(struct comedi_device *dev,
1498 struct comedi_subdevice *s,
1499 struct comedi_insn *insn,
1500 unsigned int *data)
1501 {
1502 unsigned int chan = CR_CHAN(insn->chanspec);
1503
1504 /*
1505 * Only write the last data value to the caldac. Preceding
1506 * data would be overwritten anyway.
1507 */
1508 if (insn->n > 0)
1509 write_caldac(dev, chan, data[insn->n - 1]);
1510
1511 return insn->n;
1512 }
1513
1514 static int labpc_calib_insn_read(struct comedi_device *dev,
1515 struct comedi_subdevice *s,
1516 struct comedi_insn *insn,
1517 unsigned int *data)
1518 {
1519 struct labpc_private *devpriv = dev->private;
1520 unsigned int chan = CR_CHAN(insn->chanspec);
1521 int i;
1522
1523 for (i = 0; i < insn->n; i++)
1524 data[i] = devpriv->caldac[chan];
1525
1526 return insn->n;
1527 }
1528
1529 static int labpc_eeprom_insn_write(struct comedi_device *dev,
1530 struct comedi_subdevice *s,
1531 struct comedi_insn *insn,
1532 unsigned int *data)
1533 {
1534 unsigned int chan = CR_CHAN(insn->chanspec);
1535 int ret;
1536
1537 /* only allow writes to user area of eeprom */
1538 if (chan < 16 || chan > 127)
1539 return -EINVAL;
1540
1541 /*
1542 * Only write the last data value to the eeprom. Preceding
1543 * data would be overwritten anyway.
1544 */
1545 if (insn->n > 0) {
1546 ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]);
1547 if (ret)
1548 return ret;
1549 }
1550
1551 return insn->n;
1552 }
1553
1554 static int labpc_eeprom_insn_read(struct comedi_device *dev,
1555 struct comedi_subdevice *s,
1556 struct comedi_insn *insn,
1557 unsigned int *data)
1558 {
1559 struct labpc_private *devpriv = dev->private;
1560 unsigned int chan = CR_CHAN(insn->chanspec);
1561 int i;
1562
1563 for (i = 0; i < insn->n; i++)
1564 data[i] = devpriv->eeprom_data[chan];
1565
1566 return insn->n;
1567 }
1568
1569 int labpc_common_attach(struct comedi_device *dev,
1570 unsigned int irq, unsigned long isr_flags)
1571 {
1572 const struct labpc_boardinfo *board = comedi_board(dev);
1573 struct labpc_private *devpriv = dev->private;
1574 struct comedi_subdevice *s;
1575 int ret;
1576 int i;
1577
1578 if (board->has_mmio) {
1579 devpriv->read_byte = labpc_readb;
1580 devpriv->write_byte = labpc_writeb;
1581 } else {
1582 devpriv->read_byte = labpc_inb;
1583 devpriv->write_byte = labpc_outb;
1584 }
1585
1586 /* initialize board's command registers */
1587 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG);
1588 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG);
1589 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG);
1590 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG);
1591 if (board->is_labpc1200) {
1592 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG);
1593 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG);
1594 }
1595
1596 if (irq) {
1597 ret = request_irq(irq, labpc_interrupt, isr_flags,
1598 dev->board_name, dev);
1599 if (ret == 0)
1600 dev->irq = irq;
1601 }
1602
1603 ret = comedi_alloc_subdevices(dev, 5);
1604 if (ret)
1605 return ret;
1606
1607 /* analog input subdevice */
1608 s = &dev->subdevices[0];
1609 s->type = COMEDI_SUBD_AI;
1610 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1611 s->n_chan = 8;
1612 s->len_chanlist = 8;
1613 s->maxdata = 0x0fff;
1614 s->range_table = board->is_labpc1200
1615 ? &range_labpc_1200_ai : &range_labpc_plus_ai;
1616 s->insn_read = labpc_ai_insn_read;
1617 if (dev->irq) {
1618 dev->read_subdev = s;
1619 s->subdev_flags |= SDF_CMD_READ;
1620 s->do_cmd = labpc_ai_cmd;
1621 s->do_cmdtest = labpc_ai_cmdtest;
1622 s->cancel = labpc_cancel;
1623 }
1624
1625 /* analog output */
1626 s = &dev->subdevices[1];
1627 if (board->has_ao) {
1628 s->type = COMEDI_SUBD_AO;
1629 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
1630 s->n_chan = NUM_AO_CHAN;
1631 s->maxdata = 0x0fff;
1632 s->range_table = &range_labpc_ao;
1633 s->insn_read = labpc_ao_insn_read;
1634 s->insn_write = labpc_ao_insn_write;
1635
1636 /* initialize analog outputs to a known value */
1637 for (i = 0; i < s->n_chan; i++) {
1638 short lsb, msb;
1639
1640 devpriv->ao_value[i] = s->maxdata / 2;
1641 lsb = devpriv->ao_value[i] & 0xff;
1642 msb = (devpriv->ao_value[i] >> 8) & 0xff;
1643 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
1644 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
1645 }
1646 } else {
1647 s->type = COMEDI_SUBD_UNUSED;
1648 }
1649
1650 /* 8255 dio */
1651 s = &dev->subdevices[2];
1652 ret = subdev_8255_init(dev, s,
1653 (board->has_mmio) ? labpc_8255_mmio : NULL,
1654 dev->iobase + DIO_BASE_REG);
1655 if (ret)
1656 return ret;
1657
1658 /* calibration subdevices for boards that have one */
1659 s = &dev->subdevices[3];
1660 if (board->is_labpc1200) {
1661 s->type = COMEDI_SUBD_CALIB;
1662 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1663 s->n_chan = 16;
1664 s->maxdata = 0xff;
1665 s->insn_read = labpc_calib_insn_read;
1666 s->insn_write = labpc_calib_insn_write;
1667
1668 for (i = 0; i < s->n_chan; i++)
1669 write_caldac(dev, i, s->maxdata / 2);
1670 } else
1671 s->type = COMEDI_SUBD_UNUSED;
1672
1673 /* EEPROM */
1674 s = &dev->subdevices[4];
1675 if (board->is_labpc1200) {
1676 s->type = COMEDI_SUBD_MEMORY;
1677 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1678 s->n_chan = EEPROM_SIZE;
1679 s->maxdata = 0xff;
1680 s->insn_read = labpc_eeprom_insn_read;
1681 s->insn_write = labpc_eeprom_insn_write;
1682
1683 for (i = 0; i < s->n_chan; i++)
1684 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
1685 } else
1686 s->type = COMEDI_SUBD_UNUSED;
1687
1688 return 0;
1689 }
1690 EXPORT_SYMBOL_GPL(labpc_common_attach);
1691
1692 #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA)
1693 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1694 {
1695 struct labpc_private *devpriv;
1696 unsigned int irq = it->options[1];
1697 unsigned int dma_chan = it->options[2];
1698 int ret;
1699
1700 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1701 if (!devpriv)
1702 return -ENOMEM;
1703 dev->private = devpriv;
1704
1705 ret = comedi_request_region(dev, it->options[0], LABPC_SIZE);
1706 if (ret)
1707 return ret;
1708
1709 ret = labpc_common_attach(dev, irq, 0);
1710 if (ret)
1711 return ret;
1712
1713 #ifdef CONFIG_ISA_DMA_API
1714 if (dev->irq && (dma_chan == 1 || dma_chan == 3)) {
1715 devpriv->dma_buffer = kmalloc(dma_buffer_size,
1716 GFP_KERNEL | GFP_DMA);
1717 if (devpriv->dma_buffer) {
1718 ret = request_dma(dma_chan, dev->board_name);
1719 if (ret == 0) {
1720 unsigned long dma_flags;
1721
1722 devpriv->dma_chan = dma_chan;
1723 devpriv->dma_addr =
1724 virt_to_bus(devpriv->dma_buffer);
1725
1726 dma_flags = claim_dma_lock();
1727 disable_dma(devpriv->dma_chan);
1728 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
1729 release_dma_lock(dma_flags);
1730 } else {
1731 kfree(devpriv->dma_buffer);
1732 }
1733 }
1734 }
1735 #endif
1736
1737 return 0;
1738 }
1739
1740 static void labpc_detach(struct comedi_device *dev)
1741 {
1742 struct labpc_private *devpriv = dev->private;
1743
1744 if (devpriv) {
1745 kfree(devpriv->dma_buffer);
1746 if (devpriv->dma_chan)
1747 free_dma(devpriv->dma_chan);
1748 }
1749 comedi_legacy_detach(dev);
1750 }
1751
1752 static struct comedi_driver labpc_driver = {
1753 .driver_name = "ni_labpc",
1754 .module = THIS_MODULE,
1755 .attach = labpc_attach,
1756 .detach = labpc_detach,
1757 .num_names = ARRAY_SIZE(labpc_boards),
1758 .board_name = &labpc_boards[0].name,
1759 .offset = sizeof(struct labpc_boardinfo),
1760 };
1761 module_comedi_driver(labpc_driver);
1762 #else
1763 static int __init labpc_common_init(void)
1764 {
1765 return 0;
1766 }
1767 module_init(labpc_common_init);
1768
1769 static void __exit labpc_common_exit(void)
1770 {
1771 }
1772 module_exit(labpc_common_exit);
1773 #endif
1774
1775 MODULE_AUTHOR("Comedi http://www.comedi.org");
1776 MODULE_DESCRIPTION("Comedi low-level driver");
1777 MODULE_LICENSE("GPL");
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