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staging: comedi: ni_mio_common: tidy up the frequency output subdevice init
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53 */
54
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
58 #include "8255.h"
59 #include "mite.h"
60 #include "comedi_fc.h"
61
62 /* A timeout count */
63 #define NI_TIMEOUT 1000
64 static const unsigned old_RTSI_clock_channel = 7;
65
66 /* Note: this table must match the ai_gain_* definitions */
67 static const short ni_gainlkup[][16] = {
68 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
69 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
70 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
71 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
72 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
73 [ai_gain_4] = {0, 1, 4, 7},
74 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
75 0x003, 0x004, 0x005, 0x006},
76 [ai_gain_622x] = {0, 1, 4, 5},
77 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
78 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
79 };
80
81 static const struct comedi_lrange range_ni_E_ai = {
82 16, {
83 BIP_RANGE(10),
84 BIP_RANGE(5),
85 BIP_RANGE(2.5),
86 BIP_RANGE(1),
87 BIP_RANGE(0.5),
88 BIP_RANGE(0.25),
89 BIP_RANGE(0.1),
90 BIP_RANGE(0.05),
91 UNI_RANGE(20),
92 UNI_RANGE(10),
93 UNI_RANGE(5),
94 UNI_RANGE(2),
95 UNI_RANGE(1),
96 UNI_RANGE(0.5),
97 UNI_RANGE(0.2),
98 UNI_RANGE(0.1)
99 }
100 };
101
102 static const struct comedi_lrange range_ni_E_ai_limited = {
103 8, {
104 BIP_RANGE(10),
105 BIP_RANGE(5),
106 BIP_RANGE(1),
107 BIP_RANGE(0.1),
108 UNI_RANGE(10),
109 UNI_RANGE(5),
110 UNI_RANGE(1),
111 UNI_RANGE(0.1)
112 }
113 };
114
115 static const struct comedi_lrange range_ni_E_ai_limited14 = {
116 14, {
117 BIP_RANGE(10),
118 BIP_RANGE(5),
119 BIP_RANGE(2),
120 BIP_RANGE(1),
121 BIP_RANGE(0.5),
122 BIP_RANGE(0.2),
123 BIP_RANGE(0.1),
124 UNI_RANGE(10),
125 UNI_RANGE(5),
126 UNI_RANGE(2),
127 UNI_RANGE(1),
128 UNI_RANGE(0.5),
129 UNI_RANGE(0.2),
130 UNI_RANGE(0.1)
131 }
132 };
133
134 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
135 4, {
136 BIP_RANGE(10),
137 BIP_RANGE(5),
138 BIP_RANGE(0.5),
139 BIP_RANGE(0.05)
140 }
141 };
142
143 static const struct comedi_lrange range_ni_E_ai_611x = {
144 8, {
145 BIP_RANGE(50),
146 BIP_RANGE(20),
147 BIP_RANGE(10),
148 BIP_RANGE(5),
149 BIP_RANGE(2),
150 BIP_RANGE(1),
151 BIP_RANGE(0.5),
152 BIP_RANGE(0.2)
153 }
154 };
155
156 static const struct comedi_lrange range_ni_M_ai_622x = {
157 4, {
158 BIP_RANGE(10),
159 BIP_RANGE(5),
160 BIP_RANGE(1),
161 BIP_RANGE(0.2)
162 }
163 };
164
165 static const struct comedi_lrange range_ni_M_ai_628x = {
166 7, {
167 BIP_RANGE(10),
168 BIP_RANGE(5),
169 BIP_RANGE(2),
170 BIP_RANGE(1),
171 BIP_RANGE(0.5),
172 BIP_RANGE(0.2),
173 BIP_RANGE(0.1)
174 }
175 };
176
177 static const struct comedi_lrange range_ni_E_ao_ext = {
178 4, {
179 BIP_RANGE(10),
180 UNI_RANGE(10),
181 RANGE_ext(-1, 1),
182 RANGE_ext(0, 1)
183 }
184 };
185
186 static const struct comedi_lrange *const ni_range_lkup[] = {
187 [ai_gain_16] = &range_ni_E_ai,
188 [ai_gain_8] = &range_ni_E_ai_limited,
189 [ai_gain_14] = &range_ni_E_ai_limited14,
190 [ai_gain_4] = &range_ni_E_ai_bipolar4,
191 [ai_gain_611x] = &range_ni_E_ai_611x,
192 [ai_gain_622x] = &range_ni_M_ai_622x,
193 [ai_gain_628x] = &range_ni_M_ai_628x,
194 [ai_gain_6143] = &range_bipolar5
195 };
196
197 enum aimodes {
198 AIMODE_NONE = 0,
199 AIMODE_HALF_FULL = 1,
200 AIMODE_SCAN = 2,
201 AIMODE_SAMPLE = 3,
202 };
203
204 enum ni_common_subdevices {
205 NI_AI_SUBDEV,
206 NI_AO_SUBDEV,
207 NI_DIO_SUBDEV,
208 NI_8255_DIO_SUBDEV,
209 NI_UNUSED_SUBDEV,
210 NI_CALIBRATION_SUBDEV,
211 NI_EEPROM_SUBDEV,
212 NI_PFI_DIO_SUBDEV,
213 NI_CS5529_CALIBRATION_SUBDEV,
214 NI_SERIAL_SUBDEV,
215 NI_RTSI_SUBDEV,
216 NI_GPCT0_SUBDEV,
217 NI_GPCT1_SUBDEV,
218 NI_FREQ_OUT_SUBDEV,
219 NI_NUM_SUBDEVICES
220 };
221 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
222 {
223 switch (counter_index) {
224 case 0:
225 return NI_GPCT0_SUBDEV;
226 break;
227 case 1:
228 return NI_GPCT1_SUBDEV;
229 break;
230 default:
231 break;
232 }
233 BUG();
234 return NI_GPCT0_SUBDEV;
235 }
236
237 enum timebase_nanoseconds {
238 TIMEBASE_1_NS = 50,
239 TIMEBASE_2_NS = 10000
240 };
241
242 #define SERIAL_DISABLED 0
243 #define SERIAL_600NS 600
244 #define SERIAL_1_2US 1200
245 #define SERIAL_10US 10000
246
247 static const int num_adc_stages_611x = 3;
248
249 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
250 {
251 struct ni_private *devpriv = dev->private;
252
253 if (devpriv->mite)
254 writel(data, devpriv->mite->daq_io_addr + reg);
255 else
256 outl(data, dev->iobase + reg);
257 }
258
259 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
260 {
261 struct ni_private *devpriv = dev->private;
262
263 if (devpriv->mite)
264 writew(data, devpriv->mite->daq_io_addr + reg);
265 else
266 outw(data, dev->iobase + reg);
267 }
268
269 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
270 {
271 struct ni_private *devpriv = dev->private;
272
273 if (devpriv->mite)
274 writeb(data, devpriv->mite->daq_io_addr + reg);
275 else
276 outb(data, dev->iobase + reg);
277 }
278
279 static uint32_t ni_readl(struct comedi_device *dev, int reg)
280 {
281 struct ni_private *devpriv = dev->private;
282
283 if (devpriv->mite)
284 return readl(devpriv->mite->daq_io_addr + reg);
285 else
286 return inl(dev->iobase + reg);
287 }
288
289 static uint16_t ni_readw(struct comedi_device *dev, int reg)
290 {
291 struct ni_private *devpriv = dev->private;
292
293 if (devpriv->mite)
294 return readw(devpriv->mite->daq_io_addr + reg);
295 else
296 return inw(dev->iobase + reg);
297 }
298
299 static uint8_t ni_readb(struct comedi_device *dev, int reg)
300 {
301 struct ni_private *devpriv = dev->private;
302
303 if (devpriv->mite)
304 return readb(devpriv->mite->daq_io_addr + reg);
305 else
306 return inb(dev->iobase + reg);
307 }
308
309 /*
310 * We automatically take advantage of STC registers that can be
311 * read/written directly in the I/O space of the board.
312 *
313 * The AT-MIO and DAQCard devices map the low 8 STC registers to
314 * iobase+reg*2.
315 *
316 * Most PCIMIO devices also map the low 8 STC registers but the
317 * 611x devices map the read registers to iobase+(addr-1)*2.
318 * For now non-windowed STC access is disabled if a PCIMIO device
319 * is detected (devpriv->mite has been initialized).
320 *
321 * The M series devices do not used windowed registers for the
322 * STC registers. The functions below handle the mapping of the
323 * windowed STC registers to the m series register offsets.
324 */
325
326 static void m_series_stc_writel(struct comedi_device *dev,
327 uint32_t data, int reg)
328 {
329 unsigned offset;
330
331 switch (reg) {
332 case AI_SC_Load_A_Registers:
333 offset = M_Offset_AI_SC_Load_A;
334 break;
335 case AI_SI_Load_A_Registers:
336 offset = M_Offset_AI_SI_Load_A;
337 break;
338 case AO_BC_Load_A_Register:
339 offset = M_Offset_AO_BC_Load_A;
340 break;
341 case AO_UC_Load_A_Register:
342 offset = M_Offset_AO_UC_Load_A;
343 break;
344 case AO_UI_Load_A_Register:
345 offset = M_Offset_AO_UI_Load_A;
346 break;
347 case G_Load_A_Register(0):
348 offset = M_Offset_G0_Load_A;
349 break;
350 case G_Load_A_Register(1):
351 offset = M_Offset_G1_Load_A;
352 break;
353 case G_Load_B_Register(0):
354 offset = M_Offset_G0_Load_B;
355 break;
356 case G_Load_B_Register(1):
357 offset = M_Offset_G1_Load_B;
358 break;
359 default:
360 dev_warn(dev->class_dev,
361 "%s: bug! unhandled register=0x%x in switch\n",
362 __func__, reg);
363 return;
364 }
365 ni_writel(dev, data, offset);
366 }
367
368 static void m_series_stc_writew(struct comedi_device *dev,
369 uint16_t data, int reg)
370 {
371 unsigned offset;
372
373 switch (reg) {
374 case ADC_FIFO_Clear:
375 offset = M_Offset_AI_FIFO_Clear;
376 break;
377 case AI_Command_1_Register:
378 offset = M_Offset_AI_Command_1;
379 break;
380 case AI_Command_2_Register:
381 offset = M_Offset_AI_Command_2;
382 break;
383 case AI_Mode_1_Register:
384 offset = M_Offset_AI_Mode_1;
385 break;
386 case AI_Mode_2_Register:
387 offset = M_Offset_AI_Mode_2;
388 break;
389 case AI_Mode_3_Register:
390 offset = M_Offset_AI_Mode_3;
391 break;
392 case AI_Output_Control_Register:
393 offset = M_Offset_AI_Output_Control;
394 break;
395 case AI_Personal_Register:
396 offset = M_Offset_AI_Personal;
397 break;
398 case AI_SI2_Load_A_Register:
399 /* this is a 32 bit register on m series boards */
400 ni_writel(dev, data, M_Offset_AI_SI2_Load_A);
401 return;
402 case AI_SI2_Load_B_Register:
403 /* this is a 32 bit register on m series boards */
404 ni_writel(dev, data, M_Offset_AI_SI2_Load_B);
405 return;
406 case AI_START_STOP_Select_Register:
407 offset = M_Offset_AI_START_STOP_Select;
408 break;
409 case AI_Trigger_Select_Register:
410 offset = M_Offset_AI_Trigger_Select;
411 break;
412 case Analog_Trigger_Etc_Register:
413 offset = M_Offset_Analog_Trigger_Etc;
414 break;
415 case AO_Command_1_Register:
416 offset = M_Offset_AO_Command_1;
417 break;
418 case AO_Command_2_Register:
419 offset = M_Offset_AO_Command_2;
420 break;
421 case AO_Mode_1_Register:
422 offset = M_Offset_AO_Mode_1;
423 break;
424 case AO_Mode_2_Register:
425 offset = M_Offset_AO_Mode_2;
426 break;
427 case AO_Mode_3_Register:
428 offset = M_Offset_AO_Mode_3;
429 break;
430 case AO_Output_Control_Register:
431 offset = M_Offset_AO_Output_Control;
432 break;
433 case AO_Personal_Register:
434 offset = M_Offset_AO_Personal;
435 break;
436 case AO_Start_Select_Register:
437 offset = M_Offset_AO_Start_Select;
438 break;
439 case AO_Trigger_Select_Register:
440 offset = M_Offset_AO_Trigger_Select;
441 break;
442 case Clock_and_FOUT_Register:
443 offset = M_Offset_Clock_and_FOUT;
444 break;
445 case Configuration_Memory_Clear:
446 offset = M_Offset_Configuration_Memory_Clear;
447 break;
448 case DAC_FIFO_Clear:
449 offset = M_Offset_AO_FIFO_Clear;
450 break;
451 case DIO_Control_Register:
452 dev_dbg(dev->class_dev,
453 "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n",
454 __func__, reg);
455 return;
456 case G_Autoincrement_Register(0):
457 offset = M_Offset_G0_Autoincrement;
458 break;
459 case G_Autoincrement_Register(1):
460 offset = M_Offset_G1_Autoincrement;
461 break;
462 case G_Command_Register(0):
463 offset = M_Offset_G0_Command;
464 break;
465 case G_Command_Register(1):
466 offset = M_Offset_G1_Command;
467 break;
468 case G_Input_Select_Register(0):
469 offset = M_Offset_G0_Input_Select;
470 break;
471 case G_Input_Select_Register(1):
472 offset = M_Offset_G1_Input_Select;
473 break;
474 case G_Mode_Register(0):
475 offset = M_Offset_G0_Mode;
476 break;
477 case G_Mode_Register(1):
478 offset = M_Offset_G1_Mode;
479 break;
480 case Interrupt_A_Ack_Register:
481 offset = M_Offset_Interrupt_A_Ack;
482 break;
483 case Interrupt_A_Enable_Register:
484 offset = M_Offset_Interrupt_A_Enable;
485 break;
486 case Interrupt_B_Ack_Register:
487 offset = M_Offset_Interrupt_B_Ack;
488 break;
489 case Interrupt_B_Enable_Register:
490 offset = M_Offset_Interrupt_B_Enable;
491 break;
492 case Interrupt_Control_Register:
493 offset = M_Offset_Interrupt_Control;
494 break;
495 case IO_Bidirection_Pin_Register:
496 offset = M_Offset_IO_Bidirection_Pin;
497 break;
498 case Joint_Reset_Register:
499 offset = M_Offset_Joint_Reset;
500 break;
501 case RTSI_Trig_A_Output_Register:
502 offset = M_Offset_RTSI_Trig_A_Output;
503 break;
504 case RTSI_Trig_B_Output_Register:
505 offset = M_Offset_RTSI_Trig_B_Output;
506 break;
507 case RTSI_Trig_Direction_Register:
508 offset = M_Offset_RTSI_Trig_Direction;
509 break;
510 /*
511 * FIXME: DIO_Output_Register (16 bit reg) is replaced by
512 * M_Offset_Static_Digital_Output (32 bit) and
513 * M_Offset_SCXI_Serial_Data_Out (8 bit)
514 */
515 default:
516 dev_warn(dev->class_dev,
517 "%s: bug! unhandled register=0x%x in switch\n",
518 __func__, reg);
519 return;
520 }
521 ni_writew(dev, data, offset);
522 }
523
524 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
525 {
526 unsigned offset;
527
528 switch (reg) {
529 case G_HW_Save_Register(0):
530 offset = M_Offset_G0_HW_Save;
531 break;
532 case G_HW_Save_Register(1):
533 offset = M_Offset_G1_HW_Save;
534 break;
535 case G_Save_Register(0):
536 offset = M_Offset_G0_Save;
537 break;
538 case G_Save_Register(1):
539 offset = M_Offset_G1_Save;
540 break;
541 default:
542 dev_warn(dev->class_dev,
543 "%s: bug! unhandled register=0x%x in switch\n",
544 __func__, reg);
545 return 0;
546 }
547 return ni_readl(dev, offset);
548 }
549
550 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
551 {
552 unsigned offset;
553
554 switch (reg) {
555 case AI_Status_1_Register:
556 offset = M_Offset_AI_Status_1;
557 break;
558 case AO_Status_1_Register:
559 offset = M_Offset_AO_Status_1;
560 break;
561 case AO_Status_2_Register:
562 offset = M_Offset_AO_Status_2;
563 break;
564 case DIO_Serial_Input_Register:
565 return ni_readb(dev, M_Offset_SCXI_Serial_Data_In);
566 case Joint_Status_1_Register:
567 offset = M_Offset_Joint_Status_1;
568 break;
569 case Joint_Status_2_Register:
570 offset = M_Offset_Joint_Status_2;
571 break;
572 case G_Status_Register:
573 offset = M_Offset_G01_Status;
574 break;
575 default:
576 dev_warn(dev->class_dev,
577 "%s: bug! unhandled register=0x%x in switch\n",
578 __func__, reg);
579 return 0;
580 }
581 return ni_readw(dev, offset);
582 }
583
584 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
585 {
586 struct ni_private *devpriv = dev->private;
587 unsigned long flags;
588
589 if (devpriv->is_m_series) {
590 m_series_stc_writew(dev, data, reg);
591 } else {
592 spin_lock_irqsave(&devpriv->window_lock, flags);
593 if (!devpriv->mite && reg < 8) {
594 ni_writew(dev, data, reg * 2);
595 } else {
596 ni_writew(dev, reg, Window_Address);
597 ni_writew(dev, data, Window_Data);
598 }
599 spin_unlock_irqrestore(&devpriv->window_lock, flags);
600 }
601 }
602
603 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
604 {
605 struct ni_private *devpriv = dev->private;
606
607 if (devpriv->is_m_series) {
608 m_series_stc_writel(dev, data, reg);
609 } else {
610 ni_stc_writew(dev, data >> 16, reg);
611 ni_stc_writew(dev, data & 0xffff, reg + 1);
612 }
613 }
614
615 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
616 {
617 struct ni_private *devpriv = dev->private;
618 unsigned long flags;
619 uint16_t val;
620
621 if (devpriv->is_m_series) {
622 val = m_series_stc_readw(dev, reg);
623 } else {
624 spin_lock_irqsave(&devpriv->window_lock, flags);
625 if (!devpriv->mite && reg < 8) {
626 val = ni_readw(dev, reg * 2);
627 } else {
628 ni_writew(dev, reg, Window_Address);
629 val = ni_readw(dev, Window_Data);
630 }
631 spin_unlock_irqrestore(&devpriv->window_lock, flags);
632 }
633 return val;
634 }
635
636 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
637 {
638 struct ni_private *devpriv = dev->private;
639 uint32_t val;
640
641 if (devpriv->is_m_series) {
642 val = m_series_stc_readl(dev, reg);
643 } else {
644 val = ni_stc_readw(dev, reg) << 16;
645 val |= ni_stc_readw(dev, reg + 1);
646 }
647 return val;
648 }
649
650 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
651 unsigned bit_mask, unsigned bit_values)
652 {
653 struct ni_private *devpriv = dev->private;
654 unsigned long flags;
655
656 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
657 switch (reg) {
658 case Interrupt_A_Enable_Register:
659 devpriv->int_a_enable_reg &= ~bit_mask;
660 devpriv->int_a_enable_reg |= bit_values & bit_mask;
661 ni_stc_writew(dev, devpriv->int_a_enable_reg,
662 Interrupt_A_Enable_Register);
663 break;
664 case Interrupt_B_Enable_Register:
665 devpriv->int_b_enable_reg &= ~bit_mask;
666 devpriv->int_b_enable_reg |= bit_values & bit_mask;
667 ni_stc_writew(dev, devpriv->int_b_enable_reg,
668 Interrupt_B_Enable_Register);
669 break;
670 case IO_Bidirection_Pin_Register:
671 devpriv->io_bidirection_pin_reg &= ~bit_mask;
672 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
673 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg,
674 IO_Bidirection_Pin_Register);
675 break;
676 case AI_AO_Select:
677 devpriv->ai_ao_select_reg &= ~bit_mask;
678 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
679 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
680 break;
681 case G0_G1_Select:
682 devpriv->g0_g1_select_reg &= ~bit_mask;
683 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
684 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
685 break;
686 default:
687 printk("Warning %s() called with invalid register\n", __func__);
688 printk("reg is %d\n", reg);
689 break;
690 }
691 mmiowb();
692 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
693 }
694
695 #ifdef PCIDMA
696 /* DMA channel setup */
697
698 /* negative channel means no channel */
699 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
700 {
701 unsigned bitfield;
702
703 if (channel >= 0) {
704 bitfield =
705 (ni_stc_dma_channel_select_bitfield(channel) <<
706 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
707 } else {
708 bitfield = 0;
709 }
710 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
711 }
712
713 /* negative channel means no channel */
714 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
715 {
716 unsigned bitfield;
717
718 if (channel >= 0) {
719 bitfield =
720 (ni_stc_dma_channel_select_bitfield(channel) <<
721 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
722 } else {
723 bitfield = 0;
724 }
725 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
726 }
727
728 /* negative mite_channel means no channel */
729 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
730 unsigned gpct_index,
731 int mite_channel)
732 {
733 unsigned bitfield;
734
735 if (mite_channel >= 0)
736 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
737 else
738 bitfield = 0;
739 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
740 bitfield);
741 }
742
743 /* negative mite_channel means no channel */
744 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
745 int mite_channel)
746 {
747 struct ni_private *devpriv = dev->private;
748 unsigned long flags;
749
750 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
751 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
752 if (mite_channel >= 0) {
753 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
754 under the assumption the cdio dma selection works just like ai/ao/gpct.
755 Definitely works for dma channels 0 and 1. */
756 devpriv->cdio_dma_select_reg |=
757 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
758 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
759 }
760 ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
761 mmiowb();
762 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
763 }
764
765 static int ni_request_ai_mite_channel(struct comedi_device *dev)
766 {
767 struct ni_private *devpriv = dev->private;
768 unsigned long flags;
769
770 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
771 BUG_ON(devpriv->ai_mite_chan);
772 devpriv->ai_mite_chan =
773 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
774 if (devpriv->ai_mite_chan == NULL) {
775 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
776 comedi_error(dev,
777 "failed to reserve mite dma channel for analog input.");
778 return -EBUSY;
779 }
780 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
781 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
782 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
783 return 0;
784 }
785
786 static int ni_request_ao_mite_channel(struct comedi_device *dev)
787 {
788 struct ni_private *devpriv = dev->private;
789 unsigned long flags;
790
791 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
792 BUG_ON(devpriv->ao_mite_chan);
793 devpriv->ao_mite_chan =
794 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
795 if (devpriv->ao_mite_chan == NULL) {
796 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
797 comedi_error(dev,
798 "failed to reserve mite dma channel for analog outut.");
799 return -EBUSY;
800 }
801 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
802 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
803 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
804 return 0;
805 }
806
807 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
808 unsigned gpct_index,
809 enum comedi_io_direction direction)
810 {
811 struct ni_private *devpriv = dev->private;
812 unsigned long flags;
813 struct mite_channel *mite_chan;
814
815 BUG_ON(gpct_index >= NUM_GPCT);
816 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
817 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
818 mite_chan =
819 mite_request_channel(devpriv->mite,
820 devpriv->gpct_mite_ring[gpct_index]);
821 if (mite_chan == NULL) {
822 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
823 comedi_error(dev,
824 "failed to reserve mite dma channel for counter.");
825 return -EBUSY;
826 }
827 mite_chan->dir = direction;
828 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
829 mite_chan);
830 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
831 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
832 return 0;
833 }
834
835 #endif /* PCIDMA */
836
837 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
838 {
839 #ifdef PCIDMA
840 struct ni_private *devpriv = dev->private;
841 unsigned long flags;
842
843 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
844 BUG_ON(devpriv->cdo_mite_chan);
845 devpriv->cdo_mite_chan =
846 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
847 if (devpriv->cdo_mite_chan == NULL) {
848 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
849 comedi_error(dev,
850 "failed to reserve mite dma channel for correlated digital outut.");
851 return -EBUSY;
852 }
853 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
854 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
855 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
856 #endif /* PCIDMA */
857 return 0;
858 }
859
860 static void ni_release_ai_mite_channel(struct comedi_device *dev)
861 {
862 #ifdef PCIDMA
863 struct ni_private *devpriv = dev->private;
864 unsigned long flags;
865
866 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
867 if (devpriv->ai_mite_chan) {
868 ni_set_ai_dma_channel(dev, -1);
869 mite_release_channel(devpriv->ai_mite_chan);
870 devpriv->ai_mite_chan = NULL;
871 }
872 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
873 #endif /* PCIDMA */
874 }
875
876 static void ni_release_ao_mite_channel(struct comedi_device *dev)
877 {
878 #ifdef PCIDMA
879 struct ni_private *devpriv = dev->private;
880 unsigned long flags;
881
882 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
883 if (devpriv->ao_mite_chan) {
884 ni_set_ao_dma_channel(dev, -1);
885 mite_release_channel(devpriv->ao_mite_chan);
886 devpriv->ao_mite_chan = NULL;
887 }
888 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
889 #endif /* PCIDMA */
890 }
891
892 #ifdef PCIDMA
893 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
894 unsigned gpct_index)
895 {
896 struct ni_private *devpriv = dev->private;
897 unsigned long flags;
898
899 BUG_ON(gpct_index >= NUM_GPCT);
900 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
901 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
902 struct mite_channel *mite_chan =
903 devpriv->counter_dev->counters[gpct_index].mite_chan;
904
905 ni_set_gpct_dma_channel(dev, gpct_index, -1);
906 ni_tio_set_mite_channel(&devpriv->
907 counter_dev->counters[gpct_index],
908 NULL);
909 mite_release_channel(mite_chan);
910 }
911 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
912 }
913 #endif /* PCIDMA */
914
915 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
916 {
917 #ifdef PCIDMA
918 struct ni_private *devpriv = dev->private;
919 unsigned long flags;
920
921 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
922 if (devpriv->cdo_mite_chan) {
923 ni_set_cdo_dma_channel(dev, -1);
924 mite_release_channel(devpriv->cdo_mite_chan);
925 devpriv->cdo_mite_chan = NULL;
926 }
927 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
928 #endif /* PCIDMA */
929 }
930
931 #ifdef PCIDMA
932 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
933 unsigned gpct_index, short enable)
934 {
935 struct ni_private *devpriv = dev->private;
936 uint16_t val = 0;
937 int reg;
938
939 if (devpriv->is_m_series || gpct_index > 1)
940 return;
941
942 /*
943 * e-series boards use the second irq signals to generate
944 * dma requests for their counters
945 */
946 if (gpct_index == 0) {
947 reg = Second_IRQ_A_Enable_Register;
948 if (enable)
949 val = G0_Gate_Second_Irq_Enable;
950 } else {
951 reg = Second_IRQ_B_Enable_Register;
952 if (enable)
953 val = G1_Gate_Second_Irq_Enable;
954 }
955 ni_stc_writew(dev, val, reg);
956 }
957 #endif /* PCIDMA */
958
959 static void ni_clear_ai_fifo(struct comedi_device *dev)
960 {
961 struct ni_private *devpriv = dev->private;
962 static const int timeout = 10000;
963 int i;
964
965 if (devpriv->is_6143) {
966 /* Flush the 6143 data FIFO */
967 ni_writel(dev, 0x10, AIFIFO_Control_6143);
968 ni_writel(dev, 0x00, AIFIFO_Control_6143);
969 /* Wait for complete */
970 for (i = 0; i < timeout; i++) {
971 if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
972 break;
973 udelay(1);
974 }
975 if (i == timeout) {
976 comedi_error(dev, "FIFO flush timeout.");
977 }
978 } else {
979 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
980 if (devpriv->is_625x) {
981 ni_writeb(dev, 0, M_Offset_Static_AI_Control(0));
982 ni_writeb(dev, 1, M_Offset_Static_AI_Control(0));
983 #if 0
984 /* the NI example code does 3 convert pulses for 625x boards,
985 but that appears to be wrong in practice. */
986 ni_stc_writew(dev, AI_CONVERT_Pulse,
987 AI_Command_1_Register);
988 ni_stc_writew(dev, AI_CONVERT_Pulse,
989 AI_Command_1_Register);
990 ni_stc_writew(dev, AI_CONVERT_Pulse,
991 AI_Command_1_Register);
992 #endif
993 }
994 }
995 }
996
997 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
998 int addr)
999 {
1000 struct ni_private *devpriv = dev->private;
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&devpriv->window_lock, flags);
1004 ni_writew(dev, addr, AO_Window_Address_611x);
1005 ni_writew(dev, data, AO_Window_Data_611x);
1006 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1007 }
1008
1009 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
1010 int addr)
1011 {
1012 struct ni_private *devpriv = dev->private;
1013 unsigned long flags;
1014
1015 spin_lock_irqsave(&devpriv->window_lock, flags);
1016 ni_writew(dev, addr, AO_Window_Address_611x);
1017 ni_writel(dev, data, AO_Window_Data_611x);
1018 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1019 }
1020
1021 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
1022 {
1023 struct ni_private *devpriv = dev->private;
1024 unsigned long flags;
1025 unsigned short data;
1026
1027 spin_lock_irqsave(&devpriv->window_lock, flags);
1028 ni_writew(dev, addr, AO_Window_Address_611x);
1029 data = ni_readw(dev, AO_Window_Data_611x);
1030 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1031 return data;
1032 }
1033
1034 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
1035 * share registers (such as Interrupt_A_Register) without interfering with
1036 * each other.
1037 *
1038 * NOTE: the switch/case statements are optimized out for a constant argument
1039 * so this is actually quite fast--- If you must wrap another function around this
1040 * make it inline to avoid a large speed penalty.
1041 *
1042 * value should only be 1 or 0.
1043 */
1044 static inline void ni_set_bits(struct comedi_device *dev, int reg,
1045 unsigned bits, unsigned value)
1046 {
1047 unsigned bit_values;
1048
1049 if (value)
1050 bit_values = bits;
1051 else
1052 bit_values = 0;
1053 ni_set_bitfield(dev, reg, bits, bit_values);
1054 }
1055
1056 #ifdef PCIDMA
1057 static void ni_sync_ai_dma(struct comedi_device *dev)
1058 {
1059 struct ni_private *devpriv = dev->private;
1060 struct comedi_subdevice *s = dev->read_subdev;
1061 unsigned long flags;
1062
1063 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1064 if (devpriv->ai_mite_chan)
1065 mite_sync_input_dma(devpriv->ai_mite_chan, s);
1066 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1067 }
1068
1069 static int ni_ai_drain_dma(struct comedi_device *dev)
1070 {
1071 struct ni_private *devpriv = dev->private;
1072 int i;
1073 static const int timeout = 10000;
1074 unsigned long flags;
1075 int retval = 0;
1076
1077 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1078 if (devpriv->ai_mite_chan) {
1079 for (i = 0; i < timeout; i++) {
1080 if ((ni_stc_readw(dev, AI_Status_1_Register) &
1081 AI_FIFO_Empty_St)
1082 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1083 0)
1084 break;
1085 udelay(5);
1086 }
1087 if (i == timeout) {
1088 printk("ni_mio_common: wait for dma drain timed out\n");
1089 printk
1090 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1091 mite_bytes_in_transit(devpriv->ai_mite_chan),
1092 ni_stc_readw(dev, AI_Status_1_Register));
1093 retval = -1;
1094 }
1095 }
1096 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1097
1098 ni_sync_ai_dma(dev);
1099
1100 return retval;
1101 }
1102
1103 static void mite_handle_b_linkc(struct mite_struct *mite,
1104 struct comedi_device *dev)
1105 {
1106 struct ni_private *devpriv = dev->private;
1107 struct comedi_subdevice *s = dev->write_subdev;
1108 unsigned long flags;
1109
1110 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1111 if (devpriv->ao_mite_chan)
1112 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1113 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1114 }
1115
1116 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1117 {
1118 static const int timeout = 10000;
1119 int i;
1120 for (i = 0; i < timeout; i++) {
1121 unsigned short b_status;
1122
1123 b_status = ni_stc_readw(dev, AO_Status_1_Register);
1124 if (b_status & AO_FIFO_Half_Full_St)
1125 break;
1126 /* if we poll too often, the pci bus activity seems
1127 to slow the dma transfer down */
1128 udelay(10);
1129 }
1130 if (i == timeout) {
1131 comedi_error(dev, "timed out waiting for dma load");
1132 return -EPIPE;
1133 }
1134 return 0;
1135 }
1136 #endif /* PCIDMA */
1137
1138 #ifndef PCIDMA
1139
1140 static void ni_ao_fifo_load(struct comedi_device *dev,
1141 struct comedi_subdevice *s, int n)
1142 {
1143 struct ni_private *devpriv = dev->private;
1144 struct comedi_async *async = s->async;
1145 struct comedi_cmd *cmd = &async->cmd;
1146 int chan;
1147 int i;
1148 unsigned short d;
1149 u32 packed_data;
1150 int range;
1151 int err = 1;
1152
1153 chan = async->cur_chan;
1154 for (i = 0; i < n; i++) {
1155 err &= comedi_buf_get(s, &d);
1156 if (err == 0)
1157 break;
1158
1159 range = CR_RANGE(cmd->chanlist[chan]);
1160
1161 if (devpriv->is_6xxx) {
1162 packed_data = d & 0xffff;
1163 /* 6711 only has 16 bit wide ao fifo */
1164 if (!devpriv->is_6711) {
1165 err &= comedi_buf_get(s, &d);
1166 if (err == 0)
1167 break;
1168 chan++;
1169 i++;
1170 packed_data |= (d << 16) & 0xffff0000;
1171 }
1172 ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1173 } else {
1174 ni_writew(dev, d, DAC_FIFO_Data);
1175 }
1176 chan++;
1177 chan %= cmd->chanlist_len;
1178 }
1179 async->cur_chan = chan;
1180 if (err == 0)
1181 async->events |= COMEDI_CB_OVERFLOW;
1182 }
1183
1184 /*
1185 * There's a small problem if the FIFO gets really low and we
1186 * don't have the data to fill it. Basically, if after we fill
1187 * the FIFO with all the data available, the FIFO is _still_
1188 * less than half full, we never clear the interrupt. If the
1189 * IRQ is in edge mode, we never get another interrupt, because
1190 * this one wasn't cleared. If in level mode, we get flooded
1191 * with interrupts that we can't fulfill, because nothing ever
1192 * gets put into the buffer.
1193 *
1194 * This kind of situation is recoverable, but it is easier to
1195 * just pretend we had a FIFO underrun, since there is a good
1196 * chance it will happen anyway. This is _not_ the case for
1197 * RT code, as RT code might purposely be running close to the
1198 * metal. Needs to be fixed eventually.
1199 */
1200 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1201 struct comedi_subdevice *s)
1202 {
1203 const struct ni_board_struct *board = comedi_board(dev);
1204 int n;
1205
1206 n = comedi_buf_read_n_available(s);
1207 if (n == 0) {
1208 s->async->events |= COMEDI_CB_OVERFLOW;
1209 return 0;
1210 }
1211
1212 n /= sizeof(short);
1213 if (n > board->ao_fifo_depth / 2)
1214 n = board->ao_fifo_depth / 2;
1215
1216 ni_ao_fifo_load(dev, s, n);
1217
1218 s->async->events |= COMEDI_CB_BLOCK;
1219
1220 return 1;
1221 }
1222
1223 static int ni_ao_prep_fifo(struct comedi_device *dev,
1224 struct comedi_subdevice *s)
1225 {
1226 const struct ni_board_struct *board = comedi_board(dev);
1227 struct ni_private *devpriv = dev->private;
1228 int n;
1229
1230 /* reset fifo */
1231 ni_stc_writew(dev, 1, DAC_FIFO_Clear);
1232 if (devpriv->is_6xxx)
1233 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1234
1235 /* load some data */
1236 n = comedi_buf_read_n_available(s);
1237 if (n == 0)
1238 return 0;
1239
1240 n /= sizeof(short);
1241 if (n > board->ao_fifo_depth)
1242 n = board->ao_fifo_depth;
1243
1244 ni_ao_fifo_load(dev, s, n);
1245
1246 return n;
1247 }
1248
1249 static void ni_ai_fifo_read(struct comedi_device *dev,
1250 struct comedi_subdevice *s, int n)
1251 {
1252 struct ni_private *devpriv = dev->private;
1253 struct comedi_async *async = s->async;
1254 int i;
1255
1256 if (devpriv->is_611x) {
1257 unsigned short data[2];
1258 u32 dl;
1259
1260 for (i = 0; i < n / 2; i++) {
1261 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1262 /* This may get the hi/lo data in the wrong order */
1263 data[0] = (dl >> 16) & 0xffff;
1264 data[1] = dl & 0xffff;
1265 cfc_write_array_to_buffer(s, data, sizeof(data));
1266 }
1267 /* Check if there's a single sample stuck in the FIFO */
1268 if (n % 2) {
1269 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1270 data[0] = dl & 0xffff;
1271 cfc_write_to_buffer(s, data[0]);
1272 }
1273 } else if (devpriv->is_6143) {
1274 unsigned short data[2];
1275 u32 dl;
1276
1277 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1278 for (i = 0; i < n / 2; i++) {
1279 dl = ni_readl(dev, AIFIFO_Data_6143);
1280
1281 data[0] = (dl >> 16) & 0xffff;
1282 data[1] = dl & 0xffff;
1283 cfc_write_array_to_buffer(s, data, sizeof(data));
1284 }
1285 if (n % 2) {
1286 /* Assume there is a single sample stuck in the FIFO */
1287 /* Get stranded sample into FIFO */
1288 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1289 dl = ni_readl(dev, AIFIFO_Data_6143);
1290 data[0] = (dl >> 16) & 0xffff;
1291 cfc_write_to_buffer(s, data[0]);
1292 }
1293 } else {
1294 if (n > sizeof(devpriv->ai_fifo_buffer) /
1295 sizeof(devpriv->ai_fifo_buffer[0])) {
1296 comedi_error(dev, "bug! ai_fifo_buffer too small");
1297 async->events |= COMEDI_CB_ERROR;
1298 return;
1299 }
1300 for (i = 0; i < n; i++) {
1301 devpriv->ai_fifo_buffer[i] =
1302 ni_readw(dev, ADC_FIFO_Data_Register);
1303 }
1304 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1305 n *
1306 sizeof(devpriv->ai_fifo_buffer[0]));
1307 }
1308 }
1309
1310 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1311 {
1312 const struct ni_board_struct *board = comedi_board(dev);
1313 struct comedi_subdevice *s = dev->read_subdev;
1314 int n;
1315
1316 n = board->ai_fifo_depth / 2;
1317
1318 ni_ai_fifo_read(dev, s, n);
1319 }
1320 #endif
1321
1322 /*
1323 Empties the AI fifo
1324 */
1325 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1326 {
1327 struct ni_private *devpriv = dev->private;
1328 struct comedi_subdevice *s = dev->read_subdev;
1329 unsigned short data[2];
1330 u32 dl;
1331 unsigned short fifo_empty;
1332 int i;
1333
1334 if (devpriv->is_611x) {
1335 while ((ni_stc_readw(dev, AI_Status_1_Register) &
1336 AI_FIFO_Empty_St) == 0) {
1337 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1338
1339 /* This may get the hi/lo data in the wrong order */
1340 data[0] = (dl >> 16);
1341 data[1] = (dl & 0xffff);
1342 cfc_write_array_to_buffer(s, data, sizeof(data));
1343 }
1344 } else if (devpriv->is_6143) {
1345 i = 0;
1346 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1347 dl = ni_readl(dev, AIFIFO_Data_6143);
1348
1349 /* This may get the hi/lo data in the wrong order */
1350 data[0] = (dl >> 16);
1351 data[1] = (dl & 0xffff);
1352 cfc_write_array_to_buffer(s, data, sizeof(data));
1353 i += 2;
1354 }
1355 /* Check if stranded sample is present */
1356 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1357 /* Get stranded sample into FIFO */
1358 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1359 dl = ni_readl(dev, AIFIFO_Data_6143);
1360 data[0] = (dl >> 16) & 0xffff;
1361 cfc_write_to_buffer(s, data[0]);
1362 }
1363
1364 } else {
1365 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) &
1366 AI_FIFO_Empty_St;
1367 while (fifo_empty == 0) {
1368 for (i = 0;
1369 i <
1370 sizeof(devpriv->ai_fifo_buffer) /
1371 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1372 fifo_empty = ni_stc_readw(dev,
1373 AI_Status_1_Register) &
1374 AI_FIFO_Empty_St;
1375 if (fifo_empty)
1376 break;
1377 devpriv->ai_fifo_buffer[i] =
1378 ni_readw(dev, ADC_FIFO_Data_Register);
1379 }
1380 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1381 i *
1382 sizeof(devpriv->
1383 ai_fifo_buffer[0]));
1384 }
1385 }
1386 }
1387
1388 static void get_last_sample_611x(struct comedi_device *dev)
1389 {
1390 struct ni_private *devpriv = dev->private;
1391 struct comedi_subdevice *s = dev->read_subdev;
1392 unsigned short data;
1393 u32 dl;
1394
1395 if (!devpriv->is_611x)
1396 return;
1397
1398 /* Check if there's a single sample stuck in the FIFO */
1399 if (ni_readb(dev, XXX_Status) & 0x80) {
1400 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1401 data = (dl & 0xffff);
1402 cfc_write_to_buffer(s, data);
1403 }
1404 }
1405
1406 static void get_last_sample_6143(struct comedi_device *dev)
1407 {
1408 struct ni_private *devpriv = dev->private;
1409 struct comedi_subdevice *s = dev->read_subdev;
1410 unsigned short data;
1411 u32 dl;
1412
1413 if (!devpriv->is_6143)
1414 return;
1415
1416 /* Check if there's a single sample stuck in the FIFO */
1417 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1418 /* Get stranded sample into FIFO */
1419 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1420 dl = ni_readl(dev, AIFIFO_Data_6143);
1421
1422 /* This may get the hi/lo data in the wrong order */
1423 data = (dl >> 16) & 0xffff;
1424 cfc_write_to_buffer(s, data);
1425 }
1426 }
1427
1428 static void shutdown_ai_command(struct comedi_device *dev)
1429 {
1430 struct comedi_subdevice *s = dev->read_subdev;
1431
1432 #ifdef PCIDMA
1433 ni_ai_drain_dma(dev);
1434 #endif
1435 ni_handle_fifo_dregs(dev);
1436 get_last_sample_611x(dev);
1437 get_last_sample_6143(dev);
1438
1439 s->async->events |= COMEDI_CB_EOA;
1440 }
1441
1442 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1443 {
1444 struct ni_private *devpriv = dev->private;
1445
1446 if (devpriv->aimode == AIMODE_SCAN) {
1447 #ifdef PCIDMA
1448 static const int timeout = 10;
1449 int i;
1450
1451 for (i = 0; i < timeout; i++) {
1452 ni_sync_ai_dma(dev);
1453 if ((s->async->events & COMEDI_CB_EOS))
1454 break;
1455 udelay(1);
1456 }
1457 #else
1458 ni_handle_fifo_dregs(dev);
1459 s->async->events |= COMEDI_CB_EOS;
1460 #endif
1461 }
1462 /* handle special case of single scan using AI_End_On_End_Of_Scan */
1463 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
1464 shutdown_ai_command(dev);
1465 }
1466
1467 static void handle_gpct_interrupt(struct comedi_device *dev,
1468 unsigned short counter_index)
1469 {
1470 #ifdef PCIDMA
1471 struct ni_private *devpriv = dev->private;
1472 struct comedi_subdevice *s;
1473
1474 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1475
1476 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1477 s);
1478 cfc_handle_events(dev, s);
1479 #endif
1480 }
1481
1482 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1483 {
1484 unsigned short ack = 0;
1485
1486 if (a_status & AI_SC_TC_St)
1487 ack |= AI_SC_TC_Interrupt_Ack;
1488 if (a_status & AI_START1_St)
1489 ack |= AI_START1_Interrupt_Ack;
1490 if (a_status & AI_START_St)
1491 ack |= AI_START_Interrupt_Ack;
1492 if (a_status & AI_STOP_St)
1493 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1494 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
1495 if (ack)
1496 ni_stc_writew(dev, ack, Interrupt_A_Ack_Register);
1497 }
1498
1499 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1500 unsigned ai_mite_status)
1501 {
1502 struct comedi_subdevice *s = dev->read_subdev;
1503 struct comedi_cmd *cmd = &s->async->cmd;
1504
1505 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1506 if (s->type == COMEDI_SUBD_UNUSED)
1507 return;
1508
1509 #ifdef PCIDMA
1510 if (ai_mite_status & CHSR_LINKC)
1511 ni_sync_ai_dma(dev);
1512
1513 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1514 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1515 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1516 printk
1517 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1518 ai_mite_status);
1519 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1520 /* disable_irq(dev->irq); */
1521 }
1522 #endif
1523
1524 /* test for all uncommon interrupt events at the same time */
1525 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1526 AI_SC_TC_St | AI_START1_St)) {
1527 if (status == 0xffff) {
1528 printk
1529 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1530 /* we probably aren't even running a command now,
1531 * so it's a good idea to be careful. */
1532 if (comedi_is_subdevice_running(s)) {
1533 s->async->events |=
1534 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1535 cfc_handle_events(dev, s);
1536 }
1537 return;
1538 }
1539 if (status & (AI_Overrun_St | AI_Overflow_St |
1540 AI_SC_TC_Error_St)) {
1541 printk("ni_mio_common: ai error a_status=%04x\n",
1542 status);
1543
1544 shutdown_ai_command(dev);
1545
1546 s->async->events |= COMEDI_CB_ERROR;
1547 if (status & (AI_Overrun_St | AI_Overflow_St))
1548 s->async->events |= COMEDI_CB_OVERFLOW;
1549
1550 cfc_handle_events(dev, s);
1551 return;
1552 }
1553 if (status & AI_SC_TC_St) {
1554 if (cmd->stop_src == TRIG_COUNT)
1555 shutdown_ai_command(dev);
1556 }
1557 }
1558 #ifndef PCIDMA
1559 if (status & AI_FIFO_Half_Full_St) {
1560 int i;
1561 static const int timeout = 10;
1562 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1563 *fail to get the fifo less than half full, so loop to be sure.*/
1564 for (i = 0; i < timeout; ++i) {
1565 ni_handle_fifo_half_full(dev);
1566 if ((ni_stc_readw(dev, AI_Status_1_Register) &
1567 AI_FIFO_Half_Full_St) == 0)
1568 break;
1569 }
1570 }
1571 #endif /* !PCIDMA */
1572
1573 if ((status & AI_STOP_St))
1574 ni_handle_eos(dev, s);
1575
1576 cfc_handle_events(dev, s);
1577 }
1578
1579 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1580 {
1581 unsigned short ack = 0;
1582
1583 if (b_status & AO_BC_TC_St)
1584 ack |= AO_BC_TC_Interrupt_Ack;
1585 if (b_status & AO_Overrun_St)
1586 ack |= AO_Error_Interrupt_Ack;
1587 if (b_status & AO_START_St)
1588 ack |= AO_START_Interrupt_Ack;
1589 if (b_status & AO_START1_St)
1590 ack |= AO_START1_Interrupt_Ack;
1591 if (b_status & AO_UC_TC_St)
1592 ack |= AO_UC_TC_Interrupt_Ack;
1593 if (b_status & AO_UI2_TC_St)
1594 ack |= AO_UI2_TC_Interrupt_Ack;
1595 if (b_status & AO_UPDATE_St)
1596 ack |= AO_UPDATE_Interrupt_Ack;
1597 if (ack)
1598 ni_stc_writew(dev, ack, Interrupt_B_Ack_Register);
1599 }
1600
1601 static void handle_b_interrupt(struct comedi_device *dev,
1602 unsigned short b_status, unsigned ao_mite_status)
1603 {
1604 struct comedi_subdevice *s = dev->write_subdev;
1605 /* unsigned short ack=0; */
1606
1607 #ifdef PCIDMA
1608 /* Currently, mite.c requires us to handle LINKC */
1609 if (ao_mite_status & CHSR_LINKC) {
1610 struct ni_private *devpriv = dev->private;
1611
1612 mite_handle_b_linkc(devpriv->mite, dev);
1613 }
1614
1615 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1616 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1617 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1618 printk
1619 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1620 ao_mite_status);
1621 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1622 }
1623 #endif
1624
1625 if (b_status == 0xffff)
1626 return;
1627 if (b_status & AO_Overrun_St) {
1628 printk
1629 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1630 b_status, ni_stc_readw(dev, AO_Status_2_Register));
1631 s->async->events |= COMEDI_CB_OVERFLOW;
1632 }
1633
1634 if (b_status & AO_BC_TC_St)
1635 s->async->events |= COMEDI_CB_EOA;
1636
1637 #ifndef PCIDMA
1638 if (b_status & AO_FIFO_Request_St) {
1639 int ret;
1640
1641 ret = ni_ao_fifo_half_empty(dev, s);
1642 if (!ret) {
1643 printk("ni_mio_common: AO buffer underrun\n");
1644 ni_set_bits(dev, Interrupt_B_Enable_Register,
1645 AO_FIFO_Interrupt_Enable |
1646 AO_Error_Interrupt_Enable, 0);
1647 s->async->events |= COMEDI_CB_OVERFLOW;
1648 }
1649 }
1650 #endif
1651
1652 cfc_handle_events(dev, s);
1653 }
1654
1655 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1656 void *data, unsigned int num_bytes,
1657 unsigned int chan_index)
1658 {
1659 struct ni_private *devpriv = dev->private;
1660 struct comedi_async *async = s->async;
1661 struct comedi_cmd *cmd = &async->cmd;
1662 unsigned int length = num_bytes / bytes_per_sample(s);
1663 unsigned short *array = data;
1664 unsigned int *larray = data;
1665 unsigned int i;
1666
1667 for (i = 0; i < length; i++) {
1668 #ifdef PCIDMA
1669 if (s->subdev_flags & SDF_LSAMPL)
1670 larray[i] = le32_to_cpu(larray[i]);
1671 else
1672 array[i] = le16_to_cpu(array[i]);
1673 #endif
1674 if (s->subdev_flags & SDF_LSAMPL)
1675 larray[i] += devpriv->ai_offset[chan_index];
1676 else
1677 array[i] += devpriv->ai_offset[chan_index];
1678 chan_index++;
1679 chan_index %= cmd->chanlist_len;
1680 }
1681 }
1682
1683 #ifdef PCIDMA
1684
1685 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1686 {
1687 struct ni_private *devpriv = dev->private;
1688 struct comedi_subdevice *s = dev->read_subdev;
1689 int retval;
1690 unsigned long flags;
1691
1692 retval = ni_request_ai_mite_channel(dev);
1693 if (retval)
1694 return retval;
1695 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1696
1697 /* write alloc the entire buffer */
1698 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1699
1700 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1701 if (devpriv->ai_mite_chan == NULL) {
1702 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1703 return -EIO;
1704 }
1705
1706 if (devpriv->is_611x || devpriv->is_6143)
1707 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1708 else if (devpriv->is_628x)
1709 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1710 else
1711 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1712
1713 /*start the MITE */
1714 mite_dma_arm(devpriv->ai_mite_chan);
1715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1716
1717 return 0;
1718 }
1719
1720 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1721 {
1722 struct ni_private *devpriv = dev->private;
1723 struct comedi_subdevice *s = dev->write_subdev;
1724 int retval;
1725 unsigned long flags;
1726
1727 retval = ni_request_ao_mite_channel(dev);
1728 if (retval)
1729 return retval;
1730
1731 /* read alloc the entire buffer */
1732 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1733
1734 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1735 if (devpriv->ao_mite_chan) {
1736 if (devpriv->is_611x || devpriv->is_6713) {
1737 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1738 } else {
1739 /* doing 32 instead of 16 bit wide transfers from memory
1740 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1741 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1742 }
1743 mite_dma_arm(devpriv->ao_mite_chan);
1744 } else
1745 retval = -EIO;
1746 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1747
1748 return retval;
1749 }
1750
1751 #endif /* PCIDMA */
1752
1753 /*
1754 used for both cancel ioctl and board initialization
1755
1756 this is pretty harsh for a cancel, but it works...
1757 */
1758
1759 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1760 {
1761 struct ni_private *devpriv = dev->private;
1762
1763 ni_release_ai_mite_channel(dev);
1764 /* ai configuration */
1765 ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,
1766 Joint_Reset_Register);
1767
1768 ni_set_bits(dev, Interrupt_A_Enable_Register,
1769 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1770 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1771 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1772 AI_FIFO_Interrupt_Enable, 0);
1773
1774 ni_clear_ai_fifo(dev);
1775
1776 if (!devpriv->is_6143)
1777 ni_writeb(dev, 0, Misc_Command);
1778
1779 ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1780 ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved
1781 /*| AI_Trigger_Once */,
1782 AI_Mode_1_Register);
1783 ni_stc_writew(dev, 0x0000, AI_Mode_2_Register);
1784 /* generate FIFO interrupts on non-empty */
1785 ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1786 if (devpriv->is_611x) {
1787 ni_stc_writew(dev,
1788 AI_SHIFTIN_Pulse_Width |
1789 AI_SOC_Polarity |
1790 AI_LOCALMUX_CLK_Pulse_Width,
1791 AI_Personal_Register);
1792 ni_stc_writew(dev,
1793 AI_SCAN_IN_PROG_Output_Select(3) |
1794 AI_EXTMUX_CLK_Output_Select(0) |
1795 AI_LOCALMUX_CLK_Output_Select(2) |
1796 AI_SC_TC_Output_Select(3) |
1797 AI_CONVERT_Output_Select
1798 (AI_CONVERT_Output_Enable_High),
1799 AI_Output_Control_Register);
1800 } else if (devpriv->is_6143) {
1801 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1802 AI_SOC_Polarity |
1803 AI_LOCALMUX_CLK_Pulse_Width,
1804 AI_Personal_Register);
1805 ni_stc_writew(dev,
1806 AI_SCAN_IN_PROG_Output_Select(3) |
1807 AI_EXTMUX_CLK_Output_Select(0) |
1808 AI_LOCALMUX_CLK_Output_Select(2) |
1809 AI_SC_TC_Output_Select(3) |
1810 AI_CONVERT_Output_Select
1811 (AI_CONVERT_Output_Enable_Low),
1812 AI_Output_Control_Register);
1813 } else {
1814 unsigned ai_output_control_bits;
1815 ni_stc_writew(dev,
1816 AI_SHIFTIN_Pulse_Width |
1817 AI_SOC_Polarity |
1818 AI_CONVERT_Pulse_Width |
1819 AI_LOCALMUX_CLK_Pulse_Width,
1820 AI_Personal_Register);
1821 ai_output_control_bits =
1822 AI_SCAN_IN_PROG_Output_Select(3) |
1823 AI_EXTMUX_CLK_Output_Select(0) |
1824 AI_LOCALMUX_CLK_Output_Select(2) |
1825 AI_SC_TC_Output_Select(3);
1826 if (devpriv->is_622x)
1827 ai_output_control_bits |=
1828 AI_CONVERT_Output_Select
1829 (AI_CONVERT_Output_Enable_High);
1830 else
1831 ai_output_control_bits |=
1832 AI_CONVERT_Output_Select
1833 (AI_CONVERT_Output_Enable_Low);
1834 ni_stc_writew(dev, ai_output_control_bits,
1835 AI_Output_Control_Register);
1836 }
1837 /* the following registers should not be changed, because there
1838 * are no backup registers in devpriv. If you want to change
1839 * any of these, add a backup register and other appropriate code:
1840 * AI_Mode_1_Register
1841 * AI_Mode_3_Register
1842 * AI_Personal_Register
1843 * AI_Output_Control_Register
1844 */
1845 ni_stc_writew(dev,
1846 AI_SC_TC_Error_Confirm |
1847 AI_START_Interrupt_Ack |
1848 AI_START2_Interrupt_Ack |
1849 AI_START1_Interrupt_Ack |
1850 AI_SC_TC_Interrupt_Ack |
1851 AI_Error_Interrupt_Ack |
1852 AI_STOP_Interrupt_Ack,
1853 Interrupt_A_Ack_Register); /* clear interrupts */
1854
1855 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1856
1857 return 0;
1858 }
1859
1860 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1861 {
1862 unsigned long flags;
1863 int count;
1864
1865 /* lock to avoid race with interrupt handler */
1866 spin_lock_irqsave(&dev->spinlock, flags);
1867 #ifndef PCIDMA
1868 ni_handle_fifo_dregs(dev);
1869 #else
1870 ni_sync_ai_dma(dev);
1871 #endif
1872 count = comedi_buf_n_bytes_ready(s);
1873 spin_unlock_irqrestore(&dev->spinlock, flags);
1874
1875 return count;
1876 }
1877
1878 static void ni_prime_channelgain_list(struct comedi_device *dev)
1879 {
1880 int i;
1881
1882 ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1883 for (i = 0; i < NI_TIMEOUT; ++i) {
1884 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1885 AI_FIFO_Empty_St)) {
1886 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
1887 return;
1888 }
1889 udelay(1);
1890 }
1891 printk("ni_mio_common: timeout loading channel/gain list\n");
1892 }
1893
1894 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1895 unsigned int n_chan,
1896 unsigned int *list)
1897 {
1898 const struct ni_board_struct *board = comedi_board(dev);
1899 struct ni_private *devpriv = dev->private;
1900 unsigned int chan, range, aref;
1901 unsigned int i;
1902 unsigned int dither;
1903 unsigned range_code;
1904
1905 ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1906
1907 if ((list[0] & CR_ALT_SOURCE)) {
1908 unsigned bypass_bits;
1909 chan = CR_CHAN(list[0]);
1910 range = CR_RANGE(list[0]);
1911 range_code = ni_gainlkup[board->gainlkup][range];
1912 dither = ((list[0] & CR_ALT_FILTER) != 0);
1913 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1914 bypass_bits |= chan;
1915 bypass_bits |=
1916 (devpriv->ai_calib_source) &
1917 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1918 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1919 MSeries_AI_Bypass_Mode_Mux_Mask |
1920 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1921 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1922 if (dither)
1923 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1924 /* don't use 2's complement encoding */
1925 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1926 ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1927 } else {
1928 ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass);
1929 }
1930 for (i = 0; i < n_chan; i++) {
1931 unsigned config_bits = 0;
1932 chan = CR_CHAN(list[i]);
1933 aref = CR_AREF(list[i]);
1934 range = CR_RANGE(list[i]);
1935 dither = ((list[i] & CR_ALT_FILTER) != 0);
1936
1937 range_code = ni_gainlkup[board->gainlkup][range];
1938 devpriv->ai_offset[i] = 0;
1939 switch (aref) {
1940 case AREF_DIFF:
1941 config_bits |=
1942 MSeries_AI_Config_Channel_Type_Differential_Bits;
1943 break;
1944 case AREF_COMMON:
1945 config_bits |=
1946 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1947 break;
1948 case AREF_GROUND:
1949 config_bits |=
1950 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1951 break;
1952 case AREF_OTHER:
1953 break;
1954 }
1955 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1956 config_bits |=
1957 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1958 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1959 if (i == n_chan - 1)
1960 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1961 if (dither)
1962 config_bits |= MSeries_AI_Config_Dither_Bit;
1963 /* don't use 2's complement encoding */
1964 config_bits |= MSeries_AI_Config_Polarity_Bit;
1965 ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data);
1966 }
1967 ni_prime_channelgain_list(dev);
1968 }
1969
1970 /*
1971 * Notes on the 6110 and 6111:
1972 * These boards a slightly different than the rest of the series, since
1973 * they have multiple A/D converters.
1974 * From the driver side, the configuration memory is a
1975 * little different.
1976 * Configuration Memory Low:
1977 * bits 15-9: same
1978 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1979 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1980 * 1001 gain=0.1 (+/- 50)
1981 * 1010 0.2
1982 * 1011 0.1
1983 * 0001 1
1984 * 0010 2
1985 * 0011 5
1986 * 0100 10
1987 * 0101 20
1988 * 0110 50
1989 * Configuration Memory High:
1990 * bits 12-14: Channel Type
1991 * 001 for differential
1992 * 000 for calibration
1993 * bit 11: coupling (this is not currently handled)
1994 * 1 AC coupling
1995 * 0 DC coupling
1996 * bits 0-2: channel
1997 * valid channels are 0-3
1998 */
1999 static void ni_load_channelgain_list(struct comedi_device *dev,
2000 struct comedi_subdevice *s,
2001 unsigned int n_chan, unsigned int *list)
2002 {
2003 const struct ni_board_struct *board = comedi_board(dev);
2004 struct ni_private *devpriv = dev->private;
2005 unsigned int offset = (s->maxdata + 1) >> 1;
2006 unsigned int chan, range, aref;
2007 unsigned int i;
2008 unsigned int hi, lo;
2009 unsigned int dither;
2010
2011 if (devpriv->is_m_series) {
2012 ni_m_series_load_channelgain_list(dev, n_chan, list);
2013 return;
2014 }
2015 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
2016 if (devpriv->changain_state
2017 && devpriv->changain_spec == list[0]) {
2018 /* ready to go. */
2019 return;
2020 }
2021 devpriv->changain_state = 1;
2022 devpriv->changain_spec = list[0];
2023 } else {
2024 devpriv->changain_state = 0;
2025 }
2026
2027 ni_stc_writew(dev, 1, Configuration_Memory_Clear);
2028
2029 /* Set up Calibration mode if required */
2030 if (devpriv->is_6143) {
2031 if ((list[0] & CR_ALT_SOURCE)
2032 && !devpriv->ai_calib_source_enabled) {
2033 /* Strobe Relay enable bit */
2034 ni_writew(dev, devpriv->ai_calib_source |
2035 Calibration_Channel_6143_RelayOn,
2036 Calibration_Channel_6143);
2037 ni_writew(dev, devpriv->ai_calib_source,
2038 Calibration_Channel_6143);
2039 devpriv->ai_calib_source_enabled = 1;
2040 msleep_interruptible(100); /* Allow relays to change */
2041 } else if (!(list[0] & CR_ALT_SOURCE)
2042 && devpriv->ai_calib_source_enabled) {
2043 /* Strobe Relay disable bit */
2044 ni_writew(dev, devpriv->ai_calib_source |
2045 Calibration_Channel_6143_RelayOff,
2046 Calibration_Channel_6143);
2047 ni_writew(dev, devpriv->ai_calib_source,
2048 Calibration_Channel_6143);
2049 devpriv->ai_calib_source_enabled = 0;
2050 msleep_interruptible(100); /* Allow relays to change */
2051 }
2052 }
2053
2054 for (i = 0; i < n_chan; i++) {
2055 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) {
2056 chan = devpriv->ai_calib_source;
2057 } else {
2058 chan = CR_CHAN(list[i]);
2059 }
2060 aref = CR_AREF(list[i]);
2061 range = CR_RANGE(list[i]);
2062 dither = ((list[i] & CR_ALT_FILTER) != 0);
2063
2064 /* fix the external/internal range differences */
2065 range = ni_gainlkup[board->gainlkup][range];
2066 if (devpriv->is_611x)
2067 devpriv->ai_offset[i] = offset;
2068 else
2069 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2070
2071 hi = 0;
2072 if ((list[i] & CR_ALT_SOURCE)) {
2073 if (devpriv->is_611x)
2074 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
2075 Calibration_Channel_Select_611x);
2076 } else {
2077 if (devpriv->is_611x)
2078 aref = AREF_DIFF;
2079 else if (devpriv->is_6143)
2080 aref = AREF_OTHER;
2081 switch (aref) {
2082 case AREF_DIFF:
2083 hi |= AI_DIFFERENTIAL;
2084 break;
2085 case AREF_COMMON:
2086 hi |= AI_COMMON;
2087 break;
2088 case AREF_GROUND:
2089 hi |= AI_GROUND;
2090 break;
2091 case AREF_OTHER:
2092 break;
2093 }
2094 }
2095 hi |= AI_CONFIG_CHANNEL(chan);
2096
2097 ni_writew(dev, hi, Configuration_Memory_High);
2098
2099 if (!devpriv->is_6143) {
2100 lo = range;
2101 if (i == n_chan - 1)
2102 lo |= AI_LAST_CHANNEL;
2103 if (dither)
2104 lo |= AI_DITHER;
2105
2106 ni_writew(dev, lo, Configuration_Memory_Low);
2107 }
2108 }
2109
2110 /* prime the channel/gain list */
2111 if (!devpriv->is_611x && !devpriv->is_6143)
2112 ni_prime_channelgain_list(dev);
2113 }
2114
2115 static int ni_ai_insn_read(struct comedi_device *dev,
2116 struct comedi_subdevice *s,
2117 struct comedi_insn *insn,
2118 unsigned int *data)
2119 {
2120 struct ni_private *devpriv = dev->private;
2121 unsigned int mask = (s->maxdata + 1) >> 1;
2122 int i, n;
2123 unsigned signbits;
2124 unsigned short d;
2125 unsigned long dl;
2126
2127 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
2128
2129 ni_clear_ai_fifo(dev);
2130
2131 signbits = devpriv->ai_offset[0];
2132 if (devpriv->is_611x) {
2133 for (n = 0; n < num_adc_stages_611x; n++) {
2134 ni_stc_writew(dev, AI_CONVERT_Pulse,
2135 AI_Command_1_Register);
2136 udelay(1);
2137 }
2138 for (n = 0; n < insn->n; n++) {
2139 ni_stc_writew(dev, AI_CONVERT_Pulse,
2140 AI_Command_1_Register);
2141 /* The 611x has screwy 32-bit FIFOs. */
2142 d = 0;
2143 for (i = 0; i < NI_TIMEOUT; i++) {
2144 if (ni_readb(dev, XXX_Status) & 0x80) {
2145 d = ni_readl(dev, ADC_FIFO_Data_611x);
2146 d >>= 16;
2147 d &= 0xffff;
2148 break;
2149 }
2150 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2151 AI_FIFO_Empty_St)) {
2152 d = ni_readl(dev, ADC_FIFO_Data_611x);
2153 d &= 0xffff;
2154 break;
2155 }
2156 }
2157 if (i == NI_TIMEOUT) {
2158 printk
2159 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
2160 return -ETIME;
2161 }
2162 d += signbits;
2163 data[n] = d;
2164 }
2165 } else if (devpriv->is_6143) {
2166 for (n = 0; n < insn->n; n++) {
2167 ni_stc_writew(dev, AI_CONVERT_Pulse,
2168 AI_Command_1_Register);
2169
2170 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2171 dl = 0;
2172 for (i = 0; i < NI_TIMEOUT; i++) {
2173 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
2174 /* Get stranded sample into FIFO */
2175 ni_writel(dev, 0x01,
2176 AIFIFO_Control_6143);
2177 dl = ni_readl(dev, AIFIFO_Data_6143);
2178 break;
2179 }
2180 }
2181 if (i == NI_TIMEOUT) {
2182 printk
2183 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
2184 return -ETIME;
2185 }
2186 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2187 }
2188 } else {
2189 for (n = 0; n < insn->n; n++) {
2190 ni_stc_writew(dev, AI_CONVERT_Pulse,
2191 AI_Command_1_Register);
2192 for (i = 0; i < NI_TIMEOUT; i++) {
2193 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2194 AI_FIFO_Empty_St))
2195 break;
2196 }
2197 if (i == NI_TIMEOUT) {
2198 printk
2199 ("ni_mio_common: timeout in ni_ai_insn_read\n");
2200 return -ETIME;
2201 }
2202 if (devpriv->is_m_series) {
2203 dl = ni_readl(dev, M_Offset_AI_FIFO_Data);
2204 dl &= mask;
2205 data[n] = dl;
2206 } else {
2207 d = ni_readw(dev, ADC_FIFO_Data_Register);
2208 d += signbits; /* subtle: needs to be short addition */
2209 data[n] = d;
2210 }
2211 }
2212 }
2213 return insn->n;
2214 }
2215
2216 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2217 int round_mode)
2218 {
2219 struct ni_private *devpriv = dev->private;
2220 int divider;
2221
2222 switch (round_mode) {
2223 case TRIG_ROUND_NEAREST:
2224 default:
2225 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2226 break;
2227 case TRIG_ROUND_DOWN:
2228 divider = (nanosec) / devpriv->clock_ns;
2229 break;
2230 case TRIG_ROUND_UP:
2231 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2232 break;
2233 }
2234 return divider - 1;
2235 }
2236
2237 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2238 {
2239 struct ni_private *devpriv = dev->private;
2240
2241 return devpriv->clock_ns * (timer + 1);
2242 }
2243
2244 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2245 unsigned num_channels)
2246 {
2247 const struct ni_board_struct *board = comedi_board(dev);
2248 struct ni_private *devpriv = dev->private;
2249
2250 /* simultaneously-sampled inputs */
2251 if (devpriv->is_611x || devpriv->is_6143)
2252 return board->ai_speed;
2253
2254 /* multiplexed inputs */
2255 return board->ai_speed * num_channels;
2256 }
2257
2258 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2259 struct comedi_cmd *cmd)
2260 {
2261 const struct ni_board_struct *board = comedi_board(dev);
2262 struct ni_private *devpriv = dev->private;
2263 int err = 0;
2264 unsigned int tmp;
2265 unsigned int sources;
2266
2267 /* Step 1 : check if triggers are trivially valid */
2268
2269 if ((cmd->flags & CMDF_WRITE))
2270 cmd->flags &= ~CMDF_WRITE;
2271
2272 err |= cfc_check_trigger_src(&cmd->start_src,
2273 TRIG_NOW | TRIG_INT | TRIG_EXT);
2274 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2275 TRIG_TIMER | TRIG_EXT);
2276
2277 sources = TRIG_TIMER | TRIG_EXT;
2278 if (devpriv->is_611x || devpriv->is_6143)
2279 sources |= TRIG_NOW;
2280 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2281
2282 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2283 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2284
2285 if (err)
2286 return 1;
2287
2288 /* Step 2a : make sure trigger sources are unique */
2289
2290 err |= cfc_check_trigger_is_unique(cmd->start_src);
2291 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2292 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2293 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2294
2295 /* Step 2b : and mutually compatible */
2296
2297 if (err)
2298 return 2;
2299
2300 /* Step 3: check if arguments are trivially valid */
2301
2302 switch (cmd->start_src) {
2303 case TRIG_NOW:
2304 case TRIG_INT:
2305 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2306 break;
2307 case TRIG_EXT:
2308 tmp = CR_CHAN(cmd->start_arg);
2309
2310 if (tmp > 16)
2311 tmp = 16;
2312 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2313 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2314 break;
2315 }
2316
2317 if (cmd->scan_begin_src == TRIG_TIMER) {
2318 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2319 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2320 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2321 devpriv->clock_ns * 0xffffff);
2322 } else if (cmd->scan_begin_src == TRIG_EXT) {
2323 /* external trigger */
2324 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2325
2326 if (tmp > 16)
2327 tmp = 16;
2328 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2329 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2330 } else { /* TRIG_OTHER */
2331 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2332 }
2333
2334 if (cmd->convert_src == TRIG_TIMER) {
2335 if (devpriv->is_611x || devpriv->is_6143) {
2336 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2337 } else {
2338 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2339 board->ai_speed);
2340 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2341 devpriv->clock_ns * 0xffff);
2342 }
2343 } else if (cmd->convert_src == TRIG_EXT) {
2344 /* external trigger */
2345 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2346
2347 if (tmp > 16)
2348 tmp = 16;
2349 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2350 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2351 } else if (cmd->convert_src == TRIG_NOW) {
2352 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2353 }
2354
2355 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2356
2357 if (cmd->stop_src == TRIG_COUNT) {
2358 unsigned int max_count = 0x01000000;
2359
2360 if (devpriv->is_611x)
2361 max_count -= num_adc_stages_611x;
2362 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2363 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2364 } else {
2365 /* TRIG_NONE */
2366 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2367 }
2368
2369 if (err)
2370 return 3;
2371
2372 /* step 4: fix up any arguments */
2373
2374 if (cmd->scan_begin_src == TRIG_TIMER) {
2375 tmp = cmd->scan_begin_arg;
2376 cmd->scan_begin_arg =
2377 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2378 cmd->scan_begin_arg,
2379 cmd->
2380 flags &
2381 TRIG_ROUND_MASK));
2382 if (tmp != cmd->scan_begin_arg)
2383 err++;
2384 }
2385 if (cmd->convert_src == TRIG_TIMER) {
2386 if (!devpriv->is_611x && !devpriv->is_6143) {
2387 tmp = cmd->convert_arg;
2388 cmd->convert_arg =
2389 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2390 cmd->convert_arg,
2391 cmd->
2392 flags &
2393 TRIG_ROUND_MASK));
2394 if (tmp != cmd->convert_arg)
2395 err++;
2396 if (cmd->scan_begin_src == TRIG_TIMER &&
2397 cmd->scan_begin_arg <
2398 cmd->convert_arg * cmd->scan_end_arg) {
2399 cmd->scan_begin_arg =
2400 cmd->convert_arg * cmd->scan_end_arg;
2401 err++;
2402 }
2403 }
2404 }
2405
2406 if (err)
2407 return 4;
2408
2409 return 0;
2410 }
2411
2412 static int ni_ai_inttrig(struct comedi_device *dev,
2413 struct comedi_subdevice *s,
2414 unsigned int trig_num)
2415 {
2416 struct ni_private *devpriv = dev->private;
2417 struct comedi_cmd *cmd = &s->async->cmd;
2418
2419 if (trig_num != cmd->start_arg)
2420 return -EINVAL;
2421
2422 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2423 AI_Command_2_Register);
2424 s->async->inttrig = NULL;
2425
2426 return 1;
2427 }
2428
2429 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2430 {
2431 struct ni_private *devpriv = dev->private;
2432 const struct comedi_cmd *cmd = &s->async->cmd;
2433 int timer;
2434 int mode1 = 0; /* mode1 is needed for both stop and convert */
2435 int mode2 = 0;
2436 int start_stop_select = 0;
2437 unsigned int stop_count;
2438 int interrupt_a_enable = 0;
2439
2440 if (dev->irq == 0) {
2441 comedi_error(dev, "cannot run command without an irq");
2442 return -EIO;
2443 }
2444 ni_clear_ai_fifo(dev);
2445
2446 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2447
2448 /* start configuration */
2449 ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2450
2451 /* disable analog triggering for now, since it
2452 * interferes with the use of pfi0 */
2453 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2454 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
2455 Analog_Trigger_Etc_Register);
2456
2457 switch (cmd->start_src) {
2458 case TRIG_INT:
2459 case TRIG_NOW:
2460 ni_stc_writew(dev,
2461 AI_START2_Select(0) |
2462 AI_START1_Sync | AI_START1_Edge |
2463 AI_START1_Select(0),
2464 AI_Trigger_Select_Register);
2465 break;
2466 case TRIG_EXT:
2467 {
2468 int chan = CR_CHAN(cmd->start_arg);
2469 unsigned int bits = AI_START2_Select(0) |
2470 AI_START1_Sync | AI_START1_Select(chan + 1);
2471
2472 if (cmd->start_arg & CR_INVERT)
2473 bits |= AI_START1_Polarity;
2474 if (cmd->start_arg & CR_EDGE)
2475 bits |= AI_START1_Edge;
2476 ni_stc_writew(dev, bits, AI_Trigger_Select_Register);
2477 break;
2478 }
2479 }
2480
2481 mode2 &= ~AI_Pre_Trigger;
2482 mode2 &= ~AI_SC_Initial_Load_Source;
2483 mode2 &= ~AI_SC_Reload_Mode;
2484 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2485
2486 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2487 start_stop_select |= AI_STOP_Polarity;
2488 start_stop_select |= AI_STOP_Select(31); /* logic low */
2489 start_stop_select |= AI_STOP_Sync;
2490 } else {
2491 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2492 }
2493 ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2494
2495 devpriv->ai_cmd2 = 0;
2496 switch (cmd->stop_src) {
2497 case TRIG_COUNT:
2498 stop_count = cmd->stop_arg - 1;
2499
2500 if (devpriv->is_611x) {
2501 /* have to take 3 stage adc pipeline into account */
2502 stop_count += num_adc_stages_611x;
2503 }
2504 /* stage number of scans */
2505 ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2506
2507 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2508 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2509 /* load SC (Scan Count) */
2510 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2511
2512 if (stop_count == 0) {
2513 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2514 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2515 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2516 if (cmd->chanlist_len > 1)
2517 start_stop_select |=
2518 AI_STOP_Polarity | AI_STOP_Edge;
2519 }
2520 break;
2521 case TRIG_NONE:
2522 /* stage number of scans */
2523 ni_stc_writel(dev, 0, AI_SC_Load_A_Registers);
2524
2525 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2526 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2527
2528 /* load SC (Scan Count) */
2529 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2530 break;
2531 }
2532
2533 switch (cmd->scan_begin_src) {
2534 case TRIG_TIMER:
2535 /*
2536 stop bits for non 611x boards
2537 AI_SI_Special_Trigger_Delay=0
2538 AI_Pre_Trigger=0
2539 AI_START_STOP_Select_Register:
2540 AI_START_Polarity=0 (?) rising edge
2541 AI_START_Edge=1 edge triggered
2542 AI_START_Sync=1 (?)
2543 AI_START_Select=0 SI_TC
2544 AI_STOP_Polarity=0 rising edge
2545 AI_STOP_Edge=0 level
2546 AI_STOP_Sync=1
2547 AI_STOP_Select=19 external pin (configuration mem)
2548 */
2549 start_stop_select |= AI_START_Edge | AI_START_Sync;
2550 ni_stc_writew(dev, start_stop_select,
2551 AI_START_STOP_Select_Register);
2552
2553 mode2 |= AI_SI_Reload_Mode(0);
2554 /* AI_SI_Initial_Load_Source=A */
2555 mode2 &= ~AI_SI_Initial_Load_Source;
2556 /* mode2 |= AI_SC_Reload_Mode; */
2557 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2558
2559 /* load SI */
2560 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2561 TRIG_ROUND_NEAREST);
2562 ni_stc_writel(dev, timer, AI_SI_Load_A_Registers);
2563 ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2564 break;
2565 case TRIG_EXT:
2566 if (cmd->scan_begin_arg & CR_EDGE)
2567 start_stop_select |= AI_START_Edge;
2568 /* AI_START_Polarity==1 is falling edge */
2569 if (cmd->scan_begin_arg & CR_INVERT)
2570 start_stop_select |= AI_START_Polarity;
2571 if (cmd->scan_begin_src != cmd->convert_src ||
2572 (cmd->scan_begin_arg & ~CR_EDGE) !=
2573 (cmd->convert_arg & ~CR_EDGE))
2574 start_stop_select |= AI_START_Sync;
2575 start_stop_select |=
2576 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2577 ni_stc_writew(dev, start_stop_select,
2578 AI_START_STOP_Select_Register);
2579 break;
2580 }
2581
2582 switch (cmd->convert_src) {
2583 case TRIG_TIMER:
2584 case TRIG_NOW:
2585 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2586 timer = 1;
2587 else
2588 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2589 TRIG_ROUND_NEAREST);
2590 /* 0,0 does not work */
2591 ni_stc_writew(dev, 1, AI_SI2_Load_A_Register);
2592 ni_stc_writew(dev, timer, AI_SI2_Load_B_Register);
2593
2594 /* AI_SI2_Reload_Mode = alternate */
2595 /* AI_SI2_Initial_Load_Source = A */
2596 mode2 &= ~AI_SI2_Initial_Load_Source;
2597 mode2 |= AI_SI2_Reload_Mode;
2598 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2599
2600 /* AI_SI2_Load */
2601 ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2602
2603 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2604 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2605
2606 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2607 break;
2608 case TRIG_EXT:
2609 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2610 if ((cmd->convert_arg & CR_INVERT) == 0)
2611 mode1 |= AI_CONVERT_Source_Polarity;
2612 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2613
2614 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2615 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2616
2617 break;
2618 }
2619
2620 if (dev->irq) {
2621
2622 /* interrupt on FIFO, errors, SC_TC */
2623 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2624 AI_SC_TC_Interrupt_Enable;
2625
2626 #ifndef PCIDMA
2627 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2628 #endif
2629
2630 if (cmd->flags & TRIG_WAKE_EOS
2631 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2632 /* wake on end-of-scan */
2633 devpriv->aimode = AIMODE_SCAN;
2634 } else {
2635 devpriv->aimode = AIMODE_HALF_FULL;
2636 }
2637
2638 switch (devpriv->aimode) {
2639 case AIMODE_HALF_FULL:
2640 /*generate FIFO interrupts and DMA requests on half-full */
2641 #ifdef PCIDMA
2642 ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2643 AI_Mode_3_Register);
2644 #else
2645 ni_stc_writew(dev, AI_FIFO_Mode_HF,
2646 AI_Mode_3_Register);
2647 #endif
2648 break;
2649 case AIMODE_SAMPLE:
2650 /*generate FIFO interrupts on non-empty */
2651 ni_stc_writew(dev, AI_FIFO_Mode_NE,
2652 AI_Mode_3_Register);
2653 break;
2654 case AIMODE_SCAN:
2655 #ifdef PCIDMA
2656 ni_stc_writew(dev, AI_FIFO_Mode_NE,
2657 AI_Mode_3_Register);
2658 #else
2659 ni_stc_writew(dev, AI_FIFO_Mode_HF,
2660 AI_Mode_3_Register);
2661 #endif
2662 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2663 break;
2664 default:
2665 break;
2666 }
2667
2668 /* clear interrupts */
2669 ni_stc_writew(dev,
2670 AI_Error_Interrupt_Ack |
2671 AI_STOP_Interrupt_Ack |
2672 AI_START_Interrupt_Ack |
2673 AI_START2_Interrupt_Ack |
2674 AI_START1_Interrupt_Ack |
2675 AI_SC_TC_Interrupt_Ack |
2676 AI_SC_TC_Error_Confirm,
2677 Interrupt_A_Ack_Register);
2678
2679 ni_set_bits(dev, Interrupt_A_Enable_Register,
2680 interrupt_a_enable, 1);
2681 } else {
2682 /* interrupt on nothing */
2683 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2684
2685 /* XXX start polling if necessary */
2686 }
2687
2688 /* end configuration */
2689 ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2690
2691 switch (cmd->scan_begin_src) {
2692 case TRIG_TIMER:
2693 ni_stc_writew(dev,
2694 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2695 AI_Command_1_Register);
2696 break;
2697 case TRIG_EXT:
2698 /* XXX AI_SI_Arm? */
2699 ni_stc_writew(dev,
2700 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2701 AI_Command_1_Register);
2702 break;
2703 }
2704
2705 #ifdef PCIDMA
2706 {
2707 int retval = ni_ai_setup_MITE_dma(dev);
2708 if (retval)
2709 return retval;
2710 }
2711 #endif
2712
2713 if (cmd->start_src == TRIG_NOW) {
2714 /* AI_START1_Pulse */
2715 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2716 AI_Command_2_Register);
2717 s->async->inttrig = NULL;
2718 } else if (cmd->start_src == TRIG_EXT) {
2719 s->async->inttrig = NULL;
2720 } else { /* TRIG_INT */
2721 s->async->inttrig = ni_ai_inttrig;
2722 }
2723
2724 return 0;
2725 }
2726
2727 static int ni_ai_insn_config(struct comedi_device *dev,
2728 struct comedi_subdevice *s,
2729 struct comedi_insn *insn, unsigned int *data)
2730 {
2731 struct ni_private *devpriv = dev->private;
2732
2733 if (insn->n < 1)
2734 return -EINVAL;
2735
2736 switch (data[0]) {
2737 case INSN_CONFIG_ALT_SOURCE:
2738 if (devpriv->is_m_series) {
2739 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2740 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2741 MSeries_AI_Bypass_Mode_Mux_Mask |
2742 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2743 return -EINVAL;
2744 }
2745 devpriv->ai_calib_source = data[1];
2746 } else if (devpriv->is_6143) {
2747 unsigned int calib_source;
2748
2749 calib_source = data[1] & 0xf;
2750
2751 if (calib_source > 0xF)
2752 return -EINVAL;
2753
2754 devpriv->ai_calib_source = calib_source;
2755 ni_writew(dev, calib_source, Calibration_Channel_6143);
2756 } else {
2757 unsigned int calib_source;
2758 unsigned int calib_source_adjust;
2759
2760 calib_source = data[1] & 0xf;
2761 calib_source_adjust = (data[1] >> 4) & 0xff;
2762
2763 if (calib_source >= 8)
2764 return -EINVAL;
2765 devpriv->ai_calib_source = calib_source;
2766 if (devpriv->is_611x) {
2767 ni_writeb(dev, calib_source_adjust,
2768 Cal_Gain_Select_611x);
2769 }
2770 }
2771 return 2;
2772 default:
2773 break;
2774 }
2775
2776 return -EINVAL;
2777 }
2778
2779 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2780 void *data, unsigned int num_bytes,
2781 unsigned int chan_index)
2782 {
2783 struct comedi_cmd *cmd = &s->async->cmd;
2784 unsigned int length = num_bytes / bytes_per_sample(s);
2785 unsigned short *array = data;
2786 unsigned int i;
2787
2788 for (i = 0; i < length; i++) {
2789 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2790 unsigned short val = array[i];
2791
2792 /*
2793 * Munge data from unsigned to two's complement for
2794 * bipolar ranges.
2795 */
2796 if (comedi_range_is_bipolar(s, range))
2797 val = comedi_offset_munge(s, val);
2798 #ifdef PCIDMA
2799 val = cpu_to_le16(val);
2800 #endif
2801 array[i] = val;
2802
2803 chan_index++;
2804 chan_index %= cmd->chanlist_len;
2805 }
2806 }
2807
2808 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2809 struct comedi_subdevice *s,
2810 unsigned int chanspec[],
2811 unsigned int n_chans, int timed)
2812 {
2813 struct ni_private *devpriv = dev->private;
2814 unsigned int range;
2815 unsigned int chan;
2816 unsigned int conf;
2817 int i;
2818 int invert = 0;
2819
2820 if (timed) {
2821 for (i = 0; i < s->n_chan; ++i) {
2822 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2823 ni_writeb(dev, devpriv->ao_conf[i],
2824 M_Offset_AO_Config_Bank(i));
2825 ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i));
2826 }
2827 }
2828 for (i = 0; i < n_chans; i++) {
2829 const struct comedi_krange *krange;
2830 chan = CR_CHAN(chanspec[i]);
2831 range = CR_RANGE(chanspec[i]);
2832 krange = s->range_table->range + range;
2833 invert = 0;
2834 conf = 0;
2835 switch (krange->max - krange->min) {
2836 case 20000000:
2837 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2838 ni_writeb(dev, 0,
2839 M_Offset_AO_Reference_Attenuation(chan));
2840 break;
2841 case 10000000:
2842 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2843 ni_writeb(dev, 0,
2844 M_Offset_AO_Reference_Attenuation(chan));
2845 break;
2846 case 4000000:
2847 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2848 ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2849 M_Offset_AO_Reference_Attenuation(chan));
2850 break;
2851 case 2000000:
2852 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2853 ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2854 M_Offset_AO_Reference_Attenuation(chan));
2855 break;
2856 default:
2857 printk("%s: bug! unhandled ao reference voltage\n",
2858 __func__);
2859 break;
2860 }
2861 switch (krange->max + krange->min) {
2862 case 0:
2863 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2864 break;
2865 case 10000000:
2866 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2867 break;
2868 default:
2869 printk("%s: bug! unhandled ao offset voltage\n",
2870 __func__);
2871 break;
2872 }
2873 if (timed)
2874 conf |= MSeries_AO_Update_Timed_Bit;
2875 ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan));
2876 devpriv->ao_conf[chan] = conf;
2877 ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan));
2878 }
2879 return invert;
2880 }
2881
2882 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2883 struct comedi_subdevice *s,
2884 unsigned int chanspec[],
2885 unsigned int n_chans)
2886 {
2887 struct ni_private *devpriv = dev->private;
2888 unsigned int range;
2889 unsigned int chan;
2890 unsigned int conf;
2891 int i;
2892 int invert = 0;
2893
2894 for (i = 0; i < n_chans; i++) {
2895 chan = CR_CHAN(chanspec[i]);
2896 range = CR_RANGE(chanspec[i]);
2897 conf = AO_Channel(chan);
2898
2899 if (comedi_range_is_bipolar(s, range)) {
2900 conf |= AO_Bipolar;
2901 invert = (s->maxdata + 1) >> 1;
2902 } else {
2903 invert = 0;
2904 }
2905 if (comedi_range_is_external(s, range))
2906 conf |= AO_Ext_Ref;
2907
2908 /* not all boards can deglitch, but this shouldn't hurt */
2909 if (chanspec[i] & CR_DEGLITCH)
2910 conf |= AO_Deglitch;
2911
2912 /* analog reference */
2913 /* AREF_OTHER connects AO ground to AI ground, i think */
2914 conf |= (CR_AREF(chanspec[i]) ==
2915 AREF_OTHER) ? AO_Ground_Ref : 0;
2916
2917 ni_writew(dev, conf, AO_Configuration);
2918 devpriv->ao_conf[chan] = conf;
2919 }
2920 return invert;
2921 }
2922
2923 static int ni_ao_config_chanlist(struct comedi_device *dev,
2924 struct comedi_subdevice *s,
2925 unsigned int chanspec[], unsigned int n_chans,
2926 int timed)
2927 {
2928 struct ni_private *devpriv = dev->private;
2929
2930 if (devpriv->is_m_series)
2931 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2932 timed);
2933 else
2934 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2935 }
2936
2937 static int ni_ao_insn_read(struct comedi_device *dev,
2938 struct comedi_subdevice *s,
2939 struct comedi_insn *insn,
2940 unsigned int *data)
2941 {
2942 struct ni_private *devpriv = dev->private;
2943 unsigned int chan = CR_CHAN(insn->chanspec);
2944 int i;
2945
2946 for (i = 0; i < insn->n; i++)
2947 data[i] = devpriv->ao[chan];
2948
2949 return insn->n;
2950 }
2951
2952 static int ni_ao_insn_write(struct comedi_device *dev,
2953 struct comedi_subdevice *s,
2954 struct comedi_insn *insn,
2955 unsigned int *data)
2956 {
2957 struct ni_private *devpriv = dev->private;
2958 unsigned int chan = CR_CHAN(insn->chanspec);
2959 unsigned int range = CR_RANGE(insn->chanspec);
2960 int reg;
2961 int i;
2962
2963 if (devpriv->is_6xxx) {
2964 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2965
2966 reg = DACx_Direct_Data_671x(chan);
2967 } else if (devpriv->is_m_series) {
2968 reg = M_Offset_DAC_Direct_Data(chan);
2969 } else {
2970 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2971 }
2972
2973 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2974
2975 for (i = 0; i < insn->n; i++) {
2976 unsigned int val = data[i];
2977
2978 devpriv->ao[chan] = val;
2979
2980 if (devpriv->is_6xxx) {
2981 /*
2982 * 6xxx boards have bipolar outputs, munge the
2983 * unsigned comedi values to 2's complement
2984 */
2985 val = comedi_offset_munge(s, val);
2986
2987 ni_ao_win_outw(dev, val, reg);
2988 } else if (devpriv->is_m_series) {
2989 /*
2990 * M-series boards use offset binary values for
2991 * bipolar and uinpolar outputs
2992 */
2993 ni_writew(dev, val, reg);
2994 } else {
2995 /*
2996 * Non-M series boards need two's complement values
2997 * for bipolar ranges.
2998 */
2999 if (comedi_range_is_bipolar(s, range))
3000 val = comedi_offset_munge(s, val);
3001
3002 ni_writew(dev, val, reg);
3003 }
3004 }
3005
3006 return insn->n;
3007 }
3008
3009 static int ni_ao_insn_config(struct comedi_device *dev,
3010 struct comedi_subdevice *s,
3011 struct comedi_insn *insn, unsigned int *data)
3012 {
3013 const struct ni_board_struct *board = comedi_board(dev);
3014 struct ni_private *devpriv = dev->private;
3015
3016 switch (data[0]) {
3017 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3018 switch (data[1]) {
3019 case COMEDI_OUTPUT:
3020 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3021 if (devpriv->mite)
3022 data[2] += devpriv->mite->fifo_size;
3023 break;
3024 case COMEDI_INPUT:
3025 data[2] = 0;
3026 break;
3027 default:
3028 return -EINVAL;
3029 break;
3030 }
3031 return 0;
3032 default:
3033 break;
3034 }
3035
3036 return -EINVAL;
3037 }
3038
3039 static int ni_ao_inttrig(struct comedi_device *dev,
3040 struct comedi_subdevice *s,
3041 unsigned int trig_num)
3042 {
3043 struct ni_private *devpriv = dev->private;
3044 struct comedi_cmd *cmd = &s->async->cmd;
3045 int ret;
3046 int interrupt_b_bits;
3047 int i;
3048 static const int timeout = 1000;
3049
3050 if (trig_num != cmd->start_arg)
3051 return -EINVAL;
3052
3053 /* Null trig at beginning prevent ao start trigger from executing more than
3054 once per command (and doing things like trying to allocate the ao dma channel
3055 multiple times) */
3056 s->async->inttrig = NULL;
3057
3058 ni_set_bits(dev, Interrupt_B_Enable_Register,
3059 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3060 interrupt_b_bits = AO_Error_Interrupt_Enable;
3061 #ifdef PCIDMA
3062 ni_stc_writew(dev, 1, DAC_FIFO_Clear);
3063 if (devpriv->is_6xxx)
3064 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3065 ret = ni_ao_setup_MITE_dma(dev);
3066 if (ret)
3067 return ret;
3068 ret = ni_ao_wait_for_dma_load(dev);
3069 if (ret < 0)
3070 return ret;
3071 #else
3072 ret = ni_ao_prep_fifo(dev, s);
3073 if (ret == 0)
3074 return -EPIPE;
3075
3076 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3077 #endif
3078
3079 ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3080 AO_Mode_3_Register);
3081 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3082 /* wait for DACs to be loaded */
3083 for (i = 0; i < timeout; i++) {
3084 udelay(1);
3085 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
3086 AO_TMRDACWRs_In_Progress_St) == 0)
3087 break;
3088 }
3089 if (i == timeout) {
3090 comedi_error(dev,
3091 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3092 return -EIO;
3093 }
3094 /*
3095 * stc manual says we are need to clear error interrupt after
3096 * AO_TMRDACWRs_In_Progress_St clears
3097 */
3098 ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
3099
3100 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3101
3102 ni_stc_writew(dev, devpriv->ao_cmd1 |
3103 AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3104 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3105 AO_Command_1_Register);
3106
3107 ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3108 AO_Command_2_Register);
3109
3110 return 0;
3111 }
3112
3113 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3114 {
3115 const struct ni_board_struct *board = comedi_board(dev);
3116 struct ni_private *devpriv = dev->private;
3117 const struct comedi_cmd *cmd = &s->async->cmd;
3118 int bits;
3119 int i;
3120 unsigned trigvar;
3121
3122 if (dev->irq == 0) {
3123 comedi_error(dev, "cannot run command without an irq");
3124 return -EIO;
3125 }
3126
3127 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3128
3129 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3130
3131 if (devpriv->is_6xxx) {
3132 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3133
3134 bits = 0;
3135 for (i = 0; i < cmd->chanlist_len; i++) {
3136 int chan;
3137
3138 chan = CR_CHAN(cmd->chanlist[i]);
3139 bits |= 1 << chan;
3140 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
3141 }
3142 ni_ao_win_outw(dev, bits, AO_Timed_611x);
3143 }
3144
3145 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3146
3147 if (cmd->stop_src == TRIG_NONE) {
3148 devpriv->ao_mode1 |= AO_Continuous;
3149 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3150 } else {
3151 devpriv->ao_mode1 &= ~AO_Continuous;
3152 devpriv->ao_mode1 |= AO_Trigger_Once;
3153 }
3154 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3155 switch (cmd->start_src) {
3156 case TRIG_INT:
3157 case TRIG_NOW:
3158 devpriv->ao_trigger_select &=
3159 ~(AO_START1_Polarity | AO_START1_Select(-1));
3160 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3161 ni_stc_writew(dev, devpriv->ao_trigger_select,
3162 AO_Trigger_Select_Register);
3163 break;
3164 case TRIG_EXT:
3165 devpriv->ao_trigger_select =
3166 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3167 if (cmd->start_arg & CR_INVERT)
3168 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3169 if (cmd->start_arg & CR_EDGE)
3170 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3171 ni_stc_writew(dev, devpriv->ao_trigger_select,
3172 AO_Trigger_Select_Register);
3173 break;
3174 default:
3175 BUG();
3176 break;
3177 }
3178 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3179 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3180
3181 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3182 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3183 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3184 if (cmd->stop_src == TRIG_NONE)
3185 ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3186 else
3187 ni_stc_writel(dev, 0, AO_BC_Load_A_Register);
3188 ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3189 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3190 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3191 switch (cmd->stop_src) {
3192 case TRIG_COUNT:
3193 if (devpriv->is_m_series) {
3194 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3195 ni_stc_writel(dev, cmd->stop_arg - 1,
3196 AO_UC_Load_A_Register);
3197 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3198 } else {
3199 ni_stc_writel(dev, cmd->stop_arg,
3200 AO_UC_Load_A_Register);
3201 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3202 ni_stc_writel(dev, cmd->stop_arg - 1,
3203 AO_UC_Load_A_Register);
3204 }
3205 break;
3206 case TRIG_NONE:
3207 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3208 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3209 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3210 break;
3211 default:
3212 ni_stc_writel(dev, 0, AO_UC_Load_A_Register);
3213 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3214 ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3215 }
3216
3217 devpriv->ao_mode1 &=
3218 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3219 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3220 switch (cmd->scan_begin_src) {
3221 case TRIG_TIMER:
3222 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3223 trigvar =
3224 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3225 TRIG_ROUND_NEAREST);
3226 ni_stc_writel(dev, 1, AO_UI_Load_A_Register);
3227 ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3228 ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3229 break;
3230 case TRIG_EXT:
3231 devpriv->ao_mode1 |=
3232 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3233 if (cmd->scan_begin_arg & CR_INVERT)
3234 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3235 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3236 break;
3237 default:
3238 BUG();
3239 break;
3240 }
3241 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3242 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3243 devpriv->ao_mode2 &=
3244 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3245 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3246
3247 if (cmd->scan_end_arg > 1) {
3248 devpriv->ao_mode1 |= AO_Multiple_Channels;
3249 ni_stc_writew(dev,
3250 AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
3251 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
3252 AO_Output_Control_Register);
3253 } else {
3254 unsigned bits;
3255 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3256 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3257 if (devpriv->is_m_series || devpriv->is_6xxx) {
3258 bits |= AO_Number_Of_Channels(0);
3259 } else {
3260 bits |=
3261 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3262 }
3263 ni_stc_writew(dev, bits, AO_Output_Control_Register);
3264 }
3265 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3266
3267 ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3268 AO_Command_1_Register);
3269
3270 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3271 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3272
3273 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3274 #ifdef PCIDMA
3275 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3276 #else
3277 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3278 #endif
3279 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3280 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3281
3282 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3283 AO_TMRDACWR_Pulse_Width;
3284 if (board->ao_fifo_depth)
3285 bits |= AO_FIFO_Enable;
3286 else
3287 bits |= AO_DMA_PIO_Control;
3288 #if 0
3289 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3290 verified with bus analyzer. */
3291 if (devpriv->is_m_series)
3292 bits |= AO_Number_Of_DAC_Packages;
3293 #endif
3294 ni_stc_writew(dev, bits, AO_Personal_Register);
3295 /* enable sending of ao dma requests */
3296 ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3297
3298 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3299
3300 if (cmd->stop_src == TRIG_COUNT) {
3301 ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3302 Interrupt_B_Ack_Register);
3303 ni_set_bits(dev, Interrupt_B_Enable_Register,
3304 AO_BC_TC_Interrupt_Enable, 1);
3305 }
3306
3307 s->async->inttrig = ni_ao_inttrig;
3308
3309 return 0;
3310 }
3311
3312 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3313 struct comedi_cmd *cmd)
3314 {
3315 const struct ni_board_struct *board = comedi_board(dev);
3316 struct ni_private *devpriv = dev->private;
3317 int err = 0;
3318 unsigned int tmp;
3319
3320 /* Step 1 : check if triggers are trivially valid */
3321
3322 if ((cmd->flags & CMDF_WRITE) == 0)
3323 cmd->flags |= CMDF_WRITE;
3324
3325 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3326 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3327 TRIG_TIMER | TRIG_EXT);
3328 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3329 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3330 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3331
3332 if (err)
3333 return 1;
3334
3335 /* Step 2a : make sure trigger sources are unique */
3336
3337 err |= cfc_check_trigger_is_unique(cmd->start_src);
3338 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3339 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3340
3341 /* Step 2b : and mutually compatible */
3342
3343 if (err)
3344 return 2;
3345
3346 /* Step 3: check if arguments are trivially valid */
3347
3348 switch (cmd->start_src) {
3349 case TRIG_INT:
3350 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3351 break;
3352 case TRIG_EXT:
3353 tmp = CR_CHAN(cmd->start_arg);
3354
3355 if (tmp > 18)
3356 tmp = 18;
3357 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3358 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3359 break;
3360 }
3361
3362 if (cmd->scan_begin_src == TRIG_TIMER) {
3363 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3364 board->ao_speed);
3365 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3366 devpriv->clock_ns * 0xffffff);
3367 }
3368
3369 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3370 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3371
3372 if (cmd->stop_src == TRIG_COUNT)
3373 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3374 else /* TRIG_NONE */
3375 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3376
3377 if (err)
3378 return 3;
3379
3380 /* step 4: fix up any arguments */
3381 if (cmd->scan_begin_src == TRIG_TIMER) {
3382 tmp = cmd->scan_begin_arg;
3383 cmd->scan_begin_arg =
3384 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3385 cmd->scan_begin_arg,
3386 cmd->
3387 flags &
3388 TRIG_ROUND_MASK));
3389 if (tmp != cmd->scan_begin_arg)
3390 err++;
3391 }
3392 if (err)
3393 return 4;
3394
3395 return 0;
3396 }
3397
3398 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3399 {
3400 struct ni_private *devpriv = dev->private;
3401
3402 ni_release_ao_mite_channel(dev);
3403
3404 ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3405 ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3406 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3407 ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3408 ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3409 ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3410 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3411 ni_stc_writew(dev, 0, AO_Output_Control_Register);
3412 ni_stc_writew(dev, 0, AO_Start_Select_Register);
3413 devpriv->ao_cmd1 = 0;
3414 ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3415 devpriv->ao_cmd2 = 0;
3416 ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3417 devpriv->ao_mode1 = 0;
3418 ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3419 devpriv->ao_mode2 = 0;
3420 ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3421 if (devpriv->is_m_series)
3422 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3423 else
3424 devpriv->ao_mode3 = 0;
3425 ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3426 devpriv->ao_trigger_select = 0;
3427 ni_stc_writew(dev, devpriv->ao_trigger_select,
3428 AO_Trigger_Select_Register);
3429 if (devpriv->is_6xxx) {
3430 unsigned immediate_bits = 0;
3431 unsigned i;
3432 for (i = 0; i < s->n_chan; ++i)
3433 immediate_bits |= 1 << i;
3434 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3435 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3436 }
3437 ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3438
3439 return 0;
3440 }
3441
3442 /* digital io */
3443
3444 static int ni_dio_insn_config(struct comedi_device *dev,
3445 struct comedi_subdevice *s,
3446 struct comedi_insn *insn,
3447 unsigned int *data)
3448 {
3449 struct ni_private *devpriv = dev->private;
3450 int ret;
3451
3452 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3453 if (ret)
3454 return ret;
3455
3456 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3457 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3458 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3459
3460 return insn->n;
3461 }
3462
3463 static int ni_dio_insn_bits(struct comedi_device *dev,
3464 struct comedi_subdevice *s,
3465 struct comedi_insn *insn,
3466 unsigned int *data)
3467 {
3468 struct ni_private *devpriv = dev->private;
3469
3470 /* Make sure we're not using the serial part of the dio */
3471 if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3472 return -EBUSY;
3473
3474 if (comedi_dio_update_state(s, data)) {
3475 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3476 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3477 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3478 }
3479
3480 data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
3481
3482 return insn->n;
3483 }
3484
3485 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3486 struct comedi_subdevice *s,
3487 struct comedi_insn *insn,
3488 unsigned int *data)
3489 {
3490 int ret;
3491
3492 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3493 if (ret)
3494 return ret;
3495
3496 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
3497
3498 return insn->n;
3499 }
3500
3501 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3502 struct comedi_subdevice *s,
3503 struct comedi_insn *insn,
3504 unsigned int *data)
3505 {
3506 if (comedi_dio_update_state(s, data))
3507 ni_writel(dev, s->state, M_Offset_Static_Digital_Output);
3508
3509 data[1] = ni_readl(dev, M_Offset_Static_Digital_Input);
3510
3511 return insn->n;
3512 }
3513
3514 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3515 struct comedi_subdevice *s,
3516 struct comedi_cmd *cmd)
3517 {
3518 int i;
3519
3520 for (i = 0; i < cmd->chanlist_len; ++i) {
3521 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3522
3523 if (chan != i)
3524 return -EINVAL;
3525 }
3526
3527 return 0;
3528 }
3529
3530 static int ni_cdio_cmdtest(struct comedi_device *dev,
3531 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3532 {
3533 int err = 0;
3534 int tmp;
3535
3536 /* Step 1 : check if triggers are trivially valid */
3537
3538 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3539 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3540 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3541 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3542 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3543
3544 if (err)
3545 return 1;
3546
3547 /* Step 2a : make sure trigger sources are unique */
3548 /* Step 2b : and mutually compatible */
3549
3550 if (err)
3551 return 2;
3552
3553 /* Step 3: check if arguments are trivially valid */
3554
3555 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3556
3557 tmp = cmd->scan_begin_arg;
3558 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3559 if (tmp != cmd->scan_begin_arg)
3560 err |= -EINVAL;
3561
3562 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3563 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3564 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3565
3566 if (err)
3567 return 3;
3568
3569 /* step 4: fix up any arguments */
3570
3571 if (err)
3572 return 4;
3573
3574 /* Step 5: check channel list if it exists */
3575 if (cmd->chanlist && cmd->chanlist_len > 0)
3576 err |= ni_cdio_check_chanlist(dev, s, cmd);
3577
3578 if (err)
3579 return 5;
3580
3581 return 0;
3582 }
3583
3584 static int ni_cdo_inttrig(struct comedi_device *dev,
3585 struct comedi_subdevice *s,
3586 unsigned int trig_num)
3587 {
3588 struct comedi_cmd *cmd = &s->async->cmd;
3589 const unsigned timeout = 1000;
3590 int retval = 0;
3591 unsigned i;
3592 #ifdef PCIDMA
3593 struct ni_private *devpriv = dev->private;
3594 unsigned long flags;
3595 #endif
3596
3597 if (trig_num != cmd->start_arg)
3598 return -EINVAL;
3599
3600 s->async->inttrig = NULL;
3601
3602 /* read alloc the entire buffer */
3603 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3604
3605 #ifdef PCIDMA
3606 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3607 if (devpriv->cdo_mite_chan) {
3608 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3609 mite_dma_arm(devpriv->cdo_mite_chan);
3610 } else {
3611 comedi_error(dev, "BUG: no cdo mite channel?");
3612 retval = -EIO;
3613 }
3614 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3615 if (retval < 0)
3616 return retval;
3617 #endif
3618 /*
3619 * XXX not sure what interrupt C group does
3620 * ni_writeb(dev, Interrupt_Group_C_Enable_Bit,
3621 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3622 */
3623 for (i = 0; i < timeout; ++i) {
3624 if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3625 break;
3626 udelay(10);
3627 }
3628 if (i == timeout) {
3629 comedi_error(dev, "dma failed to fill cdo fifo!");
3630 s->cancel(dev, s);
3631 return -EIO;
3632 }
3633 ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3634 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3635 M_Offset_CDIO_Command);
3636 return retval;
3637 }
3638
3639 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3640 {
3641 const struct comedi_cmd *cmd = &s->async->cmd;
3642 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3643 int retval;
3644
3645 ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command);
3646 switch (cmd->scan_begin_src) {
3647 case TRIG_EXT:
3648 cdo_mode_bits |=
3649 CR_CHAN(cmd->scan_begin_arg) &
3650 CDO_Sample_Source_Select_Mask;
3651 break;
3652 default:
3653 BUG();
3654 break;
3655 }
3656 if (cmd->scan_begin_arg & CR_INVERT)
3657 cdo_mode_bits |= CDO_Polarity_Bit;
3658 ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode);
3659 if (s->io_bits) {
3660 ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data);
3661 ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3662 ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable);
3663 } else {
3664 comedi_error(dev,
3665 "attempted to run digital output command with no lines configured as outputs");
3666 return -EIO;
3667 }
3668 retval = ni_request_cdo_mite_channel(dev);
3669 if (retval < 0)
3670 return retval;
3671
3672 s->async->inttrig = ni_cdo_inttrig;
3673
3674 return 0;
3675 }
3676
3677 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3678 {
3679 ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3680 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3681 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3682 M_Offset_CDIO_Command);
3683 /*
3684 * XXX not sure what interrupt C group does ni_writeb(dev, 0,
3685 * M_Offset_Interrupt_C_Enable);
3686 */
3687 ni_writel(dev, 0, M_Offset_CDO_Mask_Enable);
3688 ni_release_cdo_mite_channel(dev);
3689 return 0;
3690 }
3691
3692 static void handle_cdio_interrupt(struct comedi_device *dev)
3693 {
3694 struct ni_private *devpriv = dev->private;
3695 unsigned cdio_status;
3696 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3697 #ifdef PCIDMA
3698 unsigned long flags;
3699 #endif
3700
3701 if (!devpriv->is_m_series)
3702 return;
3703 #ifdef PCIDMA
3704 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3705 if (devpriv->cdo_mite_chan) {
3706 unsigned cdo_mite_status =
3707 mite_get_status(devpriv->cdo_mite_chan);
3708 if (cdo_mite_status & CHSR_LINKC) {
3709 writel(CHOR_CLRLC,
3710 devpriv->mite->mite_io_addr +
3711 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3712 }
3713 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3714 }
3715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3716 #endif
3717
3718 cdio_status = ni_readl(dev, M_Offset_CDIO_Status);
3719 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3720 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3721 /* XXX just guessing this is needed and does something useful */
3722 ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit,
3723 M_Offset_CDIO_Command);
3724 s->async->events |= COMEDI_CB_OVERFLOW;
3725 }
3726 if (cdio_status & CDO_FIFO_Empty_Bit) {
3727 /* printk("cdio fifo empty\n"); */
3728 ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3729 M_Offset_CDIO_Command);
3730 /* s->async->events |= COMEDI_CB_EOA; */
3731 }
3732 cfc_handle_events(dev, s);
3733 }
3734
3735 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3736 struct comedi_subdevice *s,
3737 unsigned char data_out,
3738 unsigned char *data_in)
3739 {
3740 struct ni_private *devpriv = dev->private;
3741 unsigned int status1;
3742 int err = 0, count = 20;
3743
3744 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3745 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3746 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3747
3748 status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3749 if (status1 & DIO_Serial_IO_In_Progress_St) {
3750 err = -EBUSY;
3751 goto Error;
3752 }
3753
3754 devpriv->dio_control |= DIO_HW_Serial_Start;
3755 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3756 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3757
3758 /* Wait until STC says we're done, but don't loop infinitely. */
3759 while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3760 DIO_Serial_IO_In_Progress_St) {
3761 /* Delay one bit per loop */
3762 udelay((devpriv->serial_interval_ns + 999) / 1000);
3763 if (--count < 0) {
3764 printk
3765 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3766 err = -ETIME;
3767 goto Error;
3768 }
3769 }
3770
3771 /* Delay for last bit. This delay is absolutely necessary, because
3772 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3773 udelay((devpriv->serial_interval_ns + 999) / 1000);
3774
3775 if (data_in != NULL)
3776 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3777
3778 Error:
3779 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3780
3781 return err;
3782 }
3783
3784 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3785 struct comedi_subdevice *s,
3786 unsigned char data_out,
3787 unsigned char *data_in)
3788 {
3789 struct ni_private *devpriv = dev->private;
3790 unsigned char mask, input = 0;
3791
3792 /* Wait for one bit before transfer */
3793 udelay((devpriv->serial_interval_ns + 999) / 1000);
3794
3795 for (mask = 0x80; mask; mask >>= 1) {
3796 /* Output current bit; note that we cannot touch s->state
3797 because it is a per-subdevice field, and serial is
3798 a separate subdevice from DIO. */
3799 devpriv->dio_output &= ~DIO_SDOUT;
3800 if (data_out & mask)
3801 devpriv->dio_output |= DIO_SDOUT;
3802 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3803
3804 /* Assert SDCLK (active low, inverted), wait for half of
3805 the delay, deassert SDCLK, and wait for the other half. */
3806 devpriv->dio_control |= DIO_Software_Serial_Control;
3807 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3808
3809 udelay((devpriv->serial_interval_ns + 999) / 2000);
3810
3811 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3812 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3813
3814 udelay((devpriv->serial_interval_ns + 999) / 2000);
3815
3816 /* Input current bit */
3817 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3818 /* printk("DIO_P_I_R: 0x%x\n", ni_stc_readw(dev, DIO_Parallel_Input_Register)); */
3819 input |= mask;
3820 }
3821 }
3822
3823 if (data_in)
3824 *data_in = input;
3825
3826 return 0;
3827 }
3828
3829 static int ni_serial_insn_config(struct comedi_device *dev,
3830 struct comedi_subdevice *s,
3831 struct comedi_insn *insn,
3832 unsigned int *data)
3833 {
3834 struct ni_private *devpriv = dev->private;
3835 int err = insn->n;
3836 unsigned char byte_out, byte_in = 0;
3837
3838 if (insn->n != 2)
3839 return -EINVAL;
3840
3841 switch (data[0]) {
3842 case INSN_CONFIG_SERIAL_CLOCK:
3843 devpriv->serial_hw_mode = 1;
3844 devpriv->dio_control |= DIO_HW_Serial_Enable;
3845
3846 if (data[1] == SERIAL_DISABLED) {
3847 devpriv->serial_hw_mode = 0;
3848 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3849 DIO_Software_Serial_Control);
3850 data[1] = SERIAL_DISABLED;
3851 devpriv->serial_interval_ns = data[1];
3852 } else if (data[1] <= SERIAL_600NS) {
3853 /* Warning: this clock speed is too fast to reliably
3854 control SCXI. */
3855 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3856 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3857 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3858 data[1] = SERIAL_600NS;
3859 devpriv->serial_interval_ns = data[1];
3860 } else if (data[1] <= SERIAL_1_2US) {
3861 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3862 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3863 DIO_Serial_Out_Divide_By_2;
3864 data[1] = SERIAL_1_2US;
3865 devpriv->serial_interval_ns = data[1];
3866 } else if (data[1] <= SERIAL_10US) {
3867 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3868 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3869 DIO_Serial_Out_Divide_By_2;
3870 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3871 600ns/1.2us. If you turn divide_by_2 off with the
3872 slow clock, you will still get 10us, except then
3873 all your delays are wrong. */
3874 data[1] = SERIAL_10US;
3875 devpriv->serial_interval_ns = data[1];
3876 } else {
3877 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3878 DIO_Software_Serial_Control);
3879 devpriv->serial_hw_mode = 0;
3880 data[1] = (data[1] / 1000) * 1000;
3881 devpriv->serial_interval_ns = data[1];
3882 }
3883
3884 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3885 ni_stc_writew(dev, devpriv->clock_and_fout,
3886 Clock_and_FOUT_Register);
3887 return 1;
3888
3889 break;
3890
3891 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3892
3893 if (devpriv->serial_interval_ns == 0)
3894 return -EINVAL;
3895
3896 byte_out = data[1] & 0xFF;
3897
3898 if (devpriv->serial_hw_mode) {
3899 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3900 &byte_in);
3901 } else if (devpriv->serial_interval_ns > 0) {
3902 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3903 &byte_in);
3904 } else {
3905 printk("ni_serial_insn_config: serial disabled!\n");
3906 return -EINVAL;
3907 }
3908 if (err < 0)
3909 return err;
3910 data[1] = byte_in & 0xFF;
3911 return insn->n;
3912
3913 break;
3914 default:
3915 return -EINVAL;
3916 }
3917
3918 }
3919
3920 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3921 {
3922 int i;
3923
3924 for (i = 0; i < s->n_chan; i++) {
3925 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3926 AO_Configuration_2_67xx);
3927 }
3928 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3929 }
3930
3931 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3932 {
3933 unsigned stc_register;
3934 switch (reg) {
3935 case NITIO_G0_AUTO_INC:
3936 stc_register = G_Autoincrement_Register(0);
3937 break;
3938 case NITIO_G1_AUTO_INC:
3939 stc_register = G_Autoincrement_Register(1);
3940 break;
3941 case NITIO_G0_CMD:
3942 stc_register = G_Command_Register(0);
3943 break;
3944 case NITIO_G1_CMD:
3945 stc_register = G_Command_Register(1);
3946 break;
3947 case NITIO_G0_HW_SAVE:
3948 stc_register = G_HW_Save_Register(0);
3949 break;
3950 case NITIO_G1_HW_SAVE:
3951 stc_register = G_HW_Save_Register(1);
3952 break;
3953 case NITIO_G0_SW_SAVE:
3954 stc_register = G_Save_Register(0);
3955 break;
3956 case NITIO_G1_SW_SAVE:
3957 stc_register = G_Save_Register(1);
3958 break;
3959 case NITIO_G0_MODE:
3960 stc_register = G_Mode_Register(0);
3961 break;
3962 case NITIO_G1_MODE:
3963 stc_register = G_Mode_Register(1);
3964 break;
3965 case NITIO_G0_LOADA:
3966 stc_register = G_Load_A_Register(0);
3967 break;
3968 case NITIO_G1_LOADA:
3969 stc_register = G_Load_A_Register(1);
3970 break;
3971 case NITIO_G0_LOADB:
3972 stc_register = G_Load_B_Register(0);
3973 break;
3974 case NITIO_G1_LOADB:
3975 stc_register = G_Load_B_Register(1);
3976 break;
3977 case NITIO_G0_INPUT_SEL:
3978 stc_register = G_Input_Select_Register(0);
3979 break;
3980 case NITIO_G1_INPUT_SEL:
3981 stc_register = G_Input_Select_Register(1);
3982 break;
3983 case NITIO_G01_STATUS:
3984 stc_register = G_Status_Register;
3985 break;
3986 case NITIO_G01_RESET:
3987 stc_register = Joint_Reset_Register;
3988 break;
3989 case NITIO_G01_STATUS1:
3990 stc_register = Joint_Status_1_Register;
3991 break;
3992 case NITIO_G01_STATUS2:
3993 stc_register = Joint_Status_2_Register;
3994 break;
3995 case NITIO_G0_INT_ACK:
3996 stc_register = Interrupt_A_Ack_Register;
3997 break;
3998 case NITIO_G1_INT_ACK:
3999 stc_register = Interrupt_B_Ack_Register;
4000 break;
4001 case NITIO_G0_STATUS:
4002 stc_register = AI_Status_1_Register;
4003 break;
4004 case NITIO_G1_STATUS:
4005 stc_register = AO_Status_1_Register;
4006 break;
4007 case NITIO_G0_INT_ENA:
4008 stc_register = Interrupt_A_Enable_Register;
4009 break;
4010 case NITIO_G1_INT_ENA:
4011 stc_register = Interrupt_B_Enable_Register;
4012 break;
4013 default:
4014 printk("%s: unhandled register 0x%x in switch.\n",
4015 __func__, reg);
4016 BUG();
4017 return 0;
4018 break;
4019 }
4020 return stc_register;
4021 }
4022
4023 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4024 enum ni_gpct_register reg)
4025 {
4026 struct comedi_device *dev = counter->counter_dev->dev;
4027 unsigned stc_register;
4028 /* bits in the join reset register which are relevant to counters */
4029 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4030 static const unsigned gpct_interrupt_a_enable_mask =
4031 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4032 static const unsigned gpct_interrupt_b_enable_mask =
4033 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4034
4035 switch (reg) {
4036 /* m-series-only registers */
4037 case NITIO_G0_CNT_MODE:
4038 ni_writew(dev, bits, M_Offset_G0_Counting_Mode);
4039 break;
4040 case NITIO_G1_CNT_MODE:
4041 ni_writew(dev, bits, M_Offset_G1_Counting_Mode);
4042 break;
4043 case NITIO_G0_GATE2:
4044 ni_writew(dev, bits, M_Offset_G0_Second_Gate);
4045 break;
4046 case NITIO_G1_GATE2:
4047 ni_writew(dev, bits, M_Offset_G1_Second_Gate);
4048 break;
4049 case NITIO_G0_DMA_CFG:
4050 ni_writew(dev, bits, M_Offset_G0_DMA_Config);
4051 break;
4052 case NITIO_G1_DMA_CFG:
4053 ni_writew(dev, bits, M_Offset_G1_DMA_Config);
4054 break;
4055 case NITIO_G0_ABZ:
4056 ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ);
4057 break;
4058 case NITIO_G1_ABZ:
4059 ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ);
4060 break;
4061
4062 /* 32 bit registers */
4063 case NITIO_G0_LOADA:
4064 case NITIO_G1_LOADA:
4065 case NITIO_G0_LOADB:
4066 case NITIO_G1_LOADB:
4067 stc_register = ni_gpct_to_stc_register(reg);
4068 ni_stc_writel(dev, bits, stc_register);
4069 break;
4070
4071 /* 16 bit registers */
4072 case NITIO_G0_INT_ENA:
4073 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4074 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4075 gpct_interrupt_a_enable_mask, bits);
4076 break;
4077 case NITIO_G1_INT_ENA:
4078 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4079 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4080 gpct_interrupt_b_enable_mask, bits);
4081 break;
4082 case NITIO_G01_RESET:
4083 BUG_ON(bits & ~gpct_joint_reset_mask);
4084 /* fall-through */
4085 default:
4086 stc_register = ni_gpct_to_stc_register(reg);
4087 ni_stc_writew(dev, bits, stc_register);
4088 }
4089 }
4090
4091 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4092 enum ni_gpct_register reg)
4093 {
4094 struct comedi_device *dev = counter->counter_dev->dev;
4095 unsigned stc_register;
4096
4097 switch (reg) {
4098 /* m-series only registers */
4099 case NITIO_G0_DMA_STATUS:
4100 return ni_readw(dev, M_Offset_G0_DMA_Status);
4101 case NITIO_G1_DMA_STATUS:
4102 return ni_readw(dev, M_Offset_G1_DMA_Status);
4103
4104 /* 32 bit registers */
4105 case NITIO_G0_HW_SAVE:
4106 case NITIO_G1_HW_SAVE:
4107 case NITIO_G0_SW_SAVE:
4108 case NITIO_G1_SW_SAVE:
4109 stc_register = ni_gpct_to_stc_register(reg);
4110 return ni_stc_readl(dev, stc_register);
4111
4112 /* 16 bit registers */
4113 default:
4114 stc_register = ni_gpct_to_stc_register(reg);
4115 return ni_stc_readw(dev, stc_register);
4116 break;
4117 }
4118 return 0;
4119 }
4120
4121 static int ni_freq_out_insn_read(struct comedi_device *dev,
4122 struct comedi_subdevice *s,
4123 struct comedi_insn *insn,
4124 unsigned int *data)
4125 {
4126 struct ni_private *devpriv = dev->private;
4127 unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask;
4128 int i;
4129
4130 for (i = 0; i < insn->n; i++)
4131 data[i] = val;
4132
4133 return insn->n;
4134 }
4135
4136 static int ni_freq_out_insn_write(struct comedi_device *dev,
4137 struct comedi_subdevice *s,
4138 struct comedi_insn *insn,
4139 unsigned int *data)
4140 {
4141 struct ni_private *devpriv = dev->private;
4142
4143 if (insn->n) {
4144 devpriv->clock_and_fout &= ~FOUT_Enable;
4145 ni_stc_writew(dev, devpriv->clock_and_fout,
4146 Clock_and_FOUT_Register);
4147 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4148
4149 /* use the last data value to set the fout divider */
4150 devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]);
4151
4152 devpriv->clock_and_fout |= FOUT_Enable;
4153 ni_stc_writew(dev, devpriv->clock_and_fout,
4154 Clock_and_FOUT_Register);
4155 }
4156 return insn->n;
4157 }
4158
4159 static int ni_freq_out_insn_config(struct comedi_device *dev,
4160 struct comedi_subdevice *s,
4161 struct comedi_insn *insn,
4162 unsigned int *data)
4163 {
4164 struct ni_private *devpriv = dev->private;
4165
4166 switch (data[0]) {
4167 case INSN_CONFIG_SET_CLOCK_SRC:
4168 switch (data[1]) {
4169 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4170 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4171 break;
4172 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4173 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4174 break;
4175 default:
4176 return -EINVAL;
4177 }
4178 ni_stc_writew(dev, devpriv->clock_and_fout,
4179 Clock_and_FOUT_Register);
4180 break;
4181 case INSN_CONFIG_GET_CLOCK_SRC:
4182 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4183 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4184 data[2] = TIMEBASE_2_NS;
4185 } else {
4186 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4187 data[2] = TIMEBASE_1_NS * 2;
4188 }
4189 break;
4190 default:
4191 return -EINVAL;
4192 }
4193 return insn->n;
4194 }
4195
4196 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4197 {
4198 struct comedi_device *dev = (struct comedi_device *)arg;
4199
4200 if (dir) {
4201 ni_writeb(dev, data, Port_A + 2 * port);
4202 return 0;
4203 } else {
4204 return ni_readb(dev, Port_A + 2 * port);
4205 }
4206 }
4207
4208 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4209 {
4210 struct ni_private *devpriv = dev->private;
4211
4212 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4213 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4214 return 3;
4215 }
4216
4217 static int ni_m_series_pwm_config(struct comedi_device *dev,
4218 struct comedi_subdevice *s,
4219 struct comedi_insn *insn,
4220 unsigned int *data)
4221 {
4222 struct ni_private *devpriv = dev->private;
4223 unsigned up_count, down_count;
4224
4225 switch (data[0]) {
4226 case INSN_CONFIG_PWM_OUTPUT:
4227 switch (data[1]) {
4228 case TRIG_ROUND_NEAREST:
4229 up_count =
4230 (data[2] +
4231 devpriv->clock_ns / 2) / devpriv->clock_ns;
4232 break;
4233 case TRIG_ROUND_DOWN:
4234 up_count = data[2] / devpriv->clock_ns;
4235 break;
4236 case TRIG_ROUND_UP:
4237 up_count =
4238 (data[2] + devpriv->clock_ns -
4239 1) / devpriv->clock_ns;
4240 break;
4241 default:
4242 return -EINVAL;
4243 break;
4244 }
4245 switch (data[3]) {
4246 case TRIG_ROUND_NEAREST:
4247 down_count =
4248 (data[4] +
4249 devpriv->clock_ns / 2) / devpriv->clock_ns;
4250 break;
4251 case TRIG_ROUND_DOWN:
4252 down_count = data[4] / devpriv->clock_ns;
4253 break;
4254 case TRIG_ROUND_UP:
4255 down_count =
4256 (data[4] + devpriv->clock_ns -
4257 1) / devpriv->clock_ns;
4258 break;
4259 default:
4260 return -EINVAL;
4261 break;
4262 }
4263 if (up_count * devpriv->clock_ns != data[2] ||
4264 down_count * devpriv->clock_ns != data[4]) {
4265 data[2] = up_count * devpriv->clock_ns;
4266 data[4] = down_count * devpriv->clock_ns;
4267 return -EAGAIN;
4268 }
4269 ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
4270 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4271 M_Offset_Cal_PWM);
4272 devpriv->pwm_up_count = up_count;
4273 devpriv->pwm_down_count = down_count;
4274 return 5;
4275 break;
4276 case INSN_CONFIG_GET_PWM_OUTPUT:
4277 return ni_get_pwm_config(dev, data);
4278 break;
4279 default:
4280 return -EINVAL;
4281 break;
4282 }
4283 return 0;
4284 }
4285
4286 static int ni_6143_pwm_config(struct comedi_device *dev,
4287 struct comedi_subdevice *s,
4288 struct comedi_insn *insn,
4289 unsigned int *data)
4290 {
4291 struct ni_private *devpriv = dev->private;
4292 unsigned up_count, down_count;
4293
4294 switch (data[0]) {
4295 case INSN_CONFIG_PWM_OUTPUT:
4296 switch (data[1]) {
4297 case TRIG_ROUND_NEAREST:
4298 up_count =
4299 (data[2] +
4300 devpriv->clock_ns / 2) / devpriv->clock_ns;
4301 break;
4302 case TRIG_ROUND_DOWN:
4303 up_count = data[2] / devpriv->clock_ns;
4304 break;
4305 case TRIG_ROUND_UP:
4306 up_count =
4307 (data[2] + devpriv->clock_ns -
4308 1) / devpriv->clock_ns;
4309 break;
4310 default:
4311 return -EINVAL;
4312 break;
4313 }
4314 switch (data[3]) {
4315 case TRIG_ROUND_NEAREST:
4316 down_count =
4317 (data[4] +
4318 devpriv->clock_ns / 2) / devpriv->clock_ns;
4319 break;
4320 case TRIG_ROUND_DOWN:
4321 down_count = data[4] / devpriv->clock_ns;
4322 break;
4323 case TRIG_ROUND_UP:
4324 down_count =
4325 (data[4] + devpriv->clock_ns -
4326 1) / devpriv->clock_ns;
4327 break;
4328 default:
4329 return -EINVAL;
4330 break;
4331 }
4332 if (up_count * devpriv->clock_ns != data[2] ||
4333 down_count * devpriv->clock_ns != data[4]) {
4334 data[2] = up_count * devpriv->clock_ns;
4335 data[4] = down_count * devpriv->clock_ns;
4336 return -EAGAIN;
4337 }
4338 ni_writel(dev, up_count, Calibration_HighTime_6143);
4339 devpriv->pwm_up_count = up_count;
4340 ni_writel(dev, down_count, Calibration_LowTime_6143);
4341 devpriv->pwm_down_count = down_count;
4342 return 5;
4343 break;
4344 case INSN_CONFIG_GET_PWM_OUTPUT:
4345 return ni_get_pwm_config(dev, data);
4346 default:
4347 return -EINVAL;
4348 break;
4349 }
4350 return 0;
4351 }
4352
4353 static int pack_mb88341(int addr, int val, int *bitstring)
4354 {
4355 /*
4356 Fujitsu MB 88341
4357 Note that address bits are reversed. Thanks to
4358 Ingo Keen for noticing this.
4359
4360 Note also that the 88341 expects address values from
4361 1-12, whereas we use channel numbers 0-11. The NI
4362 docs use 1-12, also, so be careful here.
4363 */
4364 addr++;
4365 *bitstring = ((addr & 0x1) << 11) |
4366 ((addr & 0x2) << 9) |
4367 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4368 return 12;
4369 }
4370
4371 static int pack_dac8800(int addr, int val, int *bitstring)
4372 {
4373 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4374 return 11;
4375 }
4376
4377 static int pack_dac8043(int addr, int val, int *bitstring)
4378 {
4379 *bitstring = val & 0xfff;
4380 return 12;
4381 }
4382
4383 static int pack_ad8522(int addr, int val, int *bitstring)
4384 {
4385 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4386 return 16;
4387 }
4388
4389 static int pack_ad8804(int addr, int val, int *bitstring)
4390 {
4391 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4392 return 12;
4393 }
4394
4395 static int pack_ad8842(int addr, int val, int *bitstring)
4396 {
4397 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4398 return 12;
4399 }
4400
4401 struct caldac_struct {
4402 int n_chans;
4403 int n_bits;
4404 int (*packbits)(int, int, int *);
4405 };
4406
4407 static struct caldac_struct caldacs[] = {
4408 [mb88341] = {12, 8, pack_mb88341},
4409 [dac8800] = {8, 8, pack_dac8800},
4410 [dac8043] = {1, 12, pack_dac8043},
4411 [ad8522] = {2, 12, pack_ad8522},
4412 [ad8804] = {12, 8, pack_ad8804},
4413 [ad8842] = {8, 8, pack_ad8842},
4414 [ad8804_debug] = {16, 8, pack_ad8804},
4415 };
4416
4417 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4418 {
4419 const struct ni_board_struct *board = comedi_board(dev);
4420 struct ni_private *devpriv = dev->private;
4421 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4422 int i;
4423 int type;
4424
4425 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4426 if (devpriv->caldacs[addr] == val)
4427 return;
4428 devpriv->caldacs[addr] = val;
4429
4430 for (i = 0; i < 3; i++) {
4431 type = board->caldac[i];
4432 if (type == caldac_none)
4433 break;
4434 if (addr < caldacs[type].n_chans) {
4435 bits = caldacs[type].packbits(addr, val, &bitstring);
4436 loadbit = SerDacLd(i);
4437 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4438 break;
4439 }
4440 addr -= caldacs[type].n_chans;
4441 }
4442
4443 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4444 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4445 udelay(1);
4446 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4447 Serial_Command);
4448 udelay(1);
4449 }
4450 ni_writeb(dev, loadbit, Serial_Command);
4451 udelay(1);
4452 ni_writeb(dev, 0, Serial_Command);
4453 }
4454
4455 static int ni_calib_insn_write(struct comedi_device *dev,
4456 struct comedi_subdevice *s,
4457 struct comedi_insn *insn,
4458 unsigned int *data)
4459 {
4460 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4461
4462 return 1;
4463 }
4464
4465 static int ni_calib_insn_read(struct comedi_device *dev,
4466 struct comedi_subdevice *s,
4467 struct comedi_insn *insn,
4468 unsigned int *data)
4469 {
4470 struct ni_private *devpriv = dev->private;
4471
4472 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4473
4474 return 1;
4475 }
4476
4477 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4478 {
4479 const struct ni_board_struct *board = comedi_board(dev);
4480 struct ni_private *devpriv = dev->private;
4481 int i, j;
4482 int n_dacs;
4483 int n_chans = 0;
4484 int n_bits;
4485 int diffbits = 0;
4486 int type;
4487 int chan;
4488
4489 type = board->caldac[0];
4490 if (type == caldac_none)
4491 return;
4492 n_bits = caldacs[type].n_bits;
4493 for (i = 0; i < 3; i++) {
4494 type = board->caldac[i];
4495 if (type == caldac_none)
4496 break;
4497 if (caldacs[type].n_bits != n_bits)
4498 diffbits = 1;
4499 n_chans += caldacs[type].n_chans;
4500 }
4501 n_dacs = i;
4502 s->n_chan = n_chans;
4503
4504 if (diffbits) {
4505 unsigned int *maxdata_list;
4506
4507 if (n_chans > MAX_N_CALDACS)
4508 printk("BUG! MAX_N_CALDACS too small\n");
4509 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4510 chan = 0;
4511 for (i = 0; i < n_dacs; i++) {
4512 type = board->caldac[i];
4513 for (j = 0; j < caldacs[type].n_chans; j++) {
4514 maxdata_list[chan] =
4515 (1 << caldacs[type].n_bits) - 1;
4516 chan++;
4517 }
4518 }
4519
4520 for (chan = 0; chan < s->n_chan; chan++)
4521 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4522 } else {
4523 type = board->caldac[0];
4524 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4525
4526 for (chan = 0; chan < s->n_chan; chan++)
4527 ni_write_caldac(dev, i, s->maxdata / 2);
4528 }
4529 }
4530
4531 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4532 {
4533 int bit;
4534 int bitstring;
4535
4536 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4537 ni_writeb(dev, 0x04, Serial_Command);
4538 for (bit = 0x8000; bit; bit >>= 1) {
4539 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4540 Serial_Command);
4541 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4542 Serial_Command);
4543 }
4544 bitstring = 0;
4545 for (bit = 0x80; bit; bit >>= 1) {
4546 ni_writeb(dev, 0x04, Serial_Command);
4547 ni_writeb(dev, 0x05, Serial_Command);
4548 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4549 }
4550 ni_writeb(dev, 0x00, Serial_Command);
4551
4552 return bitstring;
4553 }
4554
4555 static int ni_eeprom_insn_read(struct comedi_device *dev,
4556 struct comedi_subdevice *s,
4557 struct comedi_insn *insn,
4558 unsigned int *data)
4559 {
4560 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4561
4562 return 1;
4563 }
4564
4565 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4566 struct comedi_subdevice *s,
4567 struct comedi_insn *insn,
4568 unsigned int *data)
4569 {
4570 struct ni_private *devpriv = dev->private;
4571
4572 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4573
4574 return 1;
4575 }
4576
4577 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4578 unsigned chan)
4579 {
4580 /* pre-m-series boards have fixed signals on pfi pins */
4581 switch (chan) {
4582 case 0:
4583 return NI_PFI_OUTPUT_AI_START1;
4584 break;
4585 case 1:
4586 return NI_PFI_OUTPUT_AI_START2;
4587 break;
4588 case 2:
4589 return NI_PFI_OUTPUT_AI_CONVERT;
4590 break;
4591 case 3:
4592 return NI_PFI_OUTPUT_G_SRC1;
4593 break;
4594 case 4:
4595 return NI_PFI_OUTPUT_G_GATE1;
4596 break;
4597 case 5:
4598 return NI_PFI_OUTPUT_AO_UPDATE_N;
4599 break;
4600 case 6:
4601 return NI_PFI_OUTPUT_AO_START1;
4602 break;
4603 case 7:
4604 return NI_PFI_OUTPUT_AI_START_PULSE;
4605 break;
4606 case 8:
4607 return NI_PFI_OUTPUT_G_SRC0;
4608 break;
4609 case 9:
4610 return NI_PFI_OUTPUT_G_GATE0;
4611 break;
4612 default:
4613 printk("%s: bug, unhandled case in switch.\n", __func__);
4614 break;
4615 }
4616 return 0;
4617 }
4618
4619 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4620 unsigned chan, unsigned source)
4621 {
4622 /* pre-m-series boards have fixed signals on pfi pins */
4623 if (source != ni_old_get_pfi_routing(dev, chan))
4624 return -EINVAL;
4625 return 2;
4626 }
4627
4628 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4629 unsigned chan)
4630 {
4631 struct ni_private *devpriv = dev->private;
4632 const unsigned array_offset = chan / 3;
4633
4634 return MSeries_PFI_Output_Select_Source(chan,
4635 devpriv->pfi_output_select_reg[array_offset]);
4636 }
4637
4638 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4639 unsigned chan, unsigned source)
4640 {
4641 struct ni_private *devpriv = dev->private;
4642 unsigned pfi_reg_index;
4643 unsigned array_offset;
4644
4645 if ((source & 0x1f) != source)
4646 return -EINVAL;
4647 pfi_reg_index = 1 + chan / 3;
4648 array_offset = pfi_reg_index - 1;
4649 devpriv->pfi_output_select_reg[array_offset] &=
4650 ~MSeries_PFI_Output_Select_Mask(chan);
4651 devpriv->pfi_output_select_reg[array_offset] |=
4652 MSeries_PFI_Output_Select_Bits(chan, source);
4653 ni_writew(dev, devpriv->pfi_output_select_reg[array_offset],
4654 M_Offset_PFI_Output_Select(pfi_reg_index));
4655 return 2;
4656 }
4657
4658 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4659 {
4660 struct ni_private *devpriv = dev->private;
4661
4662 if (devpriv->is_m_series)
4663 return ni_m_series_get_pfi_routing(dev, chan);
4664 else
4665 return ni_old_get_pfi_routing(dev, chan);
4666 }
4667
4668 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4669 unsigned source)
4670 {
4671 struct ni_private *devpriv = dev->private;
4672
4673 if (devpriv->is_m_series)
4674 return ni_m_series_set_pfi_routing(dev, chan, source);
4675 else
4676 return ni_old_set_pfi_routing(dev, chan, source);
4677 }
4678
4679 static int ni_config_filter(struct comedi_device *dev,
4680 unsigned pfi_channel,
4681 enum ni_pfi_filter_select filter)
4682 {
4683 struct ni_private *devpriv = dev->private;
4684 unsigned bits;
4685
4686 if (!devpriv->is_m_series)
4687 return -ENOTSUPP;
4688
4689 bits = ni_readl(dev, M_Offset_PFI_Filter);
4690 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4691 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4692 ni_writel(dev, bits, M_Offset_PFI_Filter);
4693 return 0;
4694 }
4695
4696 static int ni_pfi_insn_config(struct comedi_device *dev,
4697 struct comedi_subdevice *s,
4698 struct comedi_insn *insn,
4699 unsigned int *data)
4700 {
4701 struct ni_private *devpriv = dev->private;
4702 unsigned int chan;
4703
4704 if (insn->n < 1)
4705 return -EINVAL;
4706
4707 chan = CR_CHAN(insn->chanspec);
4708
4709 switch (data[0]) {
4710 case COMEDI_OUTPUT:
4711 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
4712 break;
4713 case COMEDI_INPUT:
4714 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
4715 break;
4716 case INSN_CONFIG_DIO_QUERY:
4717 data[1] =
4718 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4719 COMEDI_OUTPUT : COMEDI_INPUT;
4720 return 0;
4721 break;
4722 case INSN_CONFIG_SET_ROUTING:
4723 return ni_set_pfi_routing(dev, chan, data[1]);
4724 break;
4725 case INSN_CONFIG_GET_ROUTING:
4726 data[1] = ni_get_pfi_routing(dev, chan);
4727 break;
4728 case INSN_CONFIG_FILTER:
4729 return ni_config_filter(dev, chan, data[1]);
4730 break;
4731 default:
4732 return -EINVAL;
4733 }
4734 return 0;
4735 }
4736
4737 static int ni_pfi_insn_bits(struct comedi_device *dev,
4738 struct comedi_subdevice *s,
4739 struct comedi_insn *insn,
4740 unsigned int *data)
4741 {
4742 struct ni_private *devpriv = dev->private;
4743
4744 if (!devpriv->is_m_series)
4745 return -ENOTSUPP;
4746
4747 if (comedi_dio_update_state(s, data))
4748 ni_writew(dev, s->state, M_Offset_PFI_DO);
4749
4750 data[1] = ni_readw(dev, M_Offset_PFI_DI);
4751
4752 return insn->n;
4753 }
4754
4755 static int cs5529_wait_for_idle(struct comedi_device *dev)
4756 {
4757 unsigned short status;
4758 const int timeout = HZ;
4759 int i;
4760
4761 for (i = 0; i < timeout; i++) {
4762 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4763 if ((status & CSS_ADC_BUSY) == 0)
4764 break;
4765 set_current_state(TASK_INTERRUPTIBLE);
4766 if (schedule_timeout(1))
4767 return -EIO;
4768 }
4769 /* printk("looped %i times waiting for idle\n", i); */
4770 if (i == timeout) {
4771 printk("%s: %s: timeout\n", __FILE__, __func__);
4772 return -ETIME;
4773 }
4774 return 0;
4775 }
4776
4777 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4778 {
4779 static const int timeout = 100;
4780 int i;
4781
4782 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4783 /* give time for command to start being serially clocked into cs5529.
4784 * this insures that the CSS_ADC_BUSY bit will get properly
4785 * set before we exit this function.
4786 */
4787 for (i = 0; i < timeout; i++) {
4788 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4789 break;
4790 udelay(1);
4791 }
4792 /* printk("looped %i times writing command to cs5529\n", i); */
4793 if (i == timeout)
4794 comedi_error(dev, "possible problem - never saw adc go busy?");
4795 }
4796
4797 static int cs5529_do_conversion(struct comedi_device *dev,
4798 unsigned short *data)
4799 {
4800 int retval;
4801 unsigned short status;
4802
4803 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4804 retval = cs5529_wait_for_idle(dev);
4805 if (retval) {
4806 comedi_error(dev,
4807 "timeout or signal in cs5529_do_conversion()");
4808 return -ETIME;
4809 }
4810 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4811 if (status & CSS_OSC_DETECT) {
4812 printk
4813 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4814 return -EIO;
4815 }
4816 if (status & CSS_OVERRANGE) {
4817 printk
4818 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4819 }
4820 if (data) {
4821 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4822 /* cs5529 returns 16 bit signed data in bipolar mode */
4823 *data ^= (1 << 15);
4824 }
4825 return 0;
4826 }
4827
4828 static int cs5529_ai_insn_read(struct comedi_device *dev,
4829 struct comedi_subdevice *s,
4830 struct comedi_insn *insn,
4831 unsigned int *data)
4832 {
4833 int n, retval;
4834 unsigned short sample;
4835 unsigned int channel_select;
4836 const unsigned int INTERNAL_REF = 0x1000;
4837
4838 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4839 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4840 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4841 if (insn->chanspec & CR_ALT_SOURCE)
4842 channel_select = INTERNAL_REF;
4843 else
4844 channel_select = CR_CHAN(insn->chanspec);
4845 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4846
4847 for (n = 0; n < insn->n; n++) {
4848 retval = cs5529_do_conversion(dev, &sample);
4849 if (retval < 0)
4850 return retval;
4851 data[n] = sample;
4852 }
4853 return insn->n;
4854 }
4855
4856 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4857 unsigned int reg_select_bits)
4858 {
4859 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4860 CAL_ADC_Config_Data_High_Word_67xx);
4861 ni_ao_win_outw(dev, (value & 0xffff),
4862 CAL_ADC_Config_Data_Low_Word_67xx);
4863 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4864 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4865 if (cs5529_wait_for_idle(dev))
4866 comedi_error(dev, "time or signal in cs5529_config_write()");
4867 }
4868
4869 static int init_cs5529(struct comedi_device *dev)
4870 {
4871 unsigned int config_bits =
4872 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4873
4874 #if 1
4875 /* do self-calibration */
4876 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4877 CSCMD_CONFIG_REGISTER);
4878 /* need to force a conversion for calibration to run */
4879 cs5529_do_conversion(dev, NULL);
4880 #else
4881 /* force gain calibration to 1 */
4882 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4883 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4884 CSCMD_CONFIG_REGISTER);
4885 if (cs5529_wait_for_idle(dev))
4886 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4887 #endif
4888 return 0;
4889 }
4890
4891 /*
4892 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4893 * given an arbitrary frequency input clock.
4894 */
4895 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4896 unsigned *freq_divider,
4897 unsigned *freq_multiplier,
4898 unsigned *actual_period_ns)
4899 {
4900 unsigned div;
4901 unsigned best_div = 1;
4902 static const unsigned max_div = 0x10;
4903 unsigned mult;
4904 unsigned best_mult = 1;
4905 static const unsigned max_mult = 0x100;
4906 static const unsigned pico_per_nano = 1000;
4907
4908 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4909 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4910 * 20 MHz for most timing clocks */
4911 static const unsigned target_picosec = 12500;
4912 static const unsigned fudge_factor_80_to_20Mhz = 4;
4913 int best_period_picosec = 0;
4914 for (div = 1; div <= max_div; ++div) {
4915 for (mult = 1; mult <= max_mult; ++mult) {
4916 unsigned new_period_ps =
4917 (reference_picosec * div) / mult;
4918 if (abs(new_period_ps - target_picosec) <
4919 abs(best_period_picosec - target_picosec)) {
4920 best_period_picosec = new_period_ps;
4921 best_div = div;
4922 best_mult = mult;
4923 }
4924 }
4925 }
4926 if (best_period_picosec == 0) {
4927 printk("%s: bug, failed to find pll parameters\n", __func__);
4928 return -EIO;
4929 }
4930 *freq_divider = best_div;
4931 *freq_multiplier = best_mult;
4932 *actual_period_ns =
4933 (best_period_picosec * fudge_factor_80_to_20Mhz +
4934 (pico_per_nano / 2)) / pico_per_nano;
4935 return 0;
4936 }
4937
4938 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4939 unsigned source, unsigned period_ns)
4940 {
4941 struct ni_private *devpriv = dev->private;
4942 static const unsigned min_period_ns = 50;
4943 static const unsigned max_period_ns = 1000;
4944 static const unsigned timeout = 1000;
4945 unsigned pll_control_bits;
4946 unsigned freq_divider;
4947 unsigned freq_multiplier;
4948 unsigned i;
4949 int retval;
4950
4951 if (source == NI_MIO_PLL_PXI10_CLOCK)
4952 period_ns = 100;
4953 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4954 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4955 printk
4956 ("%s: you must specify an input clock frequency between %i and %i nanosec "
4957 "for the phased-lock loop.\n", __func__,
4958 min_period_ns, max_period_ns);
4959 return -EINVAL;
4960 }
4961 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4962 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4963 RTSI_Trig_Direction_Register);
4964 pll_control_bits =
4965 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4966 devpriv->clock_and_fout2 |=
4967 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4968 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4969 switch (source) {
4970 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4971 devpriv->clock_and_fout2 |=
4972 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4973 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4974 &freq_multiplier,
4975 &devpriv->clock_ns);
4976 if (retval < 0)
4977 return retval;
4978 break;
4979 case NI_MIO_PLL_PXI10_CLOCK:
4980 /* pxi clock is 10MHz */
4981 devpriv->clock_and_fout2 |=
4982 MSeries_PLL_In_Source_Select_PXI_Clock10;
4983 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4984 &freq_multiplier,
4985 &devpriv->clock_ns);
4986 if (retval < 0)
4987 return retval;
4988 break;
4989 default:
4990 {
4991 unsigned rtsi_channel;
4992 static const unsigned max_rtsi_channel = 7;
4993 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
4994 ++rtsi_channel) {
4995 if (source ==
4996 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
4997 devpriv->clock_and_fout2 |=
4998 MSeries_PLL_In_Source_Select_RTSI_Bits
4999 (rtsi_channel);
5000 break;
5001 }
5002 }
5003 if (rtsi_channel > max_rtsi_channel)
5004 return -EINVAL;
5005 retval = ni_mseries_get_pll_parameters(period_ns,
5006 &freq_divider,
5007 &freq_multiplier,
5008 &devpriv->
5009 clock_ns);
5010 if (retval < 0)
5011 return retval;
5012 }
5013 break;
5014 }
5015 ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5016 pll_control_bits |=
5017 MSeries_PLL_Divisor_Bits(freq_divider) |
5018 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5019
5020 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5021 * freq_divider, freq_multiplier, pll_control_bits); */
5022 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5023 ni_writew(dev, pll_control_bits, M_Offset_PLL_Control);
5024 devpriv->clock_source = source;
5025 /* it seems to typically take a few hundred microseconds for PLL to lock */
5026 for (i = 0; i < timeout; ++i) {
5027 if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
5028 break;
5029 udelay(1);
5030 }
5031 if (i == timeout) {
5032 printk
5033 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5034 __func__, source, period_ns);
5035 return -ETIMEDOUT;
5036 }
5037 return 3;
5038 }
5039
5040 static int ni_set_master_clock(struct comedi_device *dev,
5041 unsigned source, unsigned period_ns)
5042 {
5043 struct ni_private *devpriv = dev->private;
5044
5045 if (source == NI_MIO_INTERNAL_CLOCK) {
5046 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5047 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5048 RTSI_Trig_Direction_Register);
5049 devpriv->clock_ns = TIMEBASE_1_NS;
5050 if (devpriv->is_m_series) {
5051 devpriv->clock_and_fout2 &=
5052 ~(MSeries_Timebase1_Select_Bit |
5053 MSeries_Timebase3_Select_Bit);
5054 ni_writew(dev, devpriv->clock_and_fout2,
5055 M_Offset_Clock_and_Fout2);
5056 ni_writew(dev, 0, M_Offset_PLL_Control);
5057 }
5058 devpriv->clock_source = source;
5059 } else {
5060 if (devpriv->is_m_series) {
5061 return ni_mseries_set_pll_master_clock(dev, source,
5062 period_ns);
5063 } else {
5064 if (source == NI_MIO_RTSI_CLOCK) {
5065 devpriv->rtsi_trig_direction_reg |=
5066 Use_RTSI_Clock_Bit;
5067 ni_stc_writew(dev,
5068 devpriv->rtsi_trig_direction_reg,
5069 RTSI_Trig_Direction_Register);
5070 if (period_ns == 0) {
5071 printk
5072 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5073 __func__);
5074 return -EINVAL;
5075 } else {
5076 devpriv->clock_ns = period_ns;
5077 }
5078 devpriv->clock_source = source;
5079 } else
5080 return -EINVAL;
5081 }
5082 }
5083 return 3;
5084 }
5085
5086 static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5087 {
5088 struct ni_private *devpriv = dev->private;
5089
5090 if (devpriv->is_m_series)
5091 return 8;
5092 else
5093 return 7;
5094 }
5095
5096 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5097 unsigned chan, unsigned source)
5098 {
5099 struct ni_private *devpriv = dev->private;
5100
5101 if (chan >= num_configurable_rtsi_channels(dev)) {
5102 if (chan == old_RTSI_clock_channel) {
5103 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5104 return 1;
5105 else {
5106 printk
5107 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5108 __func__, chan, old_RTSI_clock_channel);
5109 return 0;
5110 }
5111 }
5112 return 0;
5113 }
5114 switch (source) {
5115 case NI_RTSI_OUTPUT_ADR_START1:
5116 case NI_RTSI_OUTPUT_ADR_START2:
5117 case NI_RTSI_OUTPUT_SCLKG:
5118 case NI_RTSI_OUTPUT_DACUPDN:
5119 case NI_RTSI_OUTPUT_DA_START1:
5120 case NI_RTSI_OUTPUT_G_SRC0:
5121 case NI_RTSI_OUTPUT_G_GATE0:
5122 case NI_RTSI_OUTPUT_RGOUT0:
5123 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5124 return 1;
5125 break;
5126 case NI_RTSI_OUTPUT_RTSI_OSC:
5127 if (devpriv->is_m_series)
5128 return 1;
5129 else
5130 return 0;
5131 break;
5132 default:
5133 return 0;
5134 break;
5135 }
5136 }
5137
5138 static int ni_set_rtsi_routing(struct comedi_device *dev,
5139 unsigned chan, unsigned source)
5140 {
5141 struct ni_private *devpriv = dev->private;
5142
5143 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5144 return -EINVAL;
5145 if (chan < 4) {
5146 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5147 devpriv->rtsi_trig_a_output_reg |=
5148 RTSI_Trig_Output_Bits(chan, source);
5149 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5150 RTSI_Trig_A_Output_Register);
5151 } else if (chan < 8) {
5152 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5153 devpriv->rtsi_trig_b_output_reg |=
5154 RTSI_Trig_Output_Bits(chan, source);
5155 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5156 RTSI_Trig_B_Output_Register);
5157 }
5158 return 2;
5159 }
5160
5161 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5162 {
5163 struct ni_private *devpriv = dev->private;
5164
5165 if (chan < 4) {
5166 return RTSI_Trig_Output_Source(chan,
5167 devpriv->rtsi_trig_a_output_reg);
5168 } else if (chan < num_configurable_rtsi_channels(dev)) {
5169 return RTSI_Trig_Output_Source(chan,
5170 devpriv->rtsi_trig_b_output_reg);
5171 } else {
5172 if (chan == old_RTSI_clock_channel)
5173 return NI_RTSI_OUTPUT_RTSI_OSC;
5174 printk("%s: bug! should never get here?\n", __func__);
5175 return 0;
5176 }
5177 }
5178
5179 static int ni_rtsi_insn_config(struct comedi_device *dev,
5180 struct comedi_subdevice *s,
5181 struct comedi_insn *insn,
5182 unsigned int *data)
5183 {
5184 struct ni_private *devpriv = dev->private;
5185 unsigned int chan = CR_CHAN(insn->chanspec);
5186
5187 switch (data[0]) {
5188 case INSN_CONFIG_DIO_OUTPUT:
5189 if (chan < num_configurable_rtsi_channels(dev)) {
5190 devpriv->rtsi_trig_direction_reg |=
5191 RTSI_Output_Bit(chan, devpriv->is_m_series);
5192 } else if (chan == old_RTSI_clock_channel) {
5193 devpriv->rtsi_trig_direction_reg |=
5194 Drive_RTSI_Clock_Bit;
5195 }
5196 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5197 RTSI_Trig_Direction_Register);
5198 break;
5199 case INSN_CONFIG_DIO_INPUT:
5200 if (chan < num_configurable_rtsi_channels(dev)) {
5201 devpriv->rtsi_trig_direction_reg &=
5202 ~RTSI_Output_Bit(chan, devpriv->is_m_series);
5203 } else if (chan == old_RTSI_clock_channel) {
5204 devpriv->rtsi_trig_direction_reg &=
5205 ~Drive_RTSI_Clock_Bit;
5206 }
5207 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5208 RTSI_Trig_Direction_Register);
5209 break;
5210 case INSN_CONFIG_DIO_QUERY:
5211 if (chan < num_configurable_rtsi_channels(dev)) {
5212 data[1] =
5213 (devpriv->rtsi_trig_direction_reg &
5214 RTSI_Output_Bit(chan, devpriv->is_m_series))
5215 ? INSN_CONFIG_DIO_OUTPUT
5216 : INSN_CONFIG_DIO_INPUT;
5217 } else if (chan == old_RTSI_clock_channel) {
5218 data[1] =
5219 (devpriv->rtsi_trig_direction_reg &
5220 Drive_RTSI_Clock_Bit)
5221 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5222 }
5223 return 2;
5224 break;
5225 case INSN_CONFIG_SET_CLOCK_SRC:
5226 return ni_set_master_clock(dev, data[1], data[2]);
5227 break;
5228 case INSN_CONFIG_GET_CLOCK_SRC:
5229 data[1] = devpriv->clock_source;
5230 data[2] = devpriv->clock_ns;
5231 return 3;
5232 break;
5233 case INSN_CONFIG_SET_ROUTING:
5234 return ni_set_rtsi_routing(dev, chan, data[1]);
5235 break;
5236 case INSN_CONFIG_GET_ROUTING:
5237 data[1] = ni_get_rtsi_routing(dev, chan);
5238 return 2;
5239 break;
5240 default:
5241 return -EINVAL;
5242 break;
5243 }
5244 return 1;
5245 }
5246
5247 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5248 struct comedi_subdevice *s,
5249 struct comedi_insn *insn,
5250 unsigned int *data)
5251 {
5252 data[1] = 0;
5253
5254 return insn->n;
5255 }
5256
5257 static void ni_rtsi_init(struct comedi_device *dev)
5258 {
5259 struct ni_private *devpriv = dev->private;
5260
5261 /* Initialises the RTSI bus signal switch to a default state */
5262
5263 /* Set clock mode to internal */
5264 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5265 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5266 printk("ni_set_master_clock failed, bug?");
5267 /* default internal lines routing to RTSI bus lines */
5268 devpriv->rtsi_trig_a_output_reg =
5269 RTSI_Trig_Output_Bits(0,
5270 NI_RTSI_OUTPUT_ADR_START1) |
5271 RTSI_Trig_Output_Bits(1,
5272 NI_RTSI_OUTPUT_ADR_START2) |
5273 RTSI_Trig_Output_Bits(2,
5274 NI_RTSI_OUTPUT_SCLKG) |
5275 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5276 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5277 RTSI_Trig_A_Output_Register);
5278 devpriv->rtsi_trig_b_output_reg =
5279 RTSI_Trig_Output_Bits(4,
5280 NI_RTSI_OUTPUT_DA_START1) |
5281 RTSI_Trig_Output_Bits(5,
5282 NI_RTSI_OUTPUT_G_SRC0) |
5283 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5284 if (devpriv->is_m_series)
5285 devpriv->rtsi_trig_b_output_reg |=
5286 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5287 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5288 RTSI_Trig_B_Output_Register);
5289
5290 /*
5291 * Sets the source and direction of the 4 on board lines
5292 * ni_stc_writew(dev, 0x0000, RTSI_Board_Register);
5293 */
5294 }
5295
5296 #ifdef PCIDMA
5297 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5298 {
5299 struct ni_gpct *counter = s->private;
5300 int retval;
5301
5302 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5303 COMEDI_INPUT);
5304 if (retval) {
5305 comedi_error(dev,
5306 "no dma channel available for use by counter");
5307 return retval;
5308 }
5309 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5310 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5311
5312 return ni_tio_cmd(dev, s);
5313 }
5314
5315 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5316 {
5317 struct ni_gpct *counter = s->private;
5318 int retval;
5319
5320 retval = ni_tio_cancel(counter);
5321 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5322 ni_release_gpct_mite_channel(dev, counter->counter_index);
5323 return retval;
5324 }
5325 #endif
5326
5327 #if 0
5328 /*
5329 * Read the GPCTs current value.
5330 */
5331 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5332 {
5333 unsigned int hi1, hi2, lo;
5334
5335 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5336 ni_stc_writew(dev, devpriv->gpct_command[chan],
5337 G_Command_Register(chan));
5338
5339 devpriv->gpct_command[chan] |= G_Save_Trace;
5340 ni_stc_writew(dev, devpriv->gpct_command[chan],
5341 G_Command_Register(chan));
5342
5343 /* This procedure is used because the two registers cannot
5344 * be read atomically. */
5345 do {
5346 hi1 = ni_stc_readw(dev, G_Save_Register_High(chan));
5347 lo = ni_stc_readw(dev, G_Save_Register_Low(chan));
5348 hi2 = ni_stc_readw(dev, G_Save_Register_High(chan));
5349 } while (hi1 != hi2);
5350
5351 return (hi1 << 16) | lo;
5352 }
5353
5354 static void GPCT_Reset(struct comedi_device *dev, int chan)
5355 {
5356 int temp_ack_reg = 0;
5357
5358 /* printk("GPCT_Reset..."); */
5359 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5360
5361 switch (chan) {
5362 case 0:
5363 ni_stc_writew(dev, G0_Reset, Joint_Reset_Register);
5364 ni_set_bits(dev, Interrupt_A_Enable_Register,
5365 G0_TC_Interrupt_Enable, 0);
5366 ni_set_bits(dev, Interrupt_A_Enable_Register,
5367 G0_Gate_Interrupt_Enable, 0);
5368 temp_ack_reg |= G0_Gate_Error_Confirm;
5369 temp_ack_reg |= G0_TC_Error_Confirm;
5370 temp_ack_reg |= G0_TC_Interrupt_Ack;
5371 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5372 ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register);
5373
5374 /* problem...this interferes with the other ctr... */
5375 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5376 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5377 Analog_Trigger_Etc_Register);
5378 break;
5379 case 1:
5380 ni_stc_writew(dev, G1_Reset, Joint_Reset_Register);
5381 ni_set_bits(dev, Interrupt_B_Enable_Register,
5382 G1_TC_Interrupt_Enable, 0);
5383 ni_set_bits(dev, Interrupt_B_Enable_Register,
5384 G0_Gate_Interrupt_Enable, 0);
5385 temp_ack_reg |= G1_Gate_Error_Confirm;
5386 temp_ack_reg |= G1_TC_Error_Confirm;
5387 temp_ack_reg |= G1_TC_Interrupt_Ack;
5388 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5389 ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register);
5390
5391 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5392 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5393 Analog_Trigger_Etc_Register);
5394 break;
5395 }
5396
5397 devpriv->gpct_mode[chan] = 0;
5398 devpriv->gpct_input_select[chan] = 0;
5399 devpriv->gpct_command[chan] = 0;
5400
5401 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5402
5403 ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
5404 ni_stc_writew(dev, devpriv->gpct_input_select[chan],
5405 G_Input_Select_Register(chan));
5406 ni_stc_writew(dev, 0, G_Autoincrement_Register(chan));
5407
5408 /* printk("exit GPCT_Reset\n"); */
5409 }
5410 #endif
5411
5412 static irqreturn_t ni_E_interrupt(int irq, void *d)
5413 {
5414 struct comedi_device *dev = d;
5415 unsigned short a_status;
5416 unsigned short b_status;
5417 unsigned int ai_mite_status = 0;
5418 unsigned int ao_mite_status = 0;
5419 unsigned long flags;
5420 #ifdef PCIDMA
5421 struct ni_private *devpriv = dev->private;
5422 struct mite_struct *mite = devpriv->mite;
5423 #endif
5424
5425 if (!dev->attached)
5426 return IRQ_NONE;
5427 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5428
5429 /* lock to avoid race with comedi_poll */
5430 spin_lock_irqsave(&dev->spinlock, flags);
5431 a_status = ni_stc_readw(dev, AI_Status_1_Register);
5432 b_status = ni_stc_readw(dev, AO_Status_1_Register);
5433 #ifdef PCIDMA
5434 if (mite) {
5435 struct ni_private *devpriv = dev->private;
5436 unsigned long flags_too;
5437
5438 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5439 if (devpriv->ai_mite_chan) {
5440 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5441 if (ai_mite_status & CHSR_LINKC)
5442 writel(CHOR_CLRLC,
5443 devpriv->mite->mite_io_addr +
5444 MITE_CHOR(devpriv->
5445 ai_mite_chan->channel));
5446 }
5447 if (devpriv->ao_mite_chan) {
5448 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5449 if (ao_mite_status & CHSR_LINKC)
5450 writel(CHOR_CLRLC,
5451 mite->mite_io_addr +
5452 MITE_CHOR(devpriv->
5453 ao_mite_chan->channel));
5454 }
5455 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5456 }
5457 #endif
5458 ack_a_interrupt(dev, a_status);
5459 ack_b_interrupt(dev, b_status);
5460 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
5461 handle_a_interrupt(dev, a_status, ai_mite_status);
5462 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
5463 handle_b_interrupt(dev, b_status, ao_mite_status);
5464 handle_gpct_interrupt(dev, 0);
5465 handle_gpct_interrupt(dev, 1);
5466 handle_cdio_interrupt(dev);
5467
5468 spin_unlock_irqrestore(&dev->spinlock, flags);
5469 return IRQ_HANDLED;
5470 }
5471
5472 static int ni_alloc_private(struct comedi_device *dev)
5473 {
5474 struct ni_private *devpriv;
5475
5476 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5477 if (!devpriv)
5478 return -ENOMEM;
5479
5480 spin_lock_init(&devpriv->window_lock);
5481 spin_lock_init(&devpriv->soft_reg_copy_lock);
5482 spin_lock_init(&devpriv->mite_channel_lock);
5483
5484 return 0;
5485 }
5486
5487 static int ni_E_init(struct comedi_device *dev,
5488 unsigned interrupt_pin, unsigned irq_polarity)
5489 {
5490 const struct ni_board_struct *board = comedi_board(dev);
5491 struct ni_private *devpriv = dev->private;
5492 struct comedi_subdevice *s;
5493 int ret;
5494 int i;
5495
5496 if (board->n_aochan > MAX_N_AO_CHAN) {
5497 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
5498 return -EINVAL;
5499 }
5500
5501 /* initialize clock dividers */
5502 devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 |
5503 Slow_Internal_Timebase |
5504 Clock_To_Board_Divide_By_2 |
5505 Clock_To_Board;
5506 if (!devpriv->is_6xxx) {
5507 /* BEAM is this needed for PCI-6143 ?? */
5508 devpriv->clock_and_fout |= (AI_Output_Divide_By_2 |
5509 AO_Output_Divide_By_2);
5510 }
5511 ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
5512
5513 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5514 if (ret)
5515 return ret;
5516
5517 /* Analog Input subdevice */
5518 s = &dev->subdevices[NI_AI_SUBDEV];
5519 if (board->n_adchan) {
5520 s->type = COMEDI_SUBD_AI;
5521 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5522 if (!devpriv->is_611x)
5523 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5524 if (board->ai_maxdata > 0xffff)
5525 s->subdev_flags |= SDF_LSAMPL;
5526 if (devpriv->is_m_series)
5527 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5528 s->n_chan = board->n_adchan;
5529 s->maxdata = board->ai_maxdata;
5530 s->range_table = ni_range_lkup[board->gainlkup];
5531 s->insn_read = ni_ai_insn_read;
5532 s->insn_config = ni_ai_insn_config;
5533 if (dev->irq) {
5534 dev->read_subdev = s;
5535 s->subdev_flags |= SDF_CMD_READ;
5536 s->len_chanlist = 512;
5537 s->do_cmdtest = ni_ai_cmdtest;
5538 s->do_cmd = ni_ai_cmd;
5539 s->cancel = ni_ai_reset;
5540 s->poll = ni_ai_poll;
5541 s->munge = ni_ai_munge;
5542
5543 if (devpriv->mite)
5544 s->async_dma_dir = DMA_FROM_DEVICE;
5545 }
5546
5547 /* reset the analog input configuration */
5548 ni_ai_reset(dev, s);
5549 } else {
5550 s->type = COMEDI_SUBD_UNUSED;
5551 }
5552
5553 /* Analog Output subdevice */
5554 s = &dev->subdevices[NI_AO_SUBDEV];
5555 if (board->n_aochan) {
5556 s->type = COMEDI_SUBD_AO;
5557 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5558 if (devpriv->is_m_series)
5559 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5560 s->n_chan = board->n_aochan;
5561 s->maxdata = board->ao_maxdata;
5562 s->range_table = board->ao_range_table;
5563 s->insn_read = ni_ao_insn_read;
5564 s->insn_write = ni_ao_insn_write;
5565 s->insn_config = ni_ao_insn_config;
5566
5567 /*
5568 * Along with the IRQ we need either a FIFO or DMA for
5569 * async command support.
5570 */
5571 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5572 dev->write_subdev = s;
5573 s->subdev_flags |= SDF_CMD_WRITE;
5574 s->len_chanlist = s->n_chan;
5575 s->do_cmdtest = ni_ao_cmdtest;
5576 s->do_cmd = ni_ao_cmd;
5577 s->cancel = ni_ao_reset;
5578 if (!devpriv->is_m_series)
5579 s->munge = ni_ao_munge;
5580
5581 if (devpriv->mite)
5582 s->async_dma_dir = DMA_TO_DEVICE;
5583 }
5584
5585 if (devpriv->is_67xx)
5586 init_ao_67xx(dev, s);
5587
5588 /* reset the analog output configuration */
5589 ni_ao_reset(dev, s);
5590 } else {
5591 s->type = COMEDI_SUBD_UNUSED;
5592 }
5593
5594 /* Digital I/O subdevice */
5595 s = &dev->subdevices[NI_DIO_SUBDEV];
5596 s->type = COMEDI_SUBD_DIO;
5597 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5598 s->n_chan = board->has_32dio_chan ? 32 : 8;
5599 s->maxdata = 1;
5600 s->range_table = &range_digital;
5601 if (devpriv->is_m_series) {
5602 s->subdev_flags |= SDF_LSAMPL;
5603 s->insn_bits = ni_m_series_dio_insn_bits;
5604 s->insn_config = ni_m_series_dio_insn_config;
5605 if (dev->irq) {
5606 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5607 s->len_chanlist = s->n_chan;
5608 s->do_cmdtest = ni_cdio_cmdtest;
5609 s->do_cmd = ni_cdio_cmd;
5610 s->cancel = ni_cdio_cancel;
5611
5612 /* M-series boards use DMA */
5613 s->async_dma_dir = DMA_BIDIRECTIONAL;
5614 }
5615
5616 /* reset DIO and set all channels to inputs */
5617 ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
5618 M_Offset_CDIO_Command);
5619 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
5620 } else {
5621 s->insn_bits = ni_dio_insn_bits;
5622 s->insn_config = ni_dio_insn_config;
5623
5624 /* set all channels to inputs */
5625 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
5626 ni_writew(dev, devpriv->dio_control, DIO_Control_Register);
5627 }
5628
5629 /* 8255 device */
5630 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5631 if (board->has_8255) {
5632 ret = subdev_8255_init(dev, s, ni_8255_callback,
5633 (unsigned long)dev);
5634 if (ret)
5635 return ret;
5636 } else {
5637 s->type = COMEDI_SUBD_UNUSED;
5638 }
5639
5640 /* formerly general purpose counter/timer device, but no longer used */
5641 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5642 s->type = COMEDI_SUBD_UNUSED;
5643
5644 /* Calibration subdevice */
5645 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5646 s->type = COMEDI_SUBD_CALIB;
5647 s->subdev_flags = SDF_INTERNAL;
5648 s->n_chan = 1;
5649 s->maxdata = 0;
5650 if (devpriv->is_m_series) {
5651 /* internal PWM output used for AI nonlinearity calibration */
5652 s->insn_config = ni_m_series_pwm_config;
5653
5654 ni_writel(dev, 0x0, M_Offset_Cal_PWM);
5655 } else if (devpriv->is_6143) {
5656 /* internal PWM output used for AI nonlinearity calibration */
5657 s->insn_config = ni_6143_pwm_config;
5658 } else {
5659 s->subdev_flags |= SDF_WRITABLE;
5660 s->insn_read = ni_calib_insn_read;
5661 s->insn_write = ni_calib_insn_write;
5662
5663 /* setup the caldacs and find the real n_chan and maxdata */
5664 caldac_setup(dev, s);
5665 }
5666
5667 /* EEPROM subdevice */
5668 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5669 s->type = COMEDI_SUBD_MEMORY;
5670 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5671 s->maxdata = 0xff;
5672 if (devpriv->is_m_series) {
5673 s->n_chan = M_SERIES_EEPROM_SIZE;
5674 s->insn_read = ni_m_series_eeprom_insn_read;
5675 } else {
5676 s->n_chan = 512;
5677 s->insn_read = ni_eeprom_insn_read;
5678 }
5679
5680 /* Digital I/O (PFI) subdevice */
5681 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5682 s->type = COMEDI_SUBD_DIO;
5683 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5684 s->maxdata = 1;
5685 if (devpriv->is_m_series) {
5686 s->n_chan = 16;
5687 s->insn_bits = ni_pfi_insn_bits;
5688
5689 ni_writew(dev, s->state, M_Offset_PFI_DO);
5690 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5691 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5692 M_Offset_PFI_Output_Select(i + 1));
5693 }
5694 } else {
5695 s->n_chan = 10;
5696 }
5697 s->insn_config = ni_pfi_insn_config;
5698
5699 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
5700
5701 /* cs5529 calibration adc */
5702 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5703 if (devpriv->is_67xx) {
5704 s->type = COMEDI_SUBD_AI;
5705 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5706 /* one channel for each analog output channel */
5707 s->n_chan = board->n_aochan;
5708 s->maxdata = (1 << 16) - 1;
5709 s->range_table = &range_unknown; /* XXX */
5710 s->insn_read = cs5529_ai_insn_read;
5711 s->insn_config = NULL;
5712 init_cs5529(dev);
5713 } else {
5714 s->type = COMEDI_SUBD_UNUSED;
5715 }
5716
5717 /* Serial */
5718 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5719 s->type = COMEDI_SUBD_SERIAL;
5720 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5721 s->n_chan = 1;
5722 s->maxdata = 0xff;
5723 s->insn_config = ni_serial_insn_config;
5724 devpriv->serial_interval_ns = 0;
5725 devpriv->serial_hw_mode = 0;
5726
5727 /* RTSI */
5728 s = &dev->subdevices[NI_RTSI_SUBDEV];
5729 s->type = COMEDI_SUBD_DIO;
5730 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5731 s->n_chan = 8;
5732 s->maxdata = 1;
5733 s->insn_bits = ni_rtsi_insn_bits;
5734 s->insn_config = ni_rtsi_insn_config;
5735 ni_rtsi_init(dev);
5736
5737 /* allocate and initialize the gpct counter device */
5738 devpriv->counter_dev = ni_gpct_device_construct(dev,
5739 ni_gpct_write_register,
5740 ni_gpct_read_register,
5741 (devpriv->is_m_series)
5742 ? ni_gpct_variant_m_series
5743 : ni_gpct_variant_e_series,
5744 NUM_GPCT);
5745 if (!devpriv->counter_dev)
5746 return -ENOMEM;
5747
5748 /* Counter (gpct) subdevices */
5749 for (i = 0; i < NUM_GPCT; ++i) {
5750 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5751
5752 /* setup and initialize the counter */
5753 gpct->chip_index = 0;
5754 gpct->counter_index = i;
5755 ni_tio_init_counter(gpct);
5756
5757 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5758 s->type = COMEDI_SUBD_COUNTER;
5759 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5760 s->n_chan = 3;
5761 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5762 : 0x00ffffff;
5763 s->insn_read = ni_tio_insn_read;
5764 s->insn_write = ni_tio_insn_read;
5765 s->insn_config = ni_tio_insn_config;
5766 #ifdef PCIDMA
5767 if (dev->irq && devpriv->mite) {
5768 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5769 s->len_chanlist = 1;
5770 s->do_cmdtest = ni_tio_cmdtest;
5771 s->do_cmd = ni_gpct_cmd;
5772 s->cancel = ni_gpct_cancel;
5773
5774 s->async_dma_dir = DMA_BIDIRECTIONAL;
5775 }
5776 #endif
5777 s->private = gpct;
5778 }
5779
5780 /* Frequency output subdevice */
5781 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5782 s->type = COMEDI_SUBD_COUNTER;
5783 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5784 s->n_chan = 1;
5785 s->maxdata = 0xf;
5786 s->insn_read = ni_freq_out_insn_read;
5787 s->insn_write = ni_freq_out_insn_write;
5788 s->insn_config = ni_freq_out_insn_config;
5789
5790 if (dev->irq) {
5791 ni_stc_writew(dev,
5792 (irq_polarity ? Interrupt_Output_Polarity : 0) |
5793 (Interrupt_Output_On_3_Pins & 0) |
5794 Interrupt_A_Enable | Interrupt_B_Enable |
5795 Interrupt_A_Output_Select(interrupt_pin) |
5796 Interrupt_B_Output_Select(interrupt_pin),
5797 Interrupt_Control_Register);
5798 }
5799
5800 /* DMA setup */
5801 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5802 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5803
5804 if (devpriv->is_6xxx) {
5805 ni_writeb(dev, 0, Magic_611x);
5806 } else if (devpriv->is_m_series) {
5807 int channel;
5808 for (channel = 0; channel < board->n_aochan; ++channel) {
5809 ni_writeb(dev, 0xf,
5810 M_Offset_AO_Waveform_Order(channel));
5811 ni_writeb(dev, 0x0,
5812 M_Offset_AO_Reference_Attenuation(channel));
5813 }
5814 ni_writeb(dev, 0x0, M_Offset_AO_Calibration);
5815 }
5816
5817 return 0;
5818 }
5819
5820 static void mio_common_detach(struct comedi_device *dev)
5821 {
5822 struct ni_private *devpriv = dev->private;
5823
5824 if (devpriv) {
5825 if (devpriv->counter_dev)
5826 ni_gpct_device_destroy(devpriv->counter_dev);
5827 }
5828 }
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