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Merge tag 'ntb-4.13-bugfixes' of git://github.com/jonmason/ntb
[mirror_ubuntu-artful-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 * Hardware driver for DAQ-STC based boards
3 *
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
6 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * This file is meant to be included by another file, e.g.,
21 * ni_atmio.c or ni_pcimio.c.
22 *
23 * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
24 *
25 * References (ftp://ftp.natinst.com/support/manuals):
26 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
27 * 341079b.pdf PCI E Series RLPM
28 * 340934b.pdf DAQ-STC reference manual
29 *
30 * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
31 * release_ni611x.pdf
32 * release_ni67xx.pdf
33 *
34 * Other possibly relevant info:
35 * 320517c.pdf User manual (obsolete)
36 * 320517f.pdf User manual (new)
37 * 320889a.pdf delete
38 * 320906c.pdf maximum signal ratings
39 * 321066a.pdf about 16x
40 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
41 * 321808a.pdf about at-mio-16e-10 rev P
42 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
43 * 321838a.pdf about at-mio-16de-10 rev N
44 *
45 * ISSUES:
46 * - the interrupt routine needs to be cleaned up
47 *
48 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
49 * fully tested as yet. Terry Barnaby, BEAM Ltd.
50 */
51
52 #include <linux/interrupt.h>
53 #include <linux/sched.h>
54 #include <linux/delay.h>
55 #include "8255.h"
56 #include "mite.h"
57
58 /* A timeout count */
59 #define NI_TIMEOUT 1000
60
61 /* Note: this table must match the ai_gain_* definitions */
62 static const short ni_gainlkup[][16] = {
63 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
64 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
65 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
66 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
67 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_4] = {0, 1, 4, 7},
69 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
70 0x003, 0x004, 0x005, 0x006},
71 [ai_gain_622x] = {0, 1, 4, 5},
72 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
73 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
74 };
75
76 static const struct comedi_lrange range_ni_E_ai = {
77 16, {
78 BIP_RANGE(10),
79 BIP_RANGE(5),
80 BIP_RANGE(2.5),
81 BIP_RANGE(1),
82 BIP_RANGE(0.5),
83 BIP_RANGE(0.25),
84 BIP_RANGE(0.1),
85 BIP_RANGE(0.05),
86 UNI_RANGE(20),
87 UNI_RANGE(10),
88 UNI_RANGE(5),
89 UNI_RANGE(2),
90 UNI_RANGE(1),
91 UNI_RANGE(0.5),
92 UNI_RANGE(0.2),
93 UNI_RANGE(0.1)
94 }
95 };
96
97 static const struct comedi_lrange range_ni_E_ai_limited = {
98 8, {
99 BIP_RANGE(10),
100 BIP_RANGE(5),
101 BIP_RANGE(1),
102 BIP_RANGE(0.1),
103 UNI_RANGE(10),
104 UNI_RANGE(5),
105 UNI_RANGE(1),
106 UNI_RANGE(0.1)
107 }
108 };
109
110 static const struct comedi_lrange range_ni_E_ai_limited14 = {
111 14, {
112 BIP_RANGE(10),
113 BIP_RANGE(5),
114 BIP_RANGE(2),
115 BIP_RANGE(1),
116 BIP_RANGE(0.5),
117 BIP_RANGE(0.2),
118 BIP_RANGE(0.1),
119 UNI_RANGE(10),
120 UNI_RANGE(5),
121 UNI_RANGE(2),
122 UNI_RANGE(1),
123 UNI_RANGE(0.5),
124 UNI_RANGE(0.2),
125 UNI_RANGE(0.1)
126 }
127 };
128
129 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
130 4, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 BIP_RANGE(0.5),
134 BIP_RANGE(0.05)
135 }
136 };
137
138 static const struct comedi_lrange range_ni_E_ai_611x = {
139 8, {
140 BIP_RANGE(50),
141 BIP_RANGE(20),
142 BIP_RANGE(10),
143 BIP_RANGE(5),
144 BIP_RANGE(2),
145 BIP_RANGE(1),
146 BIP_RANGE(0.5),
147 BIP_RANGE(0.2)
148 }
149 };
150
151 static const struct comedi_lrange range_ni_M_ai_622x = {
152 4, {
153 BIP_RANGE(10),
154 BIP_RANGE(5),
155 BIP_RANGE(1),
156 BIP_RANGE(0.2)
157 }
158 };
159
160 static const struct comedi_lrange range_ni_M_ai_628x = {
161 7, {
162 BIP_RANGE(10),
163 BIP_RANGE(5),
164 BIP_RANGE(2),
165 BIP_RANGE(1),
166 BIP_RANGE(0.5),
167 BIP_RANGE(0.2),
168 BIP_RANGE(0.1)
169 }
170 };
171
172 static const struct comedi_lrange range_ni_E_ao_ext = {
173 4, {
174 BIP_RANGE(10),
175 UNI_RANGE(10),
176 RANGE_ext(-1, 1),
177 RANGE_ext(0, 1)
178 }
179 };
180
181 static const struct comedi_lrange *const ni_range_lkup[] = {
182 [ai_gain_16] = &range_ni_E_ai,
183 [ai_gain_8] = &range_ni_E_ai_limited,
184 [ai_gain_14] = &range_ni_E_ai_limited14,
185 [ai_gain_4] = &range_ni_E_ai_bipolar4,
186 [ai_gain_611x] = &range_ni_E_ai_611x,
187 [ai_gain_622x] = &range_ni_M_ai_622x,
188 [ai_gain_628x] = &range_ni_M_ai_628x,
189 [ai_gain_6143] = &range_bipolar5
190 };
191
192 enum aimodes {
193 AIMODE_NONE = 0,
194 AIMODE_HALF_FULL = 1,
195 AIMODE_SCAN = 2,
196 AIMODE_SAMPLE = 3,
197 };
198
199 enum ni_common_subdevices {
200 NI_AI_SUBDEV,
201 NI_AO_SUBDEV,
202 NI_DIO_SUBDEV,
203 NI_8255_DIO_SUBDEV,
204 NI_UNUSED_SUBDEV,
205 NI_CALIBRATION_SUBDEV,
206 NI_EEPROM_SUBDEV,
207 NI_PFI_DIO_SUBDEV,
208 NI_CS5529_CALIBRATION_SUBDEV,
209 NI_SERIAL_SUBDEV,
210 NI_RTSI_SUBDEV,
211 NI_GPCT0_SUBDEV,
212 NI_GPCT1_SUBDEV,
213 NI_FREQ_OUT_SUBDEV,
214 NI_NUM_SUBDEVICES
215 };
216
217 #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x))
218
219 enum timebase_nanoseconds {
220 TIMEBASE_1_NS = 50,
221 TIMEBASE_2_NS = 10000
222 };
223
224 #define SERIAL_DISABLED 0
225 #define SERIAL_600NS 600
226 #define SERIAL_1_2US 1200
227 #define SERIAL_10US 10000
228
229 static const int num_adc_stages_611x = 3;
230
231 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
232 {
233 if (dev->mmio)
234 writel(data, dev->mmio + reg);
235 else
236 outl(data, dev->iobase + reg);
237 }
238
239 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
240 {
241 if (dev->mmio)
242 writew(data, dev->mmio + reg);
243 else
244 outw(data, dev->iobase + reg);
245 }
246
247 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
248 {
249 if (dev->mmio)
250 writeb(data, dev->mmio + reg);
251 else
252 outb(data, dev->iobase + reg);
253 }
254
255 static unsigned int ni_readl(struct comedi_device *dev, int reg)
256 {
257 if (dev->mmio)
258 return readl(dev->mmio + reg);
259
260 return inl(dev->iobase + reg);
261 }
262
263 static unsigned int ni_readw(struct comedi_device *dev, int reg)
264 {
265 if (dev->mmio)
266 return readw(dev->mmio + reg);
267
268 return inw(dev->iobase + reg);
269 }
270
271 static unsigned int ni_readb(struct comedi_device *dev, int reg)
272 {
273 if (dev->mmio)
274 return readb(dev->mmio + reg);
275
276 return inb(dev->iobase + reg);
277 }
278
279 /*
280 * We automatically take advantage of STC registers that can be
281 * read/written directly in the I/O space of the board.
282 *
283 * The AT-MIO and DAQCard devices map the low 8 STC registers to
284 * iobase+reg*2.
285 *
286 * Most PCIMIO devices also map the low 8 STC registers but the
287 * 611x devices map the read registers to iobase+(addr-1)*2.
288 * For now non-windowed STC access is disabled if a PCIMIO device
289 * is detected (devpriv->mite has been initialized).
290 *
291 * The M series devices do not used windowed registers for the
292 * STC registers. The functions below handle the mapping of the
293 * windowed STC registers to the m series register offsets.
294 */
295
296 struct mio_regmap {
297 unsigned int mio_reg;
298 int size;
299 };
300
301 static const struct mio_regmap m_series_stc_write_regmap[] = {
302 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
303 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
304 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
305 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
306 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
307 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
308 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
309 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
310 /*
311 * NISTC_DIO_OUT_REG maps to:
312 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
313 */
314 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
315 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
316 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
317 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
318 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
319 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
320 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
321 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
322 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
323 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
324 [NISTC_G0_MODE_REG] = { 0x134, 2 },
325 [NISTC_G1_MODE_REG] = { 0x136, 2 },
326 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
327 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
328 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
329 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
330 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
331 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
332 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
333 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
334 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
335 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
336 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
337 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
338 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
339 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
340 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
341 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
342 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
343 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
344 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
345 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
346 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
347 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
348 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
349 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
350 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
351 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
352 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
353 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
354 [NISTC_RESET_REG] = { 0x190, 2 },
355 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
356 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
357 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
358 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
359 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
360 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
361 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
362 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
363 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
364 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
365 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
366 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
367 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
368 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
369 };
370
371 static void m_series_stc_write(struct comedi_device *dev,
372 unsigned int data, unsigned int reg)
373 {
374 const struct mio_regmap *regmap;
375
376 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
377 regmap = &m_series_stc_write_regmap[reg];
378 } else {
379 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
380 __func__, reg);
381 return;
382 }
383
384 switch (regmap->size) {
385 case 4:
386 ni_writel(dev, data, regmap->mio_reg);
387 break;
388 case 2:
389 ni_writew(dev, data, regmap->mio_reg);
390 break;
391 default:
392 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
393 __func__, reg);
394 break;
395 }
396 }
397
398 static const struct mio_regmap m_series_stc_read_regmap[] = {
399 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
400 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
401 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
402 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
403 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
404 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
405 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
406 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
407 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
408 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
409 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
410 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
411 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
412 [NISTC_STATUS1_REG] = { 0x136, 2 },
413 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
414 [NISTC_STATUS2_REG] = { 0x13a, 2 },
415 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
416 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
417 };
418
419 static unsigned int m_series_stc_read(struct comedi_device *dev,
420 unsigned int reg)
421 {
422 const struct mio_regmap *regmap;
423
424 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
425 regmap = &m_series_stc_read_regmap[reg];
426 } else {
427 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
428 __func__, reg);
429 return 0;
430 }
431
432 switch (regmap->size) {
433 case 4:
434 return ni_readl(dev, regmap->mio_reg);
435 case 2:
436 return ni_readw(dev, regmap->mio_reg);
437 case 1:
438 return ni_readb(dev, regmap->mio_reg);
439 default:
440 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
441 __func__, reg);
442 return 0;
443 }
444 }
445
446 static void ni_stc_writew(struct comedi_device *dev,
447 unsigned int data, int reg)
448 {
449 struct ni_private *devpriv = dev->private;
450 unsigned long flags;
451
452 if (devpriv->is_m_series) {
453 m_series_stc_write(dev, data, reg);
454 } else {
455 spin_lock_irqsave(&devpriv->window_lock, flags);
456 if (!devpriv->mite && reg < 8) {
457 ni_writew(dev, data, reg * 2);
458 } else {
459 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
460 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
461 }
462 spin_unlock_irqrestore(&devpriv->window_lock, flags);
463 }
464 }
465
466 static void ni_stc_writel(struct comedi_device *dev,
467 unsigned int data, int reg)
468 {
469 struct ni_private *devpriv = dev->private;
470
471 if (devpriv->is_m_series) {
472 m_series_stc_write(dev, data, reg);
473 } else {
474 ni_stc_writew(dev, data >> 16, reg);
475 ni_stc_writew(dev, data & 0xffff, reg + 1);
476 }
477 }
478
479 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482 unsigned long flags;
483 unsigned int val;
484
485 if (devpriv->is_m_series) {
486 val = m_series_stc_read(dev, reg);
487 } else {
488 spin_lock_irqsave(&devpriv->window_lock, flags);
489 if (!devpriv->mite && reg < 8) {
490 val = ni_readw(dev, reg * 2);
491 } else {
492 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
493 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
494 }
495 spin_unlock_irqrestore(&devpriv->window_lock, flags);
496 }
497 return val;
498 }
499
500 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
501 {
502 struct ni_private *devpriv = dev->private;
503 unsigned int val;
504
505 if (devpriv->is_m_series) {
506 val = m_series_stc_read(dev, reg);
507 } else {
508 val = ni_stc_readw(dev, reg) << 16;
509 val |= ni_stc_readw(dev, reg + 1);
510 }
511 return val;
512 }
513
514 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
515 unsigned int bit_mask,
516 unsigned int bit_values)
517 {
518 struct ni_private *devpriv = dev->private;
519 unsigned long flags;
520
521 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
522 switch (reg) {
523 case NISTC_INTA_ENA_REG:
524 devpriv->int_a_enable_reg &= ~bit_mask;
525 devpriv->int_a_enable_reg |= bit_values & bit_mask;
526 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
527 break;
528 case NISTC_INTB_ENA_REG:
529 devpriv->int_b_enable_reg &= ~bit_mask;
530 devpriv->int_b_enable_reg |= bit_values & bit_mask;
531 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
532 break;
533 case NISTC_IO_BIDIR_PIN_REG:
534 devpriv->io_bidirection_pin_reg &= ~bit_mask;
535 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
536 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
537 break;
538 case NI_E_DMA_AI_AO_SEL_REG:
539 devpriv->ai_ao_select_reg &= ~bit_mask;
540 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
541 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
542 break;
543 case NI_E_DMA_G0_G1_SEL_REG:
544 devpriv->g0_g1_select_reg &= ~bit_mask;
545 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
546 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
547 break;
548 case NI_M_CDIO_DMA_SEL_REG:
549 devpriv->cdio_dma_select_reg &= ~bit_mask;
550 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
551 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
552 break;
553 default:
554 dev_err(dev->class_dev, "called with invalid register %d\n",
555 reg);
556 break;
557 }
558 mmiowb();
559 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
560 }
561
562 #ifdef PCIDMA
563
564 /* selects the MITE channel to use for DMA */
565 #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \
566 ((x) == 4) ? 0x3 : \
567 ((x) == 5) ? 0x5 : 0x0)
568
569 /* DMA channel setup */
570 static int ni_request_ai_mite_channel(struct comedi_device *dev)
571 {
572 struct ni_private *devpriv = dev->private;
573 struct mite_channel *mite_chan;
574 unsigned long flags;
575 unsigned int bits;
576
577 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
578 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
579 if (!mite_chan) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581 dev_err(dev->class_dev,
582 "failed to reserve mite dma channel for analog input\n");
583 return -EBUSY;
584 }
585 mite_chan->dir = COMEDI_INPUT;
586 devpriv->ai_mite_chan = mite_chan;
587
588 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
589 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
590 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
591
592 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
593 return 0;
594 }
595
596 static int ni_request_ao_mite_channel(struct comedi_device *dev)
597 {
598 struct ni_private *devpriv = dev->private;
599 struct mite_channel *mite_chan;
600 unsigned long flags;
601 unsigned int bits;
602
603 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
604 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
605 if (!mite_chan) {
606 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
607 dev_err(dev->class_dev,
608 "failed to reserve mite dma channel for analog outut\n");
609 return -EBUSY;
610 }
611 mite_chan->dir = COMEDI_OUTPUT;
612 devpriv->ao_mite_chan = mite_chan;
613
614 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
615 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
616 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
617
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
619 return 0;
620 }
621
622 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
623 unsigned int gpct_index,
624 enum comedi_io_direction direction)
625 {
626 struct ni_private *devpriv = dev->private;
627 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
628 struct mite_channel *mite_chan;
629 unsigned long flags;
630 unsigned int bits;
631
632 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
633 mite_chan = mite_request_channel(devpriv->mite,
634 devpriv->gpct_mite_ring[gpct_index]);
635 if (!mite_chan) {
636 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
637 dev_err(dev->class_dev,
638 "failed to reserve mite dma channel for counter\n");
639 return -EBUSY;
640 }
641 mite_chan->dir = direction;
642 ni_tio_set_mite_channel(counter, mite_chan);
643
644 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
645 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
646 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
647 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
648
649 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
650 return 0;
651 }
652
653 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
654 {
655 struct ni_private *devpriv = dev->private;
656 struct mite_channel *mite_chan;
657 unsigned long flags;
658 unsigned int bits;
659
660 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
661 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
662 if (!mite_chan) {
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
664 dev_err(dev->class_dev,
665 "failed to reserve mite dma channel for correlated digital output\n");
666 return -EBUSY;
667 }
668 mite_chan->dir = COMEDI_OUTPUT;
669 devpriv->cdo_mite_chan = mite_chan;
670
671 /*
672 * XXX just guessing NI_STC_DMA_CHAN_SEL()
673 * returns the right bits, under the assumption the cdio dma
674 * selection works just like ai/ao/gpct.
675 * Definitely works for dma channels 0 and 1.
676 */
677 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
678 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
679 NI_M_CDIO_DMA_SEL_CDO_MASK,
680 NI_M_CDIO_DMA_SEL_CDO(bits));
681
682 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
683 return 0;
684 }
685 #endif /* PCIDMA */
686
687 static void ni_release_ai_mite_channel(struct comedi_device *dev)
688 {
689 #ifdef PCIDMA
690 struct ni_private *devpriv = dev->private;
691 unsigned long flags;
692
693 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
694 if (devpriv->ai_mite_chan) {
695 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
696 NI_E_DMA_AI_SEL_MASK, 0);
697 mite_release_channel(devpriv->ai_mite_chan);
698 devpriv->ai_mite_chan = NULL;
699 }
700 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
701 #endif /* PCIDMA */
702 }
703
704 static void ni_release_ao_mite_channel(struct comedi_device *dev)
705 {
706 #ifdef PCIDMA
707 struct ni_private *devpriv = dev->private;
708 unsigned long flags;
709
710 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
711 if (devpriv->ao_mite_chan) {
712 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
713 NI_E_DMA_AO_SEL_MASK, 0);
714 mite_release_channel(devpriv->ao_mite_chan);
715 devpriv->ao_mite_chan = NULL;
716 }
717 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
718 #endif /* PCIDMA */
719 }
720
721 #ifdef PCIDMA
722 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
723 unsigned int gpct_index)
724 {
725 struct ni_private *devpriv = dev->private;
726 unsigned long flags;
727
728 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
729 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
730 struct mite_channel *mite_chan =
731 devpriv->counter_dev->counters[gpct_index].mite_chan;
732
733 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
734 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
735 ni_tio_set_mite_channel(&devpriv->
736 counter_dev->counters[gpct_index],
737 NULL);
738 mite_release_channel(mite_chan);
739 }
740 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
741 }
742
743 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
744 {
745 struct ni_private *devpriv = dev->private;
746 unsigned long flags;
747
748 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
749 if (devpriv->cdo_mite_chan) {
750 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
751 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
752 mite_release_channel(devpriv->cdo_mite_chan);
753 devpriv->cdo_mite_chan = NULL;
754 }
755 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
756 }
757
758 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
759 unsigned int gpct_index, short enable)
760 {
761 struct ni_private *devpriv = dev->private;
762 unsigned int val = 0;
763 int reg;
764
765 if (devpriv->is_m_series || gpct_index > 1)
766 return;
767
768 /*
769 * e-series boards use the second irq signals to generate
770 * dma requests for their counters
771 */
772 if (gpct_index == 0) {
773 reg = NISTC_INTA2_ENA_REG;
774 if (enable)
775 val = NISTC_INTA_ENA_G0_GATE;
776 } else {
777 reg = NISTC_INTB2_ENA_REG;
778 if (enable)
779 val = NISTC_INTB_ENA_G1_GATE;
780 }
781 ni_stc_writew(dev, val, reg);
782 }
783 #endif /* PCIDMA */
784
785 static void ni_clear_ai_fifo(struct comedi_device *dev)
786 {
787 struct ni_private *devpriv = dev->private;
788 static const int timeout = 10000;
789 int i;
790
791 if (devpriv->is_6143) {
792 /* Flush the 6143 data FIFO */
793 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
794 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
795 /* Wait for complete */
796 for (i = 0; i < timeout; i++) {
797 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
798 break;
799 udelay(1);
800 }
801 if (i == timeout)
802 dev_err(dev->class_dev, "FIFO flush timeout\n");
803 } else {
804 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
805 if (devpriv->is_625x) {
806 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
807 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
808 #if 0
809 /*
810 * The NI example code does 3 convert pulses for 625x
811 * boards, But that appears to be wrong in practice.
812 */
813 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
814 NISTC_AI_CMD1_REG);
815 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
816 NISTC_AI_CMD1_REG);
817 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
818 NISTC_AI_CMD1_REG);
819 #endif
820 }
821 }
822 }
823
824 static inline void ni_ao_win_outw(struct comedi_device *dev,
825 unsigned int data, int addr)
826 {
827 struct ni_private *devpriv = dev->private;
828 unsigned long flags;
829
830 spin_lock_irqsave(&devpriv->window_lock, flags);
831 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
832 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
833 spin_unlock_irqrestore(&devpriv->window_lock, flags);
834 }
835
836 static inline void ni_ao_win_outl(struct comedi_device *dev,
837 unsigned int data, int addr)
838 {
839 struct ni_private *devpriv = dev->private;
840 unsigned long flags;
841
842 spin_lock_irqsave(&devpriv->window_lock, flags);
843 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
844 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
845 spin_unlock_irqrestore(&devpriv->window_lock, flags);
846 }
847
848 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
849 {
850 struct ni_private *devpriv = dev->private;
851 unsigned long flags;
852 unsigned short data;
853
854 spin_lock_irqsave(&devpriv->window_lock, flags);
855 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
856 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
857 spin_unlock_irqrestore(&devpriv->window_lock, flags);
858 return data;
859 }
860
861 /*
862 * ni_set_bits( ) allows different parts of the ni_mio_common driver to
863 * share registers (such as Interrupt_A_Register) without interfering with
864 * each other.
865 *
866 * NOTE: the switch/case statements are optimized out for a constant argument
867 * so this is actually quite fast--- If you must wrap another function around
868 * this make it inline to avoid a large speed penalty.
869 *
870 * value should only be 1 or 0.
871 */
872 static inline void ni_set_bits(struct comedi_device *dev, int reg,
873 unsigned int bits, unsigned int value)
874 {
875 unsigned int bit_values;
876
877 if (value)
878 bit_values = bits;
879 else
880 bit_values = 0;
881 ni_set_bitfield(dev, reg, bits, bit_values);
882 }
883
884 #ifdef PCIDMA
885 static void ni_sync_ai_dma(struct comedi_device *dev)
886 {
887 struct ni_private *devpriv = dev->private;
888 struct comedi_subdevice *s = dev->read_subdev;
889 unsigned long flags;
890
891 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
892 if (devpriv->ai_mite_chan)
893 mite_sync_dma(devpriv->ai_mite_chan, s);
894 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
895 }
896
897 static int ni_ai_drain_dma(struct comedi_device *dev)
898 {
899 struct ni_private *devpriv = dev->private;
900 int i;
901 static const int timeout = 10000;
902 unsigned long flags;
903 int retval = 0;
904
905 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
906 if (devpriv->ai_mite_chan) {
907 for (i = 0; i < timeout; i++) {
908 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
909 NISTC_AI_STATUS1_FIFO_E) &&
910 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
911 break;
912 udelay(5);
913 }
914 if (i == timeout) {
915 dev_err(dev->class_dev, "timed out\n");
916 dev_err(dev->class_dev,
917 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
918 mite_bytes_in_transit(devpriv->ai_mite_chan),
919 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
920 retval = -1;
921 }
922 }
923 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
924
925 ni_sync_ai_dma(dev);
926
927 return retval;
928 }
929
930 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
931 {
932 static const int timeout = 10000;
933 int i;
934
935 for (i = 0; i < timeout; i++) {
936 unsigned short b_status;
937
938 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
939 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
940 break;
941 /*
942 * If we poll too often, the pci bus activity seems
943 * to slow the dma transfer down.
944 */
945 usleep_range(10, 100);
946 }
947 if (i == timeout) {
948 dev_err(dev->class_dev, "timed out waiting for dma load\n");
949 return -EPIPE;
950 }
951 return 0;
952 }
953 #endif /* PCIDMA */
954
955 #ifndef PCIDMA
956
957 static void ni_ao_fifo_load(struct comedi_device *dev,
958 struct comedi_subdevice *s, int n)
959 {
960 struct ni_private *devpriv = dev->private;
961 int i;
962 unsigned short d;
963 unsigned int packed_data;
964
965 for (i = 0; i < n; i++) {
966 comedi_buf_read_samples(s, &d, 1);
967
968 if (devpriv->is_6xxx) {
969 packed_data = d & 0xffff;
970 /* 6711 only has 16 bit wide ao fifo */
971 if (!devpriv->is_6711) {
972 comedi_buf_read_samples(s, &d, 1);
973 i++;
974 packed_data |= (d << 16) & 0xffff0000;
975 }
976 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
977 } else {
978 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
979 }
980 }
981 }
982
983 /*
984 * There's a small problem if the FIFO gets really low and we
985 * don't have the data to fill it. Basically, if after we fill
986 * the FIFO with all the data available, the FIFO is _still_
987 * less than half full, we never clear the interrupt. If the
988 * IRQ is in edge mode, we never get another interrupt, because
989 * this one wasn't cleared. If in level mode, we get flooded
990 * with interrupts that we can't fulfill, because nothing ever
991 * gets put into the buffer.
992 *
993 * This kind of situation is recoverable, but it is easier to
994 * just pretend we had a FIFO underrun, since there is a good
995 * chance it will happen anyway. This is _not_ the case for
996 * RT code, as RT code might purposely be running close to the
997 * metal. Needs to be fixed eventually.
998 */
999 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1000 struct comedi_subdevice *s)
1001 {
1002 const struct ni_board_struct *board = dev->board_ptr;
1003 unsigned int nbytes;
1004 unsigned int nsamples;
1005
1006 nbytes = comedi_buf_read_n_available(s);
1007 if (nbytes == 0) {
1008 s->async->events |= COMEDI_CB_OVERFLOW;
1009 return 0;
1010 }
1011
1012 nsamples = comedi_bytes_to_samples(s, nbytes);
1013 if (nsamples > board->ao_fifo_depth / 2)
1014 nsamples = board->ao_fifo_depth / 2;
1015
1016 ni_ao_fifo_load(dev, s, nsamples);
1017
1018 return 1;
1019 }
1020
1021 static int ni_ao_prep_fifo(struct comedi_device *dev,
1022 struct comedi_subdevice *s)
1023 {
1024 const struct ni_board_struct *board = dev->board_ptr;
1025 struct ni_private *devpriv = dev->private;
1026 unsigned int nbytes;
1027 unsigned int nsamples;
1028
1029 /* reset fifo */
1030 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1031 if (devpriv->is_6xxx)
1032 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1033
1034 /* load some data */
1035 nbytes = comedi_buf_read_n_available(s);
1036 if (nbytes == 0)
1037 return 0;
1038
1039 nsamples = comedi_bytes_to_samples(s, nbytes);
1040 if (nsamples > board->ao_fifo_depth)
1041 nsamples = board->ao_fifo_depth;
1042
1043 ni_ao_fifo_load(dev, s, nsamples);
1044
1045 return nsamples;
1046 }
1047
1048 static void ni_ai_fifo_read(struct comedi_device *dev,
1049 struct comedi_subdevice *s, int n)
1050 {
1051 struct ni_private *devpriv = dev->private;
1052 struct comedi_async *async = s->async;
1053 unsigned int dl;
1054 unsigned short data;
1055 int i;
1056
1057 if (devpriv->is_611x) {
1058 for (i = 0; i < n / 2; i++) {
1059 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060 /* This may get the hi/lo data in the wrong order */
1061 data = (dl >> 16) & 0xffff;
1062 comedi_buf_write_samples(s, &data, 1);
1063 data = dl & 0xffff;
1064 comedi_buf_write_samples(s, &data, 1);
1065 }
1066 /* Check if there's a single sample stuck in the FIFO */
1067 if (n % 2) {
1068 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1069 data = dl & 0xffff;
1070 comedi_buf_write_samples(s, &data, 1);
1071 }
1072 } else if (devpriv->is_6143) {
1073 /*
1074 * This just reads the FIFO assuming the data is present,
1075 * no checks on the FIFO status are performed.
1076 */
1077 for (i = 0; i < n / 2; i++) {
1078 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1079
1080 data = (dl >> 16) & 0xffff;
1081 comedi_buf_write_samples(s, &data, 1);
1082 data = dl & 0xffff;
1083 comedi_buf_write_samples(s, &data, 1);
1084 }
1085 if (n % 2) {
1086 /* Assume there is a single sample stuck in the FIFO */
1087 /* Get stranded sample into FIFO */
1088 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1089 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1090 data = (dl >> 16) & 0xffff;
1091 comedi_buf_write_samples(s, &data, 1);
1092 }
1093 } else {
1094 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1095 dev_err(dev->class_dev,
1096 "bug! ai_fifo_buffer too small\n");
1097 async->events |= COMEDI_CB_ERROR;
1098 return;
1099 }
1100 for (i = 0; i < n; i++) {
1101 devpriv->ai_fifo_buffer[i] =
1102 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1103 }
1104 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1105 }
1106 }
1107
1108 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1109 {
1110 const struct ni_board_struct *board = dev->board_ptr;
1111 struct comedi_subdevice *s = dev->read_subdev;
1112 int n;
1113
1114 n = board->ai_fifo_depth / 2;
1115
1116 ni_ai_fifo_read(dev, s, n);
1117 }
1118 #endif
1119
1120 /* Empties the AI fifo */
1121 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1122 {
1123 struct ni_private *devpriv = dev->private;
1124 struct comedi_subdevice *s = dev->read_subdev;
1125 unsigned int dl;
1126 unsigned short data;
1127 int i;
1128
1129 if (devpriv->is_611x) {
1130 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1131 NISTC_AI_STATUS1_FIFO_E) == 0) {
1132 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1133
1134 /* This may get the hi/lo data in the wrong order */
1135 data = dl >> 16;
1136 comedi_buf_write_samples(s, &data, 1);
1137 data = dl & 0xffff;
1138 comedi_buf_write_samples(s, &data, 1);
1139 }
1140 } else if (devpriv->is_6143) {
1141 i = 0;
1142 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1143 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1144
1145 /* This may get the hi/lo data in the wrong order */
1146 data = dl >> 16;
1147 comedi_buf_write_samples(s, &data, 1);
1148 data = dl & 0xffff;
1149 comedi_buf_write_samples(s, &data, 1);
1150 i += 2;
1151 }
1152 /* Check if stranded sample is present */
1153 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1154 /* Get stranded sample into FIFO */
1155 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1156 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1157 data = (dl >> 16) & 0xffff;
1158 comedi_buf_write_samples(s, &data, 1);
1159 }
1160
1161 } else {
1162 unsigned short fe; /* fifo empty */
1163
1164 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1165 NISTC_AI_STATUS1_FIFO_E;
1166 while (fe == 0) {
1167 for (i = 0;
1168 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1169 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1170 NISTC_AI_STATUS1_FIFO_E;
1171 if (fe)
1172 break;
1173 devpriv->ai_fifo_buffer[i] =
1174 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1175 }
1176 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1177 }
1178 }
1179 }
1180
1181 static void get_last_sample_611x(struct comedi_device *dev)
1182 {
1183 struct ni_private *devpriv = dev->private;
1184 struct comedi_subdevice *s = dev->read_subdev;
1185 unsigned short data;
1186 unsigned int dl;
1187
1188 if (!devpriv->is_611x)
1189 return;
1190
1191 /* Check if there's a single sample stuck in the FIFO */
1192 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1193 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1194 data = dl & 0xffff;
1195 comedi_buf_write_samples(s, &data, 1);
1196 }
1197 }
1198
1199 static void get_last_sample_6143(struct comedi_device *dev)
1200 {
1201 struct ni_private *devpriv = dev->private;
1202 struct comedi_subdevice *s = dev->read_subdev;
1203 unsigned short data;
1204 unsigned int dl;
1205
1206 if (!devpriv->is_6143)
1207 return;
1208
1209 /* Check if there's a single sample stuck in the FIFO */
1210 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1211 /* Get stranded sample into FIFO */
1212 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1213 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1214
1215 /* This may get the hi/lo data in the wrong order */
1216 data = (dl >> 16) & 0xffff;
1217 comedi_buf_write_samples(s, &data, 1);
1218 }
1219 }
1220
1221 static void shutdown_ai_command(struct comedi_device *dev)
1222 {
1223 struct comedi_subdevice *s = dev->read_subdev;
1224
1225 #ifdef PCIDMA
1226 ni_ai_drain_dma(dev);
1227 #endif
1228 ni_handle_fifo_dregs(dev);
1229 get_last_sample_611x(dev);
1230 get_last_sample_6143(dev);
1231
1232 s->async->events |= COMEDI_CB_EOA;
1233 }
1234
1235 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1236 {
1237 struct ni_private *devpriv = dev->private;
1238
1239 if (devpriv->aimode == AIMODE_SCAN) {
1240 #ifdef PCIDMA
1241 static const int timeout = 10;
1242 int i;
1243
1244 for (i = 0; i < timeout; i++) {
1245 ni_sync_ai_dma(dev);
1246 if ((s->async->events & COMEDI_CB_EOS))
1247 break;
1248 udelay(1);
1249 }
1250 #else
1251 ni_handle_fifo_dregs(dev);
1252 s->async->events |= COMEDI_CB_EOS;
1253 #endif
1254 }
1255 /* handle special case of single scan */
1256 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1257 shutdown_ai_command(dev);
1258 }
1259
1260 static void handle_gpct_interrupt(struct comedi_device *dev,
1261 unsigned short counter_index)
1262 {
1263 #ifdef PCIDMA
1264 struct ni_private *devpriv = dev->private;
1265 struct comedi_subdevice *s;
1266
1267 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1268
1269 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1270 s);
1271 comedi_handle_events(dev, s);
1272 #endif
1273 }
1274
1275 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1276 {
1277 unsigned short ack = 0;
1278
1279 if (a_status & NISTC_AI_STATUS1_SC_TC)
1280 ack |= NISTC_INTA_ACK_AI_SC_TC;
1281 if (a_status & NISTC_AI_STATUS1_START1)
1282 ack |= NISTC_INTA_ACK_AI_START1;
1283 if (a_status & NISTC_AI_STATUS1_START)
1284 ack |= NISTC_INTA_ACK_AI_START;
1285 if (a_status & NISTC_AI_STATUS1_STOP)
1286 ack |= NISTC_INTA_ACK_AI_STOP;
1287 if (ack)
1288 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1289 }
1290
1291 static void handle_a_interrupt(struct comedi_device *dev,
1292 struct comedi_subdevice *s,
1293 unsigned short status)
1294 {
1295 struct comedi_cmd *cmd = &s->async->cmd;
1296
1297 /* test for all uncommon interrupt events at the same time */
1298 if (status & (NISTC_AI_STATUS1_ERR |
1299 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1300 if (status == 0xffff) {
1301 dev_err(dev->class_dev, "Card removed?\n");
1302 /*
1303 * We probably aren't even running a command now,
1304 * so it's a good idea to be careful.
1305 */
1306 if (comedi_is_subdevice_running(s))
1307 s->async->events |= COMEDI_CB_ERROR;
1308 return;
1309 }
1310 if (status & NISTC_AI_STATUS1_ERR) {
1311 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1312 status);
1313
1314 shutdown_ai_command(dev);
1315
1316 s->async->events |= COMEDI_CB_ERROR;
1317 if (status & NISTC_AI_STATUS1_OVER)
1318 s->async->events |= COMEDI_CB_OVERFLOW;
1319 return;
1320 }
1321 if (status & NISTC_AI_STATUS1_SC_TC) {
1322 if (cmd->stop_src == TRIG_COUNT)
1323 shutdown_ai_command(dev);
1324 }
1325 }
1326 #ifndef PCIDMA
1327 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1328 int i;
1329 static const int timeout = 10;
1330 /*
1331 * PCMCIA cards (at least 6036) seem to stop producing
1332 * interrupts if we fail to get the fifo less than half
1333 * full, so loop to be sure.
1334 */
1335 for (i = 0; i < timeout; ++i) {
1336 ni_handle_fifo_half_full(dev);
1337 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1338 NISTC_AI_STATUS1_FIFO_HF) == 0)
1339 break;
1340 }
1341 }
1342 #endif /* !PCIDMA */
1343
1344 if (status & NISTC_AI_STATUS1_STOP)
1345 ni_handle_eos(dev, s);
1346 }
1347
1348 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1349 {
1350 unsigned short ack = 0;
1351
1352 if (b_status & NISTC_AO_STATUS1_BC_TC)
1353 ack |= NISTC_INTB_ACK_AO_BC_TC;
1354 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1355 ack |= NISTC_INTB_ACK_AO_ERR;
1356 if (b_status & NISTC_AO_STATUS1_START)
1357 ack |= NISTC_INTB_ACK_AO_START;
1358 if (b_status & NISTC_AO_STATUS1_START1)
1359 ack |= NISTC_INTB_ACK_AO_START1;
1360 if (b_status & NISTC_AO_STATUS1_UC_TC)
1361 ack |= NISTC_INTB_ACK_AO_UC_TC;
1362 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1363 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1364 if (b_status & NISTC_AO_STATUS1_UPDATE)
1365 ack |= NISTC_INTB_ACK_AO_UPDATE;
1366 if (ack)
1367 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1368 }
1369
1370 static void handle_b_interrupt(struct comedi_device *dev,
1371 struct comedi_subdevice *s,
1372 unsigned short b_status)
1373 {
1374 if (b_status == 0xffff)
1375 return;
1376 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1377 dev_err(dev->class_dev,
1378 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1379 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1380 s->async->events |= COMEDI_CB_OVERFLOW;
1381 }
1382
1383 if (s->async->cmd.stop_src != TRIG_NONE &&
1384 b_status & NISTC_AO_STATUS1_BC_TC)
1385 s->async->events |= COMEDI_CB_EOA;
1386
1387 #ifndef PCIDMA
1388 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1389 int ret;
1390
1391 ret = ni_ao_fifo_half_empty(dev, s);
1392 if (!ret) {
1393 dev_err(dev->class_dev, "AO buffer underrun\n");
1394 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1395 NISTC_INTB_ENA_AO_FIFO |
1396 NISTC_INTB_ENA_AO_ERR, 0);
1397 s->async->events |= COMEDI_CB_OVERFLOW;
1398 }
1399 }
1400 #endif
1401 }
1402
1403 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1404 void *data, unsigned int num_bytes,
1405 unsigned int chan_index)
1406 {
1407 struct ni_private *devpriv = dev->private;
1408 struct comedi_async *async = s->async;
1409 struct comedi_cmd *cmd = &async->cmd;
1410 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1411 unsigned short *array = data;
1412 unsigned int *larray = data;
1413 unsigned int i;
1414 #ifdef PCIDMA
1415 __le16 *barray = data;
1416 __le32 *blarray = data;
1417 #endif
1418
1419 for (i = 0; i < nsamples; i++) {
1420 #ifdef PCIDMA
1421 if (s->subdev_flags & SDF_LSAMPL)
1422 larray[i] = le32_to_cpu(blarray[i]);
1423 else
1424 array[i] = le16_to_cpu(barray[i]);
1425 #endif
1426 if (s->subdev_flags & SDF_LSAMPL)
1427 larray[i] += devpriv->ai_offset[chan_index];
1428 else
1429 array[i] += devpriv->ai_offset[chan_index];
1430 chan_index++;
1431 chan_index %= cmd->chanlist_len;
1432 }
1433 }
1434
1435 #ifdef PCIDMA
1436
1437 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1438 {
1439 struct ni_private *devpriv = dev->private;
1440 struct comedi_subdevice *s = dev->read_subdev;
1441 int retval;
1442 unsigned long flags;
1443
1444 retval = ni_request_ai_mite_channel(dev);
1445 if (retval)
1446 return retval;
1447
1448 /* write alloc the entire buffer */
1449 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1450
1451 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1452 if (!devpriv->ai_mite_chan) {
1453 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1454 return -EIO;
1455 }
1456
1457 if (devpriv->is_611x || devpriv->is_6143)
1458 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1459 else if (devpriv->is_628x)
1460 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1461 else
1462 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1463
1464 /*start the MITE */
1465 mite_dma_arm(devpriv->ai_mite_chan);
1466 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1467
1468 return 0;
1469 }
1470
1471 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1472 {
1473 struct ni_private *devpriv = dev->private;
1474 struct comedi_subdevice *s = dev->write_subdev;
1475 int retval;
1476 unsigned long flags;
1477
1478 retval = ni_request_ao_mite_channel(dev);
1479 if (retval)
1480 return retval;
1481
1482 /* read alloc the entire buffer */
1483 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1484
1485 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1486 if (devpriv->ao_mite_chan) {
1487 if (devpriv->is_611x || devpriv->is_6713) {
1488 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1489 } else {
1490 /*
1491 * Doing 32 instead of 16 bit wide transfers from
1492 * memory makes the mite do 32 bit pci transfers,
1493 * doubling pci bandwidth.
1494 */
1495 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1496 }
1497 mite_dma_arm(devpriv->ao_mite_chan);
1498 } else {
1499 retval = -EIO;
1500 }
1501 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1502
1503 return retval;
1504 }
1505
1506 #endif /* PCIDMA */
1507
1508 /*
1509 * used for both cancel ioctl and board initialization
1510 *
1511 * this is pretty harsh for a cancel, but it works...
1512 */
1513 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1514 {
1515 struct ni_private *devpriv = dev->private;
1516 unsigned int ai_personal;
1517 unsigned int ai_out_ctrl;
1518
1519 ni_release_ai_mite_channel(dev);
1520 /* ai configuration */
1521 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1522 NISTC_RESET_REG);
1523
1524 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1525
1526 ni_clear_ai_fifo(dev);
1527
1528 if (!devpriv->is_6143)
1529 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1530
1531 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1532 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1533 NISTC_AI_MODE1_RSVD
1534 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1535 NISTC_AI_MODE1_REG);
1536 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1537 /* generate FIFO interrupts on non-empty */
1538 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1539 NISTC_AI_MODE3_REG);
1540
1541 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1542 NISTC_AI_PERSONAL_SOC_POLARITY |
1543 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1544 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1545 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1546 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1547 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1548 if (devpriv->is_611x) {
1549 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1550 } else if (devpriv->is_6143) {
1551 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1552 } else {
1553 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1554 if (devpriv->is_622x)
1555 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1556 else
1557 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1558 }
1559 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1560 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1561
1562 /* the following registers should not be changed, because there
1563 * are no backup registers in devpriv. If you want to change
1564 * any of these, add a backup register and other appropriate code:
1565 * NISTC_AI_MODE1_REG
1566 * NISTC_AI_MODE3_REG
1567 * NISTC_AI_PERSONAL_REG
1568 * NISTC_AI_OUT_CTRL_REG
1569 */
1570
1571 /* clear interrupts */
1572 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1573
1574 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1575
1576 return 0;
1577 }
1578
1579 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1580 {
1581 unsigned long flags;
1582 int count;
1583
1584 /* lock to avoid race with interrupt handler */
1585 spin_lock_irqsave(&dev->spinlock, flags);
1586 #ifndef PCIDMA
1587 ni_handle_fifo_dregs(dev);
1588 #else
1589 ni_sync_ai_dma(dev);
1590 #endif
1591 count = comedi_buf_n_bytes_ready(s);
1592 spin_unlock_irqrestore(&dev->spinlock, flags);
1593
1594 return count;
1595 }
1596
1597 static void ni_prime_channelgain_list(struct comedi_device *dev)
1598 {
1599 int i;
1600
1601 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1602 for (i = 0; i < NI_TIMEOUT; ++i) {
1603 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1604 NISTC_AI_STATUS1_FIFO_E)) {
1605 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1606 return;
1607 }
1608 udelay(1);
1609 }
1610 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1611 }
1612
1613 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1614 unsigned int n_chan,
1615 unsigned int *list)
1616 {
1617 const struct ni_board_struct *board = dev->board_ptr;
1618 struct ni_private *devpriv = dev->private;
1619 unsigned int chan, range, aref;
1620 unsigned int i;
1621 unsigned int dither;
1622 unsigned int range_code;
1623
1624 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1625
1626 if ((list[0] & CR_ALT_SOURCE)) {
1627 unsigned int bypass_bits;
1628
1629 chan = CR_CHAN(list[0]);
1630 range = CR_RANGE(list[0]);
1631 range_code = ni_gainlkup[board->gainlkup][range];
1632 dither = (list[0] & CR_ALT_FILTER) != 0;
1633 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1634 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1635 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1636 devpriv->ai_calib_source;
1637 if (dither)
1638 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1639 /* don't use 2's complement encoding */
1640 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1641 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1642 } else {
1643 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1644 }
1645 for (i = 0; i < n_chan; i++) {
1646 unsigned int config_bits = 0;
1647
1648 chan = CR_CHAN(list[i]);
1649 aref = CR_AREF(list[i]);
1650 range = CR_RANGE(list[i]);
1651 dither = (list[i] & CR_ALT_FILTER) != 0;
1652
1653 range_code = ni_gainlkup[board->gainlkup][range];
1654 devpriv->ai_offset[i] = 0;
1655 switch (aref) {
1656 case AREF_DIFF:
1657 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1658 break;
1659 case AREF_COMMON:
1660 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1661 break;
1662 case AREF_GROUND:
1663 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1664 break;
1665 case AREF_OTHER:
1666 break;
1667 }
1668 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1669 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1670 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1671 if (i == n_chan - 1)
1672 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1673 if (dither)
1674 config_bits |= NI_M_AI_CFG_DITHER;
1675 /* don't use 2's complement encoding */
1676 config_bits |= NI_M_AI_CFG_POLARITY;
1677 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1678 }
1679 ni_prime_channelgain_list(dev);
1680 }
1681
1682 /*
1683 * Notes on the 6110 and 6111:
1684 * These boards a slightly different than the rest of the series, since
1685 * they have multiple A/D converters.
1686 * From the driver side, the configuration memory is a
1687 * little different.
1688 * Configuration Memory Low:
1689 * bits 15-9: same
1690 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1691 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1692 * 1001 gain=0.1 (+/- 50)
1693 * 1010 0.2
1694 * 1011 0.1
1695 * 0001 1
1696 * 0010 2
1697 * 0011 5
1698 * 0100 10
1699 * 0101 20
1700 * 0110 50
1701 * Configuration Memory High:
1702 * bits 12-14: Channel Type
1703 * 001 for differential
1704 * 000 for calibration
1705 * bit 11: coupling (this is not currently handled)
1706 * 1 AC coupling
1707 * 0 DC coupling
1708 * bits 0-2: channel
1709 * valid channels are 0-3
1710 */
1711 static void ni_load_channelgain_list(struct comedi_device *dev,
1712 struct comedi_subdevice *s,
1713 unsigned int n_chan, unsigned int *list)
1714 {
1715 const struct ni_board_struct *board = dev->board_ptr;
1716 struct ni_private *devpriv = dev->private;
1717 unsigned int offset = (s->maxdata + 1) >> 1;
1718 unsigned int chan, range, aref;
1719 unsigned int i;
1720 unsigned int hi, lo;
1721 unsigned int dither;
1722
1723 if (devpriv->is_m_series) {
1724 ni_m_series_load_channelgain_list(dev, n_chan, list);
1725 return;
1726 }
1727 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1728 if (devpriv->changain_state &&
1729 devpriv->changain_spec == list[0]) {
1730 /* ready to go. */
1731 return;
1732 }
1733 devpriv->changain_state = 1;
1734 devpriv->changain_spec = list[0];
1735 } else {
1736 devpriv->changain_state = 0;
1737 }
1738
1739 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1740
1741 /* Set up Calibration mode if required */
1742 if (devpriv->is_6143) {
1743 if ((list[0] & CR_ALT_SOURCE) &&
1744 !devpriv->ai_calib_source_enabled) {
1745 /* Strobe Relay enable bit */
1746 ni_writew(dev, devpriv->ai_calib_source |
1747 NI6143_CALIB_CHAN_RELAY_ON,
1748 NI6143_CALIB_CHAN_REG);
1749 ni_writew(dev, devpriv->ai_calib_source,
1750 NI6143_CALIB_CHAN_REG);
1751 devpriv->ai_calib_source_enabled = 1;
1752 /* Allow relays to change */
1753 msleep_interruptible(100);
1754 } else if (!(list[0] & CR_ALT_SOURCE) &&
1755 devpriv->ai_calib_source_enabled) {
1756 /* Strobe Relay disable bit */
1757 ni_writew(dev, devpriv->ai_calib_source |
1758 NI6143_CALIB_CHAN_RELAY_OFF,
1759 NI6143_CALIB_CHAN_REG);
1760 ni_writew(dev, devpriv->ai_calib_source,
1761 NI6143_CALIB_CHAN_REG);
1762 devpriv->ai_calib_source_enabled = 0;
1763 /* Allow relays to change */
1764 msleep_interruptible(100);
1765 }
1766 }
1767
1768 for (i = 0; i < n_chan; i++) {
1769 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1770 chan = devpriv->ai_calib_source;
1771 else
1772 chan = CR_CHAN(list[i]);
1773 aref = CR_AREF(list[i]);
1774 range = CR_RANGE(list[i]);
1775 dither = (list[i] & CR_ALT_FILTER) != 0;
1776
1777 /* fix the external/internal range differences */
1778 range = ni_gainlkup[board->gainlkup][range];
1779 if (devpriv->is_611x)
1780 devpriv->ai_offset[i] = offset;
1781 else
1782 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1783
1784 hi = 0;
1785 if ((list[i] & CR_ALT_SOURCE)) {
1786 if (devpriv->is_611x)
1787 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1788 NI611X_CALIB_CHAN_SEL_REG);
1789 } else {
1790 if (devpriv->is_611x)
1791 aref = AREF_DIFF;
1792 else if (devpriv->is_6143)
1793 aref = AREF_OTHER;
1794 switch (aref) {
1795 case AREF_DIFF:
1796 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1797 break;
1798 case AREF_COMMON:
1799 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1800 break;
1801 case AREF_GROUND:
1802 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1803 break;
1804 case AREF_OTHER:
1805 break;
1806 }
1807 }
1808 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1809
1810 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1811
1812 if (!devpriv->is_6143) {
1813 lo = NI_E_AI_CFG_LO_GAIN(range);
1814
1815 if (i == n_chan - 1)
1816 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1817 if (dither)
1818 lo |= NI_E_AI_CFG_LO_DITHER;
1819
1820 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1821 }
1822 }
1823
1824 /* prime the channel/gain list */
1825 if (!devpriv->is_611x && !devpriv->is_6143)
1826 ni_prime_channelgain_list(dev);
1827 }
1828
1829 static int ni_ai_insn_read(struct comedi_device *dev,
1830 struct comedi_subdevice *s,
1831 struct comedi_insn *insn,
1832 unsigned int *data)
1833 {
1834 struct ni_private *devpriv = dev->private;
1835 unsigned int mask = s->maxdata;
1836 int i, n;
1837 unsigned int signbits;
1838 unsigned int d;
1839
1840 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1841
1842 ni_clear_ai_fifo(dev);
1843
1844 signbits = devpriv->ai_offset[0];
1845 if (devpriv->is_611x) {
1846 for (n = 0; n < num_adc_stages_611x; n++) {
1847 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1848 NISTC_AI_CMD1_REG);
1849 udelay(1);
1850 }
1851 for (n = 0; n < insn->n; n++) {
1852 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1853 NISTC_AI_CMD1_REG);
1854 /* The 611x has screwy 32-bit FIFOs. */
1855 d = 0;
1856 for (i = 0; i < NI_TIMEOUT; i++) {
1857 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1858 d = ni_readl(dev,
1859 NI611X_AI_FIFO_DATA_REG);
1860 d >>= 16;
1861 d &= 0xffff;
1862 break;
1863 }
1864 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1865 NISTC_AI_STATUS1_FIFO_E)) {
1866 d = ni_readl(dev,
1867 NI611X_AI_FIFO_DATA_REG);
1868 d &= 0xffff;
1869 break;
1870 }
1871 }
1872 if (i == NI_TIMEOUT) {
1873 dev_err(dev->class_dev, "timeout\n");
1874 return -ETIME;
1875 }
1876 d += signbits;
1877 data[n] = d & 0xffff;
1878 }
1879 } else if (devpriv->is_6143) {
1880 for (n = 0; n < insn->n; n++) {
1881 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1882 NISTC_AI_CMD1_REG);
1883
1884 /*
1885 * The 6143 has 32-bit FIFOs. You need to strobe a
1886 * bit to move a single 16bit stranded sample into
1887 * the FIFO.
1888 */
1889 d = 0;
1890 for (i = 0; i < NI_TIMEOUT; i++) {
1891 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1892 0x01) {
1893 /* Get stranded sample into FIFO */
1894 ni_writel(dev, 0x01,
1895 NI6143_AI_FIFO_CTRL_REG);
1896 d = ni_readl(dev,
1897 NI6143_AI_FIFO_DATA_REG);
1898 break;
1899 }
1900 }
1901 if (i == NI_TIMEOUT) {
1902 dev_err(dev->class_dev, "timeout\n");
1903 return -ETIME;
1904 }
1905 data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1906 }
1907 } else {
1908 for (n = 0; n < insn->n; n++) {
1909 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1910 NISTC_AI_CMD1_REG);
1911 for (i = 0; i < NI_TIMEOUT; i++) {
1912 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1913 NISTC_AI_STATUS1_FIFO_E))
1914 break;
1915 }
1916 if (i == NI_TIMEOUT) {
1917 dev_err(dev->class_dev, "timeout\n");
1918 return -ETIME;
1919 }
1920 if (devpriv->is_m_series) {
1921 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1922 d &= mask;
1923 data[n] = d;
1924 } else {
1925 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1926 d += signbits;
1927 data[n] = d & 0xffff;
1928 }
1929 }
1930 }
1931 return insn->n;
1932 }
1933
1934 static int ni_ns_to_timer(const struct comedi_device *dev,
1935 unsigned int nanosec, unsigned int flags)
1936 {
1937 struct ni_private *devpriv = dev->private;
1938 int divider;
1939
1940 switch (flags & CMDF_ROUND_MASK) {
1941 case CMDF_ROUND_NEAREST:
1942 default:
1943 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1944 break;
1945 case CMDF_ROUND_DOWN:
1946 divider = (nanosec) / devpriv->clock_ns;
1947 break;
1948 case CMDF_ROUND_UP:
1949 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1950 break;
1951 }
1952 return divider - 1;
1953 }
1954
1955 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1956 {
1957 struct ni_private *devpriv = dev->private;
1958
1959 return devpriv->clock_ns * (timer + 1);
1960 }
1961
1962 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1963 struct comedi_subdevice *sdev,
1964 const struct comedi_cmd *cmd,
1965 unsigned int max_count) {
1966 #ifdef PCIDMA
1967 unsigned int nbytes = max_count;
1968
1969 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1970 nbytes = cmd->stop_arg;
1971 nbytes *= comedi_bytes_per_scan(sdev);
1972
1973 if (nbytes > sdev->async->prealloc_bufsz) {
1974 if (cmd->stop_arg > 0)
1975 dev_err(sdev->device->class_dev,
1976 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
1977
1978 /*
1979 * we can only transfer up to the size of the buffer. In this
1980 * case, the user is expected to continue to write into the
1981 * comedi buffer (already implemented as a ring buffer).
1982 */
1983 nbytes = sdev->async->prealloc_bufsz;
1984 }
1985
1986 mite_init_ring_descriptors(ring, sdev, nbytes);
1987 #else
1988 dev_err(sdev->device->class_dev,
1989 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
1990 #endif
1991 }
1992
1993 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1994 unsigned int num_channels)
1995 {
1996 const struct ni_board_struct *board = dev->board_ptr;
1997 struct ni_private *devpriv = dev->private;
1998
1999 /* simultaneously-sampled inputs */
2000 if (devpriv->is_611x || devpriv->is_6143)
2001 return board->ai_speed;
2002
2003 /* multiplexed inputs */
2004 return board->ai_speed * num_channels;
2005 }
2006
2007 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2008 struct comedi_cmd *cmd)
2009 {
2010 const struct ni_board_struct *board = dev->board_ptr;
2011 struct ni_private *devpriv = dev->private;
2012 int err = 0;
2013 unsigned int tmp;
2014 unsigned int sources;
2015
2016 /* Step 1 : check if triggers are trivially valid */
2017
2018 err |= comedi_check_trigger_src(&cmd->start_src,
2019 TRIG_NOW | TRIG_INT | TRIG_EXT);
2020 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2021 TRIG_TIMER | TRIG_EXT);
2022
2023 sources = TRIG_TIMER | TRIG_EXT;
2024 if (devpriv->is_611x || devpriv->is_6143)
2025 sources |= TRIG_NOW;
2026 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2027
2028 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2029 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2030
2031 if (err)
2032 return 1;
2033
2034 /* Step 2a : make sure trigger sources are unique */
2035
2036 err |= comedi_check_trigger_is_unique(cmd->start_src);
2037 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2038 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2039 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2040
2041 /* Step 2b : and mutually compatible */
2042
2043 if (err)
2044 return 2;
2045
2046 /* Step 3: check if arguments are trivially valid */
2047
2048 switch (cmd->start_src) {
2049 case TRIG_NOW:
2050 case TRIG_INT:
2051 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2052 break;
2053 case TRIG_EXT:
2054 tmp = CR_CHAN(cmd->start_arg);
2055
2056 if (tmp > 16)
2057 tmp = 16;
2058 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2059 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2060 break;
2061 }
2062
2063 if (cmd->scan_begin_src == TRIG_TIMER) {
2064 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2065 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2066 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2067 devpriv->clock_ns *
2068 0xffffff);
2069 } else if (cmd->scan_begin_src == TRIG_EXT) {
2070 /* external trigger */
2071 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2072
2073 if (tmp > 16)
2074 tmp = 16;
2075 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2076 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2077 } else { /* TRIG_OTHER */
2078 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2079 }
2080
2081 if (cmd->convert_src == TRIG_TIMER) {
2082 if (devpriv->is_611x || devpriv->is_6143) {
2083 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2084 0);
2085 } else {
2086 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2087 board->ai_speed);
2088 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2089 devpriv->clock_ns *
2090 0xffff);
2091 }
2092 } else if (cmd->convert_src == TRIG_EXT) {
2093 /* external trigger */
2094 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2095
2096 if (tmp > 16)
2097 tmp = 16;
2098 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2099 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2100 } else if (cmd->convert_src == TRIG_NOW) {
2101 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2102 }
2103
2104 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2105 cmd->chanlist_len);
2106
2107 if (cmd->stop_src == TRIG_COUNT) {
2108 unsigned int max_count = 0x01000000;
2109
2110 if (devpriv->is_611x)
2111 max_count -= num_adc_stages_611x;
2112 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2113 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2114 } else {
2115 /* TRIG_NONE */
2116 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2117 }
2118
2119 if (err)
2120 return 3;
2121
2122 /* step 4: fix up any arguments */
2123
2124 if (cmd->scan_begin_src == TRIG_TIMER) {
2125 tmp = cmd->scan_begin_arg;
2126 cmd->scan_begin_arg =
2127 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2128 cmd->scan_begin_arg,
2129 cmd->flags));
2130 if (tmp != cmd->scan_begin_arg)
2131 err++;
2132 }
2133 if (cmd->convert_src == TRIG_TIMER) {
2134 if (!devpriv->is_611x && !devpriv->is_6143) {
2135 tmp = cmd->convert_arg;
2136 cmd->convert_arg =
2137 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2138 cmd->convert_arg,
2139 cmd->flags));
2140 if (tmp != cmd->convert_arg)
2141 err++;
2142 if (cmd->scan_begin_src == TRIG_TIMER &&
2143 cmd->scan_begin_arg <
2144 cmd->convert_arg * cmd->scan_end_arg) {
2145 cmd->scan_begin_arg =
2146 cmd->convert_arg * cmd->scan_end_arg;
2147 err++;
2148 }
2149 }
2150 }
2151
2152 if (err)
2153 return 4;
2154
2155 return 0;
2156 }
2157
2158 static int ni_ai_inttrig(struct comedi_device *dev,
2159 struct comedi_subdevice *s,
2160 unsigned int trig_num)
2161 {
2162 struct ni_private *devpriv = dev->private;
2163 struct comedi_cmd *cmd = &s->async->cmd;
2164
2165 if (trig_num != cmd->start_arg)
2166 return -EINVAL;
2167
2168 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2169 NISTC_AI_CMD2_REG);
2170 s->async->inttrig = NULL;
2171
2172 return 1;
2173 }
2174
2175 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2176 {
2177 struct ni_private *devpriv = dev->private;
2178 const struct comedi_cmd *cmd = &s->async->cmd;
2179 int timer;
2180 int mode1 = 0; /* mode1 is needed for both stop and convert */
2181 int mode2 = 0;
2182 int start_stop_select = 0;
2183 unsigned int stop_count;
2184 int interrupt_a_enable = 0;
2185 unsigned int ai_trig;
2186
2187 if (dev->irq == 0) {
2188 dev_err(dev->class_dev, "cannot run command without an irq\n");
2189 return -EIO;
2190 }
2191 ni_clear_ai_fifo(dev);
2192
2193 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2194
2195 /* start configuration */
2196 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2197
2198 /*
2199 * Disable analog triggering for now, since it interferes
2200 * with the use of pfi0.
2201 */
2202 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2203 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2204
2205 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2206 switch (cmd->start_src) {
2207 case TRIG_INT:
2208 case TRIG_NOW:
2209 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2210 NISTC_AI_TRIG_START1_SEL(0);
2211 break;
2212 case TRIG_EXT:
2213 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2214 1);
2215
2216 if (cmd->start_arg & CR_INVERT)
2217 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2218 if (cmd->start_arg & CR_EDGE)
2219 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2220 break;
2221 }
2222 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2223
2224 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2225 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2226 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2227 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2228
2229 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2230 /* logic low */
2231 start_stop_select |= NISTC_AI_STOP_POLARITY |
2232 NISTC_AI_STOP_SEL(31) |
2233 NISTC_AI_STOP_SYNC;
2234 } else {
2235 /* ai configuration memory */
2236 start_stop_select |= NISTC_AI_STOP_SEL(19);
2237 }
2238 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2239
2240 devpriv->ai_cmd2 = 0;
2241 switch (cmd->stop_src) {
2242 case TRIG_COUNT:
2243 stop_count = cmd->stop_arg - 1;
2244
2245 if (devpriv->is_611x) {
2246 /* have to take 3 stage adc pipeline into account */
2247 stop_count += num_adc_stages_611x;
2248 }
2249 /* stage number of scans */
2250 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2251
2252 mode1 |= NISTC_AI_MODE1_START_STOP |
2253 NISTC_AI_MODE1_RSVD |
2254 NISTC_AI_MODE1_TRIGGER_ONCE;
2255 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2256 /* load SC (Scan Count) */
2257 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2258
2259 if (stop_count == 0) {
2260 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2261 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2262 /*
2263 * This is required to get the last sample for
2264 * chanlist_len > 1, not sure why.
2265 */
2266 if (cmd->chanlist_len > 1)
2267 start_stop_select |= NISTC_AI_STOP_POLARITY |
2268 NISTC_AI_STOP_EDGE;
2269 }
2270 break;
2271 case TRIG_NONE:
2272 /* stage number of scans */
2273 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2274
2275 mode1 |= NISTC_AI_MODE1_START_STOP |
2276 NISTC_AI_MODE1_RSVD |
2277 NISTC_AI_MODE1_CONTINUOUS;
2278 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2279
2280 /* load SC (Scan Count) */
2281 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2282 break;
2283 }
2284
2285 switch (cmd->scan_begin_src) {
2286 case TRIG_TIMER:
2287 /*
2288 * stop bits for non 611x boards
2289 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2290 * NISTC_AI_MODE2_PRE_TRIGGER=0
2291 * NISTC_AI_START_STOP_REG:
2292 * NISTC_AI_START_POLARITY=0 (?) rising edge
2293 * NISTC_AI_START_EDGE=1 edge triggered
2294 * NISTC_AI_START_SYNC=1 (?)
2295 * NISTC_AI_START_SEL=0 SI_TC
2296 * NISTC_AI_STOP_POLARITY=0 rising edge
2297 * NISTC_AI_STOP_EDGE=0 level
2298 * NISTC_AI_STOP_SYNC=1
2299 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2300 */
2301 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2302 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2303
2304 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2305 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2306 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2307 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2308
2309 /* load SI */
2310 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2311 CMDF_ROUND_NEAREST);
2312 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2313 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2314 break;
2315 case TRIG_EXT:
2316 if (cmd->scan_begin_arg & CR_EDGE)
2317 start_stop_select |= NISTC_AI_START_EDGE;
2318 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2319 start_stop_select |= NISTC_AI_START_POLARITY;
2320 if (cmd->scan_begin_src != cmd->convert_src ||
2321 (cmd->scan_begin_arg & ~CR_EDGE) !=
2322 (cmd->convert_arg & ~CR_EDGE))
2323 start_stop_select |= NISTC_AI_START_SYNC;
2324 start_stop_select |=
2325 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2326 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2327 break;
2328 }
2329
2330 switch (cmd->convert_src) {
2331 case TRIG_TIMER:
2332 case TRIG_NOW:
2333 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2334 timer = 1;
2335 else
2336 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2337 CMDF_ROUND_NEAREST);
2338 /* 0,0 does not work */
2339 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2340 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2341
2342 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2343 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2344 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2345
2346 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2347
2348 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2349 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2350 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2351 break;
2352 case TRIG_EXT:
2353 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2354 CR_CHAN(cmd->convert_arg));
2355 if ((cmd->convert_arg & CR_INVERT) == 0)
2356 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2357 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2358
2359 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2360 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2361 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2362
2363 break;
2364 }
2365
2366 if (dev->irq) {
2367 /* interrupt on FIFO, errors, SC_TC */
2368 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2369 NISTC_INTA_ENA_AI_SC_TC;
2370
2371 #ifndef PCIDMA
2372 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2373 #endif
2374
2375 if ((cmd->flags & CMDF_WAKE_EOS) ||
2376 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2377 /* wake on end-of-scan */
2378 devpriv->aimode = AIMODE_SCAN;
2379 } else {
2380 devpriv->aimode = AIMODE_HALF_FULL;
2381 }
2382
2383 switch (devpriv->aimode) {
2384 case AIMODE_HALF_FULL:
2385 /* FIFO interrupts and DMA requests on half-full */
2386 #ifdef PCIDMA
2387 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2388 NISTC_AI_MODE3_REG);
2389 #else
2390 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2391 NISTC_AI_MODE3_REG);
2392 #endif
2393 break;
2394 case AIMODE_SAMPLE:
2395 /*generate FIFO interrupts on non-empty */
2396 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2397 NISTC_AI_MODE3_REG);
2398 break;
2399 case AIMODE_SCAN:
2400 #ifdef PCIDMA
2401 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2402 NISTC_AI_MODE3_REG);
2403 #else
2404 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2405 NISTC_AI_MODE3_REG);
2406 #endif
2407 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2408 break;
2409 default:
2410 break;
2411 }
2412
2413 /* clear interrupts */
2414 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2415
2416 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2417 } else {
2418 /* interrupt on nothing */
2419 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2420
2421 /* XXX start polling if necessary */
2422 }
2423
2424 /* end configuration */
2425 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2426
2427 switch (cmd->scan_begin_src) {
2428 case TRIG_TIMER:
2429 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2430 NISTC_AI_CMD1_SI_ARM |
2431 NISTC_AI_CMD1_DIV_ARM |
2432 NISTC_AI_CMD1_SC_ARM,
2433 NISTC_AI_CMD1_REG);
2434 break;
2435 case TRIG_EXT:
2436 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2437 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2438 NISTC_AI_CMD1_DIV_ARM |
2439 NISTC_AI_CMD1_SC_ARM,
2440 NISTC_AI_CMD1_REG);
2441 break;
2442 }
2443
2444 #ifdef PCIDMA
2445 {
2446 int retval = ni_ai_setup_MITE_dma(dev);
2447
2448 if (retval)
2449 return retval;
2450 }
2451 #endif
2452
2453 if (cmd->start_src == TRIG_NOW) {
2454 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2455 devpriv->ai_cmd2,
2456 NISTC_AI_CMD2_REG);
2457 s->async->inttrig = NULL;
2458 } else if (cmd->start_src == TRIG_EXT) {
2459 s->async->inttrig = NULL;
2460 } else { /* TRIG_INT */
2461 s->async->inttrig = ni_ai_inttrig;
2462 }
2463
2464 return 0;
2465 }
2466
2467 static int ni_ai_insn_config(struct comedi_device *dev,
2468 struct comedi_subdevice *s,
2469 struct comedi_insn *insn, unsigned int *data)
2470 {
2471 struct ni_private *devpriv = dev->private;
2472
2473 if (insn->n < 1)
2474 return -EINVAL;
2475
2476 switch (data[0]) {
2477 case INSN_CONFIG_ALT_SOURCE:
2478 if (devpriv->is_m_series) {
2479 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2480 return -EINVAL;
2481 devpriv->ai_calib_source = data[1];
2482 } else if (devpriv->is_6143) {
2483 unsigned int calib_source;
2484
2485 calib_source = data[1] & 0xf;
2486
2487 devpriv->ai_calib_source = calib_source;
2488 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2489 } else {
2490 unsigned int calib_source;
2491 unsigned int calib_source_adjust;
2492
2493 calib_source = data[1] & 0xf;
2494 calib_source_adjust = (data[1] >> 4) & 0xff;
2495
2496 if (calib_source >= 8)
2497 return -EINVAL;
2498 devpriv->ai_calib_source = calib_source;
2499 if (devpriv->is_611x) {
2500 ni_writeb(dev, calib_source_adjust,
2501 NI611X_CAL_GAIN_SEL_REG);
2502 }
2503 }
2504 return 2;
2505 default:
2506 break;
2507 }
2508
2509 return -EINVAL;
2510 }
2511
2512 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2513 void *data, unsigned int num_bytes,
2514 unsigned int chan_index)
2515 {
2516 struct comedi_cmd *cmd = &s->async->cmd;
2517 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2518 unsigned short *array = data;
2519 unsigned int i;
2520 #ifdef PCIDMA
2521 __le16 buf, *barray = data;
2522 #endif
2523
2524 for (i = 0; i < nsamples; i++) {
2525 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2526 unsigned short val = array[i];
2527
2528 /*
2529 * Munge data from unsigned to two's complement for
2530 * bipolar ranges.
2531 */
2532 if (comedi_range_is_bipolar(s, range))
2533 val = comedi_offset_munge(s, val);
2534 #ifdef PCIDMA
2535 buf = cpu_to_le16(val);
2536 barray[i] = buf;
2537 #else
2538 array[i] = val;
2539 #endif
2540 chan_index++;
2541 chan_index %= cmd->chanlist_len;
2542 }
2543 }
2544
2545 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2546 struct comedi_subdevice *s,
2547 unsigned int chanspec[],
2548 unsigned int n_chans, int timed)
2549 {
2550 struct ni_private *devpriv = dev->private;
2551 unsigned int range;
2552 unsigned int chan;
2553 unsigned int conf;
2554 int i;
2555 int invert = 0;
2556
2557 if (timed) {
2558 for (i = 0; i < s->n_chan; ++i) {
2559 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2560 ni_writeb(dev, devpriv->ao_conf[i],
2561 NI_M_AO_CFG_BANK_REG(i));
2562 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2563 }
2564 }
2565 for (i = 0; i < n_chans; i++) {
2566 const struct comedi_krange *krange;
2567
2568 chan = CR_CHAN(chanspec[i]);
2569 range = CR_RANGE(chanspec[i]);
2570 krange = s->range_table->range + range;
2571 invert = 0;
2572 conf = 0;
2573 switch (krange->max - krange->min) {
2574 case 20000000:
2575 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2576 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2577 break;
2578 case 10000000:
2579 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2580 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2581 break;
2582 case 4000000:
2583 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2584 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2585 NI_M_AO_REF_ATTENUATION_REG(chan));
2586 break;
2587 case 2000000:
2588 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2589 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2590 NI_M_AO_REF_ATTENUATION_REG(chan));
2591 break;
2592 default:
2593 dev_err(dev->class_dev,
2594 "bug! unhandled ao reference voltage\n");
2595 break;
2596 }
2597 switch (krange->max + krange->min) {
2598 case 0:
2599 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2600 break;
2601 case 10000000:
2602 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2603 break;
2604 default:
2605 dev_err(dev->class_dev,
2606 "bug! unhandled ao offset voltage\n");
2607 break;
2608 }
2609 if (timed)
2610 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2611 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2612 devpriv->ao_conf[chan] = conf;
2613 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2614 }
2615 return invert;
2616 }
2617
2618 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2619 struct comedi_subdevice *s,
2620 unsigned int chanspec[],
2621 unsigned int n_chans)
2622 {
2623 struct ni_private *devpriv = dev->private;
2624 unsigned int range;
2625 unsigned int chan;
2626 unsigned int conf;
2627 int i;
2628 int invert = 0;
2629
2630 for (i = 0; i < n_chans; i++) {
2631 chan = CR_CHAN(chanspec[i]);
2632 range = CR_RANGE(chanspec[i]);
2633 conf = NI_E_AO_DACSEL(chan);
2634
2635 if (comedi_range_is_bipolar(s, range)) {
2636 conf |= NI_E_AO_CFG_BIP;
2637 invert = (s->maxdata + 1) >> 1;
2638 } else {
2639 invert = 0;
2640 }
2641 if (comedi_range_is_external(s, range))
2642 conf |= NI_E_AO_EXT_REF;
2643
2644 /* not all boards can deglitch, but this shouldn't hurt */
2645 if (chanspec[i] & CR_DEGLITCH)
2646 conf |= NI_E_AO_DEGLITCH;
2647
2648 /* analog reference */
2649 /* AREF_OTHER connects AO ground to AI ground, i think */
2650 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2651 conf |= NI_E_AO_GROUND_REF;
2652
2653 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2654 devpriv->ao_conf[chan] = conf;
2655 }
2656 return invert;
2657 }
2658
2659 static int ni_ao_config_chanlist(struct comedi_device *dev,
2660 struct comedi_subdevice *s,
2661 unsigned int chanspec[], unsigned int n_chans,
2662 int timed)
2663 {
2664 struct ni_private *devpriv = dev->private;
2665
2666 if (devpriv->is_m_series)
2667 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2668 timed);
2669 else
2670 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2671 }
2672
2673 static int ni_ao_insn_write(struct comedi_device *dev,
2674 struct comedi_subdevice *s,
2675 struct comedi_insn *insn,
2676 unsigned int *data)
2677 {
2678 struct ni_private *devpriv = dev->private;
2679 unsigned int chan = CR_CHAN(insn->chanspec);
2680 unsigned int range = CR_RANGE(insn->chanspec);
2681 int reg;
2682 int i;
2683
2684 if (devpriv->is_6xxx) {
2685 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2686
2687 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2688 } else if (devpriv->is_m_series) {
2689 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2690 } else {
2691 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2692 }
2693
2694 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2695
2696 for (i = 0; i < insn->n; i++) {
2697 unsigned int val = data[i];
2698
2699 s->readback[chan] = val;
2700
2701 if (devpriv->is_6xxx) {
2702 /*
2703 * 6xxx boards have bipolar outputs, munge the
2704 * unsigned comedi values to 2's complement
2705 */
2706 val = comedi_offset_munge(s, val);
2707
2708 ni_ao_win_outw(dev, val, reg);
2709 } else if (devpriv->is_m_series) {
2710 /*
2711 * M-series boards use offset binary values for
2712 * bipolar and uinpolar outputs
2713 */
2714 ni_writew(dev, val, reg);
2715 } else {
2716 /*
2717 * Non-M series boards need two's complement values
2718 * for bipolar ranges.
2719 */
2720 if (comedi_range_is_bipolar(s, range))
2721 val = comedi_offset_munge(s, val);
2722
2723 ni_writew(dev, val, reg);
2724 }
2725 }
2726
2727 return insn->n;
2728 }
2729
2730 /*
2731 * Arms the AO device in preparation for a trigger event.
2732 * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2733 * not used). As a part of this preparation, this function preloads the DAC
2734 * registers with the first values of the output stream. This ensures that the
2735 * first clock cycle after the trigger can be used for output.
2736 *
2737 * Note that this function _must_ happen after a user has written data to the
2738 * output buffers via either mmap or write(fileno,...).
2739 */
2740 static int ni_ao_arm(struct comedi_device *dev,
2741 struct comedi_subdevice *s)
2742 {
2743 struct ni_private *devpriv = dev->private;
2744 int ret;
2745 int interrupt_b_bits;
2746 int i;
2747 static const int timeout = 1000;
2748
2749 /*
2750 * Prevent ao from doing things like trying to allocate the ao dma
2751 * channel multiple times.
2752 */
2753 if (!devpriv->ao_needs_arming) {
2754 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2755 __func__);
2756 return -EINVAL;
2757 }
2758
2759 devpriv->ao_needs_arming = 0;
2760
2761 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2762 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2763 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2764 #ifdef PCIDMA
2765 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2766 if (devpriv->is_6xxx)
2767 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2768 ret = ni_ao_setup_MITE_dma(dev);
2769 if (ret)
2770 return ret;
2771 ret = ni_ao_wait_for_dma_load(dev);
2772 if (ret < 0)
2773 return ret;
2774 #else
2775 ret = ni_ao_prep_fifo(dev, s);
2776 if (ret == 0)
2777 return -EPIPE;
2778
2779 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2780 #endif
2781
2782 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2783 NISTC_AO_MODE3_REG);
2784 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2785 /* wait for DACs to be loaded */
2786 for (i = 0; i < timeout; i++) {
2787 udelay(1);
2788 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2789 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2790 break;
2791 }
2792 if (i == timeout) {
2793 dev_err(dev->class_dev,
2794 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2795 return -EIO;
2796 }
2797 /*
2798 * stc manual says we are need to clear error interrupt after
2799 * AO_TMRDACWRs_In_Progress_St clears
2800 */
2801 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2802
2803 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2804
2805 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2806 NISTC_AO_CMD1_UC_ARM |
2807 NISTC_AO_CMD1_BC_ARM |
2808 devpriv->ao_cmd1,
2809 NISTC_AO_CMD1_REG);
2810
2811 return 0;
2812 }
2813
2814 static int ni_ao_insn_config(struct comedi_device *dev,
2815 struct comedi_subdevice *s,
2816 struct comedi_insn *insn, unsigned int *data)
2817 {
2818 const struct ni_board_struct *board = dev->board_ptr;
2819 struct ni_private *devpriv = dev->private;
2820 unsigned int nbytes;
2821
2822 switch (data[0]) {
2823 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2824 switch (data[1]) {
2825 case COMEDI_OUTPUT:
2826 nbytes = comedi_samples_to_bytes(s,
2827 board->ao_fifo_depth);
2828 data[2] = 1 + nbytes;
2829 if (devpriv->mite)
2830 data[2] += devpriv->mite->fifo_size;
2831 break;
2832 case COMEDI_INPUT:
2833 data[2] = 0;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838 return 0;
2839 case INSN_CONFIG_ARM:
2840 return ni_ao_arm(dev, s);
2841 default:
2842 break;
2843 }
2844
2845 return -EINVAL;
2846 }
2847
2848 static int ni_ao_inttrig(struct comedi_device *dev,
2849 struct comedi_subdevice *s,
2850 unsigned int trig_num)
2851 {
2852 struct ni_private *devpriv = dev->private;
2853 struct comedi_cmd *cmd = &s->async->cmd;
2854 int ret;
2855
2856 /*
2857 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2858 * For backwards compatibility, also allow trig_num == 0 when
2859 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2860 * in that case, the internal trigger is being used as a pre-trigger
2861 * before the external trigger.
2862 */
2863 if (!(trig_num == cmd->start_arg ||
2864 (trig_num == 0 && cmd->start_src != TRIG_INT)))
2865 return -EINVAL;
2866
2867 /*
2868 * Null trig at beginning prevent ao start trigger from executing more
2869 * than once per command.
2870 */
2871 s->async->inttrig = NULL;
2872
2873 if (devpriv->ao_needs_arming) {
2874 /* only arm this device if it still needs arming */
2875 ret = ni_ao_arm(dev, s);
2876 if (ret)
2877 return ret;
2878 }
2879
2880 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2881 NISTC_AO_CMD2_REG);
2882
2883 return 0;
2884 }
2885
2886 /*
2887 * begin ni_ao_cmd.
2888 * Organized similar to NI-STC and MHDDK examples.
2889 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2890 */
2891
2892 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2893 const struct comedi_cmd *cmd)
2894 {
2895 const struct ni_board_struct *board = dev->board_ptr;
2896 unsigned int bits;
2897
2898 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2899
2900 bits =
2901 /* fast CPU interface--only eseries */
2902 /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2903 NISTC_AO_PERSONAL_BC_SRC_SEL |
2904 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2905 /*
2906 * FIXME: start setting following bit when appropriate. Need to
2907 * determine whether board is E4 or E1.
2908 * FROM MHHDK:
2909 * if board is E4 or E1
2910 * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2911 * else
2912 * set it to 1
2913 */
2914 NISTC_AO_PERSONAL_UPDATE_PW |
2915 /* FIXME: when should we set following bit to zero? */
2916 NISTC_AO_PERSONAL_TMRDACWR_PW |
2917 (board->ao_fifo_depth ?
2918 NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2919 ;
2920 #if 0
2921 /*
2922 * FIXME:
2923 * add something like ".has_individual_dacs = 0" to ni_board_struct
2924 * since, as F Hess pointed out, not all in m series have singles. not
2925 * sure if e-series all have duals...
2926 */
2927
2928 /*
2929 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2930 * 6281, verified with bus analyzer.
2931 */
2932 if (devpriv->is_m_series)
2933 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2934 #endif
2935 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2936
2937 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2938 }
2939
2940 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2941 const struct comedi_cmd *cmd)
2942 {
2943 struct ni_private *devpriv = dev->private;
2944 unsigned int trigsel;
2945
2946 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2947
2948 /* sync */
2949 if (cmd->stop_src == TRIG_NONE) {
2950 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2951 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2952 } else {
2953 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2954 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2955 }
2956 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2957
2958 if (cmd->start_src == TRIG_INT) {
2959 trigsel = NISTC_AO_TRIG_START1_EDGE |
2960 NISTC_AO_TRIG_START1_SYNC;
2961 } else { /* TRIG_EXT */
2962 trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2963 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2964 if (cmd->start_arg & CR_INVERT)
2965 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2966 /* 0=edge detection disabled, 1=enabled */
2967 if (cmd->start_arg & CR_EDGE)
2968 trigsel |= NISTC_AO_TRIG_START1_EDGE;
2969 }
2970 ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2971
2972 /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2973
2974 /* sync */
2975 /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2976 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2977 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2978
2979 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2980 }
2981
2982 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2983 const struct comedi_cmd *cmd)
2984 {
2985 struct ni_private *devpriv = dev->private;
2986 /* Not supporting 'waveform staging' or 'local buffer with pauses' */
2987
2988 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2989 /*
2990 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2991 * set_trigger above. It is unclear whether we really need to re-write
2992 * this register with these values. The mhddk examples for e-series
2993 * show writing this in both places, but the examples for m-series show
2994 * a single write in the set_counters function (here).
2995 */
2996 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2997
2998 /* sync (upload number of buffer iterations -1) */
2999 /* indicate that we want to use BC_Load_A_Register as the source */
3000 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3001 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3002
3003 /*
3004 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3005 * ignoring BC_TC, then we will need to find a way to ignore that
3006 * interrupt in continuous mode.
3007 */
3008 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3009
3010 /* sync (issue command to load number of buffer iterations -1) */
3011 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3012
3013 /* sync (upload number of updates in buffer) */
3014 /* indicate that we want to use UC_Load_A_Register as the source */
3015 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3016 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3017
3018 /*
3019 * if a user specifies '0', this automatically assumes the entire 24bit
3020 * address space is available for the (multiple iterations of single
3021 * buffer) MISB. Otherwise, stop_arg specifies the MISB length that
3022 * will be used, regardless of whether we are in continuous mode or not.
3023 * In continuous mode, the output will just iterate indefinitely over
3024 * the MISB.
3025 */
3026 {
3027 unsigned int stop_arg = cmd->stop_arg > 0 ?
3028 (cmd->stop_arg & 0xffffff) : 0xffffff;
3029
3030 if (devpriv->is_m_series) {
3031 /*
3032 * this is how the NI example code does it for m-series
3033 * boards, verified correct with 6259
3034 */
3035 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3036
3037 /* sync (issue cmd to load number of updates in MISB) */
3038 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3039 NISTC_AO_CMD1_REG);
3040 } else {
3041 ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3042
3043 /* sync (issue cmd to load number of updates in MISB) */
3044 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3045 NISTC_AO_CMD1_REG);
3046
3047 /*
3048 * sync (upload number of updates-1 in MISB)
3049 * --eseries only?
3050 */
3051 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3052 }
3053 }
3054
3055 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3056 }
3057
3058 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3059 const struct comedi_cmd *cmd)
3060 {
3061 struct ni_private *devpriv = dev->private;
3062
3063 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3064
3065 /*
3066 * zero out these bit fields to be set below. Does an ao-reset do this
3067 * automatically?
3068 */
3069 devpriv->ao_mode1 &= ~(
3070 NISTC_AO_MODE1_UI_SRC_MASK |
3071 NISTC_AO_MODE1_UI_SRC_POLARITY |
3072 NISTC_AO_MODE1_UPDATE_SRC_MASK |
3073 NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3074 );
3075
3076 if (cmd->scan_begin_src == TRIG_TIMER) {
3077 unsigned int trigvar;
3078
3079 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3080
3081 /*
3082 * NOTE: there are several other ways of configuring internal
3083 * updates, but we'll only support one for now: using
3084 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3085 * START1 and first update, and also w/o local buffer mode w/
3086 * pauses.
3087 */
3088
3089 /*
3090 * This is already done above:
3091 * devpriv->ao_mode1 &= ~(
3092 * // set UPDATE_Source to UI_TC:
3093 * NISTC_AO_MODE1_UPDATE_SRC_MASK |
3094 * // set UPDATE_Source_Polarity to rising (required?)
3095 * NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3096 * // set UI_Source to AO_IN_TIMEBASE1:
3097 * NISTC_AO_MODE1_UI_SRC_MASK |
3098 * // set UI_Source_Polarity to rising (required?)
3099 * NISTC_AO_MODE1_UI_SRC_POLARITY
3100 * );
3101 */
3102
3103 /*
3104 * TODO: use ao_ui_clock_source to allow all possible signals
3105 * to be routed to UI_Source_Select. See tSTC.h for
3106 * eseries/ni67xx and tMSeries.h for mseries.
3107 */
3108
3109 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3110 CMDF_ROUND_NEAREST);
3111
3112 /*
3113 * Wait N TB3 ticks after the start trigger before
3114 * clocking (N must be >=2).
3115 */
3116 /* following line: 2-1 per STC */
3117 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3118 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3119 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3120 } else { /* TRIG_EXT */
3121 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
3122 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3123 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3124 CR_CHAN(cmd->scan_begin_arg));
3125 if (cmd->scan_begin_arg & CR_INVERT)
3126 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3127 }
3128
3129 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3130 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3131 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3132 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3133 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3134
3135 /* Configure DAQ-STC for Timed update mode */
3136 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3137 NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3138 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3139 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3140
3141 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3142 }
3143
3144 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3145 struct comedi_subdevice *s)
3146 {
3147 struct ni_private *devpriv = dev->private;
3148 const struct comedi_cmd *cmd = &s->async->cmd;
3149 unsigned int bits = 0;
3150
3151 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3152
3153 if (devpriv->is_6xxx) {
3154 unsigned int i;
3155
3156 bits = 0;
3157 for (i = 0; i < cmd->chanlist_len; ++i) {
3158 int chan = CR_CHAN(cmd->chanlist[i]);
3159
3160 bits |= 1 << chan;
3161 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3162 }
3163 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3164 }
3165
3166 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3167
3168 if (cmd->scan_end_arg > 1) {
3169 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3170 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3171 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3172
3173 } else {
3174 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3175 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3176 if (devpriv->is_m_series | devpriv->is_6xxx)
3177 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3178 else
3179 bits |= NISTC_AO_OUT_CTRL_CHANS(
3180 CR_CHAN(cmd->chanlist[0]));
3181 }
3182
3183 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3184 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3185
3186 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3187 }
3188
3189 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3190 const struct comedi_cmd *cmd)
3191 {
3192 struct ni_private *devpriv = dev->private;
3193
3194 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3195
3196 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3197 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3198
3199 /*
3200 * Since we are not supporting waveform staging, we ignore these errors:
3201 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3202 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3203 */
3204
3205 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3206 }
3207
3208 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3209 {
3210 struct ni_private *devpriv = dev->private;
3211
3212 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3213
3214 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3215 #ifdef PCIDMA
3216 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3217 #else
3218 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3219 #endif
3220 /* NOTE: this is where use_onboard_memory=True would be implemented */
3221 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3222 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3223
3224 /* enable sending of ao fifo requests (dma request) */
3225 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3226
3227 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3228
3229 /* we are not supporting boards with virtual fifos */
3230 }
3231
3232 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3233 struct comedi_subdevice *s)
3234 {
3235 if (s->async->cmd.stop_src == TRIG_COUNT)
3236 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3237 NISTC_INTB_ENA_AO_BC_TC, 1);
3238
3239 s->async->inttrig = ni_ao_inttrig;
3240 }
3241
3242 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3243 {
3244 struct ni_private *devpriv = dev->private;
3245 const struct comedi_cmd *cmd = &s->async->cmd;
3246
3247 if (dev->irq == 0) {
3248 dev_err(dev->class_dev, "cannot run command without an irq");
3249 return -EIO;
3250 }
3251
3252 /* ni_ao_reset should have already been done */
3253 ni_ao_cmd_personalize(dev, cmd);
3254 /* clearing fifo and preload happens elsewhere */
3255
3256 ni_ao_cmd_set_trigger(dev, cmd);
3257 ni_ao_cmd_set_counters(dev, cmd);
3258 ni_ao_cmd_set_update(dev, cmd);
3259 ni_ao_cmd_set_channels(dev, s);
3260 ni_ao_cmd_set_stop_conditions(dev, cmd);
3261 ni_ao_cmd_set_fifo_mode(dev);
3262 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3263 ni_ao_cmd_set_interrupts(dev, s);
3264
3265 /*
3266 * arm(ing) must happen later so that DMA can be setup and DACs
3267 * preloaded with the actual output buffer before starting.
3268 *
3269 * start(ing) must happen _after_ arming is completed. Starting can be
3270 * done either via ni_ao_inttrig, or via an external trigger.
3271 *
3272 * **Currently, ni_ao_inttrig will automatically attempt a call to
3273 * ni_ao_arm if the device still needs arming at that point. This
3274 * allows backwards compatibility.
3275 */
3276 devpriv->ao_needs_arming = 1;
3277 return 0;
3278 }
3279
3280 /* end ni_ao_cmd */
3281
3282 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3283 struct comedi_cmd *cmd)
3284 {
3285 const struct ni_board_struct *board = dev->board_ptr;
3286 struct ni_private *devpriv = dev->private;
3287 int err = 0;
3288 unsigned int tmp;
3289
3290 /* Step 1 : check if triggers are trivially valid */
3291
3292 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3293 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3294 TRIG_TIMER | TRIG_EXT);
3295 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3296 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3297 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3298
3299 if (err)
3300 return 1;
3301
3302 /* Step 2a : make sure trigger sources are unique */
3303
3304 err |= comedi_check_trigger_is_unique(cmd->start_src);
3305 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3306 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3307
3308 /* Step 2b : and mutually compatible */
3309
3310 if (err)
3311 return 2;
3312
3313 /* Step 3: check if arguments are trivially valid */
3314
3315 switch (cmd->start_src) {
3316 case TRIG_INT:
3317 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3318 break;
3319 case TRIG_EXT:
3320 tmp = CR_CHAN(cmd->start_arg);
3321
3322 if (tmp > 18)
3323 tmp = 18;
3324 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3325 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3326 break;
3327 }
3328
3329 if (cmd->scan_begin_src == TRIG_TIMER) {
3330 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3331 board->ao_speed);
3332 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3333 devpriv->clock_ns *
3334 0xffffff);
3335 }
3336
3337 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3338 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3339 cmd->chanlist_len);
3340 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3341
3342 if (err)
3343 return 3;
3344
3345 /* step 4: fix up any arguments */
3346 if (cmd->scan_begin_src == TRIG_TIMER) {
3347 tmp = cmd->scan_begin_arg;
3348 cmd->scan_begin_arg =
3349 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3350 cmd->scan_begin_arg,
3351 cmd->flags));
3352 if (tmp != cmd->scan_begin_arg)
3353 err++;
3354 }
3355 if (err)
3356 return 4;
3357
3358 return 0;
3359 }
3360
3361 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3362 {
3363 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3364
3365 /*
3366 * In the following, the "--sync" comments are meant to denote
3367 * asynchronous boundaries for setting the registers as described in the
3368 * DAQ-STC mostly in the order also described in the DAQ-STC.
3369 */
3370
3371 struct ni_private *devpriv = dev->private;
3372
3373 ni_release_ao_mite_channel(dev);
3374
3375 /* --sync (reset AO) */
3376 if (devpriv->is_m_series)
3377 /* following example in mhddk for m-series */
3378 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3379
3380 /*--sync (start config) */
3381 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3382
3383 /*--sync (Disarm) */
3384 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3385
3386 /*
3387 * --sync
3388 * (clear bunch of registers--mseries mhddk examples do not include
3389 * this)
3390 */
3391 devpriv->ao_cmd1 = 0;
3392 devpriv->ao_cmd2 = 0;
3393 devpriv->ao_mode1 = 0;
3394 devpriv->ao_mode2 = 0;
3395 if (devpriv->is_m_series)
3396 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3397 else
3398 devpriv->ao_mode3 = 0;
3399
3400 ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3401 ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3402 ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3403 ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3404 ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3405 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3406 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3407 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3408 ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3409
3410 /*--sync (disable interrupts) */
3411 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3412
3413 /*--sync (ack) */
3414 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3415 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3416
3417 /*--not in DAQ-STC. which doc? */
3418 if (devpriv->is_6xxx) {
3419 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3420 NI671X_AO_IMMEDIATE_REG);
3421 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3422 NI611X_AO_MISC_REG);
3423 }
3424 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3425 /*--end */
3426
3427 return 0;
3428 }
3429
3430 /* digital io */
3431
3432 static int ni_dio_insn_config(struct comedi_device *dev,
3433 struct comedi_subdevice *s,
3434 struct comedi_insn *insn,
3435 unsigned int *data)
3436 {
3437 struct ni_private *devpriv = dev->private;
3438 int ret;
3439
3440 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3441 if (ret)
3442 return ret;
3443
3444 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3445 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3446 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3447
3448 return insn->n;
3449 }
3450
3451 static int ni_dio_insn_bits(struct comedi_device *dev,
3452 struct comedi_subdevice *s,
3453 struct comedi_insn *insn,
3454 unsigned int *data)
3455 {
3456 struct ni_private *devpriv = dev->private;
3457
3458 /* Make sure we're not using the serial part of the dio */
3459 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3460 devpriv->serial_interval_ns)
3461 return -EBUSY;
3462
3463 if (comedi_dio_update_state(s, data)) {
3464 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3465 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3466 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3467 }
3468
3469 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3470
3471 return insn->n;
3472 }
3473
3474 #ifdef PCIDMA
3475 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3476 struct comedi_subdevice *s,
3477 struct comedi_insn *insn,
3478 unsigned int *data)
3479 {
3480 int ret;
3481
3482 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3483 if (ret)
3484 return ret;
3485
3486 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3487
3488 return insn->n;
3489 }
3490
3491 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3492 struct comedi_subdevice *s,
3493 struct comedi_insn *insn,
3494 unsigned int *data)
3495 {
3496 if (comedi_dio_update_state(s, data))
3497 ni_writel(dev, s->state, NI_M_DIO_REG);
3498
3499 data[1] = ni_readl(dev, NI_M_DIO_REG);
3500
3501 return insn->n;
3502 }
3503
3504 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3505 struct comedi_subdevice *s,
3506 struct comedi_cmd *cmd)
3507 {
3508 int i;
3509
3510 for (i = 0; i < cmd->chanlist_len; ++i) {
3511 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3512
3513 if (chan != i)
3514 return -EINVAL;
3515 }
3516
3517 return 0;
3518 }
3519
3520 static int ni_cdio_cmdtest(struct comedi_device *dev,
3521 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3522 {
3523 int err = 0;
3524 int tmp;
3525
3526 /* Step 1 : check if triggers are trivially valid */
3527
3528 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3529 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3530 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3531 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3532 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3533
3534 if (err)
3535 return 1;
3536
3537 /* Step 2a : make sure trigger sources are unique */
3538 /* Step 2b : and mutually compatible */
3539
3540 /* Step 3: check if arguments are trivially valid */
3541
3542 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3543
3544 tmp = cmd->scan_begin_arg;
3545 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3546 if (tmp != cmd->scan_begin_arg)
3547 err |= -EINVAL;
3548
3549 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3550 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3551 cmd->chanlist_len);
3552 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3553 s->async->prealloc_bufsz /
3554 comedi_bytes_per_scan(s));
3555
3556 if (err)
3557 return 3;
3558
3559 /* Step 4: fix up any arguments */
3560
3561 /* Step 5: check channel list if it exists */
3562
3563 if (cmd->chanlist && cmd->chanlist_len > 0)
3564 err |= ni_cdio_check_chanlist(dev, s, cmd);
3565
3566 if (err)
3567 return 5;
3568
3569 return 0;
3570 }
3571
3572 static int ni_cdo_inttrig(struct comedi_device *dev,
3573 struct comedi_subdevice *s,
3574 unsigned int trig_num)
3575 {
3576 struct comedi_cmd *cmd = &s->async->cmd;
3577 const unsigned int timeout = 1000;
3578 int retval = 0;
3579 unsigned int i;
3580 struct ni_private *devpriv = dev->private;
3581 unsigned long flags;
3582
3583 if (trig_num != cmd->start_arg)
3584 return -EINVAL;
3585
3586 s->async->inttrig = NULL;
3587
3588 /* read alloc the entire buffer */
3589 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3590
3591 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3592 if (devpriv->cdo_mite_chan) {
3593 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3594 mite_dma_arm(devpriv->cdo_mite_chan);
3595 } else {
3596 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3597 retval = -EIO;
3598 }
3599 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3600 if (retval < 0)
3601 return retval;
3602
3603 /*
3604 * XXX not sure what interrupt C group does
3605 * wait for dma to fill output fifo
3606 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3607 */
3608 for (i = 0; i < timeout; ++i) {
3609 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3610 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3611 break;
3612 usleep_range(10, 100);
3613 }
3614 if (i == timeout) {
3615 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3616 s->cancel(dev, s);
3617 return -EIO;
3618 }
3619 ni_writel(dev, NI_M_CDO_CMD_ARM |
3620 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3621 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3622 NI_M_CDIO_CMD_REG);
3623 return retval;
3624 }
3625
3626 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3627 {
3628 struct ni_private *devpriv = dev->private;
3629 const struct comedi_cmd *cmd = &s->async->cmd;
3630 unsigned int cdo_mode_bits;
3631 int retval;
3632
3633 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3634 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3635 NI_M_CDO_MODE_HALT_ON_ERROR |
3636 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3637 if (cmd->scan_begin_arg & CR_INVERT)
3638 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3639 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3640 if (s->io_bits) {
3641 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3642 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3643 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3644 } else {
3645 dev_err(dev->class_dev,
3646 "attempted to run digital output command with no lines configured as outputs\n");
3647 return -EIO;
3648 }
3649 retval = ni_request_cdo_mite_channel(dev);
3650 if (retval < 0)
3651 return retval;
3652
3653 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3654 s->async->prealloc_bufsz /
3655 comedi_bytes_per_scan(s));
3656
3657 s->async->inttrig = ni_cdo_inttrig;
3658
3659 return 0;
3660 }
3661
3662 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3663 {
3664 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3665 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3666 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3667 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3668 NI_M_CDIO_CMD_REG);
3669 /*
3670 * XXX not sure what interrupt C group does
3671 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3672 */
3673 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3674 ni_release_cdo_mite_channel(dev);
3675 return 0;
3676 }
3677
3678 static void handle_cdio_interrupt(struct comedi_device *dev)
3679 {
3680 struct ni_private *devpriv = dev->private;
3681 unsigned int cdio_status;
3682 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3683 unsigned long flags;
3684
3685 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3686 if (devpriv->cdo_mite_chan)
3687 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3688 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3689
3690 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3691 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3692 /* XXX just guessing this is needed and does something useful */
3693 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3694 NI_M_CDIO_CMD_REG);
3695 s->async->events |= COMEDI_CB_OVERFLOW;
3696 }
3697 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3698 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3699 NI_M_CDIO_CMD_REG);
3700 /* s->async->events |= COMEDI_CB_EOA; */
3701 }
3702 comedi_handle_events(dev, s);
3703 }
3704 #endif /* PCIDMA */
3705
3706 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3707 struct comedi_subdevice *s,
3708 unsigned char data_out,
3709 unsigned char *data_in)
3710 {
3711 struct ni_private *devpriv = dev->private;
3712 unsigned int status1;
3713 int err = 0, count = 20;
3714
3715 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3716 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3717 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3718
3719 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3720 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3721 err = -EBUSY;
3722 goto error;
3723 }
3724
3725 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3726 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3727 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3728
3729 /* Wait until STC says we're done, but don't loop infinitely. */
3730 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3731 NISTC_STATUS1_SERIO_IN_PROG) {
3732 /* Delay one bit per loop */
3733 udelay((devpriv->serial_interval_ns + 999) / 1000);
3734 if (--count < 0) {
3735 dev_err(dev->class_dev,
3736 "SPI serial I/O didn't finish in time!\n");
3737 err = -ETIME;
3738 goto error;
3739 }
3740 }
3741
3742 /*
3743 * Delay for last bit. This delay is absolutely necessary, because
3744 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3745 */
3746 udelay((devpriv->serial_interval_ns + 999) / 1000);
3747
3748 if (data_in)
3749 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3750
3751 error:
3752 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3753
3754 return err;
3755 }
3756
3757 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3758 struct comedi_subdevice *s,
3759 unsigned char data_out,
3760 unsigned char *data_in)
3761 {
3762 struct ni_private *devpriv = dev->private;
3763 unsigned char mask, input = 0;
3764
3765 /* Wait for one bit before transfer */
3766 udelay((devpriv->serial_interval_ns + 999) / 1000);
3767
3768 for (mask = 0x80; mask; mask >>= 1) {
3769 /*
3770 * Output current bit; note that we cannot touch s->state
3771 * because it is a per-subdevice field, and serial is
3772 * a separate subdevice from DIO.
3773 */
3774 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3775 if (data_out & mask)
3776 devpriv->dio_output |= NISTC_DIO_SDOUT;
3777 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3778
3779 /*
3780 * Assert SDCLK (active low, inverted), wait for half of
3781 * the delay, deassert SDCLK, and wait for the other half.
3782 */
3783 devpriv->dio_control |= NISTC_DIO_SDCLK;
3784 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3785
3786 udelay((devpriv->serial_interval_ns + 999) / 2000);
3787
3788 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3789 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3790
3791 udelay((devpriv->serial_interval_ns + 999) / 2000);
3792
3793 /* Input current bit */
3794 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3795 input |= mask;
3796 }
3797
3798 if (data_in)
3799 *data_in = input;
3800
3801 return 0;
3802 }
3803
3804 static int ni_serial_insn_config(struct comedi_device *dev,
3805 struct comedi_subdevice *s,
3806 struct comedi_insn *insn,
3807 unsigned int *data)
3808 {
3809 struct ni_private *devpriv = dev->private;
3810 unsigned int clk_fout = devpriv->clock_and_fout;
3811 int err = insn->n;
3812 unsigned char byte_out, byte_in = 0;
3813
3814 if (insn->n != 2)
3815 return -EINVAL;
3816
3817 switch (data[0]) {
3818 case INSN_CONFIG_SERIAL_CLOCK:
3819 devpriv->serial_hw_mode = 1;
3820 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3821
3822 if (data[1] == SERIAL_DISABLED) {
3823 devpriv->serial_hw_mode = 0;
3824 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3825 NISTC_DIO_SDCLK);
3826 data[1] = SERIAL_DISABLED;
3827 devpriv->serial_interval_ns = data[1];
3828 } else if (data[1] <= SERIAL_600NS) {
3829 /*
3830 * Warning: this clock speed is too fast to reliably
3831 * control SCXI.
3832 */
3833 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3834 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3835 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3836 data[1] = SERIAL_600NS;
3837 devpriv->serial_interval_ns = data[1];
3838 } else if (data[1] <= SERIAL_1_2US) {
3839 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3840 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3841 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3842 data[1] = SERIAL_1_2US;
3843 devpriv->serial_interval_ns = data[1];
3844 } else if (data[1] <= SERIAL_10US) {
3845 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3846 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3847 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3848 /*
3849 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3850 * 600ns/1.2us. If you turn divide_by_2 off with the
3851 * slow clock, you will still get 10us, except then
3852 * all your delays are wrong.
3853 */
3854 data[1] = SERIAL_10US;
3855 devpriv->serial_interval_ns = data[1];
3856 } else {
3857 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3858 NISTC_DIO_SDCLK);
3859 devpriv->serial_hw_mode = 0;
3860 data[1] = (data[1] / 1000) * 1000;
3861 devpriv->serial_interval_ns = data[1];
3862 }
3863 devpriv->clock_and_fout = clk_fout;
3864
3865 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3866 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3867 return 1;
3868
3869 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3870
3871 if (devpriv->serial_interval_ns == 0)
3872 return -EINVAL;
3873
3874 byte_out = data[1] & 0xFF;
3875
3876 if (devpriv->serial_hw_mode) {
3877 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3878 &byte_in);
3879 } else if (devpriv->serial_interval_ns > 0) {
3880 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3881 &byte_in);
3882 } else {
3883 dev_err(dev->class_dev, "serial disabled!\n");
3884 return -EINVAL;
3885 }
3886 if (err < 0)
3887 return err;
3888 data[1] = byte_in & 0xFF;
3889 return insn->n;
3890
3891 break;
3892 default:
3893 return -EINVAL;
3894 }
3895 }
3896
3897 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3898 {
3899 int i;
3900
3901 for (i = 0; i < s->n_chan; i++) {
3902 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3903 NI67XX_AO_CFG2_REG);
3904 }
3905 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3906 }
3907
3908 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3909 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3910 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3911 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3912 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3913 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3914 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3915 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3916 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3917 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3918 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3919 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3920 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3921 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3922 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3923 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3924 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3925 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3926 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3927 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3928 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3929 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3930 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3931 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3932 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3933 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3934 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3935 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3936 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3937 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3938 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3939 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3940 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3941 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3942 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3943 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3944 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3945 };
3946
3947 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3948 enum ni_gpct_register reg)
3949 {
3950 const struct mio_regmap *regmap;
3951
3952 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3953 regmap = &ni_gpct_to_stc_regmap[reg];
3954 } else {
3955 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3956 __func__, reg);
3957 return 0;
3958 }
3959
3960 return regmap->mio_reg;
3961 }
3962
3963 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3964 enum ni_gpct_register reg)
3965 {
3966 struct comedi_device *dev = counter->counter_dev->dev;
3967 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3968
3969 if (stc_register == 0)
3970 return;
3971
3972 switch (reg) {
3973 /* m-series only registers */
3974 case NITIO_G0_CNT_MODE:
3975 case NITIO_G1_CNT_MODE:
3976 case NITIO_G0_GATE2:
3977 case NITIO_G1_GATE2:
3978 case NITIO_G0_DMA_CFG:
3979 case NITIO_G1_DMA_CFG:
3980 case NITIO_G0_ABZ:
3981 case NITIO_G1_ABZ:
3982 ni_writew(dev, bits, stc_register);
3983 break;
3984
3985 /* 32 bit registers */
3986 case NITIO_G0_LOADA:
3987 case NITIO_G1_LOADA:
3988 case NITIO_G0_LOADB:
3989 case NITIO_G1_LOADB:
3990 ni_stc_writel(dev, bits, stc_register);
3991 break;
3992
3993 /* 16 bit registers */
3994 case NITIO_G0_INT_ENA:
3995 ni_set_bitfield(dev, stc_register,
3996 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3997 bits);
3998 break;
3999 case NITIO_G1_INT_ENA:
4000 ni_set_bitfield(dev, stc_register,
4001 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4002 bits);
4003 break;
4004 default:
4005 ni_stc_writew(dev, bits, stc_register);
4006 }
4007 }
4008
4009 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4010 enum ni_gpct_register reg)
4011 {
4012 struct comedi_device *dev = counter->counter_dev->dev;
4013 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4014
4015 if (stc_register == 0)
4016 return 0;
4017
4018 switch (reg) {
4019 /* m-series only registers */
4020 case NITIO_G0_DMA_STATUS:
4021 case NITIO_G1_DMA_STATUS:
4022 return ni_readw(dev, stc_register);
4023
4024 /* 32 bit registers */
4025 case NITIO_G0_HW_SAVE:
4026 case NITIO_G1_HW_SAVE:
4027 case NITIO_G0_SW_SAVE:
4028 case NITIO_G1_SW_SAVE:
4029 return ni_stc_readl(dev, stc_register);
4030
4031 /* 16 bit registers */
4032 default:
4033 return ni_stc_readw(dev, stc_register);
4034 }
4035 }
4036
4037 static int ni_freq_out_insn_read(struct comedi_device *dev,
4038 struct comedi_subdevice *s,
4039 struct comedi_insn *insn,
4040 unsigned int *data)
4041 {
4042 struct ni_private *devpriv = dev->private;
4043 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4044 int i;
4045
4046 for (i = 0; i < insn->n; i++)
4047 data[i] = val;
4048
4049 return insn->n;
4050 }
4051
4052 static int ni_freq_out_insn_write(struct comedi_device *dev,
4053 struct comedi_subdevice *s,
4054 struct comedi_insn *insn,
4055 unsigned int *data)
4056 {
4057 struct ni_private *devpriv = dev->private;
4058
4059 if (insn->n) {
4060 unsigned int val = data[insn->n - 1];
4061
4062 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4063 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4064 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4065
4066 /* use the last data value to set the fout divider */
4067 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4068
4069 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4070 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4071 }
4072 return insn->n;
4073 }
4074
4075 static int ni_freq_out_insn_config(struct comedi_device *dev,
4076 struct comedi_subdevice *s,
4077 struct comedi_insn *insn,
4078 unsigned int *data)
4079 {
4080 struct ni_private *devpriv = dev->private;
4081
4082 switch (data[0]) {
4083 case INSN_CONFIG_SET_CLOCK_SRC:
4084 switch (data[1]) {
4085 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4086 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4087 break;
4088 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4089 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4090 break;
4091 default:
4092 return -EINVAL;
4093 }
4094 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4095 break;
4096 case INSN_CONFIG_GET_CLOCK_SRC:
4097 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4098 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4099 data[2] = TIMEBASE_2_NS;
4100 } else {
4101 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4102 data[2] = TIMEBASE_1_NS * 2;
4103 }
4104 break;
4105 default:
4106 return -EINVAL;
4107 }
4108 return insn->n;
4109 }
4110
4111 static int ni_8255_callback(struct comedi_device *dev,
4112 int dir, int port, int data, unsigned long iobase)
4113 {
4114 if (dir) {
4115 ni_writeb(dev, data, iobase + 2 * port);
4116 return 0;
4117 }
4118
4119 return ni_readb(dev, iobase + 2 * port);
4120 }
4121
4122 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4123 {
4124 struct ni_private *devpriv = dev->private;
4125
4126 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4127 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4128 return 3;
4129 }
4130
4131 static int ni_m_series_pwm_config(struct comedi_device *dev,
4132 struct comedi_subdevice *s,
4133 struct comedi_insn *insn,
4134 unsigned int *data)
4135 {
4136 struct ni_private *devpriv = dev->private;
4137 unsigned int up_count, down_count;
4138
4139 switch (data[0]) {
4140 case INSN_CONFIG_PWM_OUTPUT:
4141 switch (data[1]) {
4142 case CMDF_ROUND_NEAREST:
4143 up_count = DIV_ROUND_CLOSEST(data[2],
4144 devpriv->clock_ns);
4145 break;
4146 case CMDF_ROUND_DOWN:
4147 up_count = data[2] / devpriv->clock_ns;
4148 break;
4149 case CMDF_ROUND_UP:
4150 up_count =
4151 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4152 break;
4153 default:
4154 return -EINVAL;
4155 }
4156 switch (data[3]) {
4157 case CMDF_ROUND_NEAREST:
4158 down_count = DIV_ROUND_CLOSEST(data[4],
4159 devpriv->clock_ns);
4160 break;
4161 case CMDF_ROUND_DOWN:
4162 down_count = data[4] / devpriv->clock_ns;
4163 break;
4164 case CMDF_ROUND_UP:
4165 down_count =
4166 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4167 break;
4168 default:
4169 return -EINVAL;
4170 }
4171 if (up_count * devpriv->clock_ns != data[2] ||
4172 down_count * devpriv->clock_ns != data[4]) {
4173 data[2] = up_count * devpriv->clock_ns;
4174 data[4] = down_count * devpriv->clock_ns;
4175 return -EAGAIN;
4176 }
4177 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4178 NI_M_CAL_PWM_LOW_TIME(down_count),
4179 NI_M_CAL_PWM_REG);
4180 devpriv->pwm_up_count = up_count;
4181 devpriv->pwm_down_count = down_count;
4182 return 5;
4183 case INSN_CONFIG_GET_PWM_OUTPUT:
4184 return ni_get_pwm_config(dev, data);
4185 default:
4186 return -EINVAL;
4187 }
4188 return 0;
4189 }
4190
4191 static int ni_6143_pwm_config(struct comedi_device *dev,
4192 struct comedi_subdevice *s,
4193 struct comedi_insn *insn,
4194 unsigned int *data)
4195 {
4196 struct ni_private *devpriv = dev->private;
4197 unsigned int up_count, down_count;
4198
4199 switch (data[0]) {
4200 case INSN_CONFIG_PWM_OUTPUT:
4201 switch (data[1]) {
4202 case CMDF_ROUND_NEAREST:
4203 up_count = DIV_ROUND_CLOSEST(data[2],
4204 devpriv->clock_ns);
4205 break;
4206 case CMDF_ROUND_DOWN:
4207 up_count = data[2] / devpriv->clock_ns;
4208 break;
4209 case CMDF_ROUND_UP:
4210 up_count =
4211 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4212 break;
4213 default:
4214 return -EINVAL;
4215 }
4216 switch (data[3]) {
4217 case CMDF_ROUND_NEAREST:
4218 down_count = DIV_ROUND_CLOSEST(data[4],
4219 devpriv->clock_ns);
4220 break;
4221 case CMDF_ROUND_DOWN:
4222 down_count = data[4] / devpriv->clock_ns;
4223 break;
4224 case CMDF_ROUND_UP:
4225 down_count =
4226 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4227 break;
4228 default:
4229 return -EINVAL;
4230 }
4231 if (up_count * devpriv->clock_ns != data[2] ||
4232 down_count * devpriv->clock_ns != data[4]) {
4233 data[2] = up_count * devpriv->clock_ns;
4234 data[4] = down_count * devpriv->clock_ns;
4235 return -EAGAIN;
4236 }
4237 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4238 devpriv->pwm_up_count = up_count;
4239 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4240 devpriv->pwm_down_count = down_count;
4241 return 5;
4242 case INSN_CONFIG_GET_PWM_OUTPUT:
4243 return ni_get_pwm_config(dev, data);
4244 default:
4245 return -EINVAL;
4246 }
4247 return 0;
4248 }
4249
4250 static int pack_mb88341(int addr, int val, int *bitstring)
4251 {
4252 /*
4253 * Fujitsu MB 88341
4254 * Note that address bits are reversed. Thanks to
4255 * Ingo Keen for noticing this.
4256 *
4257 * Note also that the 88341 expects address values from
4258 * 1-12, whereas we use channel numbers 0-11. The NI
4259 * docs use 1-12, also, so be careful here.
4260 */
4261 addr++;
4262 *bitstring = ((addr & 0x1) << 11) |
4263 ((addr & 0x2) << 9) |
4264 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4265 return 12;
4266 }
4267
4268 static int pack_dac8800(int addr, int val, int *bitstring)
4269 {
4270 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4271 return 11;
4272 }
4273
4274 static int pack_dac8043(int addr, int val, int *bitstring)
4275 {
4276 *bitstring = val & 0xfff;
4277 return 12;
4278 }
4279
4280 static int pack_ad8522(int addr, int val, int *bitstring)
4281 {
4282 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4283 return 16;
4284 }
4285
4286 static int pack_ad8804(int addr, int val, int *bitstring)
4287 {
4288 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4289 return 12;
4290 }
4291
4292 static int pack_ad8842(int addr, int val, int *bitstring)
4293 {
4294 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4295 return 12;
4296 }
4297
4298 struct caldac_struct {
4299 int n_chans;
4300 int n_bits;
4301 int (*packbits)(int, int, int *);
4302 };
4303
4304 static struct caldac_struct caldacs[] = {
4305 [mb88341] = {12, 8, pack_mb88341},
4306 [dac8800] = {8, 8, pack_dac8800},
4307 [dac8043] = {1, 12, pack_dac8043},
4308 [ad8522] = {2, 12, pack_ad8522},
4309 [ad8804] = {12, 8, pack_ad8804},
4310 [ad8842] = {8, 8, pack_ad8842},
4311 [ad8804_debug] = {16, 8, pack_ad8804},
4312 };
4313
4314 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4315 {
4316 const struct ni_board_struct *board = dev->board_ptr;
4317 struct ni_private *devpriv = dev->private;
4318 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4319 unsigned int cmd;
4320 int i;
4321 int type;
4322
4323 if (devpriv->caldacs[addr] == val)
4324 return;
4325 devpriv->caldacs[addr] = val;
4326
4327 for (i = 0; i < 3; i++) {
4328 type = board->caldac[i];
4329 if (type == caldac_none)
4330 break;
4331 if (addr < caldacs[type].n_chans) {
4332 bits = caldacs[type].packbits(addr, val, &bitstring);
4333 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4334 break;
4335 }
4336 addr -= caldacs[type].n_chans;
4337 }
4338
4339 /* bits will be 0 if there is no caldac for the given addr */
4340 if (bits == 0)
4341 return;
4342
4343 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4344 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4345 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4346 udelay(1);
4347 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4348 udelay(1);
4349 }
4350 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4351 udelay(1);
4352 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4353 }
4354
4355 static int ni_calib_insn_write(struct comedi_device *dev,
4356 struct comedi_subdevice *s,
4357 struct comedi_insn *insn,
4358 unsigned int *data)
4359 {
4360 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4361
4362 return 1;
4363 }
4364
4365 static int ni_calib_insn_read(struct comedi_device *dev,
4366 struct comedi_subdevice *s,
4367 struct comedi_insn *insn,
4368 unsigned int *data)
4369 {
4370 struct ni_private *devpriv = dev->private;
4371
4372 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4373
4374 return 1;
4375 }
4376
4377 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4378 {
4379 const struct ni_board_struct *board = dev->board_ptr;
4380 struct ni_private *devpriv = dev->private;
4381 int i, j;
4382 int n_dacs;
4383 int n_chans = 0;
4384 int n_bits;
4385 int diffbits = 0;
4386 int type;
4387 int chan;
4388
4389 type = board->caldac[0];
4390 if (type == caldac_none)
4391 return;
4392 n_bits = caldacs[type].n_bits;
4393 for (i = 0; i < 3; i++) {
4394 type = board->caldac[i];
4395 if (type == caldac_none)
4396 break;
4397 if (caldacs[type].n_bits != n_bits)
4398 diffbits = 1;
4399 n_chans += caldacs[type].n_chans;
4400 }
4401 n_dacs = i;
4402 s->n_chan = n_chans;
4403
4404 if (diffbits) {
4405 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4406
4407 if (n_chans > MAX_N_CALDACS)
4408 dev_err(dev->class_dev,
4409 "BUG! MAX_N_CALDACS too small\n");
4410 s->maxdata_list = maxdata_list;
4411 chan = 0;
4412 for (i = 0; i < n_dacs; i++) {
4413 type = board->caldac[i];
4414 for (j = 0; j < caldacs[type].n_chans; j++) {
4415 maxdata_list[chan] =
4416 (1 << caldacs[type].n_bits) - 1;
4417 chan++;
4418 }
4419 }
4420
4421 for (chan = 0; chan < s->n_chan; chan++)
4422 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4423 } else {
4424 type = board->caldac[0];
4425 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4426
4427 for (chan = 0; chan < s->n_chan; chan++)
4428 ni_write_caldac(dev, i, s->maxdata / 2);
4429 }
4430 }
4431
4432 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4433 {
4434 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4435 int bit;
4436 int bitstring;
4437
4438 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4439 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4440 for (bit = 0x8000; bit; bit >>= 1) {
4441 if (bit & bitstring)
4442 cmd |= NI_E_SERIAL_CMD_SDATA;
4443 else
4444 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4445
4446 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4447 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4448 }
4449 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4450 bitstring = 0;
4451 for (bit = 0x80; bit; bit >>= 1) {
4452 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4453 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4454 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4455 bitstring |= bit;
4456 }
4457 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4458
4459 return bitstring;
4460 }
4461
4462 static int ni_eeprom_insn_read(struct comedi_device *dev,
4463 struct comedi_subdevice *s,
4464 struct comedi_insn *insn,
4465 unsigned int *data)
4466 {
4467 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4468
4469 return 1;
4470 }
4471
4472 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4473 struct comedi_subdevice *s,
4474 struct comedi_insn *insn,
4475 unsigned int *data)
4476 {
4477 struct ni_private *devpriv = dev->private;
4478
4479 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4480
4481 return 1;
4482 }
4483
4484 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4485 unsigned int chan)
4486 {
4487 /* pre-m-series boards have fixed signals on pfi pins */
4488 switch (chan) {
4489 case 0:
4490 return NI_PFI_OUTPUT_AI_START1;
4491 case 1:
4492 return NI_PFI_OUTPUT_AI_START2;
4493 case 2:
4494 return NI_PFI_OUTPUT_AI_CONVERT;
4495 case 3:
4496 return NI_PFI_OUTPUT_G_SRC1;
4497 case 4:
4498 return NI_PFI_OUTPUT_G_GATE1;
4499 case 5:
4500 return NI_PFI_OUTPUT_AO_UPDATE_N;
4501 case 6:
4502 return NI_PFI_OUTPUT_AO_START1;
4503 case 7:
4504 return NI_PFI_OUTPUT_AI_START_PULSE;
4505 case 8:
4506 return NI_PFI_OUTPUT_G_SRC0;
4507 case 9:
4508 return NI_PFI_OUTPUT_G_GATE0;
4509 default:
4510 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4511 break;
4512 }
4513 return 0;
4514 }
4515
4516 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4517 unsigned int chan, unsigned int source)
4518 {
4519 /* pre-m-series boards have fixed signals on pfi pins */
4520 if (source != ni_old_get_pfi_routing(dev, chan))
4521 return -EINVAL;
4522 return 2;
4523 }
4524
4525 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4526 unsigned int chan)
4527 {
4528 struct ni_private *devpriv = dev->private;
4529 const unsigned int array_offset = chan / 3;
4530
4531 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4532 devpriv->pfi_output_select_reg[array_offset]);
4533 }
4534
4535 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4536 unsigned int chan, unsigned int source)
4537 {
4538 struct ni_private *devpriv = dev->private;
4539 unsigned int index = chan / 3;
4540 unsigned short val = devpriv->pfi_output_select_reg[index];
4541
4542 if ((source & 0x1f) != source)
4543 return -EINVAL;
4544
4545 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4546 val |= NI_M_PFI_OUT_SEL(chan, source);
4547 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4548 devpriv->pfi_output_select_reg[index] = val;
4549
4550 return 2;
4551 }
4552
4553 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4554 unsigned int chan)
4555 {
4556 struct ni_private *devpriv = dev->private;
4557
4558 return (devpriv->is_m_series)
4559 ? ni_m_series_get_pfi_routing(dev, chan)
4560 : ni_old_get_pfi_routing(dev, chan);
4561 }
4562
4563 static int ni_set_pfi_routing(struct comedi_device *dev,
4564 unsigned int chan, unsigned int source)
4565 {
4566 struct ni_private *devpriv = dev->private;
4567
4568 return (devpriv->is_m_series)
4569 ? ni_m_series_set_pfi_routing(dev, chan, source)
4570 : ni_old_set_pfi_routing(dev, chan, source);
4571 }
4572
4573 static int ni_config_filter(struct comedi_device *dev,
4574 unsigned int pfi_channel,
4575 enum ni_pfi_filter_select filter)
4576 {
4577 struct ni_private *devpriv = dev->private;
4578 unsigned int bits;
4579
4580 if (!devpriv->is_m_series)
4581 return -ENOTSUPP;
4582
4583 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4584 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4585 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4586 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4587 return 0;
4588 }
4589
4590 static int ni_pfi_insn_config(struct comedi_device *dev,
4591 struct comedi_subdevice *s,
4592 struct comedi_insn *insn,
4593 unsigned int *data)
4594 {
4595 struct ni_private *devpriv = dev->private;
4596 unsigned int chan;
4597
4598 if (insn->n < 1)
4599 return -EINVAL;
4600
4601 chan = CR_CHAN(insn->chanspec);
4602
4603 switch (data[0]) {
4604 case COMEDI_OUTPUT:
4605 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4606 break;
4607 case COMEDI_INPUT:
4608 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4609 break;
4610 case INSN_CONFIG_DIO_QUERY:
4611 data[1] =
4612 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4613 COMEDI_OUTPUT : COMEDI_INPUT;
4614 return 0;
4615 case INSN_CONFIG_SET_ROUTING:
4616 return ni_set_pfi_routing(dev, chan, data[1]);
4617 case INSN_CONFIG_GET_ROUTING:
4618 data[1] = ni_get_pfi_routing(dev, chan);
4619 break;
4620 case INSN_CONFIG_FILTER:
4621 return ni_config_filter(dev, chan, data[1]);
4622 default:
4623 return -EINVAL;
4624 }
4625 return 0;
4626 }
4627
4628 static int ni_pfi_insn_bits(struct comedi_device *dev,
4629 struct comedi_subdevice *s,
4630 struct comedi_insn *insn,
4631 unsigned int *data)
4632 {
4633 struct ni_private *devpriv = dev->private;
4634
4635 if (!devpriv->is_m_series)
4636 return -ENOTSUPP;
4637
4638 if (comedi_dio_update_state(s, data))
4639 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4640
4641 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4642
4643 return insn->n;
4644 }
4645
4646 static int cs5529_wait_for_idle(struct comedi_device *dev)
4647 {
4648 unsigned short status;
4649 const int timeout = HZ;
4650 int i;
4651
4652 for (i = 0; i < timeout; i++) {
4653 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4654 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4655 break;
4656 set_current_state(TASK_INTERRUPTIBLE);
4657 if (schedule_timeout(1))
4658 return -EIO;
4659 }
4660 if (i == timeout) {
4661 dev_err(dev->class_dev, "timeout\n");
4662 return -ETIME;
4663 }
4664 return 0;
4665 }
4666
4667 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4668 {
4669 static const int timeout = 100;
4670 int i;
4671
4672 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4673 /* give time for command to start being serially clocked into cs5529.
4674 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4675 * set before we exit this function.
4676 */
4677 for (i = 0; i < timeout; i++) {
4678 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4679 NI67XX_CAL_STATUS_BUSY)
4680 break;
4681 udelay(1);
4682 }
4683 if (i == timeout)
4684 dev_err(dev->class_dev,
4685 "possible problem - never saw adc go busy?\n");
4686 }
4687
4688 static int cs5529_do_conversion(struct comedi_device *dev,
4689 unsigned short *data)
4690 {
4691 int retval;
4692 unsigned short status;
4693
4694 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4695 retval = cs5529_wait_for_idle(dev);
4696 if (retval) {
4697 dev_err(dev->class_dev,
4698 "timeout or signal in cs5529_do_conversion()\n");
4699 return -ETIME;
4700 }
4701 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4702 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4703 dev_err(dev->class_dev,
4704 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4705 return -EIO;
4706 }
4707 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4708 dev_err(dev->class_dev,
4709 "cs5529 conversion error, overrange (ignoring)\n");
4710 }
4711 if (data) {
4712 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4713 /* cs5529 returns 16 bit signed data in bipolar mode */
4714 *data ^= (1 << 15);
4715 }
4716 return 0;
4717 }
4718
4719 static int cs5529_ai_insn_read(struct comedi_device *dev,
4720 struct comedi_subdevice *s,
4721 struct comedi_insn *insn,
4722 unsigned int *data)
4723 {
4724 int n, retval;
4725 unsigned short sample;
4726 unsigned int channel_select;
4727 const unsigned int INTERNAL_REF = 0x1000;
4728
4729 /*
4730 * Set calibration adc source. Docs lie, reference select bits 8 to 11
4731 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4732 * 13 causes the adc input to go overrange (maybe reads external
4733 * reference?)
4734 */
4735 if (insn->chanspec & CR_ALT_SOURCE)
4736 channel_select = INTERNAL_REF;
4737 else
4738 channel_select = CR_CHAN(insn->chanspec);
4739 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4740
4741 for (n = 0; n < insn->n; n++) {
4742 retval = cs5529_do_conversion(dev, &sample);
4743 if (retval < 0)
4744 return retval;
4745 data[n] = sample;
4746 }
4747 return insn->n;
4748 }
4749
4750 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4751 unsigned int reg_select_bits)
4752 {
4753 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4754 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4755 reg_select_bits &= CS5529_CMD_REG_MASK;
4756 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4757 if (cs5529_wait_for_idle(dev))
4758 dev_err(dev->class_dev,
4759 "timeout or signal in %s\n", __func__);
4760 }
4761
4762 static int init_cs5529(struct comedi_device *dev)
4763 {
4764 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4765 CS5529_CFG_WORD_RATE_2180;
4766
4767 #if 1
4768 /* do self-calibration */
4769 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4770 CS5529_CFG_REG);
4771 /* need to force a conversion for calibration to run */
4772 cs5529_do_conversion(dev, NULL);
4773 #else
4774 /* force gain calibration to 1 */
4775 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4776 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4777 CS5529_CFG_REG);
4778 if (cs5529_wait_for_idle(dev))
4779 dev_err(dev->class_dev,
4780 "timeout or signal in %s\n", __func__);
4781 #endif
4782 return 0;
4783 }
4784
4785 /*
4786 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4787 * given an arbitrary frequency input clock.
4788 */
4789 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4790 unsigned int *freq_divider,
4791 unsigned int *freq_multiplier,
4792 unsigned int *actual_period_ns)
4793 {
4794 unsigned int div;
4795 unsigned int best_div = 1;
4796 unsigned int mult;
4797 unsigned int best_mult = 1;
4798 static const unsigned int pico_per_nano = 1000;
4799 const unsigned int reference_picosec = reference_period_ns *
4800 pico_per_nano;
4801 /*
4802 * m-series wants the phased-locked loop to output 80MHz, which is
4803 * divided by 4 to 20 MHz for most timing clocks
4804 */
4805 static const unsigned int target_picosec = 12500;
4806 int best_period_picosec = 0;
4807
4808 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4809 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4810 unsigned int new_period_ps =
4811 (reference_picosec * div) / mult;
4812 if (abs(new_period_ps - target_picosec) <
4813 abs(best_period_picosec - target_picosec)) {
4814 best_period_picosec = new_period_ps;
4815 best_div = div;
4816 best_mult = mult;
4817 }
4818 }
4819 }
4820 if (best_period_picosec == 0)
4821 return -EIO;
4822
4823 *freq_divider = best_div;
4824 *freq_multiplier = best_mult;
4825 /* return the actual period (* fudge factor for 80 to 20 MHz) */
4826 *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4827 pico_per_nano);
4828 return 0;
4829 }
4830
4831 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4832 unsigned int source,
4833 unsigned int period_ns)
4834 {
4835 struct ni_private *devpriv = dev->private;
4836 static const unsigned int min_period_ns = 50;
4837 static const unsigned int max_period_ns = 1000;
4838 static const unsigned int timeout = 1000;
4839 unsigned int pll_control_bits;
4840 unsigned int freq_divider;
4841 unsigned int freq_multiplier;
4842 unsigned int rtsi;
4843 unsigned int i;
4844 int retval;
4845
4846 if (source == NI_MIO_PLL_PXI10_CLOCK)
4847 period_ns = 100;
4848 /*
4849 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4850 * range so we'll use that.
4851 */
4852 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4853 dev_err(dev->class_dev,
4854 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4855 __func__, min_period_ns, max_period_ns);
4856 return -EINVAL;
4857 }
4858 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4859 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4860 NISTC_RTSI_TRIG_DIR_REG);
4861 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4862 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4863 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4864 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4865 switch (source) {
4866 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4867 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4868 break;
4869 case NI_MIO_PLL_PXI10_CLOCK:
4870 /* pxi clock is 10MHz */
4871 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4872 break;
4873 default:
4874 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4875 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4876 devpriv->clock_and_fout2 |=
4877 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4878 break;
4879 }
4880 }
4881 if (rtsi > NI_M_MAX_RTSI_CHAN)
4882 return -EINVAL;
4883 break;
4884 }
4885 retval = ni_mseries_get_pll_parameters(period_ns,
4886 &freq_divider,
4887 &freq_multiplier,
4888 &devpriv->clock_ns);
4889 if (retval < 0) {
4890 dev_err(dev->class_dev,
4891 "bug, failed to find pll parameters\n");
4892 return retval;
4893 }
4894
4895 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4896 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4897 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4898
4899 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4900 devpriv->clock_source = source;
4901 /* it takes a few hundred microseconds for PLL to lock */
4902 for (i = 0; i < timeout; ++i) {
4903 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4904 break;
4905 udelay(1);
4906 }
4907 if (i == timeout) {
4908 dev_err(dev->class_dev,
4909 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4910 __func__, source, period_ns);
4911 return -ETIMEDOUT;
4912 }
4913 return 3;
4914 }
4915
4916 static int ni_set_master_clock(struct comedi_device *dev,
4917 unsigned int source, unsigned int period_ns)
4918 {
4919 struct ni_private *devpriv = dev->private;
4920
4921 if (source == NI_MIO_INTERNAL_CLOCK) {
4922 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4923 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4924 NISTC_RTSI_TRIG_DIR_REG);
4925 devpriv->clock_ns = TIMEBASE_1_NS;
4926 if (devpriv->is_m_series) {
4927 devpriv->clock_and_fout2 &=
4928 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4929 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4930 ni_writew(dev, devpriv->clock_and_fout2,
4931 NI_M_CLK_FOUT2_REG);
4932 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4933 }
4934 devpriv->clock_source = source;
4935 } else {
4936 if (devpriv->is_m_series) {
4937 return ni_mseries_set_pll_master_clock(dev, source,
4938 period_ns);
4939 } else {
4940 if (source == NI_MIO_RTSI_CLOCK) {
4941 devpriv->rtsi_trig_direction_reg |=
4942 NISTC_RTSI_TRIG_USE_CLK;
4943 ni_stc_writew(dev,
4944 devpriv->rtsi_trig_direction_reg,
4945 NISTC_RTSI_TRIG_DIR_REG);
4946 if (period_ns == 0) {
4947 dev_err(dev->class_dev,
4948 "we don't handle an unspecified clock period correctly yet, returning error\n");
4949 return -EINVAL;
4950 }
4951 devpriv->clock_ns = period_ns;
4952 devpriv->clock_source = source;
4953 } else {
4954 return -EINVAL;
4955 }
4956 }
4957 }
4958 return 3;
4959 }
4960
4961 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4962 unsigned int chan, unsigned int source)
4963 {
4964 struct ni_private *devpriv = dev->private;
4965
4966 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4967 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4968 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4969 return 1;
4970
4971 dev_err(dev->class_dev,
4972 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4973 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4974 return 0;
4975 }
4976 return 0;
4977 }
4978 switch (source) {
4979 case NI_RTSI_OUTPUT_ADR_START1:
4980 case NI_RTSI_OUTPUT_ADR_START2:
4981 case NI_RTSI_OUTPUT_SCLKG:
4982 case NI_RTSI_OUTPUT_DACUPDN:
4983 case NI_RTSI_OUTPUT_DA_START1:
4984 case NI_RTSI_OUTPUT_G_SRC0:
4985 case NI_RTSI_OUTPUT_G_GATE0:
4986 case NI_RTSI_OUTPUT_RGOUT0:
4987 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4988 return 1;
4989 case NI_RTSI_OUTPUT_RTSI_OSC:
4990 return (devpriv->is_m_series) ? 1 : 0;
4991 default:
4992 return 0;
4993 }
4994 }
4995
4996 static int ni_set_rtsi_routing(struct comedi_device *dev,
4997 unsigned int chan, unsigned int src)
4998 {
4999 struct ni_private *devpriv = dev->private;
5000
5001 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5002 return -EINVAL;
5003 if (chan < 4) {
5004 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5005 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5006 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5007 NISTC_RTSI_TRIGA_OUT_REG);
5008 } else if (chan < 8) {
5009 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5010 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5011 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5012 NISTC_RTSI_TRIGB_OUT_REG);
5013 }
5014 return 2;
5015 }
5016
5017 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5018 unsigned int chan)
5019 {
5020 struct ni_private *devpriv = dev->private;
5021
5022 if (chan < 4) {
5023 return NISTC_RTSI_TRIG_TO_SRC(chan,
5024 devpriv->rtsi_trig_a_output_reg);
5025 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5026 return NISTC_RTSI_TRIG_TO_SRC(chan,
5027 devpriv->rtsi_trig_b_output_reg);
5028 } else {
5029 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
5030 return NI_RTSI_OUTPUT_RTSI_OSC;
5031 dev_err(dev->class_dev, "bug! should never get here?\n");
5032 return 0;
5033 }
5034 }
5035
5036 static int ni_rtsi_insn_config(struct comedi_device *dev,
5037 struct comedi_subdevice *s,
5038 struct comedi_insn *insn,
5039 unsigned int *data)
5040 {
5041 struct ni_private *devpriv = dev->private;
5042 unsigned int chan = CR_CHAN(insn->chanspec);
5043 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5044
5045 switch (data[0]) {
5046 case INSN_CONFIG_DIO_OUTPUT:
5047 if (chan < max_chan) {
5048 devpriv->rtsi_trig_direction_reg |=
5049 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5050 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5051 devpriv->rtsi_trig_direction_reg |=
5052 NISTC_RTSI_TRIG_DRV_CLK;
5053 }
5054 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5055 NISTC_RTSI_TRIG_DIR_REG);
5056 break;
5057 case INSN_CONFIG_DIO_INPUT:
5058 if (chan < max_chan) {
5059 devpriv->rtsi_trig_direction_reg &=
5060 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5061 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5062 devpriv->rtsi_trig_direction_reg &=
5063 ~NISTC_RTSI_TRIG_DRV_CLK;
5064 }
5065 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5066 NISTC_RTSI_TRIG_DIR_REG);
5067 break;
5068 case INSN_CONFIG_DIO_QUERY:
5069 if (chan < max_chan) {
5070 data[1] =
5071 (devpriv->rtsi_trig_direction_reg &
5072 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5073 ? INSN_CONFIG_DIO_OUTPUT
5074 : INSN_CONFIG_DIO_INPUT;
5075 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5076 data[1] = (devpriv->rtsi_trig_direction_reg &
5077 NISTC_RTSI_TRIG_DRV_CLK)
5078 ? INSN_CONFIG_DIO_OUTPUT
5079 : INSN_CONFIG_DIO_INPUT;
5080 }
5081 return 2;
5082 case INSN_CONFIG_SET_CLOCK_SRC:
5083 return ni_set_master_clock(dev, data[1], data[2]);
5084 case INSN_CONFIG_GET_CLOCK_SRC:
5085 data[1] = devpriv->clock_source;
5086 data[2] = devpriv->clock_ns;
5087 return 3;
5088 case INSN_CONFIG_SET_ROUTING:
5089 return ni_set_rtsi_routing(dev, chan, data[1]);
5090 case INSN_CONFIG_GET_ROUTING:
5091 data[1] = ni_get_rtsi_routing(dev, chan);
5092 return 2;
5093 default:
5094 return -EINVAL;
5095 }
5096 return 1;
5097 }
5098
5099 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5100 struct comedi_subdevice *s,
5101 struct comedi_insn *insn,
5102 unsigned int *data)
5103 {
5104 data[1] = 0;
5105
5106 return insn->n;
5107 }
5108
5109 static void ni_rtsi_init(struct comedi_device *dev)
5110 {
5111 struct ni_private *devpriv = dev->private;
5112
5113 /* Initialises the RTSI bus signal switch to a default state */
5114
5115 /*
5116 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5117 * to have no effect, at least on pxi-6281, which always uses
5118 * 20MHz rtsi clock frequency
5119 */
5120 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5121 /* Set clock mode to internal */
5122 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5123 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5124 /* default internal lines routing to RTSI bus lines */
5125 devpriv->rtsi_trig_a_output_reg =
5126 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5127 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5128 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5129 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5130 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5131 NISTC_RTSI_TRIGA_OUT_REG);
5132 devpriv->rtsi_trig_b_output_reg =
5133 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5134 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5135 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5136 if (devpriv->is_m_series)
5137 devpriv->rtsi_trig_b_output_reg |=
5138 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5139 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5140 NISTC_RTSI_TRIGB_OUT_REG);
5141
5142 /*
5143 * Sets the source and direction of the 4 on board lines
5144 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5145 */
5146 }
5147
5148 #ifdef PCIDMA
5149 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5150 {
5151 struct ni_gpct *counter = s->private;
5152 int retval;
5153
5154 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5155 COMEDI_INPUT);
5156 if (retval) {
5157 dev_err(dev->class_dev,
5158 "no dma channel available for use by counter\n");
5159 return retval;
5160 }
5161 ni_tio_acknowledge(counter);
5162 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5163
5164 return ni_tio_cmd(dev, s);
5165 }
5166
5167 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5168 {
5169 struct ni_gpct *counter = s->private;
5170 int retval;
5171
5172 retval = ni_tio_cancel(counter);
5173 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5174 ni_release_gpct_mite_channel(dev, counter->counter_index);
5175 return retval;
5176 }
5177 #endif
5178
5179 static irqreturn_t ni_E_interrupt(int irq, void *d)
5180 {
5181 struct comedi_device *dev = d;
5182 struct comedi_subdevice *s_ai = dev->read_subdev;
5183 struct comedi_subdevice *s_ao = dev->write_subdev;
5184 unsigned short a_status;
5185 unsigned short b_status;
5186 unsigned long flags;
5187 #ifdef PCIDMA
5188 struct ni_private *devpriv = dev->private;
5189 #endif
5190
5191 if (!dev->attached)
5192 return IRQ_NONE;
5193 smp_mb(); /* make sure dev->attached is checked */
5194
5195 /* lock to avoid race with comedi_poll */
5196 spin_lock_irqsave(&dev->spinlock, flags);
5197 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5198 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5199 #ifdef PCIDMA
5200 if (devpriv->mite) {
5201 unsigned long flags_too;
5202
5203 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5204 if (s_ai && devpriv->ai_mite_chan)
5205 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5206 if (s_ao && devpriv->ao_mite_chan)
5207 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5208 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5209 }
5210 #endif
5211 ack_a_interrupt(dev, a_status);
5212 ack_b_interrupt(dev, b_status);
5213 if (s_ai) {
5214 if (a_status & NISTC_AI_STATUS1_INTA)
5215 handle_a_interrupt(dev, s_ai, a_status);
5216 /* handle any interrupt or dma events */
5217 comedi_handle_events(dev, s_ai);
5218 }
5219 if (s_ao) {
5220 if (b_status & NISTC_AO_STATUS1_INTB)
5221 handle_b_interrupt(dev, s_ao, b_status);
5222 /* handle any interrupt or dma events */
5223 comedi_handle_events(dev, s_ao);
5224 }
5225 handle_gpct_interrupt(dev, 0);
5226 handle_gpct_interrupt(dev, 1);
5227 #ifdef PCIDMA
5228 if (devpriv->is_m_series)
5229 handle_cdio_interrupt(dev);
5230 #endif
5231
5232 spin_unlock_irqrestore(&dev->spinlock, flags);
5233 return IRQ_HANDLED;
5234 }
5235
5236 static int ni_alloc_private(struct comedi_device *dev)
5237 {
5238 struct ni_private *devpriv;
5239
5240 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5241 if (!devpriv)
5242 return -ENOMEM;
5243
5244 spin_lock_init(&devpriv->window_lock);
5245 spin_lock_init(&devpriv->soft_reg_copy_lock);
5246 spin_lock_init(&devpriv->mite_channel_lock);
5247
5248 return 0;
5249 }
5250
5251 static int ni_E_init(struct comedi_device *dev,
5252 unsigned int interrupt_pin, unsigned int irq_polarity)
5253 {
5254 const struct ni_board_struct *board = dev->board_ptr;
5255 struct ni_private *devpriv = dev->private;
5256 struct comedi_subdevice *s;
5257 int ret;
5258 int i;
5259
5260 if (board->n_aochan > MAX_N_AO_CHAN) {
5261 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5262 return -EINVAL;
5263 }
5264
5265 /* initialize clock dividers */
5266 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5267 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5268 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5269 NISTC_CLK_FOUT_TO_BOARD;
5270 if (!devpriv->is_6xxx) {
5271 /* BEAM is this needed for PCI-6143 ?? */
5272 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5273 NISTC_CLK_FOUT_AO_OUT_DIV2);
5274 }
5275 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5276
5277 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5278 if (ret)
5279 return ret;
5280
5281 /* Analog Input subdevice */
5282 s = &dev->subdevices[NI_AI_SUBDEV];
5283 if (board->n_adchan) {
5284 s->type = COMEDI_SUBD_AI;
5285 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5286 if (!devpriv->is_611x)
5287 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5288 if (board->ai_maxdata > 0xffff)
5289 s->subdev_flags |= SDF_LSAMPL;
5290 if (devpriv->is_m_series)
5291 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5292 s->n_chan = board->n_adchan;
5293 s->maxdata = board->ai_maxdata;
5294 s->range_table = ni_range_lkup[board->gainlkup];
5295 s->insn_read = ni_ai_insn_read;
5296 s->insn_config = ni_ai_insn_config;
5297 if (dev->irq) {
5298 dev->read_subdev = s;
5299 s->subdev_flags |= SDF_CMD_READ;
5300 s->len_chanlist = 512;
5301 s->do_cmdtest = ni_ai_cmdtest;
5302 s->do_cmd = ni_ai_cmd;
5303 s->cancel = ni_ai_reset;
5304 s->poll = ni_ai_poll;
5305 s->munge = ni_ai_munge;
5306
5307 if (devpriv->mite)
5308 s->async_dma_dir = DMA_FROM_DEVICE;
5309 }
5310
5311 /* reset the analog input configuration */
5312 ni_ai_reset(dev, s);
5313 } else {
5314 s->type = COMEDI_SUBD_UNUSED;
5315 }
5316
5317 /* Analog Output subdevice */
5318 s = &dev->subdevices[NI_AO_SUBDEV];
5319 if (board->n_aochan) {
5320 s->type = COMEDI_SUBD_AO;
5321 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5322 if (devpriv->is_m_series)
5323 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5324 s->n_chan = board->n_aochan;
5325 s->maxdata = board->ao_maxdata;
5326 s->range_table = board->ao_range_table;
5327 s->insn_config = ni_ao_insn_config;
5328 s->insn_write = ni_ao_insn_write;
5329
5330 ret = comedi_alloc_subdev_readback(s);
5331 if (ret)
5332 return ret;
5333
5334 /*
5335 * Along with the IRQ we need either a FIFO or DMA for
5336 * async command support.
5337 */
5338 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5339 dev->write_subdev = s;
5340 s->subdev_flags |= SDF_CMD_WRITE;
5341 s->len_chanlist = s->n_chan;
5342 s->do_cmdtest = ni_ao_cmdtest;
5343 s->do_cmd = ni_ao_cmd;
5344 s->cancel = ni_ao_reset;
5345 if (!devpriv->is_m_series)
5346 s->munge = ni_ao_munge;
5347
5348 if (devpriv->mite)
5349 s->async_dma_dir = DMA_TO_DEVICE;
5350 }
5351
5352 if (devpriv->is_67xx)
5353 init_ao_67xx(dev, s);
5354
5355 /* reset the analog output configuration */
5356 ni_ao_reset(dev, s);
5357 } else {
5358 s->type = COMEDI_SUBD_UNUSED;
5359 }
5360
5361 /* Digital I/O subdevice */
5362 s = &dev->subdevices[NI_DIO_SUBDEV];
5363 s->type = COMEDI_SUBD_DIO;
5364 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5365 s->n_chan = board->has_32dio_chan ? 32 : 8;
5366 s->maxdata = 1;
5367 s->range_table = &range_digital;
5368 if (devpriv->is_m_series) {
5369 #ifdef PCIDMA
5370 s->subdev_flags |= SDF_LSAMPL;
5371 s->insn_bits = ni_m_series_dio_insn_bits;
5372 s->insn_config = ni_m_series_dio_insn_config;
5373 if (dev->irq) {
5374 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5375 s->len_chanlist = s->n_chan;
5376 s->do_cmdtest = ni_cdio_cmdtest;
5377 s->do_cmd = ni_cdio_cmd;
5378 s->cancel = ni_cdio_cancel;
5379
5380 /* M-series boards use DMA */
5381 s->async_dma_dir = DMA_BIDIRECTIONAL;
5382 }
5383
5384 /* reset DIO and set all channels to inputs */
5385 ni_writel(dev, NI_M_CDO_CMD_RESET |
5386 NI_M_CDI_CMD_RESET,
5387 NI_M_CDIO_CMD_REG);
5388 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5389 #endif /* PCIDMA */
5390 } else {
5391 s->insn_bits = ni_dio_insn_bits;
5392 s->insn_config = ni_dio_insn_config;
5393
5394 /* set all channels to inputs */
5395 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5396 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5397 }
5398
5399 /* 8255 device */
5400 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5401 if (board->has_8255) {
5402 ret = subdev_8255_init(dev, s, ni_8255_callback,
5403 NI_E_8255_BASE);
5404 if (ret)
5405 return ret;
5406 } else {
5407 s->type = COMEDI_SUBD_UNUSED;
5408 }
5409
5410 /* formerly general purpose counter/timer device, but no longer used */
5411 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5412 s->type = COMEDI_SUBD_UNUSED;
5413
5414 /* Calibration subdevice */
5415 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5416 s->type = COMEDI_SUBD_CALIB;
5417 s->subdev_flags = SDF_INTERNAL;
5418 s->n_chan = 1;
5419 s->maxdata = 0;
5420 if (devpriv->is_m_series) {
5421 /* internal PWM output used for AI nonlinearity calibration */
5422 s->insn_config = ni_m_series_pwm_config;
5423
5424 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5425 } else if (devpriv->is_6143) {
5426 /* internal PWM output used for AI nonlinearity calibration */
5427 s->insn_config = ni_6143_pwm_config;
5428 } else {
5429 s->subdev_flags |= SDF_WRITABLE;
5430 s->insn_read = ni_calib_insn_read;
5431 s->insn_write = ni_calib_insn_write;
5432
5433 /* setup the caldacs and find the real n_chan and maxdata */
5434 caldac_setup(dev, s);
5435 }
5436
5437 /* EEPROM subdevice */
5438 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5439 s->type = COMEDI_SUBD_MEMORY;
5440 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5441 s->maxdata = 0xff;
5442 if (devpriv->is_m_series) {
5443 s->n_chan = M_SERIES_EEPROM_SIZE;
5444 s->insn_read = ni_m_series_eeprom_insn_read;
5445 } else {
5446 s->n_chan = 512;
5447 s->insn_read = ni_eeprom_insn_read;
5448 }
5449
5450 /* Digital I/O (PFI) subdevice */
5451 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5452 s->type = COMEDI_SUBD_DIO;
5453 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5454 s->maxdata = 1;
5455 if (devpriv->is_m_series) {
5456 s->n_chan = 16;
5457 s->insn_bits = ni_pfi_insn_bits;
5458
5459 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5460 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5461 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5462 NI_M_PFI_OUT_SEL_REG(i));
5463 }
5464 } else {
5465 s->n_chan = 10;
5466 }
5467 s->insn_config = ni_pfi_insn_config;
5468
5469 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5470
5471 /* cs5529 calibration adc */
5472 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5473 if (devpriv->is_67xx) {
5474 s->type = COMEDI_SUBD_AI;
5475 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5476 /* one channel for each analog output channel */
5477 s->n_chan = board->n_aochan;
5478 s->maxdata = (1 << 16) - 1;
5479 s->range_table = &range_unknown; /* XXX */
5480 s->insn_read = cs5529_ai_insn_read;
5481 s->insn_config = NULL;
5482 init_cs5529(dev);
5483 } else {
5484 s->type = COMEDI_SUBD_UNUSED;
5485 }
5486
5487 /* Serial */
5488 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5489 s->type = COMEDI_SUBD_SERIAL;
5490 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5491 s->n_chan = 1;
5492 s->maxdata = 0xff;
5493 s->insn_config = ni_serial_insn_config;
5494 devpriv->serial_interval_ns = 0;
5495 devpriv->serial_hw_mode = 0;
5496
5497 /* RTSI */
5498 s = &dev->subdevices[NI_RTSI_SUBDEV];
5499 s->type = COMEDI_SUBD_DIO;
5500 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5501 s->n_chan = 8;
5502 s->maxdata = 1;
5503 s->insn_bits = ni_rtsi_insn_bits;
5504 s->insn_config = ni_rtsi_insn_config;
5505 ni_rtsi_init(dev);
5506
5507 /* allocate and initialize the gpct counter device */
5508 devpriv->counter_dev = ni_gpct_device_construct(dev,
5509 ni_gpct_write_register,
5510 ni_gpct_read_register,
5511 (devpriv->is_m_series)
5512 ? ni_gpct_variant_m_series
5513 : ni_gpct_variant_e_series,
5514 NUM_GPCT);
5515 if (!devpriv->counter_dev)
5516 return -ENOMEM;
5517
5518 /* Counter (gpct) subdevices */
5519 for (i = 0; i < NUM_GPCT; ++i) {
5520 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5521
5522 /* setup and initialize the counter */
5523 gpct->chip_index = 0;
5524 gpct->counter_index = i;
5525 ni_tio_init_counter(gpct);
5526
5527 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5528 s->type = COMEDI_SUBD_COUNTER;
5529 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5530 s->n_chan = 3;
5531 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5532 : 0x00ffffff;
5533 s->insn_read = ni_tio_insn_read;
5534 s->insn_write = ni_tio_insn_write;
5535 s->insn_config = ni_tio_insn_config;
5536 #ifdef PCIDMA
5537 if (dev->irq && devpriv->mite) {
5538 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5539 s->len_chanlist = 1;
5540 s->do_cmdtest = ni_tio_cmdtest;
5541 s->do_cmd = ni_gpct_cmd;
5542 s->cancel = ni_gpct_cancel;
5543
5544 s->async_dma_dir = DMA_BIDIRECTIONAL;
5545 }
5546 #endif
5547 s->private = gpct;
5548 }
5549
5550 /* Frequency output subdevice */
5551 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5552 s->type = COMEDI_SUBD_COUNTER;
5553 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5554 s->n_chan = 1;
5555 s->maxdata = 0xf;
5556 s->insn_read = ni_freq_out_insn_read;
5557 s->insn_write = ni_freq_out_insn_write;
5558 s->insn_config = ni_freq_out_insn_config;
5559
5560 if (dev->irq) {
5561 ni_stc_writew(dev,
5562 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5563 (NISTC_INT_CTRL_3PIN_INT & 0) |
5564 NISTC_INT_CTRL_INTA_ENA |
5565 NISTC_INT_CTRL_INTB_ENA |
5566 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5567 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5568 NISTC_INT_CTRL_REG);
5569 }
5570
5571 /* DMA setup */
5572 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5573 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5574
5575 if (devpriv->is_6xxx) {
5576 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5577 } else if (devpriv->is_m_series) {
5578 int channel;
5579
5580 for (channel = 0; channel < board->n_aochan; ++channel) {
5581 ni_writeb(dev, 0xf,
5582 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5583 ni_writeb(dev, 0x0,
5584 NI_M_AO_REF_ATTENUATION_REG(channel));
5585 }
5586 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5587 }
5588
5589 return 0;
5590 }
5591
5592 static void mio_common_detach(struct comedi_device *dev)
5593 {
5594 struct ni_private *devpriv = dev->private;
5595
5596 if (devpriv)
5597 ni_gpct_device_destroy(devpriv->counter_dev);
5598 }
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