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staging: comedi: ni_stc.h: rename the NI-6143 register defines
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53 */
54
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
58 #include "8255.h"
59 #include "mite.h"
60
61 /* A timeout count */
62 #define NI_TIMEOUT 1000
63
64 /* Note: this table must match the ai_gain_* definitions */
65 static const short ni_gainlkup[][16] = {
66 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
67 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
69 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
70 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
71 [ai_gain_4] = {0, 1, 4, 7},
72 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
73 0x003, 0x004, 0x005, 0x006},
74 [ai_gain_622x] = {0, 1, 4, 5},
75 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
76 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
77 };
78
79 static const struct comedi_lrange range_ni_E_ai = {
80 16, {
81 BIP_RANGE(10),
82 BIP_RANGE(5),
83 BIP_RANGE(2.5),
84 BIP_RANGE(1),
85 BIP_RANGE(0.5),
86 BIP_RANGE(0.25),
87 BIP_RANGE(0.1),
88 BIP_RANGE(0.05),
89 UNI_RANGE(20),
90 UNI_RANGE(10),
91 UNI_RANGE(5),
92 UNI_RANGE(2),
93 UNI_RANGE(1),
94 UNI_RANGE(0.5),
95 UNI_RANGE(0.2),
96 UNI_RANGE(0.1)
97 }
98 };
99
100 static const struct comedi_lrange range_ni_E_ai_limited = {
101 8, {
102 BIP_RANGE(10),
103 BIP_RANGE(5),
104 BIP_RANGE(1),
105 BIP_RANGE(0.1),
106 UNI_RANGE(10),
107 UNI_RANGE(5),
108 UNI_RANGE(1),
109 UNI_RANGE(0.1)
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
114 14, {
115 BIP_RANGE(10),
116 BIP_RANGE(5),
117 BIP_RANGE(2),
118 BIP_RANGE(1),
119 BIP_RANGE(0.5),
120 BIP_RANGE(0.2),
121 BIP_RANGE(0.1),
122 UNI_RANGE(10),
123 UNI_RANGE(5),
124 UNI_RANGE(2),
125 UNI_RANGE(1),
126 UNI_RANGE(0.5),
127 UNI_RANGE(0.2),
128 UNI_RANGE(0.1)
129 }
130 };
131
132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
133 4, {
134 BIP_RANGE(10),
135 BIP_RANGE(5),
136 BIP_RANGE(0.5),
137 BIP_RANGE(0.05)
138 }
139 };
140
141 static const struct comedi_lrange range_ni_E_ai_611x = {
142 8, {
143 BIP_RANGE(50),
144 BIP_RANGE(20),
145 BIP_RANGE(10),
146 BIP_RANGE(5),
147 BIP_RANGE(2),
148 BIP_RANGE(1),
149 BIP_RANGE(0.5),
150 BIP_RANGE(0.2)
151 }
152 };
153
154 static const struct comedi_lrange range_ni_M_ai_622x = {
155 4, {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(1),
159 BIP_RANGE(0.2)
160 }
161 };
162
163 static const struct comedi_lrange range_ni_M_ai_628x = {
164 7, {
165 BIP_RANGE(10),
166 BIP_RANGE(5),
167 BIP_RANGE(2),
168 BIP_RANGE(1),
169 BIP_RANGE(0.5),
170 BIP_RANGE(0.2),
171 BIP_RANGE(0.1)
172 }
173 };
174
175 static const struct comedi_lrange range_ni_E_ao_ext = {
176 4, {
177 BIP_RANGE(10),
178 UNI_RANGE(10),
179 RANGE_ext(-1, 1),
180 RANGE_ext(0, 1)
181 }
182 };
183
184 static const struct comedi_lrange *const ni_range_lkup[] = {
185 [ai_gain_16] = &range_ni_E_ai,
186 [ai_gain_8] = &range_ni_E_ai_limited,
187 [ai_gain_14] = &range_ni_E_ai_limited14,
188 [ai_gain_4] = &range_ni_E_ai_bipolar4,
189 [ai_gain_611x] = &range_ni_E_ai_611x,
190 [ai_gain_622x] = &range_ni_M_ai_622x,
191 [ai_gain_628x] = &range_ni_M_ai_628x,
192 [ai_gain_6143] = &range_bipolar5
193 };
194
195 enum aimodes {
196 AIMODE_NONE = 0,
197 AIMODE_HALF_FULL = 1,
198 AIMODE_SCAN = 2,
199 AIMODE_SAMPLE = 3,
200 };
201
202 enum ni_common_subdevices {
203 NI_AI_SUBDEV,
204 NI_AO_SUBDEV,
205 NI_DIO_SUBDEV,
206 NI_8255_DIO_SUBDEV,
207 NI_UNUSED_SUBDEV,
208 NI_CALIBRATION_SUBDEV,
209 NI_EEPROM_SUBDEV,
210 NI_PFI_DIO_SUBDEV,
211 NI_CS5529_CALIBRATION_SUBDEV,
212 NI_SERIAL_SUBDEV,
213 NI_RTSI_SUBDEV,
214 NI_GPCT0_SUBDEV,
215 NI_GPCT1_SUBDEV,
216 NI_FREQ_OUT_SUBDEV,
217 NI_NUM_SUBDEVICES
218 };
219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
220 {
221 switch (counter_index) {
222 case 0:
223 return NI_GPCT0_SUBDEV;
224 case 1:
225 return NI_GPCT1_SUBDEV;
226 default:
227 break;
228 }
229 BUG();
230 return NI_GPCT0_SUBDEV;
231 }
232
233 enum timebase_nanoseconds {
234 TIMEBASE_1_NS = 50,
235 TIMEBASE_2_NS = 10000
236 };
237
238 #define SERIAL_DISABLED 0
239 #define SERIAL_600NS 600
240 #define SERIAL_1_2US 1200
241 #define SERIAL_10US 10000
242
243 static const int num_adc_stages_611x = 3;
244
245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
246 {
247 if (dev->mmio)
248 writel(data, dev->mmio + reg);
249
250 outl(data, dev->iobase + reg);
251 }
252
253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
254 {
255 if (dev->mmio)
256 writew(data, dev->mmio + reg);
257
258 outw(data, dev->iobase + reg);
259 }
260
261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
262 {
263 if (dev->mmio)
264 writeb(data, dev->mmio + reg);
265
266 outb(data, dev->iobase + reg);
267 }
268
269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
270 {
271 if (dev->mmio)
272 return readl(dev->mmio + reg);
273
274 return inl(dev->iobase + reg);
275 }
276
277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
278 {
279 if (dev->mmio)
280 return readw(dev->mmio + reg);
281
282 return inw(dev->iobase + reg);
283 }
284
285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
286 {
287 if (dev->mmio)
288 return readb(dev->mmio + reg);
289
290 return inb(dev->iobase + reg);
291 }
292
293 /*
294 * We automatically take advantage of STC registers that can be
295 * read/written directly in the I/O space of the board.
296 *
297 * The AT-MIO and DAQCard devices map the low 8 STC registers to
298 * iobase+reg*2.
299 *
300 * Most PCIMIO devices also map the low 8 STC registers but the
301 * 611x devices map the read registers to iobase+(addr-1)*2.
302 * For now non-windowed STC access is disabled if a PCIMIO device
303 * is detected (devpriv->mite has been initialized).
304 *
305 * The M series devices do not used windowed registers for the
306 * STC registers. The functions below handle the mapping of the
307 * windowed STC registers to the m series register offsets.
308 */
309
310 struct mio_regmap {
311 unsigned int mio_reg;
312 int size;
313 };
314
315 static const struct mio_regmap m_series_stc_write_regmap[] = {
316 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
317 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
318 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
319 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
320 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
321 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
322 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
323 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
324 /*
325 * NISTC_DIO_OUT_REG maps to:
326 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
327 */
328 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
329 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
330 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
331 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
332 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
333 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
334 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
335 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
336 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
337 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
338 [NISTC_G0_MODE_REG] = { 0x134, 2 },
339 [NISTC_G1_MODE_REG] = { 0x136, 2 },
340 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
341 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
342 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
343 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
344 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
345 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
346 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
347 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
348 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
349 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
350 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
351 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
352 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
353 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
354 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
355 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
356 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
357 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
358 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
359 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
360 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
361 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
362 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
363 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
364 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
365 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
366 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
367 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
368 [NISTC_RESET_REG] = { 0x190, 2 },
369 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
370 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
371 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
372 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
373 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
374 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
375 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
376 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
377 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
378 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
379 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
380 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
381 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
382 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
383 };
384
385 static void m_series_stc_write(struct comedi_device *dev,
386 unsigned int data, unsigned int reg)
387 {
388 const struct mio_regmap *regmap;
389
390 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
391 regmap = &m_series_stc_write_regmap[reg];
392 } else {
393 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
394 __func__, reg);
395 return;
396 }
397
398 switch (regmap->size) {
399 case 4:
400 ni_writel(dev, data, regmap->mio_reg);
401 break;
402 case 2:
403 ni_writew(dev, data, regmap->mio_reg);
404 break;
405 default:
406 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
407 __func__, reg);
408 break;
409 }
410 }
411
412 static const struct mio_regmap m_series_stc_read_regmap[] = {
413 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
414 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
415 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
416 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
417 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
418 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
419 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
420 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
421 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
422 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
423 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
424 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
425 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
426 [NISTC_STATUS1_REG] = { 0x136, 2 },
427 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
428 [NISTC_STATUS2_REG] = { 0x13a, 2 },
429 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
430 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
431 };
432
433 static unsigned int m_series_stc_read(struct comedi_device *dev,
434 unsigned int reg)
435 {
436 const struct mio_regmap *regmap;
437
438 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
439 regmap = &m_series_stc_read_regmap[reg];
440 } else {
441 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
442 __func__, reg);
443 return 0;
444 }
445
446 switch (regmap->size) {
447 case 4:
448 return ni_readl(dev, regmap->mio_reg);
449 case 2:
450 return ni_readw(dev, regmap->mio_reg);
451 case 1:
452 return ni_readb(dev, regmap->mio_reg);
453 default:
454 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
455 __func__, reg);
456 return 0;
457 }
458 }
459
460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
461 {
462 struct ni_private *devpriv = dev->private;
463 unsigned long flags;
464
465 if (devpriv->is_m_series) {
466 m_series_stc_write(dev, data, reg);
467 } else {
468 spin_lock_irqsave(&devpriv->window_lock, flags);
469 if (!devpriv->mite && reg < 8) {
470 ni_writew(dev, data, reg * 2);
471 } else {
472 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
473 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
474 }
475 spin_unlock_irqrestore(&devpriv->window_lock, flags);
476 }
477 }
478
479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482
483 if (devpriv->is_m_series) {
484 m_series_stc_write(dev, data, reg);
485 } else {
486 ni_stc_writew(dev, data >> 16, reg);
487 ni_stc_writew(dev, data & 0xffff, reg + 1);
488 }
489 }
490
491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
492 {
493 struct ni_private *devpriv = dev->private;
494 unsigned long flags;
495 uint16_t val;
496
497 if (devpriv->is_m_series) {
498 val = m_series_stc_read(dev, reg);
499 } else {
500 spin_lock_irqsave(&devpriv->window_lock, flags);
501 if (!devpriv->mite && reg < 8) {
502 val = ni_readw(dev, reg * 2);
503 } else {
504 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
505 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
506 }
507 spin_unlock_irqrestore(&devpriv->window_lock, flags);
508 }
509 return val;
510 }
511
512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
513 {
514 struct ni_private *devpriv = dev->private;
515 uint32_t val;
516
517 if (devpriv->is_m_series) {
518 val = m_series_stc_read(dev, reg);
519 } else {
520 val = ni_stc_readw(dev, reg) << 16;
521 val |= ni_stc_readw(dev, reg + 1);
522 }
523 return val;
524 }
525
526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
527 unsigned bit_mask, unsigned bit_values)
528 {
529 struct ni_private *devpriv = dev->private;
530 unsigned long flags;
531
532 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
533 switch (reg) {
534 case NISTC_INTA_ENA_REG:
535 devpriv->int_a_enable_reg &= ~bit_mask;
536 devpriv->int_a_enable_reg |= bit_values & bit_mask;
537 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
538 break;
539 case NISTC_INTB_ENA_REG:
540 devpriv->int_b_enable_reg &= ~bit_mask;
541 devpriv->int_b_enable_reg |= bit_values & bit_mask;
542 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
543 break;
544 case NISTC_IO_BIDIR_PIN_REG:
545 devpriv->io_bidirection_pin_reg &= ~bit_mask;
546 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
547 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
548 break;
549 case NI_E_DMA_AI_AO_SEL_REG:
550 devpriv->ai_ao_select_reg &= ~bit_mask;
551 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
552 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
553 break;
554 case NI_E_DMA_G0_G1_SEL_REG:
555 devpriv->g0_g1_select_reg &= ~bit_mask;
556 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
557 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
558 break;
559 default:
560 dev_err(dev->class_dev, "called with invalid register %d\n",
561 reg);
562 break;
563 }
564 mmiowb();
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
566 }
567
568 #ifdef PCIDMA
569 /* DMA channel setup */
570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
571 {
572 if (channel < 4)
573 return 1 << channel;
574 if (channel == 4)
575 return 0x3;
576 if (channel == 5)
577 return 0x5;
578 BUG();
579 return 0;
580 }
581
582 /* negative channel means no channel */
583 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
584 {
585 unsigned bits = 0;
586
587 if (channel >= 0)
588 bits = ni_stc_dma_channel_select_bitfield(channel);
589
590 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
591 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
592 }
593
594 /* negative channel means no channel */
595 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
596 {
597 unsigned bits = 0;
598
599 if (channel >= 0)
600 bits = ni_stc_dma_channel_select_bitfield(channel);
601
602 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
603 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
604 }
605
606 /* negative channel means no channel */
607 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
608 unsigned gpct_index,
609 int channel)
610 {
611 unsigned bits = 0;
612
613 if (channel >= 0)
614 bits = ni_stc_dma_channel_select_bitfield(channel);
615
616 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
617 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
618 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
619 }
620
621 /* negative mite_channel means no channel */
622 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
623 int mite_channel)
624 {
625 struct ni_private *devpriv = dev->private;
626 unsigned long flags;
627 unsigned bits;
628
629 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
630 devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
631 if (mite_channel >= 0) {
632 /*
633 * XXX just guessing ni_stc_dma_channel_select_bitfield()
634 * returns the right bits, under the assumption the cdio dma
635 * selection works just like ai/ao/gpct.
636 * Definitely works for dma channels 0 and 1.
637 */
638 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
639 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
640 }
641 ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
642 mmiowb();
643 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
644 }
645
646 static int ni_request_ai_mite_channel(struct comedi_device *dev)
647 {
648 struct ni_private *devpriv = dev->private;
649 unsigned long flags;
650
651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
652 BUG_ON(devpriv->ai_mite_chan);
653 devpriv->ai_mite_chan =
654 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
655 if (!devpriv->ai_mite_chan) {
656 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
657 dev_err(dev->class_dev,
658 "failed to reserve mite dma channel for analog input\n");
659 return -EBUSY;
660 }
661 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
662 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
664 return 0;
665 }
666
667 static int ni_request_ao_mite_channel(struct comedi_device *dev)
668 {
669 struct ni_private *devpriv = dev->private;
670 unsigned long flags;
671
672 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
673 BUG_ON(devpriv->ao_mite_chan);
674 devpriv->ao_mite_chan =
675 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
676 if (!devpriv->ao_mite_chan) {
677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
678 dev_err(dev->class_dev,
679 "failed to reserve mite dma channel for analog outut\n");
680 return -EBUSY;
681 }
682 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
683 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
684 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
685 return 0;
686 }
687
688 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
689 unsigned gpct_index,
690 enum comedi_io_direction direction)
691 {
692 struct ni_private *devpriv = dev->private;
693 unsigned long flags;
694 struct mite_channel *mite_chan;
695
696 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
697 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
698 mite_chan =
699 mite_request_channel(devpriv->mite,
700 devpriv->gpct_mite_ring[gpct_index]);
701 if (!mite_chan) {
702 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
703 dev_err(dev->class_dev,
704 "failed to reserve mite dma channel for counter\n");
705 return -EBUSY;
706 }
707 mite_chan->dir = direction;
708 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
709 mite_chan);
710 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
711 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
712 return 0;
713 }
714
715 #endif /* PCIDMA */
716
717 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
718 {
719 #ifdef PCIDMA
720 struct ni_private *devpriv = dev->private;
721 unsigned long flags;
722
723 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
724 BUG_ON(devpriv->cdo_mite_chan);
725 devpriv->cdo_mite_chan =
726 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
727 if (!devpriv->cdo_mite_chan) {
728 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
729 dev_err(dev->class_dev,
730 "failed to reserve mite dma channel for correlated digital output\n");
731 return -EBUSY;
732 }
733 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
734 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
735 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
736 #endif /* PCIDMA */
737 return 0;
738 }
739
740 static void ni_release_ai_mite_channel(struct comedi_device *dev)
741 {
742 #ifdef PCIDMA
743 struct ni_private *devpriv = dev->private;
744 unsigned long flags;
745
746 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
747 if (devpriv->ai_mite_chan) {
748 ni_set_ai_dma_channel(dev, -1);
749 mite_release_channel(devpriv->ai_mite_chan);
750 devpriv->ai_mite_chan = NULL;
751 }
752 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
753 #endif /* PCIDMA */
754 }
755
756 static void ni_release_ao_mite_channel(struct comedi_device *dev)
757 {
758 #ifdef PCIDMA
759 struct ni_private *devpriv = dev->private;
760 unsigned long flags;
761
762 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
763 if (devpriv->ao_mite_chan) {
764 ni_set_ao_dma_channel(dev, -1);
765 mite_release_channel(devpriv->ao_mite_chan);
766 devpriv->ao_mite_chan = NULL;
767 }
768 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
769 #endif /* PCIDMA */
770 }
771
772 #ifdef PCIDMA
773 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
774 unsigned gpct_index)
775 {
776 struct ni_private *devpriv = dev->private;
777 unsigned long flags;
778
779 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
780 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
781 struct mite_channel *mite_chan =
782 devpriv->counter_dev->counters[gpct_index].mite_chan;
783
784 ni_set_gpct_dma_channel(dev, gpct_index, -1);
785 ni_tio_set_mite_channel(&devpriv->
786 counter_dev->counters[gpct_index],
787 NULL);
788 mite_release_channel(mite_chan);
789 }
790 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
791 }
792 #endif /* PCIDMA */
793
794 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
795 {
796 #ifdef PCIDMA
797 struct ni_private *devpriv = dev->private;
798 unsigned long flags;
799
800 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
801 if (devpriv->cdo_mite_chan) {
802 ni_set_cdo_dma_channel(dev, -1);
803 mite_release_channel(devpriv->cdo_mite_chan);
804 devpriv->cdo_mite_chan = NULL;
805 }
806 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
807 #endif /* PCIDMA */
808 }
809
810 #ifdef PCIDMA
811 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
812 unsigned gpct_index, short enable)
813 {
814 struct ni_private *devpriv = dev->private;
815 uint16_t val = 0;
816 int reg;
817
818 if (devpriv->is_m_series || gpct_index > 1)
819 return;
820
821 /*
822 * e-series boards use the second irq signals to generate
823 * dma requests for their counters
824 */
825 if (gpct_index == 0) {
826 reg = NISTC_INTA2_ENA_REG;
827 if (enable)
828 val = NISTC_INTA_ENA_G0_GATE;
829 } else {
830 reg = NISTC_INTB2_ENA_REG;
831 if (enable)
832 val = NISTC_INTB_ENA_G1_GATE;
833 }
834 ni_stc_writew(dev, val, reg);
835 }
836 #endif /* PCIDMA */
837
838 static void ni_clear_ai_fifo(struct comedi_device *dev)
839 {
840 struct ni_private *devpriv = dev->private;
841 static const int timeout = 10000;
842 int i;
843
844 if (devpriv->is_6143) {
845 /* Flush the 6143 data FIFO */
846 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
847 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
848 /* Wait for complete */
849 for (i = 0; i < timeout; i++) {
850 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
851 break;
852 udelay(1);
853 }
854 if (i == timeout)
855 dev_err(dev->class_dev, "FIFO flush timeout\n");
856 } else {
857 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
858 if (devpriv->is_625x) {
859 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
860 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
861 #if 0
862 /* the NI example code does 3 convert pulses for 625x boards,
863 but that appears to be wrong in practice. */
864 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
865 NISTC_AI_CMD1_REG);
866 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
867 NISTC_AI_CMD1_REG);
868 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
869 NISTC_AI_CMD1_REG);
870 #endif
871 }
872 }
873 }
874
875 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
876 int addr)
877 {
878 struct ni_private *devpriv = dev->private;
879 unsigned long flags;
880
881 spin_lock_irqsave(&devpriv->window_lock, flags);
882 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
883 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
884 spin_unlock_irqrestore(&devpriv->window_lock, flags);
885 }
886
887 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
888 int addr)
889 {
890 struct ni_private *devpriv = dev->private;
891 unsigned long flags;
892
893 spin_lock_irqsave(&devpriv->window_lock, flags);
894 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
895 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
896 spin_unlock_irqrestore(&devpriv->window_lock, flags);
897 }
898
899 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
900 {
901 struct ni_private *devpriv = dev->private;
902 unsigned long flags;
903 unsigned short data;
904
905 spin_lock_irqsave(&devpriv->window_lock, flags);
906 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
907 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
908 spin_unlock_irqrestore(&devpriv->window_lock, flags);
909 return data;
910 }
911
912 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
913 * share registers (such as Interrupt_A_Register) without interfering with
914 * each other.
915 *
916 * NOTE: the switch/case statements are optimized out for a constant argument
917 * so this is actually quite fast--- If you must wrap another function around this
918 * make it inline to avoid a large speed penalty.
919 *
920 * value should only be 1 or 0.
921 */
922 static inline void ni_set_bits(struct comedi_device *dev, int reg,
923 unsigned bits, unsigned value)
924 {
925 unsigned bit_values;
926
927 if (value)
928 bit_values = bits;
929 else
930 bit_values = 0;
931 ni_set_bitfield(dev, reg, bits, bit_values);
932 }
933
934 #ifdef PCIDMA
935 static void ni_sync_ai_dma(struct comedi_device *dev)
936 {
937 struct ni_private *devpriv = dev->private;
938 struct comedi_subdevice *s = dev->read_subdev;
939 unsigned long flags;
940
941 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
942 if (devpriv->ai_mite_chan)
943 mite_sync_input_dma(devpriv->ai_mite_chan, s);
944 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
945 }
946
947 static int ni_ai_drain_dma(struct comedi_device *dev)
948 {
949 struct ni_private *devpriv = dev->private;
950 int i;
951 static const int timeout = 10000;
952 unsigned long flags;
953 int retval = 0;
954
955 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
956 if (devpriv->ai_mite_chan) {
957 for (i = 0; i < timeout; i++) {
958 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
959 NISTC_AI_STATUS1_FIFO_E)
960 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
961 0)
962 break;
963 udelay(5);
964 }
965 if (i == timeout) {
966 dev_err(dev->class_dev, "timed out\n");
967 dev_err(dev->class_dev,
968 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
969 mite_bytes_in_transit(devpriv->ai_mite_chan),
970 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
971 retval = -1;
972 }
973 }
974 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
975
976 ni_sync_ai_dma(dev);
977
978 return retval;
979 }
980
981 static void mite_handle_b_linkc(struct mite_struct *mite,
982 struct comedi_device *dev)
983 {
984 struct ni_private *devpriv = dev->private;
985 struct comedi_subdevice *s = dev->write_subdev;
986 unsigned long flags;
987
988 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
989 if (devpriv->ao_mite_chan)
990 mite_sync_output_dma(devpriv->ao_mite_chan, s);
991 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
992 }
993
994 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
995 {
996 static const int timeout = 10000;
997 int i;
998
999 for (i = 0; i < timeout; i++) {
1000 unsigned short b_status;
1001
1002 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1003 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1004 break;
1005 /* if we poll too often, the pci bus activity seems
1006 to slow the dma transfer down */
1007 udelay(10);
1008 }
1009 if (i == timeout) {
1010 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1011 return -EPIPE;
1012 }
1013 return 0;
1014 }
1015 #endif /* PCIDMA */
1016
1017 #ifndef PCIDMA
1018
1019 static void ni_ao_fifo_load(struct comedi_device *dev,
1020 struct comedi_subdevice *s, int n)
1021 {
1022 struct ni_private *devpriv = dev->private;
1023 int i;
1024 unsigned short d;
1025 u32 packed_data;
1026
1027 for (i = 0; i < n; i++) {
1028 comedi_buf_read_samples(s, &d, 1);
1029
1030 if (devpriv->is_6xxx) {
1031 packed_data = d & 0xffff;
1032 /* 6711 only has 16 bit wide ao fifo */
1033 if (!devpriv->is_6711) {
1034 comedi_buf_read_samples(s, &d, 1);
1035 i++;
1036 packed_data |= (d << 16) & 0xffff0000;
1037 }
1038 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1039 } else {
1040 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1041 }
1042 }
1043 }
1044
1045 /*
1046 * There's a small problem if the FIFO gets really low and we
1047 * don't have the data to fill it. Basically, if after we fill
1048 * the FIFO with all the data available, the FIFO is _still_
1049 * less than half full, we never clear the interrupt. If the
1050 * IRQ is in edge mode, we never get another interrupt, because
1051 * this one wasn't cleared. If in level mode, we get flooded
1052 * with interrupts that we can't fulfill, because nothing ever
1053 * gets put into the buffer.
1054 *
1055 * This kind of situation is recoverable, but it is easier to
1056 * just pretend we had a FIFO underrun, since there is a good
1057 * chance it will happen anyway. This is _not_ the case for
1058 * RT code, as RT code might purposely be running close to the
1059 * metal. Needs to be fixed eventually.
1060 */
1061 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1062 struct comedi_subdevice *s)
1063 {
1064 const struct ni_board_struct *board = dev->board_ptr;
1065 unsigned int nbytes;
1066 unsigned int nsamples;
1067
1068 nbytes = comedi_buf_read_n_available(s);
1069 if (nbytes == 0) {
1070 s->async->events |= COMEDI_CB_OVERFLOW;
1071 return 0;
1072 }
1073
1074 nsamples = comedi_bytes_to_samples(s, nbytes);
1075 if (nsamples > board->ao_fifo_depth / 2)
1076 nsamples = board->ao_fifo_depth / 2;
1077
1078 ni_ao_fifo_load(dev, s, nsamples);
1079
1080 return 1;
1081 }
1082
1083 static int ni_ao_prep_fifo(struct comedi_device *dev,
1084 struct comedi_subdevice *s)
1085 {
1086 const struct ni_board_struct *board = dev->board_ptr;
1087 struct ni_private *devpriv = dev->private;
1088 unsigned int nbytes;
1089 unsigned int nsamples;
1090
1091 /* reset fifo */
1092 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1093 if (devpriv->is_6xxx)
1094 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1095
1096 /* load some data */
1097 nbytes = comedi_buf_read_n_available(s);
1098 if (nbytes == 0)
1099 return 0;
1100
1101 nsamples = comedi_bytes_to_samples(s, nbytes);
1102 if (nsamples > board->ao_fifo_depth)
1103 nsamples = board->ao_fifo_depth;
1104
1105 ni_ao_fifo_load(dev, s, nsamples);
1106
1107 return nsamples;
1108 }
1109
1110 static void ni_ai_fifo_read(struct comedi_device *dev,
1111 struct comedi_subdevice *s, int n)
1112 {
1113 struct ni_private *devpriv = dev->private;
1114 struct comedi_async *async = s->async;
1115 u32 dl;
1116 unsigned short data;
1117 int i;
1118
1119 if (devpriv->is_611x) {
1120 for (i = 0; i < n / 2; i++) {
1121 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1122 /* This may get the hi/lo data in the wrong order */
1123 data = (dl >> 16) & 0xffff;
1124 comedi_buf_write_samples(s, &data, 1);
1125 data = dl & 0xffff;
1126 comedi_buf_write_samples(s, &data, 1);
1127 }
1128 /* Check if there's a single sample stuck in the FIFO */
1129 if (n % 2) {
1130 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1131 data = dl & 0xffff;
1132 comedi_buf_write_samples(s, &data, 1);
1133 }
1134 } else if (devpriv->is_6143) {
1135 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1136 for (i = 0; i < n / 2; i++) {
1137 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1138
1139 data = (dl >> 16) & 0xffff;
1140 comedi_buf_write_samples(s, &data, 1);
1141 data = dl & 0xffff;
1142 comedi_buf_write_samples(s, &data, 1);
1143 }
1144 if (n % 2) {
1145 /* Assume there is a single sample stuck in the FIFO */
1146 /* Get stranded sample into FIFO */
1147 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1148 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149 data = (dl >> 16) & 0xffff;
1150 comedi_buf_write_samples(s, &data, 1);
1151 }
1152 } else {
1153 if (n > sizeof(devpriv->ai_fifo_buffer) /
1154 sizeof(devpriv->ai_fifo_buffer[0])) {
1155 dev_err(dev->class_dev,
1156 "bug! ai_fifo_buffer too small\n");
1157 async->events |= COMEDI_CB_ERROR;
1158 return;
1159 }
1160 for (i = 0; i < n; i++) {
1161 devpriv->ai_fifo_buffer[i] =
1162 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1163 }
1164 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1165 }
1166 }
1167
1168 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1169 {
1170 const struct ni_board_struct *board = dev->board_ptr;
1171 struct comedi_subdevice *s = dev->read_subdev;
1172 int n;
1173
1174 n = board->ai_fifo_depth / 2;
1175
1176 ni_ai_fifo_read(dev, s, n);
1177 }
1178 #endif
1179
1180 /*
1181 Empties the AI fifo
1182 */
1183 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1184 {
1185 struct ni_private *devpriv = dev->private;
1186 struct comedi_subdevice *s = dev->read_subdev;
1187 u32 dl;
1188 unsigned short data;
1189 unsigned short fifo_empty;
1190 int i;
1191
1192 if (devpriv->is_611x) {
1193 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1194 NISTC_AI_STATUS1_FIFO_E) == 0) {
1195 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1196
1197 /* This may get the hi/lo data in the wrong order */
1198 data = dl >> 16;
1199 comedi_buf_write_samples(s, &data, 1);
1200 data = dl & 0xffff;
1201 comedi_buf_write_samples(s, &data, 1);
1202 }
1203 } else if (devpriv->is_6143) {
1204 i = 0;
1205 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1206 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1207
1208 /* This may get the hi/lo data in the wrong order */
1209 data = dl >> 16;
1210 comedi_buf_write_samples(s, &data, 1);
1211 data = dl & 0xffff;
1212 comedi_buf_write_samples(s, &data, 1);
1213 i += 2;
1214 }
1215 /* Check if stranded sample is present */
1216 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1217 /* Get stranded sample into FIFO */
1218 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1219 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1220 data = (dl >> 16) & 0xffff;
1221 comedi_buf_write_samples(s, &data, 1);
1222 }
1223
1224 } else {
1225 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1226 NISTC_AI_STATUS1_FIFO_E;
1227 while (fifo_empty == 0) {
1228 for (i = 0;
1229 i <
1230 sizeof(devpriv->ai_fifo_buffer) /
1231 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1232 fifo_empty = ni_stc_readw(dev,
1233 NISTC_AI_STATUS1_REG) &
1234 NISTC_AI_STATUS1_FIFO_E;
1235 if (fifo_empty)
1236 break;
1237 devpriv->ai_fifo_buffer[i] =
1238 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1239 }
1240 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1241 }
1242 }
1243 }
1244
1245 static void get_last_sample_611x(struct comedi_device *dev)
1246 {
1247 struct ni_private *devpriv = dev->private;
1248 struct comedi_subdevice *s = dev->read_subdev;
1249 unsigned short data;
1250 u32 dl;
1251
1252 if (!devpriv->is_611x)
1253 return;
1254
1255 /* Check if there's a single sample stuck in the FIFO */
1256 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1257 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1258 data = dl & 0xffff;
1259 comedi_buf_write_samples(s, &data, 1);
1260 }
1261 }
1262
1263 static void get_last_sample_6143(struct comedi_device *dev)
1264 {
1265 struct ni_private *devpriv = dev->private;
1266 struct comedi_subdevice *s = dev->read_subdev;
1267 unsigned short data;
1268 u32 dl;
1269
1270 if (!devpriv->is_6143)
1271 return;
1272
1273 /* Check if there's a single sample stuck in the FIFO */
1274 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1275 /* Get stranded sample into FIFO */
1276 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1277 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1278
1279 /* This may get the hi/lo data in the wrong order */
1280 data = (dl >> 16) & 0xffff;
1281 comedi_buf_write_samples(s, &data, 1);
1282 }
1283 }
1284
1285 static void shutdown_ai_command(struct comedi_device *dev)
1286 {
1287 struct comedi_subdevice *s = dev->read_subdev;
1288
1289 #ifdef PCIDMA
1290 ni_ai_drain_dma(dev);
1291 #endif
1292 ni_handle_fifo_dregs(dev);
1293 get_last_sample_611x(dev);
1294 get_last_sample_6143(dev);
1295
1296 s->async->events |= COMEDI_CB_EOA;
1297 }
1298
1299 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1300 {
1301 struct ni_private *devpriv = dev->private;
1302
1303 if (devpriv->aimode == AIMODE_SCAN) {
1304 #ifdef PCIDMA
1305 static const int timeout = 10;
1306 int i;
1307
1308 for (i = 0; i < timeout; i++) {
1309 ni_sync_ai_dma(dev);
1310 if ((s->async->events & COMEDI_CB_EOS))
1311 break;
1312 udelay(1);
1313 }
1314 #else
1315 ni_handle_fifo_dregs(dev);
1316 s->async->events |= COMEDI_CB_EOS;
1317 #endif
1318 }
1319 /* handle special case of single scan */
1320 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1321 shutdown_ai_command(dev);
1322 }
1323
1324 static void handle_gpct_interrupt(struct comedi_device *dev,
1325 unsigned short counter_index)
1326 {
1327 #ifdef PCIDMA
1328 struct ni_private *devpriv = dev->private;
1329 struct comedi_subdevice *s;
1330
1331 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1332
1333 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1334 s);
1335 comedi_handle_events(dev, s);
1336 #endif
1337 }
1338
1339 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1340 {
1341 unsigned short ack = 0;
1342
1343 if (a_status & NISTC_AI_STATUS1_SC_TC)
1344 ack |= NISTC_INTA_ACK_AI_SC_TC;
1345 if (a_status & NISTC_AI_STATUS1_START1)
1346 ack |= NISTC_INTA_ACK_AI_START1;
1347 if (a_status & NISTC_AI_STATUS1_START)
1348 ack |= NISTC_INTA_ACK_AI_START;
1349 if (a_status & NISTC_AI_STATUS1_STOP)
1350 ack |= NISTC_INTA_ACK_AI_STOP;
1351 if (ack)
1352 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1353 }
1354
1355 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1356 unsigned ai_mite_status)
1357 {
1358 struct comedi_subdevice *s = dev->read_subdev;
1359 struct comedi_cmd *cmd = &s->async->cmd;
1360
1361 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1362 if (s->type == COMEDI_SUBD_UNUSED)
1363 return;
1364
1365 #ifdef PCIDMA
1366 if (ai_mite_status & CHSR_LINKC)
1367 ni_sync_ai_dma(dev);
1368
1369 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1370 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1371 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1372 dev_err(dev->class_dev,
1373 "unknown mite interrupt (ai_mite_status=%08x)\n",
1374 ai_mite_status);
1375 s->async->events |= COMEDI_CB_ERROR;
1376 /* disable_irq(dev->irq); */
1377 }
1378 #endif
1379
1380 /* test for all uncommon interrupt events at the same time */
1381 if (status & (NISTC_AI_STATUS1_ERR |
1382 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1383 if (status == 0xffff) {
1384 dev_err(dev->class_dev, "Card removed?\n");
1385 /* we probably aren't even running a command now,
1386 * so it's a good idea to be careful. */
1387 if (comedi_is_subdevice_running(s)) {
1388 s->async->events |= COMEDI_CB_ERROR;
1389 comedi_handle_events(dev, s);
1390 }
1391 return;
1392 }
1393 if (status & NISTC_AI_STATUS1_ERR) {
1394 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1395 status);
1396
1397 shutdown_ai_command(dev);
1398
1399 s->async->events |= COMEDI_CB_ERROR;
1400 if (status & NISTC_AI_STATUS1_OVER)
1401 s->async->events |= COMEDI_CB_OVERFLOW;
1402
1403 comedi_handle_events(dev, s);
1404 return;
1405 }
1406 if (status & NISTC_AI_STATUS1_SC_TC) {
1407 if (cmd->stop_src == TRIG_COUNT)
1408 shutdown_ai_command(dev);
1409 }
1410 }
1411 #ifndef PCIDMA
1412 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1413 int i;
1414 static const int timeout = 10;
1415 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1416 *fail to get the fifo less than half full, so loop to be sure.*/
1417 for (i = 0; i < timeout; ++i) {
1418 ni_handle_fifo_half_full(dev);
1419 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1420 NISTC_AI_STATUS1_FIFO_HF) == 0)
1421 break;
1422 }
1423 }
1424 #endif /* !PCIDMA */
1425
1426 if (status & NISTC_AI_STATUS1_STOP)
1427 ni_handle_eos(dev, s);
1428
1429 comedi_handle_events(dev, s);
1430 }
1431
1432 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1433 {
1434 unsigned short ack = 0;
1435
1436 if (b_status & NISTC_AO_STATUS1_BC_TC)
1437 ack |= NISTC_INTB_ACK_AO_BC_TC;
1438 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1439 ack |= NISTC_INTB_ACK_AO_ERR;
1440 if (b_status & NISTC_AO_STATUS1_START)
1441 ack |= NISTC_INTB_ACK_AO_START;
1442 if (b_status & NISTC_AO_STATUS1_START1)
1443 ack |= NISTC_INTB_ACK_AO_START1;
1444 if (b_status & NISTC_AO_STATUS1_UC_TC)
1445 ack |= NISTC_INTB_ACK_AO_UC_TC;
1446 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1447 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1448 if (b_status & NISTC_AO_STATUS1_UPDATE)
1449 ack |= NISTC_INTB_ACK_AO_UPDATE;
1450 if (ack)
1451 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1452 }
1453
1454 static void handle_b_interrupt(struct comedi_device *dev,
1455 unsigned short b_status, unsigned ao_mite_status)
1456 {
1457 struct comedi_subdevice *s = dev->write_subdev;
1458 /* unsigned short ack=0; */
1459
1460 #ifdef PCIDMA
1461 /* Currently, mite.c requires us to handle LINKC */
1462 if (ao_mite_status & CHSR_LINKC) {
1463 struct ni_private *devpriv = dev->private;
1464
1465 mite_handle_b_linkc(devpriv->mite, dev);
1466 }
1467
1468 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1469 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1470 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1471 dev_err(dev->class_dev,
1472 "unknown mite interrupt (ao_mite_status=%08x)\n",
1473 ao_mite_status);
1474 s->async->events |= COMEDI_CB_ERROR;
1475 }
1476 #endif
1477
1478 if (b_status == 0xffff)
1479 return;
1480 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1481 dev_err(dev->class_dev,
1482 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1483 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1484 s->async->events |= COMEDI_CB_OVERFLOW;
1485 }
1486
1487 if (b_status & NISTC_AO_STATUS1_BC_TC)
1488 s->async->events |= COMEDI_CB_EOA;
1489
1490 #ifndef PCIDMA
1491 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1492 int ret;
1493
1494 ret = ni_ao_fifo_half_empty(dev, s);
1495 if (!ret) {
1496 dev_err(dev->class_dev, "AO buffer underrun\n");
1497 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1498 NISTC_INTB_ENA_AO_FIFO |
1499 NISTC_INTB_ENA_AO_ERR, 0);
1500 s->async->events |= COMEDI_CB_OVERFLOW;
1501 }
1502 }
1503 #endif
1504
1505 comedi_handle_events(dev, s);
1506 }
1507
1508 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1509 void *data, unsigned int num_bytes,
1510 unsigned int chan_index)
1511 {
1512 struct ni_private *devpriv = dev->private;
1513 struct comedi_async *async = s->async;
1514 struct comedi_cmd *cmd = &async->cmd;
1515 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1516 unsigned short *array = data;
1517 unsigned int *larray = data;
1518 unsigned int i;
1519
1520 for (i = 0; i < nsamples; i++) {
1521 #ifdef PCIDMA
1522 if (s->subdev_flags & SDF_LSAMPL)
1523 larray[i] = le32_to_cpu(larray[i]);
1524 else
1525 array[i] = le16_to_cpu(array[i]);
1526 #endif
1527 if (s->subdev_flags & SDF_LSAMPL)
1528 larray[i] += devpriv->ai_offset[chan_index];
1529 else
1530 array[i] += devpriv->ai_offset[chan_index];
1531 chan_index++;
1532 chan_index %= cmd->chanlist_len;
1533 }
1534 }
1535
1536 #ifdef PCIDMA
1537
1538 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1539 {
1540 struct ni_private *devpriv = dev->private;
1541 struct comedi_subdevice *s = dev->read_subdev;
1542 int retval;
1543 unsigned long flags;
1544
1545 retval = ni_request_ai_mite_channel(dev);
1546 if (retval)
1547 return retval;
1548
1549 /* write alloc the entire buffer */
1550 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1551
1552 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1553 if (!devpriv->ai_mite_chan) {
1554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1555 return -EIO;
1556 }
1557
1558 if (devpriv->is_611x || devpriv->is_6143)
1559 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1560 else if (devpriv->is_628x)
1561 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1562 else
1563 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1564
1565 /*start the MITE */
1566 mite_dma_arm(devpriv->ai_mite_chan);
1567 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1568
1569 return 0;
1570 }
1571
1572 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1573 {
1574 struct ni_private *devpriv = dev->private;
1575 struct comedi_subdevice *s = dev->write_subdev;
1576 int retval;
1577 unsigned long flags;
1578
1579 retval = ni_request_ao_mite_channel(dev);
1580 if (retval)
1581 return retval;
1582
1583 /* read alloc the entire buffer */
1584 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1585
1586 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1587 if (devpriv->ao_mite_chan) {
1588 if (devpriv->is_611x || devpriv->is_6713) {
1589 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1590 } else {
1591 /* doing 32 instead of 16 bit wide transfers from memory
1592 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1593 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1594 }
1595 mite_dma_arm(devpriv->ao_mite_chan);
1596 } else {
1597 retval = -EIO;
1598 }
1599 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1600
1601 return retval;
1602 }
1603
1604 #endif /* PCIDMA */
1605
1606 /*
1607 used for both cancel ioctl and board initialization
1608
1609 this is pretty harsh for a cancel, but it works...
1610 */
1611
1612 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1613 {
1614 struct ni_private *devpriv = dev->private;
1615 unsigned ai_personal;
1616 unsigned ai_out_ctrl;
1617
1618 ni_release_ai_mite_channel(dev);
1619 /* ai configuration */
1620 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1621 NISTC_RESET_REG);
1622
1623 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1624
1625 ni_clear_ai_fifo(dev);
1626
1627 if (!devpriv->is_6143)
1628 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1629
1630 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1631 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1632 NISTC_AI_MODE1_RSVD
1633 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1634 NISTC_AI_MODE1_REG);
1635 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1636 /* generate FIFO interrupts on non-empty */
1637 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1638 NISTC_AI_MODE3_REG);
1639
1640 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1641 NISTC_AI_PERSONAL_SOC_POLARITY |
1642 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1643 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1644 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1645 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1646 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1647 if (devpriv->is_611x) {
1648 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1649 } else if (devpriv->is_6143) {
1650 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1651 } else {
1652 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1653 if (devpriv->is_622x)
1654 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1655 else
1656 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1657 }
1658 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1659 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1660
1661 /* the following registers should not be changed, because there
1662 * are no backup registers in devpriv. If you want to change
1663 * any of these, add a backup register and other appropriate code:
1664 * NISTC_AI_MODE1_REG
1665 * NISTC_AI_MODE3_REG
1666 * NISTC_AI_PERSONAL_REG
1667 * NISTC_AI_OUT_CTRL_REG
1668 */
1669
1670 /* clear interrupts */
1671 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1672
1673 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1674
1675 return 0;
1676 }
1677
1678 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1679 {
1680 unsigned long flags;
1681 int count;
1682
1683 /* lock to avoid race with interrupt handler */
1684 spin_lock_irqsave(&dev->spinlock, flags);
1685 #ifndef PCIDMA
1686 ni_handle_fifo_dregs(dev);
1687 #else
1688 ni_sync_ai_dma(dev);
1689 #endif
1690 count = comedi_buf_n_bytes_ready(s);
1691 spin_unlock_irqrestore(&dev->spinlock, flags);
1692
1693 return count;
1694 }
1695
1696 static void ni_prime_channelgain_list(struct comedi_device *dev)
1697 {
1698 int i;
1699
1700 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1701 for (i = 0; i < NI_TIMEOUT; ++i) {
1702 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1703 NISTC_AI_STATUS1_FIFO_E)) {
1704 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1705 return;
1706 }
1707 udelay(1);
1708 }
1709 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1710 }
1711
1712 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1713 unsigned int n_chan,
1714 unsigned int *list)
1715 {
1716 const struct ni_board_struct *board = dev->board_ptr;
1717 struct ni_private *devpriv = dev->private;
1718 unsigned int chan, range, aref;
1719 unsigned int i;
1720 unsigned int dither;
1721 unsigned range_code;
1722
1723 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1724
1725 if ((list[0] & CR_ALT_SOURCE)) {
1726 unsigned bypass_bits;
1727
1728 chan = CR_CHAN(list[0]);
1729 range = CR_RANGE(list[0]);
1730 range_code = ni_gainlkup[board->gainlkup][range];
1731 dither = (list[0] & CR_ALT_FILTER) != 0;
1732 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1733 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1734 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1735 devpriv->ai_calib_source;
1736 if (dither)
1737 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1738 /* don't use 2's complement encoding */
1739 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1740 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1741 } else {
1742 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1743 }
1744 for (i = 0; i < n_chan; i++) {
1745 unsigned config_bits = 0;
1746
1747 chan = CR_CHAN(list[i]);
1748 aref = CR_AREF(list[i]);
1749 range = CR_RANGE(list[i]);
1750 dither = (list[i] & CR_ALT_FILTER) != 0;
1751
1752 range_code = ni_gainlkup[board->gainlkup][range];
1753 devpriv->ai_offset[i] = 0;
1754 switch (aref) {
1755 case AREF_DIFF:
1756 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1757 break;
1758 case AREF_COMMON:
1759 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1760 break;
1761 case AREF_GROUND:
1762 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1763 break;
1764 case AREF_OTHER:
1765 break;
1766 }
1767 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1768 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1769 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1770 if (i == n_chan - 1)
1771 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1772 if (dither)
1773 config_bits |= NI_M_AI_CFG_DITHER;
1774 /* don't use 2's complement encoding */
1775 config_bits |= NI_M_AI_CFG_POLARITY;
1776 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1777 }
1778 ni_prime_channelgain_list(dev);
1779 }
1780
1781 /*
1782 * Notes on the 6110 and 6111:
1783 * These boards a slightly different than the rest of the series, since
1784 * they have multiple A/D converters.
1785 * From the driver side, the configuration memory is a
1786 * little different.
1787 * Configuration Memory Low:
1788 * bits 15-9: same
1789 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1790 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1791 * 1001 gain=0.1 (+/- 50)
1792 * 1010 0.2
1793 * 1011 0.1
1794 * 0001 1
1795 * 0010 2
1796 * 0011 5
1797 * 0100 10
1798 * 0101 20
1799 * 0110 50
1800 * Configuration Memory High:
1801 * bits 12-14: Channel Type
1802 * 001 for differential
1803 * 000 for calibration
1804 * bit 11: coupling (this is not currently handled)
1805 * 1 AC coupling
1806 * 0 DC coupling
1807 * bits 0-2: channel
1808 * valid channels are 0-3
1809 */
1810 static void ni_load_channelgain_list(struct comedi_device *dev,
1811 struct comedi_subdevice *s,
1812 unsigned int n_chan, unsigned int *list)
1813 {
1814 const struct ni_board_struct *board = dev->board_ptr;
1815 struct ni_private *devpriv = dev->private;
1816 unsigned int offset = (s->maxdata + 1) >> 1;
1817 unsigned int chan, range, aref;
1818 unsigned int i;
1819 unsigned int hi, lo;
1820 unsigned int dither;
1821
1822 if (devpriv->is_m_series) {
1823 ni_m_series_load_channelgain_list(dev, n_chan, list);
1824 return;
1825 }
1826 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1827 if (devpriv->changain_state
1828 && devpriv->changain_spec == list[0]) {
1829 /* ready to go. */
1830 return;
1831 }
1832 devpriv->changain_state = 1;
1833 devpriv->changain_spec = list[0];
1834 } else {
1835 devpriv->changain_state = 0;
1836 }
1837
1838 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1839
1840 /* Set up Calibration mode if required */
1841 if (devpriv->is_6143) {
1842 if ((list[0] & CR_ALT_SOURCE)
1843 && !devpriv->ai_calib_source_enabled) {
1844 /* Strobe Relay enable bit */
1845 ni_writew(dev, devpriv->ai_calib_source |
1846 NI6143_CALIB_CHAN_RELAY_ON,
1847 NI6143_CALIB_CHAN_REG);
1848 ni_writew(dev, devpriv->ai_calib_source,
1849 NI6143_CALIB_CHAN_REG);
1850 devpriv->ai_calib_source_enabled = 1;
1851 msleep_interruptible(100); /* Allow relays to change */
1852 } else if (!(list[0] & CR_ALT_SOURCE)
1853 && devpriv->ai_calib_source_enabled) {
1854 /* Strobe Relay disable bit */
1855 ni_writew(dev, devpriv->ai_calib_source |
1856 NI6143_CALIB_CHAN_RELAY_OFF,
1857 NI6143_CALIB_CHAN_REG);
1858 ni_writew(dev, devpriv->ai_calib_source,
1859 NI6143_CALIB_CHAN_REG);
1860 devpriv->ai_calib_source_enabled = 0;
1861 msleep_interruptible(100); /* Allow relays to change */
1862 }
1863 }
1864
1865 for (i = 0; i < n_chan; i++) {
1866 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1867 chan = devpriv->ai_calib_source;
1868 else
1869 chan = CR_CHAN(list[i]);
1870 aref = CR_AREF(list[i]);
1871 range = CR_RANGE(list[i]);
1872 dither = (list[i] & CR_ALT_FILTER) != 0;
1873
1874 /* fix the external/internal range differences */
1875 range = ni_gainlkup[board->gainlkup][range];
1876 if (devpriv->is_611x)
1877 devpriv->ai_offset[i] = offset;
1878 else
1879 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1880
1881 hi = 0;
1882 if ((list[i] & CR_ALT_SOURCE)) {
1883 if (devpriv->is_611x)
1884 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1885 NI611X_CALIB_CHAN_SEL_REG);
1886 } else {
1887 if (devpriv->is_611x)
1888 aref = AREF_DIFF;
1889 else if (devpriv->is_6143)
1890 aref = AREF_OTHER;
1891 switch (aref) {
1892 case AREF_DIFF:
1893 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1894 break;
1895 case AREF_COMMON:
1896 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1897 break;
1898 case AREF_GROUND:
1899 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1900 break;
1901 case AREF_OTHER:
1902 break;
1903 }
1904 }
1905 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1906
1907 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1908
1909 if (!devpriv->is_6143) {
1910 lo = NI_E_AI_CFG_LO_GAIN(range);
1911
1912 if (i == n_chan - 1)
1913 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1914 if (dither)
1915 lo |= NI_E_AI_CFG_LO_DITHER;
1916
1917 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1918 }
1919 }
1920
1921 /* prime the channel/gain list */
1922 if (!devpriv->is_611x && !devpriv->is_6143)
1923 ni_prime_channelgain_list(dev);
1924 }
1925
1926 static int ni_ai_insn_read(struct comedi_device *dev,
1927 struct comedi_subdevice *s,
1928 struct comedi_insn *insn,
1929 unsigned int *data)
1930 {
1931 struct ni_private *devpriv = dev->private;
1932 unsigned int mask = (s->maxdata + 1) >> 1;
1933 int i, n;
1934 unsigned signbits;
1935 unsigned int d;
1936 unsigned long dl;
1937
1938 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1939
1940 ni_clear_ai_fifo(dev);
1941
1942 signbits = devpriv->ai_offset[0];
1943 if (devpriv->is_611x) {
1944 for (n = 0; n < num_adc_stages_611x; n++) {
1945 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1946 NISTC_AI_CMD1_REG);
1947 udelay(1);
1948 }
1949 for (n = 0; n < insn->n; n++) {
1950 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1951 NISTC_AI_CMD1_REG);
1952 /* The 611x has screwy 32-bit FIFOs. */
1953 d = 0;
1954 for (i = 0; i < NI_TIMEOUT; i++) {
1955 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1956 d = ni_readl(dev,
1957 NI611X_AI_FIFO_DATA_REG);
1958 d >>= 16;
1959 d &= 0xffff;
1960 break;
1961 }
1962 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1963 NISTC_AI_STATUS1_FIFO_E)) {
1964 d = ni_readl(dev,
1965 NI611X_AI_FIFO_DATA_REG);
1966 d &= 0xffff;
1967 break;
1968 }
1969 }
1970 if (i == NI_TIMEOUT) {
1971 dev_err(dev->class_dev, "timeout\n");
1972 return -ETIME;
1973 }
1974 d += signbits;
1975 data[n] = d;
1976 }
1977 } else if (devpriv->is_6143) {
1978 for (n = 0; n < insn->n; n++) {
1979 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1980 NISTC_AI_CMD1_REG);
1981
1982 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1983 dl = 0;
1984 for (i = 0; i < NI_TIMEOUT; i++) {
1985 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1986 0x01) {
1987 /* Get stranded sample into FIFO */
1988 ni_writel(dev, 0x01,
1989 NI6143_AI_FIFO_CTRL_REG);
1990 dl = ni_readl(dev,
1991 NI6143_AI_FIFO_DATA_REG);
1992 break;
1993 }
1994 }
1995 if (i == NI_TIMEOUT) {
1996 dev_err(dev->class_dev, "timeout\n");
1997 return -ETIME;
1998 }
1999 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2000 }
2001 } else {
2002 for (n = 0; n < insn->n; n++) {
2003 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2004 NISTC_AI_CMD1_REG);
2005 for (i = 0; i < NI_TIMEOUT; i++) {
2006 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2007 NISTC_AI_STATUS1_FIFO_E))
2008 break;
2009 }
2010 if (i == NI_TIMEOUT) {
2011 dev_err(dev->class_dev, "timeout\n");
2012 return -ETIME;
2013 }
2014 if (devpriv->is_m_series) {
2015 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2016 dl &= mask;
2017 data[n] = dl;
2018 } else {
2019 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2020 d += signbits; /* subtle: needs to be short addition */
2021 data[n] = d;
2022 }
2023 }
2024 }
2025 return insn->n;
2026 }
2027
2028 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2029 unsigned int flags)
2030 {
2031 struct ni_private *devpriv = dev->private;
2032 int divider;
2033
2034 switch (flags & CMDF_ROUND_MASK) {
2035 case CMDF_ROUND_NEAREST:
2036 default:
2037 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2038 break;
2039 case CMDF_ROUND_DOWN:
2040 divider = (nanosec) / devpriv->clock_ns;
2041 break;
2042 case CMDF_ROUND_UP:
2043 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2044 break;
2045 }
2046 return divider - 1;
2047 }
2048
2049 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2050 {
2051 struct ni_private *devpriv = dev->private;
2052
2053 return devpriv->clock_ns * (timer + 1);
2054 }
2055
2056 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2057 unsigned num_channels)
2058 {
2059 const struct ni_board_struct *board = dev->board_ptr;
2060 struct ni_private *devpriv = dev->private;
2061
2062 /* simultaneously-sampled inputs */
2063 if (devpriv->is_611x || devpriv->is_6143)
2064 return board->ai_speed;
2065
2066 /* multiplexed inputs */
2067 return board->ai_speed * num_channels;
2068 }
2069
2070 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2071 struct comedi_cmd *cmd)
2072 {
2073 const struct ni_board_struct *board = dev->board_ptr;
2074 struct ni_private *devpriv = dev->private;
2075 int err = 0;
2076 unsigned int tmp;
2077 unsigned int sources;
2078
2079 /* Step 1 : check if triggers are trivially valid */
2080
2081 err |= comedi_check_trigger_src(&cmd->start_src,
2082 TRIG_NOW | TRIG_INT | TRIG_EXT);
2083 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2084 TRIG_TIMER | TRIG_EXT);
2085
2086 sources = TRIG_TIMER | TRIG_EXT;
2087 if (devpriv->is_611x || devpriv->is_6143)
2088 sources |= TRIG_NOW;
2089 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2090
2091 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2092 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2093
2094 if (err)
2095 return 1;
2096
2097 /* Step 2a : make sure trigger sources are unique */
2098
2099 err |= comedi_check_trigger_is_unique(cmd->start_src);
2100 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2101 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2102 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2103
2104 /* Step 2b : and mutually compatible */
2105
2106 if (err)
2107 return 2;
2108
2109 /* Step 3: check if arguments are trivially valid */
2110
2111 switch (cmd->start_src) {
2112 case TRIG_NOW:
2113 case TRIG_INT:
2114 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2115 break;
2116 case TRIG_EXT:
2117 tmp = CR_CHAN(cmd->start_arg);
2118
2119 if (tmp > 16)
2120 tmp = 16;
2121 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2122 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2123 break;
2124 }
2125
2126 if (cmd->scan_begin_src == TRIG_TIMER) {
2127 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2128 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2129 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2130 devpriv->clock_ns *
2131 0xffffff);
2132 } else if (cmd->scan_begin_src == TRIG_EXT) {
2133 /* external trigger */
2134 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2135
2136 if (tmp > 16)
2137 tmp = 16;
2138 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2139 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2140 } else { /* TRIG_OTHER */
2141 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2142 }
2143
2144 if (cmd->convert_src == TRIG_TIMER) {
2145 if (devpriv->is_611x || devpriv->is_6143) {
2146 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2147 0);
2148 } else {
2149 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2150 board->ai_speed);
2151 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2152 devpriv->clock_ns *
2153 0xffff);
2154 }
2155 } else if (cmd->convert_src == TRIG_EXT) {
2156 /* external trigger */
2157 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2158
2159 if (tmp > 16)
2160 tmp = 16;
2161 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2162 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2163 } else if (cmd->convert_src == TRIG_NOW) {
2164 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2165 }
2166
2167 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2168 cmd->chanlist_len);
2169
2170 if (cmd->stop_src == TRIG_COUNT) {
2171 unsigned int max_count = 0x01000000;
2172
2173 if (devpriv->is_611x)
2174 max_count -= num_adc_stages_611x;
2175 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2176 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2177 } else {
2178 /* TRIG_NONE */
2179 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2180 }
2181
2182 if (err)
2183 return 3;
2184
2185 /* step 4: fix up any arguments */
2186
2187 if (cmd->scan_begin_src == TRIG_TIMER) {
2188 tmp = cmd->scan_begin_arg;
2189 cmd->scan_begin_arg =
2190 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2191 cmd->scan_begin_arg,
2192 cmd->flags));
2193 if (tmp != cmd->scan_begin_arg)
2194 err++;
2195 }
2196 if (cmd->convert_src == TRIG_TIMER) {
2197 if (!devpriv->is_611x && !devpriv->is_6143) {
2198 tmp = cmd->convert_arg;
2199 cmd->convert_arg =
2200 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2201 cmd->convert_arg,
2202 cmd->flags));
2203 if (tmp != cmd->convert_arg)
2204 err++;
2205 if (cmd->scan_begin_src == TRIG_TIMER &&
2206 cmd->scan_begin_arg <
2207 cmd->convert_arg * cmd->scan_end_arg) {
2208 cmd->scan_begin_arg =
2209 cmd->convert_arg * cmd->scan_end_arg;
2210 err++;
2211 }
2212 }
2213 }
2214
2215 if (err)
2216 return 4;
2217
2218 return 0;
2219 }
2220
2221 static int ni_ai_inttrig(struct comedi_device *dev,
2222 struct comedi_subdevice *s,
2223 unsigned int trig_num)
2224 {
2225 struct ni_private *devpriv = dev->private;
2226 struct comedi_cmd *cmd = &s->async->cmd;
2227
2228 if (trig_num != cmd->start_arg)
2229 return -EINVAL;
2230
2231 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2232 NISTC_AI_CMD2_REG);
2233 s->async->inttrig = NULL;
2234
2235 return 1;
2236 }
2237
2238 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2239 {
2240 struct ni_private *devpriv = dev->private;
2241 const struct comedi_cmd *cmd = &s->async->cmd;
2242 int timer;
2243 int mode1 = 0; /* mode1 is needed for both stop and convert */
2244 int mode2 = 0;
2245 int start_stop_select = 0;
2246 unsigned int stop_count;
2247 int interrupt_a_enable = 0;
2248 unsigned ai_trig;
2249
2250 if (dev->irq == 0) {
2251 dev_err(dev->class_dev, "cannot run command without an irq\n");
2252 return -EIO;
2253 }
2254 ni_clear_ai_fifo(dev);
2255
2256 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2257
2258 /* start configuration */
2259 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2260
2261 /* disable analog triggering for now, since it
2262 * interferes with the use of pfi0 */
2263 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2264 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2265
2266 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2267 switch (cmd->start_src) {
2268 case TRIG_INT:
2269 case TRIG_NOW:
2270 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2271 NISTC_AI_TRIG_START1_SEL(0),
2272 NISTC_AI_TRIG_SEL_REG;
2273 break;
2274 case TRIG_EXT:
2275 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2276 1);
2277
2278 if (cmd->start_arg & CR_INVERT)
2279 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2280 if (cmd->start_arg & CR_EDGE)
2281 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2282 break;
2283 }
2284 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2285
2286 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2287 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2288 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2289 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2290
2291 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2292 /* logic low */
2293 start_stop_select |= NISTC_AI_STOP_POLARITY |
2294 NISTC_AI_STOP_SEL(31) |
2295 NISTC_AI_STOP_SYNC;
2296 } else {
2297 /* ai configuration memory */
2298 start_stop_select |= NISTC_AI_STOP_SEL(19);
2299 }
2300 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2301
2302 devpriv->ai_cmd2 = 0;
2303 switch (cmd->stop_src) {
2304 case TRIG_COUNT:
2305 stop_count = cmd->stop_arg - 1;
2306
2307 if (devpriv->is_611x) {
2308 /* have to take 3 stage adc pipeline into account */
2309 stop_count += num_adc_stages_611x;
2310 }
2311 /* stage number of scans */
2312 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2313
2314 mode1 |= NISTC_AI_MODE1_START_STOP |
2315 NISTC_AI_MODE1_RSVD |
2316 NISTC_AI_MODE1_TRIGGER_ONCE;
2317 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2318 /* load SC (Scan Count) */
2319 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2320
2321 if (stop_count == 0) {
2322 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2323 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2324 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2325 if (cmd->chanlist_len > 1)
2326 start_stop_select |= NISTC_AI_STOP_POLARITY |
2327 NISTC_AI_STOP_EDGE;
2328 }
2329 break;
2330 case TRIG_NONE:
2331 /* stage number of scans */
2332 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2333
2334 mode1 |= NISTC_AI_MODE1_START_STOP |
2335 NISTC_AI_MODE1_RSVD |
2336 NISTC_AI_MODE1_CONTINUOUS;
2337 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2338
2339 /* load SC (Scan Count) */
2340 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2341 break;
2342 }
2343
2344 switch (cmd->scan_begin_src) {
2345 case TRIG_TIMER:
2346 /*
2347 * stop bits for non 611x boards
2348 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2349 * NISTC_AI_MODE2_PRE_TRIGGER=0
2350 * NISTC_AI_START_STOP_REG:
2351 * NISTC_AI_START_POLARITY=0 (?) rising edge
2352 * NISTC_AI_START_EDGE=1 edge triggered
2353 * NISTC_AI_START_SYNC=1 (?)
2354 * NISTC_AI_START_SEL=0 SI_TC
2355 * NISTC_AI_STOP_POLARITY=0 rising edge
2356 * NISTC_AI_STOP_EDGE=0 level
2357 * NISTC_AI_STOP_SYNC=1
2358 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2359 */
2360 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2361 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2362
2363 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2364 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2365 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2366 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2367
2368 /* load SI */
2369 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2370 CMDF_ROUND_NEAREST);
2371 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2372 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2373 break;
2374 case TRIG_EXT:
2375 if (cmd->scan_begin_arg & CR_EDGE)
2376 start_stop_select |= NISTC_AI_START_EDGE;
2377 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2378 start_stop_select |= NISTC_AI_START_POLARITY;
2379 if (cmd->scan_begin_src != cmd->convert_src ||
2380 (cmd->scan_begin_arg & ~CR_EDGE) !=
2381 (cmd->convert_arg & ~CR_EDGE))
2382 start_stop_select |= NISTC_AI_START_SYNC;
2383 start_stop_select |=
2384 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2385 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2386 break;
2387 }
2388
2389 switch (cmd->convert_src) {
2390 case TRIG_TIMER:
2391 case TRIG_NOW:
2392 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2393 timer = 1;
2394 else
2395 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2396 CMDF_ROUND_NEAREST);
2397 /* 0,0 does not work */
2398 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2399 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2400
2401 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2402 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2403 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2404
2405 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2406
2407 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2408 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2409 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2410 break;
2411 case TRIG_EXT:
2412 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2413 if ((cmd->convert_arg & CR_INVERT) == 0)
2414 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2415 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2416
2417 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2418 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2419 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2420
2421 break;
2422 }
2423
2424 if (dev->irq) {
2425 /* interrupt on FIFO, errors, SC_TC */
2426 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2427 NISTC_INTA_ENA_AI_SC_TC;
2428
2429 #ifndef PCIDMA
2430 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2431 #endif
2432
2433 if ((cmd->flags & CMDF_WAKE_EOS) ||
2434 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2435 /* wake on end-of-scan */
2436 devpriv->aimode = AIMODE_SCAN;
2437 } else {
2438 devpriv->aimode = AIMODE_HALF_FULL;
2439 }
2440
2441 switch (devpriv->aimode) {
2442 case AIMODE_HALF_FULL:
2443 /*generate FIFO interrupts and DMA requests on half-full */
2444 #ifdef PCIDMA
2445 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2446 NISTC_AI_MODE3_REG);
2447 #else
2448 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2449 NISTC_AI_MODE3_REG);
2450 #endif
2451 break;
2452 case AIMODE_SAMPLE:
2453 /*generate FIFO interrupts on non-empty */
2454 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2455 NISTC_AI_MODE3_REG);
2456 break;
2457 case AIMODE_SCAN:
2458 #ifdef PCIDMA
2459 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2460 NISTC_AI_MODE3_REG);
2461 #else
2462 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2463 NISTC_AI_MODE3_REG);
2464 #endif
2465 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2466 break;
2467 default:
2468 break;
2469 }
2470
2471 /* clear interrupts */
2472 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2473
2474 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2475 } else {
2476 /* interrupt on nothing */
2477 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2478
2479 /* XXX start polling if necessary */
2480 }
2481
2482 /* end configuration */
2483 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2484
2485 switch (cmd->scan_begin_src) {
2486 case TRIG_TIMER:
2487 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2488 NISTC_AI_CMD1_SI_ARM |
2489 NISTC_AI_CMD1_DIV_ARM |
2490 NISTC_AI_CMD1_SC_ARM,
2491 NISTC_AI_CMD1_REG);
2492 break;
2493 case TRIG_EXT:
2494 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2495 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2496 NISTC_AI_CMD1_DIV_ARM |
2497 NISTC_AI_CMD1_SC_ARM,
2498 NISTC_AI_CMD1_REG);
2499 break;
2500 }
2501
2502 #ifdef PCIDMA
2503 {
2504 int retval = ni_ai_setup_MITE_dma(dev);
2505
2506 if (retval)
2507 return retval;
2508 }
2509 #endif
2510
2511 if (cmd->start_src == TRIG_NOW) {
2512 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2513 devpriv->ai_cmd2,
2514 NISTC_AI_CMD2_REG);
2515 s->async->inttrig = NULL;
2516 } else if (cmd->start_src == TRIG_EXT) {
2517 s->async->inttrig = NULL;
2518 } else { /* TRIG_INT */
2519 s->async->inttrig = ni_ai_inttrig;
2520 }
2521
2522 return 0;
2523 }
2524
2525 static int ni_ai_insn_config(struct comedi_device *dev,
2526 struct comedi_subdevice *s,
2527 struct comedi_insn *insn, unsigned int *data)
2528 {
2529 struct ni_private *devpriv = dev->private;
2530
2531 if (insn->n < 1)
2532 return -EINVAL;
2533
2534 switch (data[0]) {
2535 case INSN_CONFIG_ALT_SOURCE:
2536 if (devpriv->is_m_series) {
2537 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2538 return -EINVAL;
2539 devpriv->ai_calib_source = data[1];
2540 } else if (devpriv->is_6143) {
2541 unsigned int calib_source;
2542
2543 calib_source = data[1] & 0xf;
2544
2545 devpriv->ai_calib_source = calib_source;
2546 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2547 } else {
2548 unsigned int calib_source;
2549 unsigned int calib_source_adjust;
2550
2551 calib_source = data[1] & 0xf;
2552 calib_source_adjust = (data[1] >> 4) & 0xff;
2553
2554 if (calib_source >= 8)
2555 return -EINVAL;
2556 devpriv->ai_calib_source = calib_source;
2557 if (devpriv->is_611x) {
2558 ni_writeb(dev, calib_source_adjust,
2559 NI611X_CAL_GAIN_SEL_REG);
2560 }
2561 }
2562 return 2;
2563 default:
2564 break;
2565 }
2566
2567 return -EINVAL;
2568 }
2569
2570 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2571 void *data, unsigned int num_bytes,
2572 unsigned int chan_index)
2573 {
2574 struct comedi_cmd *cmd = &s->async->cmd;
2575 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2576 unsigned short *array = data;
2577 unsigned int i;
2578
2579 for (i = 0; i < nsamples; i++) {
2580 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2581 unsigned short val = array[i];
2582
2583 /*
2584 * Munge data from unsigned to two's complement for
2585 * bipolar ranges.
2586 */
2587 if (comedi_range_is_bipolar(s, range))
2588 val = comedi_offset_munge(s, val);
2589 #ifdef PCIDMA
2590 val = cpu_to_le16(val);
2591 #endif
2592 array[i] = val;
2593
2594 chan_index++;
2595 chan_index %= cmd->chanlist_len;
2596 }
2597 }
2598
2599 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2600 struct comedi_subdevice *s,
2601 unsigned int chanspec[],
2602 unsigned int n_chans, int timed)
2603 {
2604 struct ni_private *devpriv = dev->private;
2605 unsigned int range;
2606 unsigned int chan;
2607 unsigned int conf;
2608 int i;
2609 int invert = 0;
2610
2611 if (timed) {
2612 for (i = 0; i < s->n_chan; ++i) {
2613 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2614 ni_writeb(dev, devpriv->ao_conf[i],
2615 NI_M_AO_CFG_BANK_REG(i));
2616 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2617 }
2618 }
2619 for (i = 0; i < n_chans; i++) {
2620 const struct comedi_krange *krange;
2621
2622 chan = CR_CHAN(chanspec[i]);
2623 range = CR_RANGE(chanspec[i]);
2624 krange = s->range_table->range + range;
2625 invert = 0;
2626 conf = 0;
2627 switch (krange->max - krange->min) {
2628 case 20000000:
2629 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2630 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2631 break;
2632 case 10000000:
2633 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2634 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2635 break;
2636 case 4000000:
2637 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2638 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2639 NI_M_AO_REF_ATTENUATION_REG(chan));
2640 break;
2641 case 2000000:
2642 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2643 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2644 NI_M_AO_REF_ATTENUATION_REG(chan));
2645 break;
2646 default:
2647 dev_err(dev->class_dev,
2648 "bug! unhandled ao reference voltage\n");
2649 break;
2650 }
2651 switch (krange->max + krange->min) {
2652 case 0:
2653 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2654 break;
2655 case 10000000:
2656 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2657 break;
2658 default:
2659 dev_err(dev->class_dev,
2660 "bug! unhandled ao offset voltage\n");
2661 break;
2662 }
2663 if (timed)
2664 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2665 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2666 devpriv->ao_conf[chan] = conf;
2667 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2668 }
2669 return invert;
2670 }
2671
2672 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2673 struct comedi_subdevice *s,
2674 unsigned int chanspec[],
2675 unsigned int n_chans)
2676 {
2677 struct ni_private *devpriv = dev->private;
2678 unsigned int range;
2679 unsigned int chan;
2680 unsigned int conf;
2681 int i;
2682 int invert = 0;
2683
2684 for (i = 0; i < n_chans; i++) {
2685 chan = CR_CHAN(chanspec[i]);
2686 range = CR_RANGE(chanspec[i]);
2687 conf = NI_E_AO_DACSEL(chan);
2688
2689 if (comedi_range_is_bipolar(s, range)) {
2690 conf |= NI_E_AO_CFG_BIP;
2691 invert = (s->maxdata + 1) >> 1;
2692 } else {
2693 invert = 0;
2694 }
2695 if (comedi_range_is_external(s, range))
2696 conf |= NI_E_AO_EXT_REF;
2697
2698 /* not all boards can deglitch, but this shouldn't hurt */
2699 if (chanspec[i] & CR_DEGLITCH)
2700 conf |= NI_E_AO_DEGLITCH;
2701
2702 /* analog reference */
2703 /* AREF_OTHER connects AO ground to AI ground, i think */
2704 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2705 conf |= NI_E_AO_GROUND_REF;
2706
2707 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2708 devpriv->ao_conf[chan] = conf;
2709 }
2710 return invert;
2711 }
2712
2713 static int ni_ao_config_chanlist(struct comedi_device *dev,
2714 struct comedi_subdevice *s,
2715 unsigned int chanspec[], unsigned int n_chans,
2716 int timed)
2717 {
2718 struct ni_private *devpriv = dev->private;
2719
2720 if (devpriv->is_m_series)
2721 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2722 timed);
2723 else
2724 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2725 }
2726
2727 static int ni_ao_insn_write(struct comedi_device *dev,
2728 struct comedi_subdevice *s,
2729 struct comedi_insn *insn,
2730 unsigned int *data)
2731 {
2732 struct ni_private *devpriv = dev->private;
2733 unsigned int chan = CR_CHAN(insn->chanspec);
2734 unsigned int range = CR_RANGE(insn->chanspec);
2735 int reg;
2736 int i;
2737
2738 if (devpriv->is_6xxx) {
2739 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2740
2741 reg = DACx_Direct_Data_671x(chan);
2742 } else if (devpriv->is_m_series) {
2743 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2744 } else {
2745 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2746 }
2747
2748 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2749
2750 for (i = 0; i < insn->n; i++) {
2751 unsigned int val = data[i];
2752
2753 s->readback[chan] = val;
2754
2755 if (devpriv->is_6xxx) {
2756 /*
2757 * 6xxx boards have bipolar outputs, munge the
2758 * unsigned comedi values to 2's complement
2759 */
2760 val = comedi_offset_munge(s, val);
2761
2762 ni_ao_win_outw(dev, val, reg);
2763 } else if (devpriv->is_m_series) {
2764 /*
2765 * M-series boards use offset binary values for
2766 * bipolar and uinpolar outputs
2767 */
2768 ni_writew(dev, val, reg);
2769 } else {
2770 /*
2771 * Non-M series boards need two's complement values
2772 * for bipolar ranges.
2773 */
2774 if (comedi_range_is_bipolar(s, range))
2775 val = comedi_offset_munge(s, val);
2776
2777 ni_writew(dev, val, reg);
2778 }
2779 }
2780
2781 return insn->n;
2782 }
2783
2784 static int ni_ao_insn_config(struct comedi_device *dev,
2785 struct comedi_subdevice *s,
2786 struct comedi_insn *insn, unsigned int *data)
2787 {
2788 const struct ni_board_struct *board = dev->board_ptr;
2789 struct ni_private *devpriv = dev->private;
2790 unsigned int nbytes;
2791
2792 switch (data[0]) {
2793 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2794 switch (data[1]) {
2795 case COMEDI_OUTPUT:
2796 nbytes = comedi_samples_to_bytes(s,
2797 board->ao_fifo_depth);
2798 data[2] = 1 + nbytes;
2799 if (devpriv->mite)
2800 data[2] += devpriv->mite->fifo_size;
2801 break;
2802 case COMEDI_INPUT:
2803 data[2] = 0;
2804 break;
2805 default:
2806 return -EINVAL;
2807 }
2808 return 0;
2809 default:
2810 break;
2811 }
2812
2813 return -EINVAL;
2814 }
2815
2816 static int ni_ao_inttrig(struct comedi_device *dev,
2817 struct comedi_subdevice *s,
2818 unsigned int trig_num)
2819 {
2820 struct ni_private *devpriv = dev->private;
2821 struct comedi_cmd *cmd = &s->async->cmd;
2822 int ret;
2823 int interrupt_b_bits;
2824 int i;
2825 static const int timeout = 1000;
2826
2827 if (trig_num != cmd->start_arg)
2828 return -EINVAL;
2829
2830 /* Null trig at beginning prevent ao start trigger from executing more than
2831 once per command (and doing things like trying to allocate the ao dma channel
2832 multiple times) */
2833 s->async->inttrig = NULL;
2834
2835 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2836 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2837 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2838 #ifdef PCIDMA
2839 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2840 if (devpriv->is_6xxx)
2841 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2842 ret = ni_ao_setup_MITE_dma(dev);
2843 if (ret)
2844 return ret;
2845 ret = ni_ao_wait_for_dma_load(dev);
2846 if (ret < 0)
2847 return ret;
2848 #else
2849 ret = ni_ao_prep_fifo(dev, s);
2850 if (ret == 0)
2851 return -EPIPE;
2852
2853 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2854 #endif
2855
2856 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2857 NISTC_AO_MODE3_REG);
2858 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2859 /* wait for DACs to be loaded */
2860 for (i = 0; i < timeout; i++) {
2861 udelay(1);
2862 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2863 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2864 break;
2865 }
2866 if (i == timeout) {
2867 dev_err(dev->class_dev,
2868 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2869 return -EIO;
2870 }
2871 /*
2872 * stc manual says we are need to clear error interrupt after
2873 * AO_TMRDACWRs_In_Progress_St clears
2874 */
2875 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2876
2877 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2878
2879 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2880 NISTC_AO_CMD1_UC_ARM |
2881 NISTC_AO_CMD1_BC_ARM |
2882 NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2883 NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2884 devpriv->ao_cmd1,
2885 NISTC_AO_CMD1_REG);
2886
2887 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2888 NISTC_AO_CMD2_REG);
2889
2890 return 0;
2891 }
2892
2893 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2894 {
2895 const struct ni_board_struct *board = dev->board_ptr;
2896 struct ni_private *devpriv = dev->private;
2897 const struct comedi_cmd *cmd = &s->async->cmd;
2898 int bits;
2899 int i;
2900 unsigned trigvar;
2901 unsigned val;
2902
2903 if (dev->irq == 0) {
2904 dev_err(dev->class_dev, "cannot run command without an irq\n");
2905 return -EIO;
2906 }
2907
2908 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2909
2910 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2911
2912 if (devpriv->is_6xxx) {
2913 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
2914
2915 bits = 0;
2916 for (i = 0; i < cmd->chanlist_len; i++) {
2917 int chan;
2918
2919 chan = CR_CHAN(cmd->chanlist[i]);
2920 bits |= 1 << chan;
2921 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
2922 }
2923 ni_ao_win_outw(dev, bits, AO_Timed_611x);
2924 }
2925
2926 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2927
2928 if (cmd->stop_src == TRIG_NONE) {
2929 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2930 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2931 } else {
2932 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2933 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2934 }
2935 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2936
2937 val = devpriv->ao_trigger_select;
2938 switch (cmd->start_src) {
2939 case TRIG_INT:
2940 case TRIG_NOW:
2941 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2942 NISTC_AO_TRIG_START1_SEL_MASK);
2943 val |= NISTC_AO_TRIG_START1_EDGE |
2944 NISTC_AO_TRIG_START1_SYNC;
2945 break;
2946 case TRIG_EXT:
2947 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2948 if (cmd->start_arg & CR_INVERT) {
2949 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2950 val |= NISTC_AO_TRIG_START1_POLARITY;
2951 }
2952 if (cmd->start_arg & CR_EDGE) {
2953 /* 0=edge detection disabled, 1=enabled */
2954 val |= NISTC_AO_TRIG_START1_EDGE;
2955 }
2956 ni_stc_writew(dev, devpriv->ao_trigger_select,
2957 NISTC_AO_TRIG_SEL_REG);
2958 break;
2959 default:
2960 BUG();
2961 break;
2962 }
2963 devpriv->ao_trigger_select = val;
2964 ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2965
2966 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2967 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2968
2969 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2970 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2971 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2972 if (cmd->stop_src == TRIG_NONE)
2973 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2974 else
2975 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2976 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2977 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2978 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2979 switch (cmd->stop_src) {
2980 case TRIG_COUNT:
2981 if (devpriv->is_m_series) {
2982 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
2983 ni_stc_writel(dev, cmd->stop_arg - 1,
2984 NISTC_AO_UC_LOADA_REG);
2985 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2986 NISTC_AO_CMD1_REG);
2987 } else {
2988 ni_stc_writel(dev, cmd->stop_arg,
2989 NISTC_AO_UC_LOADA_REG);
2990 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2991 NISTC_AO_CMD1_REG);
2992 ni_stc_writel(dev, cmd->stop_arg - 1,
2993 NISTC_AO_UC_LOADA_REG);
2994 }
2995 break;
2996 case TRIG_NONE:
2997 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2998 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
2999 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3000 break;
3001 default:
3002 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3003 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3004 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3005 }
3006
3007 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3008 NISTC_AO_MODE1_UI_SRC_MASK |
3009 NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3010 NISTC_AO_MODE1_UI_SRC_POLARITY);
3011 switch (cmd->scan_begin_src) {
3012 case TRIG_TIMER:
3013 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3014 trigvar =
3015 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3016 CMDF_ROUND_NEAREST);
3017 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3018 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3019 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3020 break;
3021 case TRIG_EXT:
3022 devpriv->ao_mode1 |=
3023 NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3024 if (cmd->scan_begin_arg & CR_INVERT)
3025 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3026 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3027 break;
3028 default:
3029 BUG();
3030 break;
3031 }
3032 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3033 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3034 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3035 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3036 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3037
3038 if (cmd->scan_end_arg > 1) {
3039 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3040 ni_stc_writew(dev,
3041 NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3042 NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3043 NISTC_AO_OUT_CTRL_REG);
3044 } else {
3045 unsigned bits;
3046
3047 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3048 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3049 if (devpriv->is_m_series || devpriv->is_6xxx) {
3050 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3051 } else {
3052 bits |=
3053 NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3054 }
3055 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3056 }
3057 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3058
3059 ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3060 NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3061 NISTC_AO_CMD1_REG);
3062
3063 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3064 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3065
3066 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3067 #ifdef PCIDMA
3068 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3069 #else
3070 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3071 #endif
3072 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3073 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3074
3075 bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3076 NISTC_AO_PERSONAL_UPDATE_PW |
3077 NISTC_AO_PERSONAL_TMRDACWR_PW;
3078 if (board->ao_fifo_depth)
3079 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3080 else
3081 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3082 #if 0
3083 /*
3084 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3085 * for 6281, verified with bus analyzer.
3086 */
3087 if (devpriv->is_m_series)
3088 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3089 #endif
3090 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3091 /* enable sending of ao dma requests */
3092 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3093
3094 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3095
3096 if (cmd->stop_src == TRIG_COUNT) {
3097 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3098 NISTC_INTB_ACK_REG);
3099 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3100 NISTC_INTB_ENA_AO_BC_TC, 1);
3101 }
3102
3103 s->async->inttrig = ni_ao_inttrig;
3104
3105 return 0;
3106 }
3107
3108 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3109 struct comedi_cmd *cmd)
3110 {
3111 const struct ni_board_struct *board = dev->board_ptr;
3112 struct ni_private *devpriv = dev->private;
3113 int err = 0;
3114 unsigned int tmp;
3115
3116 /* Step 1 : check if triggers are trivially valid */
3117
3118 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3119 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3120 TRIG_TIMER | TRIG_EXT);
3121 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3122 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3123 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3124
3125 if (err)
3126 return 1;
3127
3128 /* Step 2a : make sure trigger sources are unique */
3129
3130 err |= comedi_check_trigger_is_unique(cmd->start_src);
3131 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3132 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3133
3134 /* Step 2b : and mutually compatible */
3135
3136 if (err)
3137 return 2;
3138
3139 /* Step 3: check if arguments are trivially valid */
3140
3141 switch (cmd->start_src) {
3142 case TRIG_INT:
3143 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3144 break;
3145 case TRIG_EXT:
3146 tmp = CR_CHAN(cmd->start_arg);
3147
3148 if (tmp > 18)
3149 tmp = 18;
3150 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3151 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3152 break;
3153 }
3154
3155 if (cmd->scan_begin_src == TRIG_TIMER) {
3156 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3157 board->ao_speed);
3158 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3159 devpriv->clock_ns *
3160 0xffffff);
3161 }
3162
3163 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3164 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3165 cmd->chanlist_len);
3166
3167 if (cmd->stop_src == TRIG_COUNT)
3168 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3169 else /* TRIG_NONE */
3170 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3171
3172 if (err)
3173 return 3;
3174
3175 /* step 4: fix up any arguments */
3176 if (cmd->scan_begin_src == TRIG_TIMER) {
3177 tmp = cmd->scan_begin_arg;
3178 cmd->scan_begin_arg =
3179 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3180 cmd->scan_begin_arg,
3181 cmd->flags));
3182 if (tmp != cmd->scan_begin_arg)
3183 err++;
3184 }
3185 if (err)
3186 return 4;
3187
3188 return 0;
3189 }
3190
3191 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3192 {
3193 struct ni_private *devpriv = dev->private;
3194
3195 ni_release_ao_mite_channel(dev);
3196
3197 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3198 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3199 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3200 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3201 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3202 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3203 NISTC_AO_PERSONAL_UPDATE_PW |
3204 NISTC_AO_PERSONAL_TMRDACWR_PW,
3205 NISTC_AO_PERSONAL_REG);
3206 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3207 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3208 devpriv->ao_cmd1 = 0;
3209 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3210 devpriv->ao_cmd2 = 0;
3211 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3212 devpriv->ao_mode1 = 0;
3213 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3214 devpriv->ao_mode2 = 0;
3215 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3216 if (devpriv->is_m_series)
3217 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3218 else
3219 devpriv->ao_mode3 = 0;
3220 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3221 devpriv->ao_trigger_select = 0;
3222 ni_stc_writew(dev, devpriv->ao_trigger_select,
3223 NISTC_AO_TRIG_SEL_REG);
3224 if (devpriv->is_6xxx) {
3225 unsigned immediate_bits = 0;
3226 unsigned i;
3227
3228 for (i = 0; i < s->n_chan; ++i)
3229 immediate_bits |= 1 << i;
3230 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3231 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3232 }
3233 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3234
3235 return 0;
3236 }
3237
3238 /* digital io */
3239
3240 static int ni_dio_insn_config(struct comedi_device *dev,
3241 struct comedi_subdevice *s,
3242 struct comedi_insn *insn,
3243 unsigned int *data)
3244 {
3245 struct ni_private *devpriv = dev->private;
3246 int ret;
3247
3248 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3249 if (ret)
3250 return ret;
3251
3252 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3253 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3254 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3255
3256 return insn->n;
3257 }
3258
3259 static int ni_dio_insn_bits(struct comedi_device *dev,
3260 struct comedi_subdevice *s,
3261 struct comedi_insn *insn,
3262 unsigned int *data)
3263 {
3264 struct ni_private *devpriv = dev->private;
3265
3266 /* Make sure we're not using the serial part of the dio */
3267 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3268 devpriv->serial_interval_ns)
3269 return -EBUSY;
3270
3271 if (comedi_dio_update_state(s, data)) {
3272 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3273 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3274 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3275 }
3276
3277 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3278
3279 return insn->n;
3280 }
3281
3282 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3283 struct comedi_subdevice *s,
3284 struct comedi_insn *insn,
3285 unsigned int *data)
3286 {
3287 int ret;
3288
3289 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3290 if (ret)
3291 return ret;
3292
3293 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3294
3295 return insn->n;
3296 }
3297
3298 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3299 struct comedi_subdevice *s,
3300 struct comedi_insn *insn,
3301 unsigned int *data)
3302 {
3303 if (comedi_dio_update_state(s, data))
3304 ni_writel(dev, s->state, NI_M_DIO_REG);
3305
3306 data[1] = ni_readl(dev, NI_M_DIO_REG);
3307
3308 return insn->n;
3309 }
3310
3311 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3312 struct comedi_subdevice *s,
3313 struct comedi_cmd *cmd)
3314 {
3315 int i;
3316
3317 for (i = 0; i < cmd->chanlist_len; ++i) {
3318 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3319
3320 if (chan != i)
3321 return -EINVAL;
3322 }
3323
3324 return 0;
3325 }
3326
3327 static int ni_cdio_cmdtest(struct comedi_device *dev,
3328 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3329 {
3330 int err = 0;
3331 int tmp;
3332
3333 /* Step 1 : check if triggers are trivially valid */
3334
3335 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3336 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3337 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3338 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3339 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3340
3341 if (err)
3342 return 1;
3343
3344 /* Step 2a : make sure trigger sources are unique */
3345 /* Step 2b : and mutually compatible */
3346
3347 /* Step 3: check if arguments are trivially valid */
3348
3349 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3350
3351 tmp = cmd->scan_begin_arg;
3352 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3353 if (tmp != cmd->scan_begin_arg)
3354 err |= -EINVAL;
3355
3356 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3357 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3358 cmd->chanlist_len);
3359 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3360
3361 if (err)
3362 return 3;
3363
3364 /* Step 4: fix up any arguments */
3365
3366 /* Step 5: check channel list if it exists */
3367
3368 if (cmd->chanlist && cmd->chanlist_len > 0)
3369 err |= ni_cdio_check_chanlist(dev, s, cmd);
3370
3371 if (err)
3372 return 5;
3373
3374 return 0;
3375 }
3376
3377 static int ni_cdo_inttrig(struct comedi_device *dev,
3378 struct comedi_subdevice *s,
3379 unsigned int trig_num)
3380 {
3381 struct comedi_cmd *cmd = &s->async->cmd;
3382 const unsigned timeout = 1000;
3383 int retval = 0;
3384 unsigned i;
3385 #ifdef PCIDMA
3386 struct ni_private *devpriv = dev->private;
3387 unsigned long flags;
3388 #endif
3389
3390 if (trig_num != cmd->start_arg)
3391 return -EINVAL;
3392
3393 s->async->inttrig = NULL;
3394
3395 /* read alloc the entire buffer */
3396 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3397
3398 #ifdef PCIDMA
3399 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3400 if (devpriv->cdo_mite_chan) {
3401 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3402 mite_dma_arm(devpriv->cdo_mite_chan);
3403 } else {
3404 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3405 retval = -EIO;
3406 }
3407 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3408 if (retval < 0)
3409 return retval;
3410 #endif
3411 /*
3412 * XXX not sure what interrupt C group does
3413 * wait for dma to fill output fifo
3414 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3415 */
3416 for (i = 0; i < timeout; ++i) {
3417 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3418 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3419 break;
3420 udelay(10);
3421 }
3422 if (i == timeout) {
3423 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3424 s->cancel(dev, s);
3425 return -EIO;
3426 }
3427 ni_writel(dev, NI_M_CDO_CMD_ARM |
3428 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3429 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3430 NI_M_CDIO_CMD_REG);
3431 return retval;
3432 }
3433
3434 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3435 {
3436 const struct comedi_cmd *cmd = &s->async->cmd;
3437 unsigned cdo_mode_bits;
3438 int retval;
3439
3440 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3441 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3442 NI_M_CDO_MODE_HALT_ON_ERROR |
3443 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3444 if (cmd->scan_begin_arg & CR_INVERT)
3445 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3446 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3447 if (s->io_bits) {
3448 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3449 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3450 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3451 } else {
3452 dev_err(dev->class_dev,
3453 "attempted to run digital output command with no lines configured as outputs\n");
3454 return -EIO;
3455 }
3456 retval = ni_request_cdo_mite_channel(dev);
3457 if (retval < 0)
3458 return retval;
3459
3460 s->async->inttrig = ni_cdo_inttrig;
3461
3462 return 0;
3463 }
3464
3465 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3466 {
3467 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3468 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3469 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3470 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3471 NI_M_CDIO_CMD_REG);
3472 /*
3473 * XXX not sure what interrupt C group does
3474 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3475 */
3476 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3477 ni_release_cdo_mite_channel(dev);
3478 return 0;
3479 }
3480
3481 static void handle_cdio_interrupt(struct comedi_device *dev)
3482 {
3483 struct ni_private *devpriv = dev->private;
3484 unsigned cdio_status;
3485 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3486 #ifdef PCIDMA
3487 unsigned long flags;
3488 #endif
3489
3490 if (!devpriv->is_m_series)
3491 return;
3492 #ifdef PCIDMA
3493 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3494 if (devpriv->cdo_mite_chan) {
3495 unsigned cdo_mite_status =
3496 mite_get_status(devpriv->cdo_mite_chan);
3497 if (cdo_mite_status & CHSR_LINKC) {
3498 writel(CHOR_CLRLC,
3499 devpriv->mite->mite_io_addr +
3500 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3501 }
3502 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3503 }
3504 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3505 #endif
3506
3507 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3508 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3509 /* XXX just guessing this is needed and does something useful */
3510 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3511 NI_M_CDIO_CMD_REG);
3512 s->async->events |= COMEDI_CB_OVERFLOW;
3513 }
3514 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3515 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3516 NI_M_CDIO_CMD_REG);
3517 /* s->async->events |= COMEDI_CB_EOA; */
3518 }
3519 comedi_handle_events(dev, s);
3520 }
3521
3522 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3523 struct comedi_subdevice *s,
3524 unsigned char data_out,
3525 unsigned char *data_in)
3526 {
3527 struct ni_private *devpriv = dev->private;
3528 unsigned int status1;
3529 int err = 0, count = 20;
3530
3531 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3532 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3533 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3534
3535 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3536 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3537 err = -EBUSY;
3538 goto Error;
3539 }
3540
3541 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3542 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3543 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3544
3545 /* Wait until STC says we're done, but don't loop infinitely. */
3546 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3547 NISTC_STATUS1_SERIO_IN_PROG) {
3548 /* Delay one bit per loop */
3549 udelay((devpriv->serial_interval_ns + 999) / 1000);
3550 if (--count < 0) {
3551 dev_err(dev->class_dev,
3552 "SPI serial I/O didn't finish in time!\n");
3553 err = -ETIME;
3554 goto Error;
3555 }
3556 }
3557
3558 /*
3559 * Delay for last bit. This delay is absolutely necessary, because
3560 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3561 */
3562 udelay((devpriv->serial_interval_ns + 999) / 1000);
3563
3564 if (data_in)
3565 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3566
3567 Error:
3568 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3569
3570 return err;
3571 }
3572
3573 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3574 struct comedi_subdevice *s,
3575 unsigned char data_out,
3576 unsigned char *data_in)
3577 {
3578 struct ni_private *devpriv = dev->private;
3579 unsigned char mask, input = 0;
3580
3581 /* Wait for one bit before transfer */
3582 udelay((devpriv->serial_interval_ns + 999) / 1000);
3583
3584 for (mask = 0x80; mask; mask >>= 1) {
3585 /* Output current bit; note that we cannot touch s->state
3586 because it is a per-subdevice field, and serial is
3587 a separate subdevice from DIO. */
3588 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3589 if (data_out & mask)
3590 devpriv->dio_output |= NISTC_DIO_SDOUT;
3591 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3592
3593 /* Assert SDCLK (active low, inverted), wait for half of
3594 the delay, deassert SDCLK, and wait for the other half. */
3595 devpriv->dio_control |= NISTC_DIO_SDCLK;
3596 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3597
3598 udelay((devpriv->serial_interval_ns + 999) / 2000);
3599
3600 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3601 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3602
3603 udelay((devpriv->serial_interval_ns + 999) / 2000);
3604
3605 /* Input current bit */
3606 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3607 input |= mask;
3608 }
3609
3610 if (data_in)
3611 *data_in = input;
3612
3613 return 0;
3614 }
3615
3616 static int ni_serial_insn_config(struct comedi_device *dev,
3617 struct comedi_subdevice *s,
3618 struct comedi_insn *insn,
3619 unsigned int *data)
3620 {
3621 struct ni_private *devpriv = dev->private;
3622 unsigned clk_fout = devpriv->clock_and_fout;
3623 int err = insn->n;
3624 unsigned char byte_out, byte_in = 0;
3625
3626 if (insn->n != 2)
3627 return -EINVAL;
3628
3629 switch (data[0]) {
3630 case INSN_CONFIG_SERIAL_CLOCK:
3631 devpriv->serial_hw_mode = 1;
3632 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3633
3634 if (data[1] == SERIAL_DISABLED) {
3635 devpriv->serial_hw_mode = 0;
3636 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3637 NISTC_DIO_SDCLK);
3638 data[1] = SERIAL_DISABLED;
3639 devpriv->serial_interval_ns = data[1];
3640 } else if (data[1] <= SERIAL_600NS) {
3641 /* Warning: this clock speed is too fast to reliably
3642 control SCXI. */
3643 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3644 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3645 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3646 data[1] = SERIAL_600NS;
3647 devpriv->serial_interval_ns = data[1];
3648 } else if (data[1] <= SERIAL_1_2US) {
3649 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3650 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3651 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3652 data[1] = SERIAL_1_2US;
3653 devpriv->serial_interval_ns = data[1];
3654 } else if (data[1] <= SERIAL_10US) {
3655 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3656 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3657 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3658 /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3659 600ns/1.2us. If you turn divide_by_2 off with the
3660 slow clock, you will still get 10us, except then
3661 all your delays are wrong. */
3662 data[1] = SERIAL_10US;
3663 devpriv->serial_interval_ns = data[1];
3664 } else {
3665 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3666 NISTC_DIO_SDCLK);
3667 devpriv->serial_hw_mode = 0;
3668 data[1] = (data[1] / 1000) * 1000;
3669 devpriv->serial_interval_ns = data[1];
3670 }
3671 devpriv->clock_and_fout = clk_fout;
3672
3673 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3674 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3675 return 1;
3676
3677 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3678
3679 if (devpriv->serial_interval_ns == 0)
3680 return -EINVAL;
3681
3682 byte_out = data[1] & 0xFF;
3683
3684 if (devpriv->serial_hw_mode) {
3685 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3686 &byte_in);
3687 } else if (devpriv->serial_interval_ns > 0) {
3688 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3689 &byte_in);
3690 } else {
3691 dev_err(dev->class_dev, "serial disabled!\n");
3692 return -EINVAL;
3693 }
3694 if (err < 0)
3695 return err;
3696 data[1] = byte_in & 0xFF;
3697 return insn->n;
3698
3699 break;
3700 default:
3701 return -EINVAL;
3702 }
3703 }
3704
3705 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3706 {
3707 int i;
3708
3709 for (i = 0; i < s->n_chan; i++) {
3710 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3711 AO_Configuration_2_67xx);
3712 }
3713 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3714 }
3715
3716 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3717 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3718 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3719 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3720 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3721 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3722 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3723 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3724 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3725 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3726 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3727 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3728 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3729 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3730 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3731 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3732 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3733 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3734 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3735 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3736 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3737 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3738 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3739 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3740 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3741 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3742 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3743 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3744 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3745 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3746 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3747 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3748 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3749 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3750 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3751 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3752 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3753 };
3754
3755 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3756 enum ni_gpct_register reg)
3757 {
3758 const struct mio_regmap *regmap;
3759
3760 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3761 regmap = &ni_gpct_to_stc_regmap[reg];
3762 } else {
3763 dev_warn(dev->class_dev,"%s: unhandled register 0x%x\n",
3764 __func__, reg);
3765 return 0;
3766 }
3767
3768 return regmap->mio_reg;
3769 }
3770
3771 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3772 enum ni_gpct_register reg)
3773 {
3774 struct comedi_device *dev = counter->counter_dev->dev;
3775 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3776 static const unsigned gpct_interrupt_a_enable_mask =
3777 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3778 static const unsigned gpct_interrupt_b_enable_mask =
3779 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3780
3781 if (stc_register == 0)
3782 return;
3783
3784 switch (reg) {
3785 /* m-series only registers */
3786 case NITIO_G0_CNT_MODE:
3787 case NITIO_G1_CNT_MODE:
3788 case NITIO_G0_GATE2:
3789 case NITIO_G1_GATE2:
3790 case NITIO_G0_DMA_CFG:
3791 case NITIO_G1_DMA_CFG:
3792 case NITIO_G0_ABZ:
3793 case NITIO_G1_ABZ:
3794 ni_writew(dev, bits, stc_register);
3795 break;
3796
3797 /* 32 bit registers */
3798 case NITIO_G0_LOADA:
3799 case NITIO_G1_LOADA:
3800 case NITIO_G0_LOADB:
3801 case NITIO_G1_LOADB:
3802 ni_stc_writel(dev, bits, stc_register);
3803 break;
3804
3805 /* 16 bit registers */
3806 case NITIO_G0_INT_ENA:
3807 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3808 ni_set_bitfield(dev, stc_register,
3809 gpct_interrupt_a_enable_mask, bits);
3810 break;
3811 case NITIO_G1_INT_ENA:
3812 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3813 ni_set_bitfield(dev, stc_register,
3814 gpct_interrupt_b_enable_mask, bits);
3815 break;
3816 case NITIO_G01_RESET:
3817 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3818 /* fall-through */
3819 default:
3820 ni_stc_writew(dev, bits, stc_register);
3821 }
3822 }
3823
3824 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3825 enum ni_gpct_register reg)
3826 {
3827 struct comedi_device *dev = counter->counter_dev->dev;
3828 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3829
3830 if (stc_register == 0)
3831 return 0;
3832
3833 switch (reg) {
3834 /* m-series only registers */
3835 case NITIO_G0_DMA_STATUS:
3836 case NITIO_G1_DMA_STATUS:
3837 return ni_readw(dev, stc_register);
3838
3839 /* 32 bit registers */
3840 case NITIO_G0_HW_SAVE:
3841 case NITIO_G1_HW_SAVE:
3842 case NITIO_G0_SW_SAVE:
3843 case NITIO_G1_SW_SAVE:
3844 return ni_stc_readl(dev, stc_register);
3845
3846 /* 16 bit registers */
3847 default:
3848 return ni_stc_readw(dev, stc_register);
3849 }
3850 }
3851
3852 static int ni_freq_out_insn_read(struct comedi_device *dev,
3853 struct comedi_subdevice *s,
3854 struct comedi_insn *insn,
3855 unsigned int *data)
3856 {
3857 struct ni_private *devpriv = dev->private;
3858 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3859 int i;
3860
3861 for (i = 0; i < insn->n; i++)
3862 data[i] = val;
3863
3864 return insn->n;
3865 }
3866
3867 static int ni_freq_out_insn_write(struct comedi_device *dev,
3868 struct comedi_subdevice *s,
3869 struct comedi_insn *insn,
3870 unsigned int *data)
3871 {
3872 struct ni_private *devpriv = dev->private;
3873
3874 if (insn->n) {
3875 unsigned int val = data[insn->n - 1];
3876
3877 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3878 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3879 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3880
3881 /* use the last data value to set the fout divider */
3882 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3883
3884 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3885 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3886 }
3887 return insn->n;
3888 }
3889
3890 static int ni_freq_out_insn_config(struct comedi_device *dev,
3891 struct comedi_subdevice *s,
3892 struct comedi_insn *insn,
3893 unsigned int *data)
3894 {
3895 struct ni_private *devpriv = dev->private;
3896
3897 switch (data[0]) {
3898 case INSN_CONFIG_SET_CLOCK_SRC:
3899 switch (data[1]) {
3900 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3901 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3902 break;
3903 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3904 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3905 break;
3906 default:
3907 return -EINVAL;
3908 }
3909 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3910 break;
3911 case INSN_CONFIG_GET_CLOCK_SRC:
3912 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3913 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3914 data[2] = TIMEBASE_2_NS;
3915 } else {
3916 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3917 data[2] = TIMEBASE_1_NS * 2;
3918 }
3919 break;
3920 default:
3921 return -EINVAL;
3922 }
3923 return insn->n;
3924 }
3925
3926 static int ni_8255_callback(struct comedi_device *dev,
3927 int dir, int port, int data, unsigned long iobase)
3928 {
3929 if (dir) {
3930 ni_writeb(dev, data, iobase + 2 * port);
3931 return 0;
3932 }
3933
3934 return ni_readb(dev, iobase + 2 * port);
3935 }
3936
3937 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3938 {
3939 struct ni_private *devpriv = dev->private;
3940
3941 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3942 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3943 return 3;
3944 }
3945
3946 static int ni_m_series_pwm_config(struct comedi_device *dev,
3947 struct comedi_subdevice *s,
3948 struct comedi_insn *insn,
3949 unsigned int *data)
3950 {
3951 struct ni_private *devpriv = dev->private;
3952 unsigned up_count, down_count;
3953
3954 switch (data[0]) {
3955 case INSN_CONFIG_PWM_OUTPUT:
3956 switch (data[1]) {
3957 case CMDF_ROUND_NEAREST:
3958 up_count =
3959 (data[2] +
3960 devpriv->clock_ns / 2) / devpriv->clock_ns;
3961 break;
3962 case CMDF_ROUND_DOWN:
3963 up_count = data[2] / devpriv->clock_ns;
3964 break;
3965 case CMDF_ROUND_UP:
3966 up_count =
3967 (data[2] + devpriv->clock_ns -
3968 1) / devpriv->clock_ns;
3969 break;
3970 default:
3971 return -EINVAL;
3972 }
3973 switch (data[3]) {
3974 case CMDF_ROUND_NEAREST:
3975 down_count =
3976 (data[4] +
3977 devpriv->clock_ns / 2) / devpriv->clock_ns;
3978 break;
3979 case CMDF_ROUND_DOWN:
3980 down_count = data[4] / devpriv->clock_ns;
3981 break;
3982 case CMDF_ROUND_UP:
3983 down_count =
3984 (data[4] + devpriv->clock_ns -
3985 1) / devpriv->clock_ns;
3986 break;
3987 default:
3988 return -EINVAL;
3989 }
3990 if (up_count * devpriv->clock_ns != data[2] ||
3991 down_count * devpriv->clock_ns != data[4]) {
3992 data[2] = up_count * devpriv->clock_ns;
3993 data[4] = down_count * devpriv->clock_ns;
3994 return -EAGAIN;
3995 }
3996 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
3997 NI_M_CAL_PWM_LOW_TIME(down_count),
3998 NI_M_CAL_PWM_REG);
3999 devpriv->pwm_up_count = up_count;
4000 devpriv->pwm_down_count = down_count;
4001 return 5;
4002 case INSN_CONFIG_GET_PWM_OUTPUT:
4003 return ni_get_pwm_config(dev, data);
4004 default:
4005 return -EINVAL;
4006 }
4007 return 0;
4008 }
4009
4010 static int ni_6143_pwm_config(struct comedi_device *dev,
4011 struct comedi_subdevice *s,
4012 struct comedi_insn *insn,
4013 unsigned int *data)
4014 {
4015 struct ni_private *devpriv = dev->private;
4016 unsigned up_count, down_count;
4017
4018 switch (data[0]) {
4019 case INSN_CONFIG_PWM_OUTPUT:
4020 switch (data[1]) {
4021 case CMDF_ROUND_NEAREST:
4022 up_count =
4023 (data[2] +
4024 devpriv->clock_ns / 2) / devpriv->clock_ns;
4025 break;
4026 case CMDF_ROUND_DOWN:
4027 up_count = data[2] / devpriv->clock_ns;
4028 break;
4029 case CMDF_ROUND_UP:
4030 up_count =
4031 (data[2] + devpriv->clock_ns -
4032 1) / devpriv->clock_ns;
4033 break;
4034 default:
4035 return -EINVAL;
4036 }
4037 switch (data[3]) {
4038 case CMDF_ROUND_NEAREST:
4039 down_count =
4040 (data[4] +
4041 devpriv->clock_ns / 2) / devpriv->clock_ns;
4042 break;
4043 case CMDF_ROUND_DOWN:
4044 down_count = data[4] / devpriv->clock_ns;
4045 break;
4046 case CMDF_ROUND_UP:
4047 down_count =
4048 (data[4] + devpriv->clock_ns -
4049 1) / devpriv->clock_ns;
4050 break;
4051 default:
4052 return -EINVAL;
4053 }
4054 if (up_count * devpriv->clock_ns != data[2] ||
4055 down_count * devpriv->clock_ns != data[4]) {
4056 data[2] = up_count * devpriv->clock_ns;
4057 data[4] = down_count * devpriv->clock_ns;
4058 return -EAGAIN;
4059 }
4060 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4061 devpriv->pwm_up_count = up_count;
4062 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4063 devpriv->pwm_down_count = down_count;
4064 return 5;
4065 case INSN_CONFIG_GET_PWM_OUTPUT:
4066 return ni_get_pwm_config(dev, data);
4067 default:
4068 return -EINVAL;
4069 }
4070 return 0;
4071 }
4072
4073 static int pack_mb88341(int addr, int val, int *bitstring)
4074 {
4075 /*
4076 Fujitsu MB 88341
4077 Note that address bits are reversed. Thanks to
4078 Ingo Keen for noticing this.
4079
4080 Note also that the 88341 expects address values from
4081 1-12, whereas we use channel numbers 0-11. The NI
4082 docs use 1-12, also, so be careful here.
4083 */
4084 addr++;
4085 *bitstring = ((addr & 0x1) << 11) |
4086 ((addr & 0x2) << 9) |
4087 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4088 return 12;
4089 }
4090
4091 static int pack_dac8800(int addr, int val, int *bitstring)
4092 {
4093 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4094 return 11;
4095 }
4096
4097 static int pack_dac8043(int addr, int val, int *bitstring)
4098 {
4099 *bitstring = val & 0xfff;
4100 return 12;
4101 }
4102
4103 static int pack_ad8522(int addr, int val, int *bitstring)
4104 {
4105 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4106 return 16;
4107 }
4108
4109 static int pack_ad8804(int addr, int val, int *bitstring)
4110 {
4111 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4112 return 12;
4113 }
4114
4115 static int pack_ad8842(int addr, int val, int *bitstring)
4116 {
4117 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4118 return 12;
4119 }
4120
4121 struct caldac_struct {
4122 int n_chans;
4123 int n_bits;
4124 int (*packbits)(int, int, int *);
4125 };
4126
4127 static struct caldac_struct caldacs[] = {
4128 [mb88341] = {12, 8, pack_mb88341},
4129 [dac8800] = {8, 8, pack_dac8800},
4130 [dac8043] = {1, 12, pack_dac8043},
4131 [ad8522] = {2, 12, pack_ad8522},
4132 [ad8804] = {12, 8, pack_ad8804},
4133 [ad8842] = {8, 8, pack_ad8842},
4134 [ad8804_debug] = {16, 8, pack_ad8804},
4135 };
4136
4137 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4138 {
4139 const struct ni_board_struct *board = dev->board_ptr;
4140 struct ni_private *devpriv = dev->private;
4141 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4142 unsigned int cmd;
4143 int i;
4144 int type;
4145
4146 if (devpriv->caldacs[addr] == val)
4147 return;
4148 devpriv->caldacs[addr] = val;
4149
4150 for (i = 0; i < 3; i++) {
4151 type = board->caldac[i];
4152 if (type == caldac_none)
4153 break;
4154 if (addr < caldacs[type].n_chans) {
4155 bits = caldacs[type].packbits(addr, val, &bitstring);
4156 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4157 break;
4158 }
4159 addr -= caldacs[type].n_chans;
4160 }
4161
4162 /* bits will be 0 if there is no caldac for the given addr */
4163 if (bits == 0)
4164 return;
4165
4166 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4167 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4168 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4169 udelay(1);
4170 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4171 udelay(1);
4172 }
4173 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4174 udelay(1);
4175 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4176 }
4177
4178 static int ni_calib_insn_write(struct comedi_device *dev,
4179 struct comedi_subdevice *s,
4180 struct comedi_insn *insn,
4181 unsigned int *data)
4182 {
4183 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4184
4185 return 1;
4186 }
4187
4188 static int ni_calib_insn_read(struct comedi_device *dev,
4189 struct comedi_subdevice *s,
4190 struct comedi_insn *insn,
4191 unsigned int *data)
4192 {
4193 struct ni_private *devpriv = dev->private;
4194
4195 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4196
4197 return 1;
4198 }
4199
4200 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4201 {
4202 const struct ni_board_struct *board = dev->board_ptr;
4203 struct ni_private *devpriv = dev->private;
4204 int i, j;
4205 int n_dacs;
4206 int n_chans = 0;
4207 int n_bits;
4208 int diffbits = 0;
4209 int type;
4210 int chan;
4211
4212 type = board->caldac[0];
4213 if (type == caldac_none)
4214 return;
4215 n_bits = caldacs[type].n_bits;
4216 for (i = 0; i < 3; i++) {
4217 type = board->caldac[i];
4218 if (type == caldac_none)
4219 break;
4220 if (caldacs[type].n_bits != n_bits)
4221 diffbits = 1;
4222 n_chans += caldacs[type].n_chans;
4223 }
4224 n_dacs = i;
4225 s->n_chan = n_chans;
4226
4227 if (diffbits) {
4228 unsigned int *maxdata_list;
4229
4230 if (n_chans > MAX_N_CALDACS)
4231 dev_err(dev->class_dev,
4232 "BUG! MAX_N_CALDACS too small\n");
4233 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4234 chan = 0;
4235 for (i = 0; i < n_dacs; i++) {
4236 type = board->caldac[i];
4237 for (j = 0; j < caldacs[type].n_chans; j++) {
4238 maxdata_list[chan] =
4239 (1 << caldacs[type].n_bits) - 1;
4240 chan++;
4241 }
4242 }
4243
4244 for (chan = 0; chan < s->n_chan; chan++)
4245 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4246 } else {
4247 type = board->caldac[0];
4248 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4249
4250 for (chan = 0; chan < s->n_chan; chan++)
4251 ni_write_caldac(dev, i, s->maxdata / 2);
4252 }
4253 }
4254
4255 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4256 {
4257 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4258 int bit;
4259 int bitstring;
4260
4261 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4262 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4263 for (bit = 0x8000; bit; bit >>= 1) {
4264 if (bit & bitstring)
4265 cmd |= NI_E_SERIAL_CMD_SDATA;
4266 else
4267 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4268
4269 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4270 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4271 }
4272 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4273 bitstring = 0;
4274 for (bit = 0x80; bit; bit >>= 1) {
4275 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4276 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4277 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4278 bitstring |= bit;
4279 }
4280 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4281
4282 return bitstring;
4283 }
4284
4285 static int ni_eeprom_insn_read(struct comedi_device *dev,
4286 struct comedi_subdevice *s,
4287 struct comedi_insn *insn,
4288 unsigned int *data)
4289 {
4290 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4291
4292 return 1;
4293 }
4294
4295 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4296 struct comedi_subdevice *s,
4297 struct comedi_insn *insn,
4298 unsigned int *data)
4299 {
4300 struct ni_private *devpriv = dev->private;
4301
4302 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4303
4304 return 1;
4305 }
4306
4307 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4308 unsigned chan)
4309 {
4310 /* pre-m-series boards have fixed signals on pfi pins */
4311 switch (chan) {
4312 case 0:
4313 return NI_PFI_OUTPUT_AI_START1;
4314 case 1:
4315 return NI_PFI_OUTPUT_AI_START2;
4316 case 2:
4317 return NI_PFI_OUTPUT_AI_CONVERT;
4318 case 3:
4319 return NI_PFI_OUTPUT_G_SRC1;
4320 case 4:
4321 return NI_PFI_OUTPUT_G_GATE1;
4322 case 5:
4323 return NI_PFI_OUTPUT_AO_UPDATE_N;
4324 case 6:
4325 return NI_PFI_OUTPUT_AO_START1;
4326 case 7:
4327 return NI_PFI_OUTPUT_AI_START_PULSE;
4328 case 8:
4329 return NI_PFI_OUTPUT_G_SRC0;
4330 case 9:
4331 return NI_PFI_OUTPUT_G_GATE0;
4332 default:
4333 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4334 break;
4335 }
4336 return 0;
4337 }
4338
4339 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4340 unsigned chan, unsigned source)
4341 {
4342 /* pre-m-series boards have fixed signals on pfi pins */
4343 if (source != ni_old_get_pfi_routing(dev, chan))
4344 return -EINVAL;
4345 return 2;
4346 }
4347
4348 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4349 unsigned chan)
4350 {
4351 struct ni_private *devpriv = dev->private;
4352 const unsigned array_offset = chan / 3;
4353
4354 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4355 devpriv->pfi_output_select_reg[array_offset]);
4356 }
4357
4358 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4359 unsigned chan, unsigned source)
4360 {
4361 struct ni_private *devpriv = dev->private;
4362 unsigned index = chan / 3;
4363 unsigned short val = devpriv->pfi_output_select_reg[index];
4364
4365 if ((source & 0x1f) != source)
4366 return -EINVAL;
4367
4368 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4369 val |= NI_M_PFI_OUT_SEL(chan, source);
4370 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4371 devpriv->pfi_output_select_reg[index] = val;
4372
4373 return 2;
4374 }
4375
4376 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4377 {
4378 struct ni_private *devpriv = dev->private;
4379
4380 return (devpriv->is_m_series)
4381 ? ni_m_series_get_pfi_routing(dev, chan)
4382 : ni_old_get_pfi_routing(dev, chan);
4383 }
4384
4385 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4386 unsigned source)
4387 {
4388 struct ni_private *devpriv = dev->private;
4389
4390 return (devpriv->is_m_series)
4391 ? ni_m_series_set_pfi_routing(dev, chan, source)
4392 : ni_old_set_pfi_routing(dev, chan, source);
4393 }
4394
4395 static int ni_config_filter(struct comedi_device *dev,
4396 unsigned pfi_channel,
4397 enum ni_pfi_filter_select filter)
4398 {
4399 struct ni_private *devpriv = dev->private;
4400 unsigned bits;
4401
4402 if (!devpriv->is_m_series)
4403 return -ENOTSUPP;
4404
4405 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4406 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4407 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4408 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4409 return 0;
4410 }
4411
4412 static int ni_pfi_insn_config(struct comedi_device *dev,
4413 struct comedi_subdevice *s,
4414 struct comedi_insn *insn,
4415 unsigned int *data)
4416 {
4417 struct ni_private *devpriv = dev->private;
4418 unsigned int chan;
4419
4420 if (insn->n < 1)
4421 return -EINVAL;
4422
4423 chan = CR_CHAN(insn->chanspec);
4424
4425 switch (data[0]) {
4426 case COMEDI_OUTPUT:
4427 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4428 break;
4429 case COMEDI_INPUT:
4430 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4431 break;
4432 case INSN_CONFIG_DIO_QUERY:
4433 data[1] =
4434 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4435 COMEDI_OUTPUT : COMEDI_INPUT;
4436 return 0;
4437 case INSN_CONFIG_SET_ROUTING:
4438 return ni_set_pfi_routing(dev, chan, data[1]);
4439 case INSN_CONFIG_GET_ROUTING:
4440 data[1] = ni_get_pfi_routing(dev, chan);
4441 break;
4442 case INSN_CONFIG_FILTER:
4443 return ni_config_filter(dev, chan, data[1]);
4444 default:
4445 return -EINVAL;
4446 }
4447 return 0;
4448 }
4449
4450 static int ni_pfi_insn_bits(struct comedi_device *dev,
4451 struct comedi_subdevice *s,
4452 struct comedi_insn *insn,
4453 unsigned int *data)
4454 {
4455 struct ni_private *devpriv = dev->private;
4456
4457 if (!devpriv->is_m_series)
4458 return -ENOTSUPP;
4459
4460 if (comedi_dio_update_state(s, data))
4461 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4462
4463 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4464
4465 return insn->n;
4466 }
4467
4468 static int cs5529_wait_for_idle(struct comedi_device *dev)
4469 {
4470 unsigned short status;
4471 const int timeout = HZ;
4472 int i;
4473
4474 for (i = 0; i < timeout; i++) {
4475 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4476 if ((status & CSS_ADC_BUSY) == 0)
4477 break;
4478 set_current_state(TASK_INTERRUPTIBLE);
4479 if (schedule_timeout(1))
4480 return -EIO;
4481 }
4482 if (i == timeout) {
4483 dev_err(dev->class_dev, "timeout\n");
4484 return -ETIME;
4485 }
4486 return 0;
4487 }
4488
4489 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4490 {
4491 static const int timeout = 100;
4492 int i;
4493
4494 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4495 /* give time for command to start being serially clocked into cs5529.
4496 * this insures that the CSS_ADC_BUSY bit will get properly
4497 * set before we exit this function.
4498 */
4499 for (i = 0; i < timeout; i++) {
4500 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4501 break;
4502 udelay(1);
4503 }
4504 if (i == timeout)
4505 dev_err(dev->class_dev,
4506 "possible problem - never saw adc go busy?\n");
4507 }
4508
4509 static int cs5529_do_conversion(struct comedi_device *dev,
4510 unsigned short *data)
4511 {
4512 int retval;
4513 unsigned short status;
4514
4515 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4516 retval = cs5529_wait_for_idle(dev);
4517 if (retval) {
4518 dev_err(dev->class_dev,
4519 "timeout or signal in cs5529_do_conversion()\n");
4520 return -ETIME;
4521 }
4522 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4523 if (status & CSS_OSC_DETECT) {
4524 dev_err(dev->class_dev,
4525 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4526 return -EIO;
4527 }
4528 if (status & CSS_OVERRANGE) {
4529 dev_err(dev->class_dev,
4530 "cs5529 conversion error, overrange (ignoring)\n");
4531 }
4532 if (data) {
4533 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4534 /* cs5529 returns 16 bit signed data in bipolar mode */
4535 *data ^= (1 << 15);
4536 }
4537 return 0;
4538 }
4539
4540 static int cs5529_ai_insn_read(struct comedi_device *dev,
4541 struct comedi_subdevice *s,
4542 struct comedi_insn *insn,
4543 unsigned int *data)
4544 {
4545 int n, retval;
4546 unsigned short sample;
4547 unsigned int channel_select;
4548 const unsigned int INTERNAL_REF = 0x1000;
4549
4550 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4551 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4552 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4553 if (insn->chanspec & CR_ALT_SOURCE)
4554 channel_select = INTERNAL_REF;
4555 else
4556 channel_select = CR_CHAN(insn->chanspec);
4557 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4558
4559 for (n = 0; n < insn->n; n++) {
4560 retval = cs5529_do_conversion(dev, &sample);
4561 if (retval < 0)
4562 return retval;
4563 data[n] = sample;
4564 }
4565 return insn->n;
4566 }
4567
4568 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4569 unsigned int reg_select_bits)
4570 {
4571 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4572 CAL_ADC_Config_Data_High_Word_67xx);
4573 ni_ao_win_outw(dev, (value & 0xffff),
4574 CAL_ADC_Config_Data_Low_Word_67xx);
4575 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4576 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4577 if (cs5529_wait_for_idle(dev))
4578 dev_err(dev->class_dev,
4579 "timeout or signal in %s\n", __func__);
4580 }
4581
4582 static int init_cs5529(struct comedi_device *dev)
4583 {
4584 unsigned int config_bits =
4585 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4586
4587 #if 1
4588 /* do self-calibration */
4589 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4590 CSCMD_CONFIG_REGISTER);
4591 /* need to force a conversion for calibration to run */
4592 cs5529_do_conversion(dev, NULL);
4593 #else
4594 /* force gain calibration to 1 */
4595 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4596 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4597 CSCMD_CONFIG_REGISTER);
4598 if (cs5529_wait_for_idle(dev))
4599 dev_err(dev->class_dev,
4600 "timeout or signal in %s\n", __func__);
4601 #endif
4602 return 0;
4603 }
4604
4605 /*
4606 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4607 * given an arbitrary frequency input clock.
4608 */
4609 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4610 unsigned *freq_divider,
4611 unsigned *freq_multiplier,
4612 unsigned *actual_period_ns)
4613 {
4614 unsigned div;
4615 unsigned best_div = 1;
4616 unsigned mult;
4617 unsigned best_mult = 1;
4618 static const unsigned pico_per_nano = 1000;
4619
4620 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4621 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4622 * 20 MHz for most timing clocks */
4623 static const unsigned target_picosec = 12500;
4624 static const unsigned fudge_factor_80_to_20Mhz = 4;
4625 int best_period_picosec = 0;
4626
4627 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4628 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4629 unsigned new_period_ps =
4630 (reference_picosec * div) / mult;
4631 if (abs(new_period_ps - target_picosec) <
4632 abs(best_period_picosec - target_picosec)) {
4633 best_period_picosec = new_period_ps;
4634 best_div = div;
4635 best_mult = mult;
4636 }
4637 }
4638 }
4639 if (best_period_picosec == 0)
4640 return -EIO;
4641
4642 *freq_divider = best_div;
4643 *freq_multiplier = best_mult;
4644 *actual_period_ns =
4645 (best_period_picosec * fudge_factor_80_to_20Mhz +
4646 (pico_per_nano / 2)) / pico_per_nano;
4647 return 0;
4648 }
4649
4650 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4651 unsigned source, unsigned period_ns)
4652 {
4653 struct ni_private *devpriv = dev->private;
4654 static const unsigned min_period_ns = 50;
4655 static const unsigned max_period_ns = 1000;
4656 static const unsigned timeout = 1000;
4657 unsigned pll_control_bits;
4658 unsigned freq_divider;
4659 unsigned freq_multiplier;
4660 unsigned rtsi;
4661 unsigned i;
4662 int retval;
4663
4664 if (source == NI_MIO_PLL_PXI10_CLOCK)
4665 period_ns = 100;
4666 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4667 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4668 dev_err(dev->class_dev,
4669 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4670 __func__, min_period_ns, max_period_ns);
4671 return -EINVAL;
4672 }
4673 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4674 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4675 NISTC_RTSI_TRIG_DIR_REG);
4676 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4677 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4678 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4679 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4680 switch (source) {
4681 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4682 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4683 break;
4684 case NI_MIO_PLL_PXI10_CLOCK:
4685 /* pxi clock is 10MHz */
4686 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4687 break;
4688 default:
4689 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4690 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4691 devpriv->clock_and_fout2 |=
4692 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4693 break;
4694 }
4695 }
4696 if (rtsi > NI_M_MAX_RTSI_CHAN)
4697 return -EINVAL;
4698 break;
4699 }
4700 retval = ni_mseries_get_pll_parameters(period_ns,
4701 &freq_divider,
4702 &freq_multiplier,
4703 &devpriv->clock_ns);
4704 if (retval < 0) {
4705 dev_err(dev->class_dev,
4706 "bug, failed to find pll parameters\n");
4707 return retval;
4708 }
4709
4710 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4711 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4712 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4713
4714 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4715 devpriv->clock_source = source;
4716 /* it seems to typically take a few hundred microseconds for PLL to lock */
4717 for (i = 0; i < timeout; ++i) {
4718 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4719 break;
4720 udelay(1);
4721 }
4722 if (i == timeout) {
4723 dev_err(dev->class_dev,
4724 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4725 __func__, source, period_ns);
4726 return -ETIMEDOUT;
4727 }
4728 return 3;
4729 }
4730
4731 static int ni_set_master_clock(struct comedi_device *dev,
4732 unsigned source, unsigned period_ns)
4733 {
4734 struct ni_private *devpriv = dev->private;
4735
4736 if (source == NI_MIO_INTERNAL_CLOCK) {
4737 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4738 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4739 NISTC_RTSI_TRIG_DIR_REG);
4740 devpriv->clock_ns = TIMEBASE_1_NS;
4741 if (devpriv->is_m_series) {
4742 devpriv->clock_and_fout2 &=
4743 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4744 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4745 ni_writew(dev, devpriv->clock_and_fout2,
4746 NI_M_CLK_FOUT2_REG);
4747 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4748 }
4749 devpriv->clock_source = source;
4750 } else {
4751 if (devpriv->is_m_series) {
4752 return ni_mseries_set_pll_master_clock(dev, source,
4753 period_ns);
4754 } else {
4755 if (source == NI_MIO_RTSI_CLOCK) {
4756 devpriv->rtsi_trig_direction_reg |=
4757 NISTC_RTSI_TRIG_USE_CLK;
4758 ni_stc_writew(dev,
4759 devpriv->rtsi_trig_direction_reg,
4760 NISTC_RTSI_TRIG_DIR_REG);
4761 if (period_ns == 0) {
4762 dev_err(dev->class_dev,
4763 "we don't handle an unspecified clock period correctly yet, returning error\n");
4764 return -EINVAL;
4765 }
4766 devpriv->clock_ns = period_ns;
4767 devpriv->clock_source = source;
4768 } else {
4769 return -EINVAL;
4770 }
4771 }
4772 }
4773 return 3;
4774 }
4775
4776 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4777 unsigned chan, unsigned source)
4778 {
4779 struct ni_private *devpriv = dev->private;
4780
4781 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4782 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4783 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4784 return 1;
4785
4786 dev_err(dev->class_dev,
4787 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4788 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4789 return 0;
4790 }
4791 return 0;
4792 }
4793 switch (source) {
4794 case NI_RTSI_OUTPUT_ADR_START1:
4795 case NI_RTSI_OUTPUT_ADR_START2:
4796 case NI_RTSI_OUTPUT_SCLKG:
4797 case NI_RTSI_OUTPUT_DACUPDN:
4798 case NI_RTSI_OUTPUT_DA_START1:
4799 case NI_RTSI_OUTPUT_G_SRC0:
4800 case NI_RTSI_OUTPUT_G_GATE0:
4801 case NI_RTSI_OUTPUT_RGOUT0:
4802 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4803 return 1;
4804 case NI_RTSI_OUTPUT_RTSI_OSC:
4805 return (devpriv->is_m_series) ? 1 : 0;
4806 default:
4807 return 0;
4808 }
4809 }
4810
4811 static int ni_set_rtsi_routing(struct comedi_device *dev,
4812 unsigned chan, unsigned src)
4813 {
4814 struct ni_private *devpriv = dev->private;
4815
4816 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4817 return -EINVAL;
4818 if (chan < 4) {
4819 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4820 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4821 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4822 NISTC_RTSI_TRIGA_OUT_REG);
4823 } else if (chan < 8) {
4824 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4825 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4826 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4827 NISTC_RTSI_TRIGB_OUT_REG);
4828 }
4829 return 2;
4830 }
4831
4832 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4833 {
4834 struct ni_private *devpriv = dev->private;
4835
4836 if (chan < 4) {
4837 return NISTC_RTSI_TRIG_TO_SRC(chan,
4838 devpriv->rtsi_trig_a_output_reg);
4839 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4840 return NISTC_RTSI_TRIG_TO_SRC(chan,
4841 devpriv->rtsi_trig_b_output_reg);
4842 } else {
4843 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4844 return NI_RTSI_OUTPUT_RTSI_OSC;
4845 dev_err(dev->class_dev, "bug! should never get here?\n");
4846 return 0;
4847 }
4848 }
4849
4850 static int ni_rtsi_insn_config(struct comedi_device *dev,
4851 struct comedi_subdevice *s,
4852 struct comedi_insn *insn,
4853 unsigned int *data)
4854 {
4855 struct ni_private *devpriv = dev->private;
4856 unsigned int chan = CR_CHAN(insn->chanspec);
4857 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4858
4859 switch (data[0]) {
4860 case INSN_CONFIG_DIO_OUTPUT:
4861 if (chan < max_chan) {
4862 devpriv->rtsi_trig_direction_reg |=
4863 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4864 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4865 devpriv->rtsi_trig_direction_reg |=
4866 NISTC_RTSI_TRIG_DRV_CLK;
4867 }
4868 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4869 NISTC_RTSI_TRIG_DIR_REG);
4870 break;
4871 case INSN_CONFIG_DIO_INPUT:
4872 if (chan < max_chan) {
4873 devpriv->rtsi_trig_direction_reg &=
4874 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4875 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4876 devpriv->rtsi_trig_direction_reg &=
4877 ~NISTC_RTSI_TRIG_DRV_CLK;
4878 }
4879 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4880 NISTC_RTSI_TRIG_DIR_REG);
4881 break;
4882 case INSN_CONFIG_DIO_QUERY:
4883 if (chan < max_chan) {
4884 data[1] =
4885 (devpriv->rtsi_trig_direction_reg &
4886 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4887 ? INSN_CONFIG_DIO_OUTPUT
4888 : INSN_CONFIG_DIO_INPUT;
4889 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4890 data[1] = (devpriv->rtsi_trig_direction_reg &
4891 NISTC_RTSI_TRIG_DRV_CLK)
4892 ? INSN_CONFIG_DIO_OUTPUT
4893 : INSN_CONFIG_DIO_INPUT;
4894 }
4895 return 2;
4896 case INSN_CONFIG_SET_CLOCK_SRC:
4897 return ni_set_master_clock(dev, data[1], data[2]);
4898 case INSN_CONFIG_GET_CLOCK_SRC:
4899 data[1] = devpriv->clock_source;
4900 data[2] = devpriv->clock_ns;
4901 return 3;
4902 case INSN_CONFIG_SET_ROUTING:
4903 return ni_set_rtsi_routing(dev, chan, data[1]);
4904 case INSN_CONFIG_GET_ROUTING:
4905 data[1] = ni_get_rtsi_routing(dev, chan);
4906 return 2;
4907 default:
4908 return -EINVAL;
4909 }
4910 return 1;
4911 }
4912
4913 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4914 struct comedi_subdevice *s,
4915 struct comedi_insn *insn,
4916 unsigned int *data)
4917 {
4918 data[1] = 0;
4919
4920 return insn->n;
4921 }
4922
4923 static void ni_rtsi_init(struct comedi_device *dev)
4924 {
4925 struct ni_private *devpriv = dev->private;
4926
4927 /* Initialises the RTSI bus signal switch to a default state */
4928
4929 /*
4930 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4931 * to have no effect, at least on pxi-6281, which always uses
4932 * 20MHz rtsi clock frequency
4933 */
4934 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4935 /* Set clock mode to internal */
4936 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4937 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4938 /* default internal lines routing to RTSI bus lines */
4939 devpriv->rtsi_trig_a_output_reg =
4940 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4941 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4942 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4943 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4944 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4945 NISTC_RTSI_TRIGA_OUT_REG);
4946 devpriv->rtsi_trig_b_output_reg =
4947 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4948 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4949 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4950 if (devpriv->is_m_series)
4951 devpriv->rtsi_trig_b_output_reg |=
4952 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4953 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4954 NISTC_RTSI_TRIGB_OUT_REG);
4955
4956 /*
4957 * Sets the source and direction of the 4 on board lines
4958 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4959 */
4960 }
4961
4962 #ifdef PCIDMA
4963 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4964 {
4965 struct ni_gpct *counter = s->private;
4966 int retval;
4967
4968 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4969 COMEDI_INPUT);
4970 if (retval) {
4971 dev_err(dev->class_dev,
4972 "no dma channel available for use by counter\n");
4973 return retval;
4974 }
4975 ni_tio_acknowledge(counter);
4976 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4977
4978 return ni_tio_cmd(dev, s);
4979 }
4980
4981 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4982 {
4983 struct ni_gpct *counter = s->private;
4984 int retval;
4985
4986 retval = ni_tio_cancel(counter);
4987 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4988 ni_release_gpct_mite_channel(dev, counter->counter_index);
4989 return retval;
4990 }
4991 #endif
4992
4993 static irqreturn_t ni_E_interrupt(int irq, void *d)
4994 {
4995 struct comedi_device *dev = d;
4996 unsigned short a_status;
4997 unsigned short b_status;
4998 unsigned int ai_mite_status = 0;
4999 unsigned int ao_mite_status = 0;
5000 unsigned long flags;
5001 #ifdef PCIDMA
5002 struct ni_private *devpriv = dev->private;
5003 struct mite_struct *mite = devpriv->mite;
5004 #endif
5005
5006 if (!dev->attached)
5007 return IRQ_NONE;
5008 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5009
5010 /* lock to avoid race with comedi_poll */
5011 spin_lock_irqsave(&dev->spinlock, flags);
5012 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5013 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5014 #ifdef PCIDMA
5015 if (mite) {
5016 struct ni_private *devpriv = dev->private;
5017 unsigned long flags_too;
5018
5019 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5020 if (devpriv->ai_mite_chan) {
5021 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5022 if (ai_mite_status & CHSR_LINKC)
5023 writel(CHOR_CLRLC,
5024 devpriv->mite->mite_io_addr +
5025 MITE_CHOR(devpriv->
5026 ai_mite_chan->channel));
5027 }
5028 if (devpriv->ao_mite_chan) {
5029 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5030 if (ao_mite_status & CHSR_LINKC)
5031 writel(CHOR_CLRLC,
5032 mite->mite_io_addr +
5033 MITE_CHOR(devpriv->
5034 ao_mite_chan->channel));
5035 }
5036 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5037 }
5038 #endif
5039 ack_a_interrupt(dev, a_status);
5040 ack_b_interrupt(dev, b_status);
5041 if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5042 handle_a_interrupt(dev, a_status, ai_mite_status);
5043 if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5044 handle_b_interrupt(dev, b_status, ao_mite_status);
5045 handle_gpct_interrupt(dev, 0);
5046 handle_gpct_interrupt(dev, 1);
5047 handle_cdio_interrupt(dev);
5048
5049 spin_unlock_irqrestore(&dev->spinlock, flags);
5050 return IRQ_HANDLED;
5051 }
5052
5053 static int ni_alloc_private(struct comedi_device *dev)
5054 {
5055 struct ni_private *devpriv;
5056
5057 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5058 if (!devpriv)
5059 return -ENOMEM;
5060
5061 spin_lock_init(&devpriv->window_lock);
5062 spin_lock_init(&devpriv->soft_reg_copy_lock);
5063 spin_lock_init(&devpriv->mite_channel_lock);
5064
5065 return 0;
5066 }
5067
5068 static int ni_E_init(struct comedi_device *dev,
5069 unsigned interrupt_pin, unsigned irq_polarity)
5070 {
5071 const struct ni_board_struct *board = dev->board_ptr;
5072 struct ni_private *devpriv = dev->private;
5073 struct comedi_subdevice *s;
5074 int ret;
5075 int i;
5076
5077 if (board->n_aochan > MAX_N_AO_CHAN) {
5078 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5079 return -EINVAL;
5080 }
5081
5082 /* initialize clock dividers */
5083 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5084 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5085 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5086 NISTC_CLK_FOUT_TO_BOARD;
5087 if (!devpriv->is_6xxx) {
5088 /* BEAM is this needed for PCI-6143 ?? */
5089 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5090 NISTC_CLK_FOUT_AO_OUT_DIV2);
5091 }
5092 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5093
5094 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5095 if (ret)
5096 return ret;
5097
5098 /* Analog Input subdevice */
5099 s = &dev->subdevices[NI_AI_SUBDEV];
5100 if (board->n_adchan) {
5101 s->type = COMEDI_SUBD_AI;
5102 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5103 if (!devpriv->is_611x)
5104 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5105 if (board->ai_maxdata > 0xffff)
5106 s->subdev_flags |= SDF_LSAMPL;
5107 if (devpriv->is_m_series)
5108 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5109 s->n_chan = board->n_adchan;
5110 s->maxdata = board->ai_maxdata;
5111 s->range_table = ni_range_lkup[board->gainlkup];
5112 s->insn_read = ni_ai_insn_read;
5113 s->insn_config = ni_ai_insn_config;
5114 if (dev->irq) {
5115 dev->read_subdev = s;
5116 s->subdev_flags |= SDF_CMD_READ;
5117 s->len_chanlist = 512;
5118 s->do_cmdtest = ni_ai_cmdtest;
5119 s->do_cmd = ni_ai_cmd;
5120 s->cancel = ni_ai_reset;
5121 s->poll = ni_ai_poll;
5122 s->munge = ni_ai_munge;
5123
5124 if (devpriv->mite)
5125 s->async_dma_dir = DMA_FROM_DEVICE;
5126 }
5127
5128 /* reset the analog input configuration */
5129 ni_ai_reset(dev, s);
5130 } else {
5131 s->type = COMEDI_SUBD_UNUSED;
5132 }
5133
5134 /* Analog Output subdevice */
5135 s = &dev->subdevices[NI_AO_SUBDEV];
5136 if (board->n_aochan) {
5137 s->type = COMEDI_SUBD_AO;
5138 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5139 if (devpriv->is_m_series)
5140 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5141 s->n_chan = board->n_aochan;
5142 s->maxdata = board->ao_maxdata;
5143 s->range_table = board->ao_range_table;
5144 s->insn_config = ni_ao_insn_config;
5145 s->insn_write = ni_ao_insn_write;
5146
5147 ret = comedi_alloc_subdev_readback(s);
5148 if (ret)
5149 return ret;
5150
5151 /*
5152 * Along with the IRQ we need either a FIFO or DMA for
5153 * async command support.
5154 */
5155 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5156 dev->write_subdev = s;
5157 s->subdev_flags |= SDF_CMD_WRITE;
5158 s->len_chanlist = s->n_chan;
5159 s->do_cmdtest = ni_ao_cmdtest;
5160 s->do_cmd = ni_ao_cmd;
5161 s->cancel = ni_ao_reset;
5162 if (!devpriv->is_m_series)
5163 s->munge = ni_ao_munge;
5164
5165 if (devpriv->mite)
5166 s->async_dma_dir = DMA_TO_DEVICE;
5167 }
5168
5169 if (devpriv->is_67xx)
5170 init_ao_67xx(dev, s);
5171
5172 /* reset the analog output configuration */
5173 ni_ao_reset(dev, s);
5174 } else {
5175 s->type = COMEDI_SUBD_UNUSED;
5176 }
5177
5178 /* Digital I/O subdevice */
5179 s = &dev->subdevices[NI_DIO_SUBDEV];
5180 s->type = COMEDI_SUBD_DIO;
5181 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5182 s->n_chan = board->has_32dio_chan ? 32 : 8;
5183 s->maxdata = 1;
5184 s->range_table = &range_digital;
5185 if (devpriv->is_m_series) {
5186 s->subdev_flags |= SDF_LSAMPL;
5187 s->insn_bits = ni_m_series_dio_insn_bits;
5188 s->insn_config = ni_m_series_dio_insn_config;
5189 if (dev->irq) {
5190 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5191 s->len_chanlist = s->n_chan;
5192 s->do_cmdtest = ni_cdio_cmdtest;
5193 s->do_cmd = ni_cdio_cmd;
5194 s->cancel = ni_cdio_cancel;
5195
5196 /* M-series boards use DMA */
5197 s->async_dma_dir = DMA_BIDIRECTIONAL;
5198 }
5199
5200 /* reset DIO and set all channels to inputs */
5201 ni_writel(dev, NI_M_CDO_CMD_RESET |
5202 NI_M_CDI_CMD_RESET,
5203 NI_M_CDIO_CMD_REG);
5204 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5205 } else {
5206 s->insn_bits = ni_dio_insn_bits;
5207 s->insn_config = ni_dio_insn_config;
5208
5209 /* set all channels to inputs */
5210 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5211 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5212 }
5213
5214 /* 8255 device */
5215 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5216 if (board->has_8255) {
5217 ret = subdev_8255_init(dev, s, ni_8255_callback,
5218 NI_E_8255_BASE);
5219 if (ret)
5220 return ret;
5221 } else {
5222 s->type = COMEDI_SUBD_UNUSED;
5223 }
5224
5225 /* formerly general purpose counter/timer device, but no longer used */
5226 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5227 s->type = COMEDI_SUBD_UNUSED;
5228
5229 /* Calibration subdevice */
5230 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5231 s->type = COMEDI_SUBD_CALIB;
5232 s->subdev_flags = SDF_INTERNAL;
5233 s->n_chan = 1;
5234 s->maxdata = 0;
5235 if (devpriv->is_m_series) {
5236 /* internal PWM output used for AI nonlinearity calibration */
5237 s->insn_config = ni_m_series_pwm_config;
5238
5239 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5240 } else if (devpriv->is_6143) {
5241 /* internal PWM output used for AI nonlinearity calibration */
5242 s->insn_config = ni_6143_pwm_config;
5243 } else {
5244 s->subdev_flags |= SDF_WRITABLE;
5245 s->insn_read = ni_calib_insn_read;
5246 s->insn_write = ni_calib_insn_write;
5247
5248 /* setup the caldacs and find the real n_chan and maxdata */
5249 caldac_setup(dev, s);
5250 }
5251
5252 /* EEPROM subdevice */
5253 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5254 s->type = COMEDI_SUBD_MEMORY;
5255 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5256 s->maxdata = 0xff;
5257 if (devpriv->is_m_series) {
5258 s->n_chan = M_SERIES_EEPROM_SIZE;
5259 s->insn_read = ni_m_series_eeprom_insn_read;
5260 } else {
5261 s->n_chan = 512;
5262 s->insn_read = ni_eeprom_insn_read;
5263 }
5264
5265 /* Digital I/O (PFI) subdevice */
5266 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5267 s->type = COMEDI_SUBD_DIO;
5268 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5269 s->maxdata = 1;
5270 if (devpriv->is_m_series) {
5271 s->n_chan = 16;
5272 s->insn_bits = ni_pfi_insn_bits;
5273
5274 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5275 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5276 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5277 NI_M_PFI_OUT_SEL_REG(i));
5278 }
5279 } else {
5280 s->n_chan = 10;
5281 }
5282 s->insn_config = ni_pfi_insn_config;
5283
5284 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5285
5286 /* cs5529 calibration adc */
5287 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5288 if (devpriv->is_67xx) {
5289 s->type = COMEDI_SUBD_AI;
5290 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5291 /* one channel for each analog output channel */
5292 s->n_chan = board->n_aochan;
5293 s->maxdata = (1 << 16) - 1;
5294 s->range_table = &range_unknown; /* XXX */
5295 s->insn_read = cs5529_ai_insn_read;
5296 s->insn_config = NULL;
5297 init_cs5529(dev);
5298 } else {
5299 s->type = COMEDI_SUBD_UNUSED;
5300 }
5301
5302 /* Serial */
5303 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5304 s->type = COMEDI_SUBD_SERIAL;
5305 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5306 s->n_chan = 1;
5307 s->maxdata = 0xff;
5308 s->insn_config = ni_serial_insn_config;
5309 devpriv->serial_interval_ns = 0;
5310 devpriv->serial_hw_mode = 0;
5311
5312 /* RTSI */
5313 s = &dev->subdevices[NI_RTSI_SUBDEV];
5314 s->type = COMEDI_SUBD_DIO;
5315 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5316 s->n_chan = 8;
5317 s->maxdata = 1;
5318 s->insn_bits = ni_rtsi_insn_bits;
5319 s->insn_config = ni_rtsi_insn_config;
5320 ni_rtsi_init(dev);
5321
5322 /* allocate and initialize the gpct counter device */
5323 devpriv->counter_dev = ni_gpct_device_construct(dev,
5324 ni_gpct_write_register,
5325 ni_gpct_read_register,
5326 (devpriv->is_m_series)
5327 ? ni_gpct_variant_m_series
5328 : ni_gpct_variant_e_series,
5329 NUM_GPCT);
5330 if (!devpriv->counter_dev)
5331 return -ENOMEM;
5332
5333 /* Counter (gpct) subdevices */
5334 for (i = 0; i < NUM_GPCT; ++i) {
5335 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5336
5337 /* setup and initialize the counter */
5338 gpct->chip_index = 0;
5339 gpct->counter_index = i;
5340 ni_tio_init_counter(gpct);
5341
5342 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5343 s->type = COMEDI_SUBD_COUNTER;
5344 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5345 s->n_chan = 3;
5346 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5347 : 0x00ffffff;
5348 s->insn_read = ni_tio_insn_read;
5349 s->insn_write = ni_tio_insn_read;
5350 s->insn_config = ni_tio_insn_config;
5351 #ifdef PCIDMA
5352 if (dev->irq && devpriv->mite) {
5353 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5354 s->len_chanlist = 1;
5355 s->do_cmdtest = ni_tio_cmdtest;
5356 s->do_cmd = ni_gpct_cmd;
5357 s->cancel = ni_gpct_cancel;
5358
5359 s->async_dma_dir = DMA_BIDIRECTIONAL;
5360 }
5361 #endif
5362 s->private = gpct;
5363 }
5364
5365 /* Frequency output subdevice */
5366 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5367 s->type = COMEDI_SUBD_COUNTER;
5368 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5369 s->n_chan = 1;
5370 s->maxdata = 0xf;
5371 s->insn_read = ni_freq_out_insn_read;
5372 s->insn_write = ni_freq_out_insn_write;
5373 s->insn_config = ni_freq_out_insn_config;
5374
5375 if (dev->irq) {
5376 ni_stc_writew(dev,
5377 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5378 (NISTC_INT_CTRL_3PIN_INT & 0) |
5379 NISTC_INT_CTRL_INTA_ENA |
5380 NISTC_INT_CTRL_INTB_ENA |
5381 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5382 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5383 NISTC_INT_CTRL_REG);
5384 }
5385
5386 /* DMA setup */
5387 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5388 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5389
5390 if (devpriv->is_6xxx) {
5391 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5392 } else if (devpriv->is_m_series) {
5393 int channel;
5394
5395 for (channel = 0; channel < board->n_aochan; ++channel) {
5396 ni_writeb(dev, 0xf,
5397 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5398 ni_writeb(dev, 0x0,
5399 NI_M_AO_REF_ATTENUATION_REG(channel));
5400 }
5401 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5402 }
5403
5404 return 0;
5405 }
5406
5407 static void mio_common_detach(struct comedi_device *dev)
5408 {
5409 struct ni_private *devpriv = dev->private;
5410
5411 if (devpriv) {
5412 if (devpriv->counter_dev)
5413 ni_gpct_device_destroy(devpriv->counter_dev);
5414 }
5415 }
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