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[mirror_ubuntu-zesty-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 * Hardware driver for DAQ-STC based boards
3 *
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
6 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * This file is meant to be included by another file, e.g.,
21 * ni_atmio.c or ni_pcimio.c.
22 *
23 * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
24 *
25 * References (ftp://ftp.natinst.com/support/manuals):
26 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
27 * 341079b.pdf PCI E Series RLPM
28 * 340934b.pdf DAQ-STC reference manual
29 *
30 * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
31 * release_ni611x.pdf
32 * release_ni67xx.pdf
33 *
34 * Other possibly relevant info:
35 * 320517c.pdf User manual (obsolete)
36 * 320517f.pdf User manual (new)
37 * 320889a.pdf delete
38 * 320906c.pdf maximum signal ratings
39 * 321066a.pdf about 16x
40 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
41 * 321808a.pdf about at-mio-16e-10 rev P
42 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
43 * 321838a.pdf about at-mio-16de-10 rev N
44 *
45 * ISSUES:
46 * - the interrupt routine needs to be cleaned up
47 *
48 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
49 * fully tested as yet. Terry Barnaby, BEAM Ltd.
50 */
51
52 #include <linux/interrupt.h>
53 #include <linux/sched.h>
54 #include <linux/delay.h>
55 #include "8255.h"
56 #include "mite.h"
57
58 /* A timeout count */
59 #define NI_TIMEOUT 1000
60
61 /* Note: this table must match the ai_gain_* definitions */
62 static const short ni_gainlkup[][16] = {
63 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
64 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
65 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
66 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
67 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_4] = {0, 1, 4, 7},
69 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
70 0x003, 0x004, 0x005, 0x006},
71 [ai_gain_622x] = {0, 1, 4, 5},
72 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
73 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
74 };
75
76 static const struct comedi_lrange range_ni_E_ai = {
77 16, {
78 BIP_RANGE(10),
79 BIP_RANGE(5),
80 BIP_RANGE(2.5),
81 BIP_RANGE(1),
82 BIP_RANGE(0.5),
83 BIP_RANGE(0.25),
84 BIP_RANGE(0.1),
85 BIP_RANGE(0.05),
86 UNI_RANGE(20),
87 UNI_RANGE(10),
88 UNI_RANGE(5),
89 UNI_RANGE(2),
90 UNI_RANGE(1),
91 UNI_RANGE(0.5),
92 UNI_RANGE(0.2),
93 UNI_RANGE(0.1)
94 }
95 };
96
97 static const struct comedi_lrange range_ni_E_ai_limited = {
98 8, {
99 BIP_RANGE(10),
100 BIP_RANGE(5),
101 BIP_RANGE(1),
102 BIP_RANGE(0.1),
103 UNI_RANGE(10),
104 UNI_RANGE(5),
105 UNI_RANGE(1),
106 UNI_RANGE(0.1)
107 }
108 };
109
110 static const struct comedi_lrange range_ni_E_ai_limited14 = {
111 14, {
112 BIP_RANGE(10),
113 BIP_RANGE(5),
114 BIP_RANGE(2),
115 BIP_RANGE(1),
116 BIP_RANGE(0.5),
117 BIP_RANGE(0.2),
118 BIP_RANGE(0.1),
119 UNI_RANGE(10),
120 UNI_RANGE(5),
121 UNI_RANGE(2),
122 UNI_RANGE(1),
123 UNI_RANGE(0.5),
124 UNI_RANGE(0.2),
125 UNI_RANGE(0.1)
126 }
127 };
128
129 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
130 4, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 BIP_RANGE(0.5),
134 BIP_RANGE(0.05)
135 }
136 };
137
138 static const struct comedi_lrange range_ni_E_ai_611x = {
139 8, {
140 BIP_RANGE(50),
141 BIP_RANGE(20),
142 BIP_RANGE(10),
143 BIP_RANGE(5),
144 BIP_RANGE(2),
145 BIP_RANGE(1),
146 BIP_RANGE(0.5),
147 BIP_RANGE(0.2)
148 }
149 };
150
151 static const struct comedi_lrange range_ni_M_ai_622x = {
152 4, {
153 BIP_RANGE(10),
154 BIP_RANGE(5),
155 BIP_RANGE(1),
156 BIP_RANGE(0.2)
157 }
158 };
159
160 static const struct comedi_lrange range_ni_M_ai_628x = {
161 7, {
162 BIP_RANGE(10),
163 BIP_RANGE(5),
164 BIP_RANGE(2),
165 BIP_RANGE(1),
166 BIP_RANGE(0.5),
167 BIP_RANGE(0.2),
168 BIP_RANGE(0.1)
169 }
170 };
171
172 static const struct comedi_lrange range_ni_E_ao_ext = {
173 4, {
174 BIP_RANGE(10),
175 UNI_RANGE(10),
176 RANGE_ext(-1, 1),
177 RANGE_ext(0, 1)
178 }
179 };
180
181 static const struct comedi_lrange *const ni_range_lkup[] = {
182 [ai_gain_16] = &range_ni_E_ai,
183 [ai_gain_8] = &range_ni_E_ai_limited,
184 [ai_gain_14] = &range_ni_E_ai_limited14,
185 [ai_gain_4] = &range_ni_E_ai_bipolar4,
186 [ai_gain_611x] = &range_ni_E_ai_611x,
187 [ai_gain_622x] = &range_ni_M_ai_622x,
188 [ai_gain_628x] = &range_ni_M_ai_628x,
189 [ai_gain_6143] = &range_bipolar5
190 };
191
192 enum aimodes {
193 AIMODE_NONE = 0,
194 AIMODE_HALF_FULL = 1,
195 AIMODE_SCAN = 2,
196 AIMODE_SAMPLE = 3,
197 };
198
199 enum ni_common_subdevices {
200 NI_AI_SUBDEV,
201 NI_AO_SUBDEV,
202 NI_DIO_SUBDEV,
203 NI_8255_DIO_SUBDEV,
204 NI_UNUSED_SUBDEV,
205 NI_CALIBRATION_SUBDEV,
206 NI_EEPROM_SUBDEV,
207 NI_PFI_DIO_SUBDEV,
208 NI_CS5529_CALIBRATION_SUBDEV,
209 NI_SERIAL_SUBDEV,
210 NI_RTSI_SUBDEV,
211 NI_GPCT0_SUBDEV,
212 NI_GPCT1_SUBDEV,
213 NI_FREQ_OUT_SUBDEV,
214 NI_NUM_SUBDEVICES
215 };
216
217 #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x))
218
219 enum timebase_nanoseconds {
220 TIMEBASE_1_NS = 50,
221 TIMEBASE_2_NS = 10000
222 };
223
224 #define SERIAL_DISABLED 0
225 #define SERIAL_600NS 600
226 #define SERIAL_1_2US 1200
227 #define SERIAL_10US 10000
228
229 static const int num_adc_stages_611x = 3;
230
231 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
232 {
233 if (dev->mmio)
234 writel(data, dev->mmio + reg);
235 else
236 outl(data, dev->iobase + reg);
237 }
238
239 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
240 {
241 if (dev->mmio)
242 writew(data, dev->mmio + reg);
243 else
244 outw(data, dev->iobase + reg);
245 }
246
247 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
248 {
249 if (dev->mmio)
250 writeb(data, dev->mmio + reg);
251 else
252 outb(data, dev->iobase + reg);
253 }
254
255 static unsigned int ni_readl(struct comedi_device *dev, int reg)
256 {
257 if (dev->mmio)
258 return readl(dev->mmio + reg);
259
260 return inl(dev->iobase + reg);
261 }
262
263 static unsigned int ni_readw(struct comedi_device *dev, int reg)
264 {
265 if (dev->mmio)
266 return readw(dev->mmio + reg);
267
268 return inw(dev->iobase + reg);
269 }
270
271 static unsigned int ni_readb(struct comedi_device *dev, int reg)
272 {
273 if (dev->mmio)
274 return readb(dev->mmio + reg);
275
276 return inb(dev->iobase + reg);
277 }
278
279 /*
280 * We automatically take advantage of STC registers that can be
281 * read/written directly in the I/O space of the board.
282 *
283 * The AT-MIO and DAQCard devices map the low 8 STC registers to
284 * iobase+reg*2.
285 *
286 * Most PCIMIO devices also map the low 8 STC registers but the
287 * 611x devices map the read registers to iobase+(addr-1)*2.
288 * For now non-windowed STC access is disabled if a PCIMIO device
289 * is detected (devpriv->mite has been initialized).
290 *
291 * The M series devices do not used windowed registers for the
292 * STC registers. The functions below handle the mapping of the
293 * windowed STC registers to the m series register offsets.
294 */
295
296 struct mio_regmap {
297 unsigned int mio_reg;
298 int size;
299 };
300
301 static const struct mio_regmap m_series_stc_write_regmap[] = {
302 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
303 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
304 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
305 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
306 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
307 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
308 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
309 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
310 /*
311 * NISTC_DIO_OUT_REG maps to:
312 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
313 */
314 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
315 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
316 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
317 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
318 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
319 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
320 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
321 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
322 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
323 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
324 [NISTC_G0_MODE_REG] = { 0x134, 2 },
325 [NISTC_G1_MODE_REG] = { 0x136, 2 },
326 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
327 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
328 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
329 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
330 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
331 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
332 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
333 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
334 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
335 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
336 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
337 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
338 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
339 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
340 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
341 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
342 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
343 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
344 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
345 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
346 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
347 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
348 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
349 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
350 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
351 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
352 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
353 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
354 [NISTC_RESET_REG] = { 0x190, 2 },
355 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
356 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
357 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
358 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
359 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
360 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
361 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
362 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
363 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
364 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
365 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
366 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
367 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
368 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
369 };
370
371 static void m_series_stc_write(struct comedi_device *dev,
372 unsigned int data, unsigned int reg)
373 {
374 const struct mio_regmap *regmap;
375
376 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
377 regmap = &m_series_stc_write_regmap[reg];
378 } else {
379 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
380 __func__, reg);
381 return;
382 }
383
384 switch (regmap->size) {
385 case 4:
386 ni_writel(dev, data, regmap->mio_reg);
387 break;
388 case 2:
389 ni_writew(dev, data, regmap->mio_reg);
390 break;
391 default:
392 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
393 __func__, reg);
394 break;
395 }
396 }
397
398 static const struct mio_regmap m_series_stc_read_regmap[] = {
399 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
400 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
401 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
402 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
403 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
404 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
405 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
406 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
407 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
408 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
409 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
410 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
411 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
412 [NISTC_STATUS1_REG] = { 0x136, 2 },
413 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
414 [NISTC_STATUS2_REG] = { 0x13a, 2 },
415 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
416 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
417 };
418
419 static unsigned int m_series_stc_read(struct comedi_device *dev,
420 unsigned int reg)
421 {
422 const struct mio_regmap *regmap;
423
424 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
425 regmap = &m_series_stc_read_regmap[reg];
426 } else {
427 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
428 __func__, reg);
429 return 0;
430 }
431
432 switch (regmap->size) {
433 case 4:
434 return ni_readl(dev, regmap->mio_reg);
435 case 2:
436 return ni_readw(dev, regmap->mio_reg);
437 case 1:
438 return ni_readb(dev, regmap->mio_reg);
439 default:
440 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
441 __func__, reg);
442 return 0;
443 }
444 }
445
446 static void ni_stc_writew(struct comedi_device *dev,
447 unsigned int data, int reg)
448 {
449 struct ni_private *devpriv = dev->private;
450 unsigned long flags;
451
452 if (devpriv->is_m_series) {
453 m_series_stc_write(dev, data, reg);
454 } else {
455 spin_lock_irqsave(&devpriv->window_lock, flags);
456 if (!devpriv->mite && reg < 8) {
457 ni_writew(dev, data, reg * 2);
458 } else {
459 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
460 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
461 }
462 spin_unlock_irqrestore(&devpriv->window_lock, flags);
463 }
464 }
465
466 static void ni_stc_writel(struct comedi_device *dev,
467 unsigned int data, int reg)
468 {
469 struct ni_private *devpriv = dev->private;
470
471 if (devpriv->is_m_series) {
472 m_series_stc_write(dev, data, reg);
473 } else {
474 ni_stc_writew(dev, data >> 16, reg);
475 ni_stc_writew(dev, data & 0xffff, reg + 1);
476 }
477 }
478
479 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482 unsigned long flags;
483 unsigned int val;
484
485 if (devpriv->is_m_series) {
486 val = m_series_stc_read(dev, reg);
487 } else {
488 spin_lock_irqsave(&devpriv->window_lock, flags);
489 if (!devpriv->mite && reg < 8) {
490 val = ni_readw(dev, reg * 2);
491 } else {
492 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
493 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
494 }
495 spin_unlock_irqrestore(&devpriv->window_lock, flags);
496 }
497 return val;
498 }
499
500 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
501 {
502 struct ni_private *devpriv = dev->private;
503 unsigned int val;
504
505 if (devpriv->is_m_series) {
506 val = m_series_stc_read(dev, reg);
507 } else {
508 val = ni_stc_readw(dev, reg) << 16;
509 val |= ni_stc_readw(dev, reg + 1);
510 }
511 return val;
512 }
513
514 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
515 unsigned int bit_mask,
516 unsigned int bit_values)
517 {
518 struct ni_private *devpriv = dev->private;
519 unsigned long flags;
520
521 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
522 switch (reg) {
523 case NISTC_INTA_ENA_REG:
524 devpriv->int_a_enable_reg &= ~bit_mask;
525 devpriv->int_a_enable_reg |= bit_values & bit_mask;
526 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
527 break;
528 case NISTC_INTB_ENA_REG:
529 devpriv->int_b_enable_reg &= ~bit_mask;
530 devpriv->int_b_enable_reg |= bit_values & bit_mask;
531 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
532 break;
533 case NISTC_IO_BIDIR_PIN_REG:
534 devpriv->io_bidirection_pin_reg &= ~bit_mask;
535 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
536 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
537 break;
538 case NI_E_DMA_AI_AO_SEL_REG:
539 devpriv->ai_ao_select_reg &= ~bit_mask;
540 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
541 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
542 break;
543 case NI_E_DMA_G0_G1_SEL_REG:
544 devpriv->g0_g1_select_reg &= ~bit_mask;
545 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
546 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
547 break;
548 case NI_M_CDIO_DMA_SEL_REG:
549 devpriv->cdio_dma_select_reg &= ~bit_mask;
550 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
551 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
552 break;
553 default:
554 dev_err(dev->class_dev, "called with invalid register %d\n",
555 reg);
556 break;
557 }
558 mmiowb();
559 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
560 }
561
562 #ifdef PCIDMA
563
564 /* selects the MITE channel to use for DMA */
565 #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \
566 ((x) == 4) ? 0x3 : \
567 ((x) == 5) ? 0x5 : 0x0)
568
569 /* DMA channel setup */
570 static int ni_request_ai_mite_channel(struct comedi_device *dev)
571 {
572 struct ni_private *devpriv = dev->private;
573 struct mite_channel *mite_chan;
574 unsigned long flags;
575 unsigned int bits;
576
577 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
578 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
579 if (!mite_chan) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581 dev_err(dev->class_dev,
582 "failed to reserve mite dma channel for analog input\n");
583 return -EBUSY;
584 }
585 mite_chan->dir = COMEDI_INPUT;
586 devpriv->ai_mite_chan = mite_chan;
587
588 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
589 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
590 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
591
592 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
593 return 0;
594 }
595
596 static int ni_request_ao_mite_channel(struct comedi_device *dev)
597 {
598 struct ni_private *devpriv = dev->private;
599 struct mite_channel *mite_chan;
600 unsigned long flags;
601 unsigned int bits;
602
603 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
604 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
605 if (!mite_chan) {
606 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
607 dev_err(dev->class_dev,
608 "failed to reserve mite dma channel for analog outut\n");
609 return -EBUSY;
610 }
611 mite_chan->dir = COMEDI_OUTPUT;
612 devpriv->ao_mite_chan = mite_chan;
613
614 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
615 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
616 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
617
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
619 return 0;
620 }
621
622 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
623 unsigned int gpct_index,
624 enum comedi_io_direction direction)
625 {
626 struct ni_private *devpriv = dev->private;
627 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
628 struct mite_channel *mite_chan;
629 unsigned long flags;
630 unsigned int bits;
631
632 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
633 mite_chan = mite_request_channel(devpriv->mite,
634 devpriv->gpct_mite_ring[gpct_index]);
635 if (!mite_chan) {
636 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
637 dev_err(dev->class_dev,
638 "failed to reserve mite dma channel for counter\n");
639 return -EBUSY;
640 }
641 mite_chan->dir = direction;
642 ni_tio_set_mite_channel(counter, mite_chan);
643
644 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
645 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
646 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
647 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
648
649 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
650 return 0;
651 }
652
653 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
654 {
655 struct ni_private *devpriv = dev->private;
656 struct mite_channel *mite_chan;
657 unsigned long flags;
658 unsigned int bits;
659
660 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
661 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
662 if (!mite_chan) {
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
664 dev_err(dev->class_dev,
665 "failed to reserve mite dma channel for correlated digital output\n");
666 return -EBUSY;
667 }
668 mite_chan->dir = COMEDI_OUTPUT;
669 devpriv->cdo_mite_chan = mite_chan;
670
671 /*
672 * XXX just guessing NI_STC_DMA_CHAN_SEL()
673 * returns the right bits, under the assumption the cdio dma
674 * selection works just like ai/ao/gpct.
675 * Definitely works for dma channels 0 and 1.
676 */
677 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
678 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
679 NI_M_CDIO_DMA_SEL_CDO_MASK,
680 NI_M_CDIO_DMA_SEL_CDO(bits));
681
682 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
683 return 0;
684 }
685 #endif /* PCIDMA */
686
687 static void ni_release_ai_mite_channel(struct comedi_device *dev)
688 {
689 #ifdef PCIDMA
690 struct ni_private *devpriv = dev->private;
691 unsigned long flags;
692
693 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
694 if (devpriv->ai_mite_chan) {
695 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
696 NI_E_DMA_AI_SEL_MASK, 0);
697 mite_release_channel(devpriv->ai_mite_chan);
698 devpriv->ai_mite_chan = NULL;
699 }
700 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
701 #endif /* PCIDMA */
702 }
703
704 static void ni_release_ao_mite_channel(struct comedi_device *dev)
705 {
706 #ifdef PCIDMA
707 struct ni_private *devpriv = dev->private;
708 unsigned long flags;
709
710 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
711 if (devpriv->ao_mite_chan) {
712 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
713 NI_E_DMA_AO_SEL_MASK, 0);
714 mite_release_channel(devpriv->ao_mite_chan);
715 devpriv->ao_mite_chan = NULL;
716 }
717 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
718 #endif /* PCIDMA */
719 }
720
721 #ifdef PCIDMA
722 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
723 unsigned int gpct_index)
724 {
725 struct ni_private *devpriv = dev->private;
726 unsigned long flags;
727
728 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
729 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
730 struct mite_channel *mite_chan =
731 devpriv->counter_dev->counters[gpct_index].mite_chan;
732
733 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
734 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
735 ni_tio_set_mite_channel(&devpriv->
736 counter_dev->counters[gpct_index],
737 NULL);
738 mite_release_channel(mite_chan);
739 }
740 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
741 }
742
743 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
744 {
745 struct ni_private *devpriv = dev->private;
746 unsigned long flags;
747
748 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
749 if (devpriv->cdo_mite_chan) {
750 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
751 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
752 mite_release_channel(devpriv->cdo_mite_chan);
753 devpriv->cdo_mite_chan = NULL;
754 }
755 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
756 }
757
758 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
759 unsigned int gpct_index, short enable)
760 {
761 struct ni_private *devpriv = dev->private;
762 unsigned int val = 0;
763 int reg;
764
765 if (devpriv->is_m_series || gpct_index > 1)
766 return;
767
768 /*
769 * e-series boards use the second irq signals to generate
770 * dma requests for their counters
771 */
772 if (gpct_index == 0) {
773 reg = NISTC_INTA2_ENA_REG;
774 if (enable)
775 val = NISTC_INTA_ENA_G0_GATE;
776 } else {
777 reg = NISTC_INTB2_ENA_REG;
778 if (enable)
779 val = NISTC_INTB_ENA_G1_GATE;
780 }
781 ni_stc_writew(dev, val, reg);
782 }
783 #endif /* PCIDMA */
784
785 static void ni_clear_ai_fifo(struct comedi_device *dev)
786 {
787 struct ni_private *devpriv = dev->private;
788 static const int timeout = 10000;
789 int i;
790
791 if (devpriv->is_6143) {
792 /* Flush the 6143 data FIFO */
793 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
794 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
795 /* Wait for complete */
796 for (i = 0; i < timeout; i++) {
797 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
798 break;
799 udelay(1);
800 }
801 if (i == timeout)
802 dev_err(dev->class_dev, "FIFO flush timeout\n");
803 } else {
804 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
805 if (devpriv->is_625x) {
806 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
807 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
808 #if 0
809 /*
810 * The NI example code does 3 convert pulses for 625x
811 * boards, But that appears to be wrong in practice.
812 */
813 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
814 NISTC_AI_CMD1_REG);
815 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
816 NISTC_AI_CMD1_REG);
817 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
818 NISTC_AI_CMD1_REG);
819 #endif
820 }
821 }
822 }
823
824 static inline void ni_ao_win_outw(struct comedi_device *dev,
825 unsigned int data, int addr)
826 {
827 struct ni_private *devpriv = dev->private;
828 unsigned long flags;
829
830 spin_lock_irqsave(&devpriv->window_lock, flags);
831 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
832 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
833 spin_unlock_irqrestore(&devpriv->window_lock, flags);
834 }
835
836 static inline void ni_ao_win_outl(struct comedi_device *dev,
837 unsigned int data, int addr)
838 {
839 struct ni_private *devpriv = dev->private;
840 unsigned long flags;
841
842 spin_lock_irqsave(&devpriv->window_lock, flags);
843 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
844 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
845 spin_unlock_irqrestore(&devpriv->window_lock, flags);
846 }
847
848 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
849 {
850 struct ni_private *devpriv = dev->private;
851 unsigned long flags;
852 unsigned short data;
853
854 spin_lock_irqsave(&devpriv->window_lock, flags);
855 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
856 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
857 spin_unlock_irqrestore(&devpriv->window_lock, flags);
858 return data;
859 }
860
861 /*
862 * ni_set_bits( ) allows different parts of the ni_mio_common driver to
863 * share registers (such as Interrupt_A_Register) without interfering with
864 * each other.
865 *
866 * NOTE: the switch/case statements are optimized out for a constant argument
867 * so this is actually quite fast--- If you must wrap another function around
868 * this make it inline to avoid a large speed penalty.
869 *
870 * value should only be 1 or 0.
871 */
872 static inline void ni_set_bits(struct comedi_device *dev, int reg,
873 unsigned int bits, unsigned int value)
874 {
875 unsigned int bit_values;
876
877 if (value)
878 bit_values = bits;
879 else
880 bit_values = 0;
881 ni_set_bitfield(dev, reg, bits, bit_values);
882 }
883
884 #ifdef PCIDMA
885 static void ni_sync_ai_dma(struct comedi_device *dev)
886 {
887 struct ni_private *devpriv = dev->private;
888 struct comedi_subdevice *s = dev->read_subdev;
889 unsigned long flags;
890
891 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
892 if (devpriv->ai_mite_chan)
893 mite_sync_dma(devpriv->ai_mite_chan, s);
894 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
895 }
896
897 static int ni_ai_drain_dma(struct comedi_device *dev)
898 {
899 struct ni_private *devpriv = dev->private;
900 int i;
901 static const int timeout = 10000;
902 unsigned long flags;
903 int retval = 0;
904
905 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
906 if (devpriv->ai_mite_chan) {
907 for (i = 0; i < timeout; i++) {
908 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
909 NISTC_AI_STATUS1_FIFO_E) &&
910 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
911 break;
912 udelay(5);
913 }
914 if (i == timeout) {
915 dev_err(dev->class_dev, "timed out\n");
916 dev_err(dev->class_dev,
917 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
918 mite_bytes_in_transit(devpriv->ai_mite_chan),
919 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
920 retval = -1;
921 }
922 }
923 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
924
925 ni_sync_ai_dma(dev);
926
927 return retval;
928 }
929
930 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
931 {
932 static const int timeout = 10000;
933 int i;
934
935 for (i = 0; i < timeout; i++) {
936 unsigned short b_status;
937
938 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
939 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
940 break;
941 /*
942 * If we poll too often, the pci bus activity seems
943 * to slow the dma transfer down.
944 */
945 usleep_range(10, 100);
946 }
947 if (i == timeout) {
948 dev_err(dev->class_dev, "timed out waiting for dma load\n");
949 return -EPIPE;
950 }
951 return 0;
952 }
953 #endif /* PCIDMA */
954
955 #ifndef PCIDMA
956
957 static void ni_ao_fifo_load(struct comedi_device *dev,
958 struct comedi_subdevice *s, int n)
959 {
960 struct ni_private *devpriv = dev->private;
961 int i;
962 unsigned short d;
963 unsigned int packed_data;
964
965 for (i = 0; i < n; i++) {
966 comedi_buf_read_samples(s, &d, 1);
967
968 if (devpriv->is_6xxx) {
969 packed_data = d & 0xffff;
970 /* 6711 only has 16 bit wide ao fifo */
971 if (!devpriv->is_6711) {
972 comedi_buf_read_samples(s, &d, 1);
973 i++;
974 packed_data |= (d << 16) & 0xffff0000;
975 }
976 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
977 } else {
978 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
979 }
980 }
981 }
982
983 /*
984 * There's a small problem if the FIFO gets really low and we
985 * don't have the data to fill it. Basically, if after we fill
986 * the FIFO with all the data available, the FIFO is _still_
987 * less than half full, we never clear the interrupt. If the
988 * IRQ is in edge mode, we never get another interrupt, because
989 * this one wasn't cleared. If in level mode, we get flooded
990 * with interrupts that we can't fulfill, because nothing ever
991 * gets put into the buffer.
992 *
993 * This kind of situation is recoverable, but it is easier to
994 * just pretend we had a FIFO underrun, since there is a good
995 * chance it will happen anyway. This is _not_ the case for
996 * RT code, as RT code might purposely be running close to the
997 * metal. Needs to be fixed eventually.
998 */
999 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1000 struct comedi_subdevice *s)
1001 {
1002 const struct ni_board_struct *board = dev->board_ptr;
1003 unsigned int nbytes;
1004 unsigned int nsamples;
1005
1006 nbytes = comedi_buf_read_n_available(s);
1007 if (nbytes == 0) {
1008 s->async->events |= COMEDI_CB_OVERFLOW;
1009 return 0;
1010 }
1011
1012 nsamples = comedi_bytes_to_samples(s, nbytes);
1013 if (nsamples > board->ao_fifo_depth / 2)
1014 nsamples = board->ao_fifo_depth / 2;
1015
1016 ni_ao_fifo_load(dev, s, nsamples);
1017
1018 return 1;
1019 }
1020
1021 static int ni_ao_prep_fifo(struct comedi_device *dev,
1022 struct comedi_subdevice *s)
1023 {
1024 const struct ni_board_struct *board = dev->board_ptr;
1025 struct ni_private *devpriv = dev->private;
1026 unsigned int nbytes;
1027 unsigned int nsamples;
1028
1029 /* reset fifo */
1030 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1031 if (devpriv->is_6xxx)
1032 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1033
1034 /* load some data */
1035 nbytes = comedi_buf_read_n_available(s);
1036 if (nbytes == 0)
1037 return 0;
1038
1039 nsamples = comedi_bytes_to_samples(s, nbytes);
1040 if (nsamples > board->ao_fifo_depth)
1041 nsamples = board->ao_fifo_depth;
1042
1043 ni_ao_fifo_load(dev, s, nsamples);
1044
1045 return nsamples;
1046 }
1047
1048 static void ni_ai_fifo_read(struct comedi_device *dev,
1049 struct comedi_subdevice *s, int n)
1050 {
1051 struct ni_private *devpriv = dev->private;
1052 struct comedi_async *async = s->async;
1053 unsigned int dl;
1054 unsigned short data;
1055 int i;
1056
1057 if (devpriv->is_611x) {
1058 for (i = 0; i < n / 2; i++) {
1059 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060 /* This may get the hi/lo data in the wrong order */
1061 data = (dl >> 16) & 0xffff;
1062 comedi_buf_write_samples(s, &data, 1);
1063 data = dl & 0xffff;
1064 comedi_buf_write_samples(s, &data, 1);
1065 }
1066 /* Check if there's a single sample stuck in the FIFO */
1067 if (n % 2) {
1068 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1069 data = dl & 0xffff;
1070 comedi_buf_write_samples(s, &data, 1);
1071 }
1072 } else if (devpriv->is_6143) {
1073 /*
1074 * This just reads the FIFO assuming the data is present,
1075 * no checks on the FIFO status are performed.
1076 */
1077 for (i = 0; i < n / 2; i++) {
1078 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1079
1080 data = (dl >> 16) & 0xffff;
1081 comedi_buf_write_samples(s, &data, 1);
1082 data = dl & 0xffff;
1083 comedi_buf_write_samples(s, &data, 1);
1084 }
1085 if (n % 2) {
1086 /* Assume there is a single sample stuck in the FIFO */
1087 /* Get stranded sample into FIFO */
1088 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1089 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1090 data = (dl >> 16) & 0xffff;
1091 comedi_buf_write_samples(s, &data, 1);
1092 }
1093 } else {
1094 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1095 dev_err(dev->class_dev,
1096 "bug! ai_fifo_buffer too small\n");
1097 async->events |= COMEDI_CB_ERROR;
1098 return;
1099 }
1100 for (i = 0; i < n; i++) {
1101 devpriv->ai_fifo_buffer[i] =
1102 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1103 }
1104 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1105 }
1106 }
1107
1108 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1109 {
1110 const struct ni_board_struct *board = dev->board_ptr;
1111 struct comedi_subdevice *s = dev->read_subdev;
1112 int n;
1113
1114 n = board->ai_fifo_depth / 2;
1115
1116 ni_ai_fifo_read(dev, s, n);
1117 }
1118 #endif
1119
1120 /* Empties the AI fifo */
1121 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1122 {
1123 struct ni_private *devpriv = dev->private;
1124 struct comedi_subdevice *s = dev->read_subdev;
1125 unsigned int dl;
1126 unsigned short data;
1127 int i;
1128
1129 if (devpriv->is_611x) {
1130 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1131 NISTC_AI_STATUS1_FIFO_E) == 0) {
1132 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1133
1134 /* This may get the hi/lo data in the wrong order */
1135 data = dl >> 16;
1136 comedi_buf_write_samples(s, &data, 1);
1137 data = dl & 0xffff;
1138 comedi_buf_write_samples(s, &data, 1);
1139 }
1140 } else if (devpriv->is_6143) {
1141 i = 0;
1142 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1143 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1144
1145 /* This may get the hi/lo data in the wrong order */
1146 data = dl >> 16;
1147 comedi_buf_write_samples(s, &data, 1);
1148 data = dl & 0xffff;
1149 comedi_buf_write_samples(s, &data, 1);
1150 i += 2;
1151 }
1152 /* Check if stranded sample is present */
1153 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1154 /* Get stranded sample into FIFO */
1155 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1156 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1157 data = (dl >> 16) & 0xffff;
1158 comedi_buf_write_samples(s, &data, 1);
1159 }
1160
1161 } else {
1162 unsigned short fe; /* fifo empty */
1163
1164 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1165 NISTC_AI_STATUS1_FIFO_E;
1166 while (fe == 0) {
1167 for (i = 0;
1168 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1169 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1170 NISTC_AI_STATUS1_FIFO_E;
1171 if (fe)
1172 break;
1173 devpriv->ai_fifo_buffer[i] =
1174 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1175 }
1176 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1177 }
1178 }
1179 }
1180
1181 static void get_last_sample_611x(struct comedi_device *dev)
1182 {
1183 struct ni_private *devpriv = dev->private;
1184 struct comedi_subdevice *s = dev->read_subdev;
1185 unsigned short data;
1186 unsigned int dl;
1187
1188 if (!devpriv->is_611x)
1189 return;
1190
1191 /* Check if there's a single sample stuck in the FIFO */
1192 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1193 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1194 data = dl & 0xffff;
1195 comedi_buf_write_samples(s, &data, 1);
1196 }
1197 }
1198
1199 static void get_last_sample_6143(struct comedi_device *dev)
1200 {
1201 struct ni_private *devpriv = dev->private;
1202 struct comedi_subdevice *s = dev->read_subdev;
1203 unsigned short data;
1204 unsigned int dl;
1205
1206 if (!devpriv->is_6143)
1207 return;
1208
1209 /* Check if there's a single sample stuck in the FIFO */
1210 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1211 /* Get stranded sample into FIFO */
1212 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1213 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1214
1215 /* This may get the hi/lo data in the wrong order */
1216 data = (dl >> 16) & 0xffff;
1217 comedi_buf_write_samples(s, &data, 1);
1218 }
1219 }
1220
1221 static void shutdown_ai_command(struct comedi_device *dev)
1222 {
1223 struct comedi_subdevice *s = dev->read_subdev;
1224
1225 #ifdef PCIDMA
1226 ni_ai_drain_dma(dev);
1227 #endif
1228 ni_handle_fifo_dregs(dev);
1229 get_last_sample_611x(dev);
1230 get_last_sample_6143(dev);
1231
1232 s->async->events |= COMEDI_CB_EOA;
1233 }
1234
1235 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1236 {
1237 struct ni_private *devpriv = dev->private;
1238
1239 if (devpriv->aimode == AIMODE_SCAN) {
1240 #ifdef PCIDMA
1241 static const int timeout = 10;
1242 int i;
1243
1244 for (i = 0; i < timeout; i++) {
1245 ni_sync_ai_dma(dev);
1246 if ((s->async->events & COMEDI_CB_EOS))
1247 break;
1248 udelay(1);
1249 }
1250 #else
1251 ni_handle_fifo_dregs(dev);
1252 s->async->events |= COMEDI_CB_EOS;
1253 #endif
1254 }
1255 /* handle special case of single scan */
1256 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1257 shutdown_ai_command(dev);
1258 }
1259
1260 static void handle_gpct_interrupt(struct comedi_device *dev,
1261 unsigned short counter_index)
1262 {
1263 #ifdef PCIDMA
1264 struct ni_private *devpriv = dev->private;
1265 struct comedi_subdevice *s;
1266
1267 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1268
1269 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1270 s);
1271 comedi_handle_events(dev, s);
1272 #endif
1273 }
1274
1275 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1276 {
1277 unsigned short ack = 0;
1278
1279 if (a_status & NISTC_AI_STATUS1_SC_TC)
1280 ack |= NISTC_INTA_ACK_AI_SC_TC;
1281 if (a_status & NISTC_AI_STATUS1_START1)
1282 ack |= NISTC_INTA_ACK_AI_START1;
1283 if (a_status & NISTC_AI_STATUS1_START)
1284 ack |= NISTC_INTA_ACK_AI_START;
1285 if (a_status & NISTC_AI_STATUS1_STOP)
1286 ack |= NISTC_INTA_ACK_AI_STOP;
1287 if (ack)
1288 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1289 }
1290
1291 static void handle_a_interrupt(struct comedi_device *dev,
1292 struct comedi_subdevice *s,
1293 unsigned short status)
1294 {
1295 struct comedi_cmd *cmd = &s->async->cmd;
1296
1297 /* test for all uncommon interrupt events at the same time */
1298 if (status & (NISTC_AI_STATUS1_ERR |
1299 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1300 if (status == 0xffff) {
1301 dev_err(dev->class_dev, "Card removed?\n");
1302 /*
1303 * We probably aren't even running a command now,
1304 * so it's a good idea to be careful.
1305 */
1306 if (comedi_is_subdevice_running(s))
1307 s->async->events |= COMEDI_CB_ERROR;
1308 return;
1309 }
1310 if (status & NISTC_AI_STATUS1_ERR) {
1311 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1312 status);
1313
1314 shutdown_ai_command(dev);
1315
1316 s->async->events |= COMEDI_CB_ERROR;
1317 if (status & NISTC_AI_STATUS1_OVER)
1318 s->async->events |= COMEDI_CB_OVERFLOW;
1319 return;
1320 }
1321 if (status & NISTC_AI_STATUS1_SC_TC) {
1322 if (cmd->stop_src == TRIG_COUNT)
1323 shutdown_ai_command(dev);
1324 }
1325 }
1326 #ifndef PCIDMA
1327 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1328 int i;
1329 static const int timeout = 10;
1330 /*
1331 * PCMCIA cards (at least 6036) seem to stop producing
1332 * interrupts if we fail to get the fifo less than half
1333 * full, so loop to be sure.
1334 */
1335 for (i = 0; i < timeout; ++i) {
1336 ni_handle_fifo_half_full(dev);
1337 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1338 NISTC_AI_STATUS1_FIFO_HF) == 0)
1339 break;
1340 }
1341 }
1342 #endif /* !PCIDMA */
1343
1344 if (status & NISTC_AI_STATUS1_STOP)
1345 ni_handle_eos(dev, s);
1346 }
1347
1348 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1349 {
1350 unsigned short ack = 0;
1351
1352 if (b_status & NISTC_AO_STATUS1_BC_TC)
1353 ack |= NISTC_INTB_ACK_AO_BC_TC;
1354 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1355 ack |= NISTC_INTB_ACK_AO_ERR;
1356 if (b_status & NISTC_AO_STATUS1_START)
1357 ack |= NISTC_INTB_ACK_AO_START;
1358 if (b_status & NISTC_AO_STATUS1_START1)
1359 ack |= NISTC_INTB_ACK_AO_START1;
1360 if (b_status & NISTC_AO_STATUS1_UC_TC)
1361 ack |= NISTC_INTB_ACK_AO_UC_TC;
1362 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1363 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1364 if (b_status & NISTC_AO_STATUS1_UPDATE)
1365 ack |= NISTC_INTB_ACK_AO_UPDATE;
1366 if (ack)
1367 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1368 }
1369
1370 static void handle_b_interrupt(struct comedi_device *dev,
1371 struct comedi_subdevice *s,
1372 unsigned short b_status)
1373 {
1374 if (b_status == 0xffff)
1375 return;
1376 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1377 dev_err(dev->class_dev,
1378 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1379 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1380 s->async->events |= COMEDI_CB_OVERFLOW;
1381 }
1382
1383 if (s->async->cmd.stop_src != TRIG_NONE &&
1384 b_status & NISTC_AO_STATUS1_BC_TC)
1385 s->async->events |= COMEDI_CB_EOA;
1386
1387 #ifndef PCIDMA
1388 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1389 int ret;
1390
1391 ret = ni_ao_fifo_half_empty(dev, s);
1392 if (!ret) {
1393 dev_err(dev->class_dev, "AO buffer underrun\n");
1394 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1395 NISTC_INTB_ENA_AO_FIFO |
1396 NISTC_INTB_ENA_AO_ERR, 0);
1397 s->async->events |= COMEDI_CB_OVERFLOW;
1398 }
1399 }
1400 #endif
1401 }
1402
1403 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1404 void *data, unsigned int num_bytes,
1405 unsigned int chan_index)
1406 {
1407 struct ni_private *devpriv = dev->private;
1408 struct comedi_async *async = s->async;
1409 struct comedi_cmd *cmd = &async->cmd;
1410 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1411 unsigned short *array = data;
1412 unsigned int *larray = data;
1413 unsigned int i;
1414 #ifdef PCIDMA
1415 __le16 *barray = data;
1416 __le32 *blarray = data;
1417 #endif
1418
1419 for (i = 0; i < nsamples; i++) {
1420 #ifdef PCIDMA
1421 if (s->subdev_flags & SDF_LSAMPL)
1422 larray[i] = le32_to_cpu(blarray[i]);
1423 else
1424 array[i] = le16_to_cpu(barray[i]);
1425 #endif
1426 if (s->subdev_flags & SDF_LSAMPL)
1427 larray[i] += devpriv->ai_offset[chan_index];
1428 else
1429 array[i] += devpriv->ai_offset[chan_index];
1430 chan_index++;
1431 chan_index %= cmd->chanlist_len;
1432 }
1433 }
1434
1435 #ifdef PCIDMA
1436
1437 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1438 {
1439 struct ni_private *devpriv = dev->private;
1440 struct comedi_subdevice *s = dev->read_subdev;
1441 int retval;
1442 unsigned long flags;
1443
1444 retval = ni_request_ai_mite_channel(dev);
1445 if (retval)
1446 return retval;
1447
1448 /* write alloc the entire buffer */
1449 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1450
1451 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1452 if (!devpriv->ai_mite_chan) {
1453 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1454 return -EIO;
1455 }
1456
1457 if (devpriv->is_611x || devpriv->is_6143)
1458 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1459 else if (devpriv->is_628x)
1460 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1461 else
1462 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1463
1464 /*start the MITE */
1465 mite_dma_arm(devpriv->ai_mite_chan);
1466 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1467
1468 return 0;
1469 }
1470
1471 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1472 {
1473 struct ni_private *devpriv = dev->private;
1474 struct comedi_subdevice *s = dev->write_subdev;
1475 int retval;
1476 unsigned long flags;
1477
1478 retval = ni_request_ao_mite_channel(dev);
1479 if (retval)
1480 return retval;
1481
1482 /* read alloc the entire buffer */
1483 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1484
1485 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1486 if (devpriv->ao_mite_chan) {
1487 if (devpriv->is_611x || devpriv->is_6713) {
1488 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1489 } else {
1490 /*
1491 * Doing 32 instead of 16 bit wide transfers from
1492 * memory makes the mite do 32 bit pci transfers,
1493 * doubling pci bandwidth.
1494 */
1495 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1496 }
1497 mite_dma_arm(devpriv->ao_mite_chan);
1498 } else {
1499 retval = -EIO;
1500 }
1501 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1502
1503 return retval;
1504 }
1505
1506 #endif /* PCIDMA */
1507
1508 /*
1509 * used for both cancel ioctl and board initialization
1510 *
1511 * this is pretty harsh for a cancel, but it works...
1512 */
1513 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1514 {
1515 struct ni_private *devpriv = dev->private;
1516 unsigned int ai_personal;
1517 unsigned int ai_out_ctrl;
1518
1519 ni_release_ai_mite_channel(dev);
1520 /* ai configuration */
1521 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1522 NISTC_RESET_REG);
1523
1524 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1525
1526 ni_clear_ai_fifo(dev);
1527
1528 if (!devpriv->is_6143)
1529 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1530
1531 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1532 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1533 NISTC_AI_MODE1_RSVD
1534 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1535 NISTC_AI_MODE1_REG);
1536 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1537 /* generate FIFO interrupts on non-empty */
1538 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1539 NISTC_AI_MODE3_REG);
1540
1541 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1542 NISTC_AI_PERSONAL_SOC_POLARITY |
1543 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1544 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1545 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1546 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1547 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1548 if (devpriv->is_611x) {
1549 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1550 } else if (devpriv->is_6143) {
1551 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1552 } else {
1553 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1554 if (devpriv->is_622x)
1555 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1556 else
1557 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1558 }
1559 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1560 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1561
1562 /* the following registers should not be changed, because there
1563 * are no backup registers in devpriv. If you want to change
1564 * any of these, add a backup register and other appropriate code:
1565 * NISTC_AI_MODE1_REG
1566 * NISTC_AI_MODE3_REG
1567 * NISTC_AI_PERSONAL_REG
1568 * NISTC_AI_OUT_CTRL_REG
1569 */
1570
1571 /* clear interrupts */
1572 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1573
1574 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1575
1576 return 0;
1577 }
1578
1579 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1580 {
1581 unsigned long flags;
1582 int count;
1583
1584 /* lock to avoid race with interrupt handler */
1585 spin_lock_irqsave(&dev->spinlock, flags);
1586 #ifndef PCIDMA
1587 ni_handle_fifo_dregs(dev);
1588 #else
1589 ni_sync_ai_dma(dev);
1590 #endif
1591 count = comedi_buf_n_bytes_ready(s);
1592 spin_unlock_irqrestore(&dev->spinlock, flags);
1593
1594 return count;
1595 }
1596
1597 static void ni_prime_channelgain_list(struct comedi_device *dev)
1598 {
1599 int i;
1600
1601 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1602 for (i = 0; i < NI_TIMEOUT; ++i) {
1603 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1604 NISTC_AI_STATUS1_FIFO_E)) {
1605 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1606 return;
1607 }
1608 udelay(1);
1609 }
1610 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1611 }
1612
1613 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1614 unsigned int n_chan,
1615 unsigned int *list)
1616 {
1617 const struct ni_board_struct *board = dev->board_ptr;
1618 struct ni_private *devpriv = dev->private;
1619 unsigned int chan, range, aref;
1620 unsigned int i;
1621 unsigned int dither;
1622 unsigned int range_code;
1623
1624 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1625
1626 if ((list[0] & CR_ALT_SOURCE)) {
1627 unsigned int bypass_bits;
1628
1629 chan = CR_CHAN(list[0]);
1630 range = CR_RANGE(list[0]);
1631 range_code = ni_gainlkup[board->gainlkup][range];
1632 dither = (list[0] & CR_ALT_FILTER) != 0;
1633 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1634 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1635 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1636 devpriv->ai_calib_source;
1637 if (dither)
1638 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1639 /* don't use 2's complement encoding */
1640 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1641 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1642 } else {
1643 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1644 }
1645 for (i = 0; i < n_chan; i++) {
1646 unsigned int config_bits = 0;
1647
1648 chan = CR_CHAN(list[i]);
1649 aref = CR_AREF(list[i]);
1650 range = CR_RANGE(list[i]);
1651 dither = (list[i] & CR_ALT_FILTER) != 0;
1652
1653 range_code = ni_gainlkup[board->gainlkup][range];
1654 devpriv->ai_offset[i] = 0;
1655 switch (aref) {
1656 case AREF_DIFF:
1657 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1658 break;
1659 case AREF_COMMON:
1660 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1661 break;
1662 case AREF_GROUND:
1663 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1664 break;
1665 case AREF_OTHER:
1666 break;
1667 }
1668 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1669 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1670 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1671 if (i == n_chan - 1)
1672 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1673 if (dither)
1674 config_bits |= NI_M_AI_CFG_DITHER;
1675 /* don't use 2's complement encoding */
1676 config_bits |= NI_M_AI_CFG_POLARITY;
1677 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1678 }
1679 ni_prime_channelgain_list(dev);
1680 }
1681
1682 /*
1683 * Notes on the 6110 and 6111:
1684 * These boards a slightly different than the rest of the series, since
1685 * they have multiple A/D converters.
1686 * From the driver side, the configuration memory is a
1687 * little different.
1688 * Configuration Memory Low:
1689 * bits 15-9: same
1690 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1691 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1692 * 1001 gain=0.1 (+/- 50)
1693 * 1010 0.2
1694 * 1011 0.1
1695 * 0001 1
1696 * 0010 2
1697 * 0011 5
1698 * 0100 10
1699 * 0101 20
1700 * 0110 50
1701 * Configuration Memory High:
1702 * bits 12-14: Channel Type
1703 * 001 for differential
1704 * 000 for calibration
1705 * bit 11: coupling (this is not currently handled)
1706 * 1 AC coupling
1707 * 0 DC coupling
1708 * bits 0-2: channel
1709 * valid channels are 0-3
1710 */
1711 static void ni_load_channelgain_list(struct comedi_device *dev,
1712 struct comedi_subdevice *s,
1713 unsigned int n_chan, unsigned int *list)
1714 {
1715 const struct ni_board_struct *board = dev->board_ptr;
1716 struct ni_private *devpriv = dev->private;
1717 unsigned int offset = (s->maxdata + 1) >> 1;
1718 unsigned int chan, range, aref;
1719 unsigned int i;
1720 unsigned int hi, lo;
1721 unsigned int dither;
1722
1723 if (devpriv->is_m_series) {
1724 ni_m_series_load_channelgain_list(dev, n_chan, list);
1725 return;
1726 }
1727 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1728 if (devpriv->changain_state &&
1729 devpriv->changain_spec == list[0]) {
1730 /* ready to go. */
1731 return;
1732 }
1733 devpriv->changain_state = 1;
1734 devpriv->changain_spec = list[0];
1735 } else {
1736 devpriv->changain_state = 0;
1737 }
1738
1739 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1740
1741 /* Set up Calibration mode if required */
1742 if (devpriv->is_6143) {
1743 if ((list[0] & CR_ALT_SOURCE) &&
1744 !devpriv->ai_calib_source_enabled) {
1745 /* Strobe Relay enable bit */
1746 ni_writew(dev, devpriv->ai_calib_source |
1747 NI6143_CALIB_CHAN_RELAY_ON,
1748 NI6143_CALIB_CHAN_REG);
1749 ni_writew(dev, devpriv->ai_calib_source,
1750 NI6143_CALIB_CHAN_REG);
1751 devpriv->ai_calib_source_enabled = 1;
1752 /* Allow relays to change */
1753 msleep_interruptible(100);
1754 } else if (!(list[0] & CR_ALT_SOURCE) &&
1755 devpriv->ai_calib_source_enabled) {
1756 /* Strobe Relay disable bit */
1757 ni_writew(dev, devpriv->ai_calib_source |
1758 NI6143_CALIB_CHAN_RELAY_OFF,
1759 NI6143_CALIB_CHAN_REG);
1760 ni_writew(dev, devpriv->ai_calib_source,
1761 NI6143_CALIB_CHAN_REG);
1762 devpriv->ai_calib_source_enabled = 0;
1763 /* Allow relays to change */
1764 msleep_interruptible(100);
1765 }
1766 }
1767
1768 for (i = 0; i < n_chan; i++) {
1769 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1770 chan = devpriv->ai_calib_source;
1771 else
1772 chan = CR_CHAN(list[i]);
1773 aref = CR_AREF(list[i]);
1774 range = CR_RANGE(list[i]);
1775 dither = (list[i] & CR_ALT_FILTER) != 0;
1776
1777 /* fix the external/internal range differences */
1778 range = ni_gainlkup[board->gainlkup][range];
1779 if (devpriv->is_611x)
1780 devpriv->ai_offset[i] = offset;
1781 else
1782 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1783
1784 hi = 0;
1785 if ((list[i] & CR_ALT_SOURCE)) {
1786 if (devpriv->is_611x)
1787 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1788 NI611X_CALIB_CHAN_SEL_REG);
1789 } else {
1790 if (devpriv->is_611x)
1791 aref = AREF_DIFF;
1792 else if (devpriv->is_6143)
1793 aref = AREF_OTHER;
1794 switch (aref) {
1795 case AREF_DIFF:
1796 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1797 break;
1798 case AREF_COMMON:
1799 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1800 break;
1801 case AREF_GROUND:
1802 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1803 break;
1804 case AREF_OTHER:
1805 break;
1806 }
1807 }
1808 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1809
1810 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1811
1812 if (!devpriv->is_6143) {
1813 lo = NI_E_AI_CFG_LO_GAIN(range);
1814
1815 if (i == n_chan - 1)
1816 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1817 if (dither)
1818 lo |= NI_E_AI_CFG_LO_DITHER;
1819
1820 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1821 }
1822 }
1823
1824 /* prime the channel/gain list */
1825 if (!devpriv->is_611x && !devpriv->is_6143)
1826 ni_prime_channelgain_list(dev);
1827 }
1828
1829 static int ni_ai_insn_read(struct comedi_device *dev,
1830 struct comedi_subdevice *s,
1831 struct comedi_insn *insn,
1832 unsigned int *data)
1833 {
1834 struct ni_private *devpriv = dev->private;
1835 unsigned int mask = (s->maxdata + 1) >> 1;
1836 int i, n;
1837 unsigned int signbits;
1838 unsigned int d;
1839 unsigned long dl;
1840
1841 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1842
1843 ni_clear_ai_fifo(dev);
1844
1845 signbits = devpriv->ai_offset[0];
1846 if (devpriv->is_611x) {
1847 for (n = 0; n < num_adc_stages_611x; n++) {
1848 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1849 NISTC_AI_CMD1_REG);
1850 udelay(1);
1851 }
1852 for (n = 0; n < insn->n; n++) {
1853 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1854 NISTC_AI_CMD1_REG);
1855 /* The 611x has screwy 32-bit FIFOs. */
1856 d = 0;
1857 for (i = 0; i < NI_TIMEOUT; i++) {
1858 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1859 d = ni_readl(dev,
1860 NI611X_AI_FIFO_DATA_REG);
1861 d >>= 16;
1862 d &= 0xffff;
1863 break;
1864 }
1865 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1866 NISTC_AI_STATUS1_FIFO_E)) {
1867 d = ni_readl(dev,
1868 NI611X_AI_FIFO_DATA_REG);
1869 d &= 0xffff;
1870 break;
1871 }
1872 }
1873 if (i == NI_TIMEOUT) {
1874 dev_err(dev->class_dev, "timeout\n");
1875 return -ETIME;
1876 }
1877 d += signbits;
1878 data[n] = d;
1879 }
1880 } else if (devpriv->is_6143) {
1881 for (n = 0; n < insn->n; n++) {
1882 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1883 NISTC_AI_CMD1_REG);
1884
1885 /*
1886 * The 6143 has 32-bit FIFOs. You need to strobe a
1887 * bit to move a single 16bit stranded sample into
1888 * the FIFO.
1889 */
1890 dl = 0;
1891 for (i = 0; i < NI_TIMEOUT; i++) {
1892 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1893 0x01) {
1894 /* Get stranded sample into FIFO */
1895 ni_writel(dev, 0x01,
1896 NI6143_AI_FIFO_CTRL_REG);
1897 dl = ni_readl(dev,
1898 NI6143_AI_FIFO_DATA_REG);
1899 break;
1900 }
1901 }
1902 if (i == NI_TIMEOUT) {
1903 dev_err(dev->class_dev, "timeout\n");
1904 return -ETIME;
1905 }
1906 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1907 }
1908 } else {
1909 for (n = 0; n < insn->n; n++) {
1910 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1911 NISTC_AI_CMD1_REG);
1912 for (i = 0; i < NI_TIMEOUT; i++) {
1913 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1914 NISTC_AI_STATUS1_FIFO_E))
1915 break;
1916 }
1917 if (i == NI_TIMEOUT) {
1918 dev_err(dev->class_dev, "timeout\n");
1919 return -ETIME;
1920 }
1921 if (devpriv->is_m_series) {
1922 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1923 dl &= mask;
1924 data[n] = dl;
1925 } else {
1926 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1927 /* subtle: needs to be short addition */
1928 d += signbits;
1929 data[n] = d;
1930 }
1931 }
1932 }
1933 return insn->n;
1934 }
1935
1936 static int ni_ns_to_timer(const struct comedi_device *dev,
1937 unsigned int nanosec, unsigned int flags)
1938 {
1939 struct ni_private *devpriv = dev->private;
1940 int divider;
1941
1942 switch (flags & CMDF_ROUND_MASK) {
1943 case CMDF_ROUND_NEAREST:
1944 default:
1945 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1946 break;
1947 case CMDF_ROUND_DOWN:
1948 divider = (nanosec) / devpriv->clock_ns;
1949 break;
1950 case CMDF_ROUND_UP:
1951 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1952 break;
1953 }
1954 return divider - 1;
1955 }
1956
1957 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1958 {
1959 struct ni_private *devpriv = dev->private;
1960
1961 return devpriv->clock_ns * (timer + 1);
1962 }
1963
1964 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1965 struct comedi_subdevice *sdev,
1966 const struct comedi_cmd *cmd,
1967 unsigned int max_count) {
1968 #ifdef PCIDMA
1969 unsigned int nbytes = max_count;
1970
1971 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1972 nbytes = cmd->stop_arg;
1973 nbytes *= comedi_bytes_per_scan(sdev);
1974
1975 if (nbytes > sdev->async->prealloc_bufsz) {
1976 if (cmd->stop_arg > 0)
1977 dev_err(sdev->device->class_dev,
1978 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
1979
1980 /*
1981 * we can only transfer up to the size of the buffer. In this
1982 * case, the user is expected to continue to write into the
1983 * comedi buffer (already implemented as a ring buffer).
1984 */
1985 nbytes = sdev->async->prealloc_bufsz;
1986 }
1987
1988 mite_init_ring_descriptors(ring, sdev, nbytes);
1989 #else
1990 dev_err(sdev->device->class_dev,
1991 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
1992 #endif
1993 }
1994
1995 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1996 unsigned int num_channels)
1997 {
1998 const struct ni_board_struct *board = dev->board_ptr;
1999 struct ni_private *devpriv = dev->private;
2000
2001 /* simultaneously-sampled inputs */
2002 if (devpriv->is_611x || devpriv->is_6143)
2003 return board->ai_speed;
2004
2005 /* multiplexed inputs */
2006 return board->ai_speed * num_channels;
2007 }
2008
2009 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2010 struct comedi_cmd *cmd)
2011 {
2012 const struct ni_board_struct *board = dev->board_ptr;
2013 struct ni_private *devpriv = dev->private;
2014 int err = 0;
2015 unsigned int tmp;
2016 unsigned int sources;
2017
2018 /* Step 1 : check if triggers are trivially valid */
2019
2020 err |= comedi_check_trigger_src(&cmd->start_src,
2021 TRIG_NOW | TRIG_INT | TRIG_EXT);
2022 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2023 TRIG_TIMER | TRIG_EXT);
2024
2025 sources = TRIG_TIMER | TRIG_EXT;
2026 if (devpriv->is_611x || devpriv->is_6143)
2027 sources |= TRIG_NOW;
2028 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2029
2030 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2031 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2032
2033 if (err)
2034 return 1;
2035
2036 /* Step 2a : make sure trigger sources are unique */
2037
2038 err |= comedi_check_trigger_is_unique(cmd->start_src);
2039 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2040 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2041 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2042
2043 /* Step 2b : and mutually compatible */
2044
2045 if (err)
2046 return 2;
2047
2048 /* Step 3: check if arguments are trivially valid */
2049
2050 switch (cmd->start_src) {
2051 case TRIG_NOW:
2052 case TRIG_INT:
2053 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2054 break;
2055 case TRIG_EXT:
2056 tmp = CR_CHAN(cmd->start_arg);
2057
2058 if (tmp > 16)
2059 tmp = 16;
2060 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2061 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2062 break;
2063 }
2064
2065 if (cmd->scan_begin_src == TRIG_TIMER) {
2066 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2067 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2068 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2069 devpriv->clock_ns *
2070 0xffffff);
2071 } else if (cmd->scan_begin_src == TRIG_EXT) {
2072 /* external trigger */
2073 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2074
2075 if (tmp > 16)
2076 tmp = 16;
2077 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2078 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2079 } else { /* TRIG_OTHER */
2080 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2081 }
2082
2083 if (cmd->convert_src == TRIG_TIMER) {
2084 if (devpriv->is_611x || devpriv->is_6143) {
2085 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2086 0);
2087 } else {
2088 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2089 board->ai_speed);
2090 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2091 devpriv->clock_ns *
2092 0xffff);
2093 }
2094 } else if (cmd->convert_src == TRIG_EXT) {
2095 /* external trigger */
2096 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2097
2098 if (tmp > 16)
2099 tmp = 16;
2100 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2101 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2102 } else if (cmd->convert_src == TRIG_NOW) {
2103 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2104 }
2105
2106 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2107 cmd->chanlist_len);
2108
2109 if (cmd->stop_src == TRIG_COUNT) {
2110 unsigned int max_count = 0x01000000;
2111
2112 if (devpriv->is_611x)
2113 max_count -= num_adc_stages_611x;
2114 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2115 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2116 } else {
2117 /* TRIG_NONE */
2118 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2119 }
2120
2121 if (err)
2122 return 3;
2123
2124 /* step 4: fix up any arguments */
2125
2126 if (cmd->scan_begin_src == TRIG_TIMER) {
2127 tmp = cmd->scan_begin_arg;
2128 cmd->scan_begin_arg =
2129 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2130 cmd->scan_begin_arg,
2131 cmd->flags));
2132 if (tmp != cmd->scan_begin_arg)
2133 err++;
2134 }
2135 if (cmd->convert_src == TRIG_TIMER) {
2136 if (!devpriv->is_611x && !devpriv->is_6143) {
2137 tmp = cmd->convert_arg;
2138 cmd->convert_arg =
2139 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2140 cmd->convert_arg,
2141 cmd->flags));
2142 if (tmp != cmd->convert_arg)
2143 err++;
2144 if (cmd->scan_begin_src == TRIG_TIMER &&
2145 cmd->scan_begin_arg <
2146 cmd->convert_arg * cmd->scan_end_arg) {
2147 cmd->scan_begin_arg =
2148 cmd->convert_arg * cmd->scan_end_arg;
2149 err++;
2150 }
2151 }
2152 }
2153
2154 if (err)
2155 return 4;
2156
2157 return 0;
2158 }
2159
2160 static int ni_ai_inttrig(struct comedi_device *dev,
2161 struct comedi_subdevice *s,
2162 unsigned int trig_num)
2163 {
2164 struct ni_private *devpriv = dev->private;
2165 struct comedi_cmd *cmd = &s->async->cmd;
2166
2167 if (trig_num != cmd->start_arg)
2168 return -EINVAL;
2169
2170 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2171 NISTC_AI_CMD2_REG);
2172 s->async->inttrig = NULL;
2173
2174 return 1;
2175 }
2176
2177 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2178 {
2179 struct ni_private *devpriv = dev->private;
2180 const struct comedi_cmd *cmd = &s->async->cmd;
2181 int timer;
2182 int mode1 = 0; /* mode1 is needed for both stop and convert */
2183 int mode2 = 0;
2184 int start_stop_select = 0;
2185 unsigned int stop_count;
2186 int interrupt_a_enable = 0;
2187 unsigned int ai_trig;
2188
2189 if (dev->irq == 0) {
2190 dev_err(dev->class_dev, "cannot run command without an irq\n");
2191 return -EIO;
2192 }
2193 ni_clear_ai_fifo(dev);
2194
2195 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2196
2197 /* start configuration */
2198 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2199
2200 /*
2201 * Disable analog triggering for now, since it interferes
2202 * with the use of pfi0.
2203 */
2204 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2205 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2206
2207 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2208 switch (cmd->start_src) {
2209 case TRIG_INT:
2210 case TRIG_NOW:
2211 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2212 NISTC_AI_TRIG_START1_SEL(0);
2213 break;
2214 case TRIG_EXT:
2215 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2216 1);
2217
2218 if (cmd->start_arg & CR_INVERT)
2219 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2220 if (cmd->start_arg & CR_EDGE)
2221 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2222 break;
2223 }
2224 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2225
2226 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2227 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2228 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2229 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2230
2231 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2232 /* logic low */
2233 start_stop_select |= NISTC_AI_STOP_POLARITY |
2234 NISTC_AI_STOP_SEL(31) |
2235 NISTC_AI_STOP_SYNC;
2236 } else {
2237 /* ai configuration memory */
2238 start_stop_select |= NISTC_AI_STOP_SEL(19);
2239 }
2240 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2241
2242 devpriv->ai_cmd2 = 0;
2243 switch (cmd->stop_src) {
2244 case TRIG_COUNT:
2245 stop_count = cmd->stop_arg - 1;
2246
2247 if (devpriv->is_611x) {
2248 /* have to take 3 stage adc pipeline into account */
2249 stop_count += num_adc_stages_611x;
2250 }
2251 /* stage number of scans */
2252 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2253
2254 mode1 |= NISTC_AI_MODE1_START_STOP |
2255 NISTC_AI_MODE1_RSVD |
2256 NISTC_AI_MODE1_TRIGGER_ONCE;
2257 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2258 /* load SC (Scan Count) */
2259 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2260
2261 if (stop_count == 0) {
2262 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2263 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2264 /*
2265 * This is required to get the last sample for
2266 * chanlist_len > 1, not sure why.
2267 */
2268 if (cmd->chanlist_len > 1)
2269 start_stop_select |= NISTC_AI_STOP_POLARITY |
2270 NISTC_AI_STOP_EDGE;
2271 }
2272 break;
2273 case TRIG_NONE:
2274 /* stage number of scans */
2275 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2276
2277 mode1 |= NISTC_AI_MODE1_START_STOP |
2278 NISTC_AI_MODE1_RSVD |
2279 NISTC_AI_MODE1_CONTINUOUS;
2280 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2281
2282 /* load SC (Scan Count) */
2283 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2284 break;
2285 }
2286
2287 switch (cmd->scan_begin_src) {
2288 case TRIG_TIMER:
2289 /*
2290 * stop bits for non 611x boards
2291 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2292 * NISTC_AI_MODE2_PRE_TRIGGER=0
2293 * NISTC_AI_START_STOP_REG:
2294 * NISTC_AI_START_POLARITY=0 (?) rising edge
2295 * NISTC_AI_START_EDGE=1 edge triggered
2296 * NISTC_AI_START_SYNC=1 (?)
2297 * NISTC_AI_START_SEL=0 SI_TC
2298 * NISTC_AI_STOP_POLARITY=0 rising edge
2299 * NISTC_AI_STOP_EDGE=0 level
2300 * NISTC_AI_STOP_SYNC=1
2301 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2302 */
2303 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2304 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2305
2306 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2307 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2308 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2309 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2310
2311 /* load SI */
2312 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2313 CMDF_ROUND_NEAREST);
2314 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2315 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2316 break;
2317 case TRIG_EXT:
2318 if (cmd->scan_begin_arg & CR_EDGE)
2319 start_stop_select |= NISTC_AI_START_EDGE;
2320 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2321 start_stop_select |= NISTC_AI_START_POLARITY;
2322 if (cmd->scan_begin_src != cmd->convert_src ||
2323 (cmd->scan_begin_arg & ~CR_EDGE) !=
2324 (cmd->convert_arg & ~CR_EDGE))
2325 start_stop_select |= NISTC_AI_START_SYNC;
2326 start_stop_select |=
2327 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2328 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2329 break;
2330 }
2331
2332 switch (cmd->convert_src) {
2333 case TRIG_TIMER:
2334 case TRIG_NOW:
2335 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2336 timer = 1;
2337 else
2338 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2339 CMDF_ROUND_NEAREST);
2340 /* 0,0 does not work */
2341 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2342 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2343
2344 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2345 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2346 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2347
2348 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2349
2350 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2351 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2352 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2353 break;
2354 case TRIG_EXT:
2355 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2356 CR_CHAN(cmd->convert_arg));
2357 if ((cmd->convert_arg & CR_INVERT) == 0)
2358 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2359 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2360
2361 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2362 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2363 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2364
2365 break;
2366 }
2367
2368 if (dev->irq) {
2369 /* interrupt on FIFO, errors, SC_TC */
2370 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2371 NISTC_INTA_ENA_AI_SC_TC;
2372
2373 #ifndef PCIDMA
2374 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2375 #endif
2376
2377 if ((cmd->flags & CMDF_WAKE_EOS) ||
2378 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2379 /* wake on end-of-scan */
2380 devpriv->aimode = AIMODE_SCAN;
2381 } else {
2382 devpriv->aimode = AIMODE_HALF_FULL;
2383 }
2384
2385 switch (devpriv->aimode) {
2386 case AIMODE_HALF_FULL:
2387 /* FIFO interrupts and DMA requests on half-full */
2388 #ifdef PCIDMA
2389 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2390 NISTC_AI_MODE3_REG);
2391 #else
2392 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2393 NISTC_AI_MODE3_REG);
2394 #endif
2395 break;
2396 case AIMODE_SAMPLE:
2397 /*generate FIFO interrupts on non-empty */
2398 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2399 NISTC_AI_MODE3_REG);
2400 break;
2401 case AIMODE_SCAN:
2402 #ifdef PCIDMA
2403 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2404 NISTC_AI_MODE3_REG);
2405 #else
2406 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2407 NISTC_AI_MODE3_REG);
2408 #endif
2409 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2410 break;
2411 default:
2412 break;
2413 }
2414
2415 /* clear interrupts */
2416 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2417
2418 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2419 } else {
2420 /* interrupt on nothing */
2421 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2422
2423 /* XXX start polling if necessary */
2424 }
2425
2426 /* end configuration */
2427 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2428
2429 switch (cmd->scan_begin_src) {
2430 case TRIG_TIMER:
2431 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2432 NISTC_AI_CMD1_SI_ARM |
2433 NISTC_AI_CMD1_DIV_ARM |
2434 NISTC_AI_CMD1_SC_ARM,
2435 NISTC_AI_CMD1_REG);
2436 break;
2437 case TRIG_EXT:
2438 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2439 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2440 NISTC_AI_CMD1_DIV_ARM |
2441 NISTC_AI_CMD1_SC_ARM,
2442 NISTC_AI_CMD1_REG);
2443 break;
2444 }
2445
2446 #ifdef PCIDMA
2447 {
2448 int retval = ni_ai_setup_MITE_dma(dev);
2449
2450 if (retval)
2451 return retval;
2452 }
2453 #endif
2454
2455 if (cmd->start_src == TRIG_NOW) {
2456 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2457 devpriv->ai_cmd2,
2458 NISTC_AI_CMD2_REG);
2459 s->async->inttrig = NULL;
2460 } else if (cmd->start_src == TRIG_EXT) {
2461 s->async->inttrig = NULL;
2462 } else { /* TRIG_INT */
2463 s->async->inttrig = ni_ai_inttrig;
2464 }
2465
2466 return 0;
2467 }
2468
2469 static int ni_ai_insn_config(struct comedi_device *dev,
2470 struct comedi_subdevice *s,
2471 struct comedi_insn *insn, unsigned int *data)
2472 {
2473 struct ni_private *devpriv = dev->private;
2474
2475 if (insn->n < 1)
2476 return -EINVAL;
2477
2478 switch (data[0]) {
2479 case INSN_CONFIG_ALT_SOURCE:
2480 if (devpriv->is_m_series) {
2481 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2482 return -EINVAL;
2483 devpriv->ai_calib_source = data[1];
2484 } else if (devpriv->is_6143) {
2485 unsigned int calib_source;
2486
2487 calib_source = data[1] & 0xf;
2488
2489 devpriv->ai_calib_source = calib_source;
2490 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2491 } else {
2492 unsigned int calib_source;
2493 unsigned int calib_source_adjust;
2494
2495 calib_source = data[1] & 0xf;
2496 calib_source_adjust = (data[1] >> 4) & 0xff;
2497
2498 if (calib_source >= 8)
2499 return -EINVAL;
2500 devpriv->ai_calib_source = calib_source;
2501 if (devpriv->is_611x) {
2502 ni_writeb(dev, calib_source_adjust,
2503 NI611X_CAL_GAIN_SEL_REG);
2504 }
2505 }
2506 return 2;
2507 default:
2508 break;
2509 }
2510
2511 return -EINVAL;
2512 }
2513
2514 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2515 void *data, unsigned int num_bytes,
2516 unsigned int chan_index)
2517 {
2518 struct comedi_cmd *cmd = &s->async->cmd;
2519 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2520 unsigned short *array = data;
2521 unsigned int i;
2522 #ifdef PCIDMA
2523 __le16 buf, *barray = data;
2524 #endif
2525
2526 for (i = 0; i < nsamples; i++) {
2527 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2528 unsigned short val = array[i];
2529
2530 /*
2531 * Munge data from unsigned to two's complement for
2532 * bipolar ranges.
2533 */
2534 if (comedi_range_is_bipolar(s, range))
2535 val = comedi_offset_munge(s, val);
2536 #ifdef PCIDMA
2537 buf = cpu_to_le16(val);
2538 barray[i] = buf;
2539 #else
2540 array[i] = val;
2541 #endif
2542 chan_index++;
2543 chan_index %= cmd->chanlist_len;
2544 }
2545 }
2546
2547 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2548 struct comedi_subdevice *s,
2549 unsigned int chanspec[],
2550 unsigned int n_chans, int timed)
2551 {
2552 struct ni_private *devpriv = dev->private;
2553 unsigned int range;
2554 unsigned int chan;
2555 unsigned int conf;
2556 int i;
2557 int invert = 0;
2558
2559 if (timed) {
2560 for (i = 0; i < s->n_chan; ++i) {
2561 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2562 ni_writeb(dev, devpriv->ao_conf[i],
2563 NI_M_AO_CFG_BANK_REG(i));
2564 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2565 }
2566 }
2567 for (i = 0; i < n_chans; i++) {
2568 const struct comedi_krange *krange;
2569
2570 chan = CR_CHAN(chanspec[i]);
2571 range = CR_RANGE(chanspec[i]);
2572 krange = s->range_table->range + range;
2573 invert = 0;
2574 conf = 0;
2575 switch (krange->max - krange->min) {
2576 case 20000000:
2577 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2578 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2579 break;
2580 case 10000000:
2581 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2582 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2583 break;
2584 case 4000000:
2585 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2586 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2587 NI_M_AO_REF_ATTENUATION_REG(chan));
2588 break;
2589 case 2000000:
2590 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2591 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2592 NI_M_AO_REF_ATTENUATION_REG(chan));
2593 break;
2594 default:
2595 dev_err(dev->class_dev,
2596 "bug! unhandled ao reference voltage\n");
2597 break;
2598 }
2599 switch (krange->max + krange->min) {
2600 case 0:
2601 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2602 break;
2603 case 10000000:
2604 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2605 break;
2606 default:
2607 dev_err(dev->class_dev,
2608 "bug! unhandled ao offset voltage\n");
2609 break;
2610 }
2611 if (timed)
2612 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2613 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2614 devpriv->ao_conf[chan] = conf;
2615 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2616 }
2617 return invert;
2618 }
2619
2620 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2621 struct comedi_subdevice *s,
2622 unsigned int chanspec[],
2623 unsigned int n_chans)
2624 {
2625 struct ni_private *devpriv = dev->private;
2626 unsigned int range;
2627 unsigned int chan;
2628 unsigned int conf;
2629 int i;
2630 int invert = 0;
2631
2632 for (i = 0; i < n_chans; i++) {
2633 chan = CR_CHAN(chanspec[i]);
2634 range = CR_RANGE(chanspec[i]);
2635 conf = NI_E_AO_DACSEL(chan);
2636
2637 if (comedi_range_is_bipolar(s, range)) {
2638 conf |= NI_E_AO_CFG_BIP;
2639 invert = (s->maxdata + 1) >> 1;
2640 } else {
2641 invert = 0;
2642 }
2643 if (comedi_range_is_external(s, range))
2644 conf |= NI_E_AO_EXT_REF;
2645
2646 /* not all boards can deglitch, but this shouldn't hurt */
2647 if (chanspec[i] & CR_DEGLITCH)
2648 conf |= NI_E_AO_DEGLITCH;
2649
2650 /* analog reference */
2651 /* AREF_OTHER connects AO ground to AI ground, i think */
2652 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2653 conf |= NI_E_AO_GROUND_REF;
2654
2655 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2656 devpriv->ao_conf[chan] = conf;
2657 }
2658 return invert;
2659 }
2660
2661 static int ni_ao_config_chanlist(struct comedi_device *dev,
2662 struct comedi_subdevice *s,
2663 unsigned int chanspec[], unsigned int n_chans,
2664 int timed)
2665 {
2666 struct ni_private *devpriv = dev->private;
2667
2668 if (devpriv->is_m_series)
2669 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2670 timed);
2671 else
2672 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2673 }
2674
2675 static int ni_ao_insn_write(struct comedi_device *dev,
2676 struct comedi_subdevice *s,
2677 struct comedi_insn *insn,
2678 unsigned int *data)
2679 {
2680 struct ni_private *devpriv = dev->private;
2681 unsigned int chan = CR_CHAN(insn->chanspec);
2682 unsigned int range = CR_RANGE(insn->chanspec);
2683 int reg;
2684 int i;
2685
2686 if (devpriv->is_6xxx) {
2687 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2688
2689 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2690 } else if (devpriv->is_m_series) {
2691 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2692 } else {
2693 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2694 }
2695
2696 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2697
2698 for (i = 0; i < insn->n; i++) {
2699 unsigned int val = data[i];
2700
2701 s->readback[chan] = val;
2702
2703 if (devpriv->is_6xxx) {
2704 /*
2705 * 6xxx boards have bipolar outputs, munge the
2706 * unsigned comedi values to 2's complement
2707 */
2708 val = comedi_offset_munge(s, val);
2709
2710 ni_ao_win_outw(dev, val, reg);
2711 } else if (devpriv->is_m_series) {
2712 /*
2713 * M-series boards use offset binary values for
2714 * bipolar and uinpolar outputs
2715 */
2716 ni_writew(dev, val, reg);
2717 } else {
2718 /*
2719 * Non-M series boards need two's complement values
2720 * for bipolar ranges.
2721 */
2722 if (comedi_range_is_bipolar(s, range))
2723 val = comedi_offset_munge(s, val);
2724
2725 ni_writew(dev, val, reg);
2726 }
2727 }
2728
2729 return insn->n;
2730 }
2731
2732 static int ni_ao_insn_config(struct comedi_device *dev,
2733 struct comedi_subdevice *s,
2734 struct comedi_insn *insn, unsigned int *data)
2735 {
2736 const struct ni_board_struct *board = dev->board_ptr;
2737 struct ni_private *devpriv = dev->private;
2738 unsigned int nbytes;
2739
2740 switch (data[0]) {
2741 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2742 switch (data[1]) {
2743 case COMEDI_OUTPUT:
2744 nbytes = comedi_samples_to_bytes(s,
2745 board->ao_fifo_depth);
2746 data[2] = 1 + nbytes;
2747 if (devpriv->mite)
2748 data[2] += devpriv->mite->fifo_size;
2749 break;
2750 case COMEDI_INPUT:
2751 data[2] = 0;
2752 break;
2753 default:
2754 return -EINVAL;
2755 }
2756 return 0;
2757 default:
2758 break;
2759 }
2760
2761 return -EINVAL;
2762 }
2763
2764 static int ni_ao_inttrig(struct comedi_device *dev,
2765 struct comedi_subdevice *s,
2766 unsigned int trig_num)
2767 {
2768 struct ni_private *devpriv = dev->private;
2769 struct comedi_cmd *cmd = &s->async->cmd;
2770 int ret;
2771 int interrupt_b_bits;
2772 int i;
2773 static const int timeout = 1000;
2774
2775 if (trig_num != cmd->start_arg)
2776 return -EINVAL;
2777
2778 /*
2779 * Null trig at beginning prevent ao start trigger from executing more
2780 * than once per command (and doing things like trying to allocate the
2781 * ao dma channel multiple times).
2782 */
2783 s->async->inttrig = NULL;
2784
2785 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2786 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2787 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2788 #ifdef PCIDMA
2789 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2790 if (devpriv->is_6xxx)
2791 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2792 ret = ni_ao_setup_MITE_dma(dev);
2793 if (ret)
2794 return ret;
2795 ret = ni_ao_wait_for_dma_load(dev);
2796 if (ret < 0)
2797 return ret;
2798 #else
2799 ret = ni_ao_prep_fifo(dev, s);
2800 if (ret == 0)
2801 return -EPIPE;
2802
2803 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2804 #endif
2805
2806 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2807 NISTC_AO_MODE3_REG);
2808 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2809 /* wait for DACs to be loaded */
2810 for (i = 0; i < timeout; i++) {
2811 udelay(1);
2812 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2813 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2814 break;
2815 }
2816 if (i == timeout) {
2817 dev_err(dev->class_dev,
2818 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2819 return -EIO;
2820 }
2821 /*
2822 * stc manual says we are need to clear error interrupt after
2823 * AO_TMRDACWRs_In_Progress_St clears
2824 */
2825 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2826
2827 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2828
2829 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2830 NISTC_AO_CMD1_UC_ARM |
2831 NISTC_AO_CMD1_BC_ARM |
2832 devpriv->ao_cmd1,
2833 NISTC_AO_CMD1_REG);
2834
2835 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2836 NISTC_AO_CMD2_REG);
2837
2838 return 0;
2839 }
2840
2841 /*
2842 * begin ni_ao_cmd.
2843 * Organized similar to NI-STC and MHDDK examples.
2844 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2845 */
2846
2847 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2848 const struct comedi_cmd *cmd)
2849 {
2850 const struct ni_board_struct *board = dev->board_ptr;
2851 unsigned int bits;
2852
2853 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2854
2855 bits =
2856 /* fast CPU interface--only eseries */
2857 /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2858 NISTC_AO_PERSONAL_BC_SRC_SEL |
2859 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2860 /*
2861 * FIXME: start setting following bit when appropriate. Need to
2862 * determine whether board is E4 or E1.
2863 * FROM MHHDK:
2864 * if board is E4 or E1
2865 * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2866 * else
2867 * set it to 1
2868 */
2869 NISTC_AO_PERSONAL_UPDATE_PW |
2870 /* FIXME: when should we set following bit to zero? */
2871 NISTC_AO_PERSONAL_TMRDACWR_PW |
2872 (board->ao_fifo_depth ?
2873 NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2874 ;
2875 #if 0
2876 /*
2877 * FIXME:
2878 * add something like ".has_individual_dacs = 0" to ni_board_struct
2879 * since, as F Hess pointed out, not all in m series have singles. not
2880 * sure if e-series all have duals...
2881 */
2882
2883 /*
2884 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2885 * 6281, verified with bus analyzer.
2886 */
2887 if (devpriv->is_m_series)
2888 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2889 #endif
2890 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2891
2892 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2893 }
2894
2895 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2896 const struct comedi_cmd *cmd)
2897 {
2898 struct ni_private *devpriv = dev->private;
2899 unsigned int trigsel;
2900
2901 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2902
2903 /* sync */
2904 if (cmd->stop_src == TRIG_NONE) {
2905 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2906 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2907 } else {
2908 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2909 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2910 }
2911 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2912
2913 if (cmd->start_src == TRIG_INT) {
2914 trigsel = NISTC_AO_TRIG_START1_EDGE |
2915 NISTC_AO_TRIG_START1_SYNC;
2916 } else { /* TRIG_EXT */
2917 trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2918 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2919 if (cmd->start_arg & CR_INVERT)
2920 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2921 /* 0=edge detection disabled, 1=enabled */
2922 if (cmd->start_arg & CR_EDGE)
2923 trigsel |= NISTC_AO_TRIG_START1_EDGE;
2924 }
2925 ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2926
2927 /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2928
2929 /* sync */
2930 /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2931 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2932 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2933
2934 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2935 }
2936
2937 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2938 const struct comedi_cmd *cmd)
2939 {
2940 struct ni_private *devpriv = dev->private;
2941 /* Not supporting 'waveform staging' or 'local buffer with pauses' */
2942
2943 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2944 /*
2945 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2946 * set_trigger above. It is unclear whether we really need to re-write
2947 * this register with these values. The mhddk examples for e-series
2948 * show writing this in both places, but the examples for m-series show
2949 * a single write in the set_counters function (here).
2950 */
2951 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2952
2953 /* sync (upload number of buffer iterations -1) */
2954 /* indicate that we want to use BC_Load_A_Register as the source */
2955 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2956 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2957
2958 /*
2959 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
2960 * ignoring BC_TC, then we will need to find a way to ignore that
2961 * interrupt in continuous mode.
2962 */
2963 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
2964
2965 /* sync (issue command to load number of buffer iterations -1) */
2966 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2967
2968 /* sync (upload number of updates in buffer) */
2969 /* indicate that we want to use UC_Load_A_Register as the source */
2970 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2971 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2972
2973 /*
2974 * if a user specifies '0', this automatically assumes the entire 24bit
2975 * address space is available for the (multiple iterations of single
2976 * buffer) MISB. Otherwise, stop_arg specifies the MISB length that
2977 * will be used, regardless of whether we are in continuous mode or not.
2978 * In continuous mode, the output will just iterate indefinitely over
2979 * the MISB.
2980 */
2981 {
2982 unsigned int stop_arg = cmd->stop_arg > 0 ?
2983 (cmd->stop_arg & 0xffffff) : 0xffffff;
2984
2985 if (devpriv->is_m_series) {
2986 /*
2987 * this is how the NI example code does it for m-series
2988 * boards, verified correct with 6259
2989 */
2990 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
2991
2992 /* sync (issue cmd to load number of updates in MISB) */
2993 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2994 NISTC_AO_CMD1_REG);
2995 } else {
2996 ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
2997
2998 /* sync (issue cmd to load number of updates in MISB) */
2999 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3000 NISTC_AO_CMD1_REG);
3001
3002 /*
3003 * sync (upload number of updates-1 in MISB)
3004 * --eseries only?
3005 */
3006 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3007 }
3008 }
3009
3010 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3011 }
3012
3013 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3014 const struct comedi_cmd *cmd)
3015 {
3016 struct ni_private *devpriv = dev->private;
3017
3018 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3019
3020 /*
3021 * zero out these bit fields to be set below. Does an ao-reset do this
3022 * automatically?
3023 */
3024 devpriv->ao_mode1 &= ~(
3025 NISTC_AO_MODE1_UI_SRC_MASK |
3026 NISTC_AO_MODE1_UI_SRC_POLARITY |
3027 NISTC_AO_MODE1_UPDATE_SRC_MASK |
3028 NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3029 );
3030
3031 if (cmd->scan_begin_src == TRIG_TIMER) {
3032 unsigned int trigvar;
3033
3034 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3035
3036 /*
3037 * NOTE: there are several other ways of configuring internal
3038 * updates, but we'll only support one for now: using
3039 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3040 * START1 and first update, and also w/o local buffer mode w/
3041 * pauses.
3042 */
3043
3044 /*
3045 * This is already done above:
3046 * devpriv->ao_mode1 &= ~(
3047 * // set UPDATE_Source to UI_TC:
3048 * NISTC_AO_MODE1_UPDATE_SRC_MASK |
3049 * // set UPDATE_Source_Polarity to rising (required?)
3050 * NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3051 * // set UI_Source to AO_IN_TIMEBASE1:
3052 * NISTC_AO_MODE1_UI_SRC_MASK |
3053 * // set UI_Source_Polarity to rising (required?)
3054 * NISTC_AO_MODE1_UI_SRC_POLARITY
3055 * );
3056 */
3057
3058 /*
3059 * TODO: use ao_ui_clock_source to allow all possible signals
3060 * to be routed to UI_Source_Select. See tSTC.h for
3061 * eseries/ni67xx and tMSeries.h for mseries.
3062 */
3063
3064 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3065 CMDF_ROUND_NEAREST);
3066
3067 /*
3068 * Wait N TB3 ticks after the start trigger before
3069 * clocking (N must be >=2).
3070 */
3071 /* following line: 2-1 per STC */
3072 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3073 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3074 /* following line: N-1 per STC */
3075 ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG);
3076 } else { /* TRIG_EXT */
3077 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
3078 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3079 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3080 CR_CHAN(cmd->scan_begin_arg));
3081 if (cmd->scan_begin_arg & CR_INVERT)
3082 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3083 }
3084
3085 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3086 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3087 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3088 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3089 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3090
3091 /* Configure DAQ-STC for Timed update mode */
3092 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3093 NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3094 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3095 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3096
3097 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3098 }
3099
3100 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3101 struct comedi_subdevice *s)
3102 {
3103 struct ni_private *devpriv = dev->private;
3104 const struct comedi_cmd *cmd = &s->async->cmd;
3105 unsigned int bits = 0;
3106
3107 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3108
3109 if (devpriv->is_6xxx) {
3110 unsigned int i;
3111
3112 bits = 0;
3113 for (i = 0; i < cmd->chanlist_len; ++i) {
3114 int chan = CR_CHAN(cmd->chanlist[i]);
3115
3116 bits |= 1 << chan;
3117 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3118 }
3119 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3120 }
3121
3122 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3123
3124 if (cmd->scan_end_arg > 1) {
3125 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3126 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3127 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3128
3129 } else {
3130 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3131 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3132 if (devpriv->is_m_series | devpriv->is_6xxx)
3133 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3134 else
3135 bits |= NISTC_AO_OUT_CTRL_CHANS(
3136 CR_CHAN(cmd->chanlist[0]));
3137 }
3138
3139 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3140 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3141
3142 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3143 }
3144
3145 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3146 const struct comedi_cmd *cmd)
3147 {
3148 struct ni_private *devpriv = dev->private;
3149
3150 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3151
3152 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3153 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3154
3155 /*
3156 * Since we are not supporting waveform staging, we ignore these errors:
3157 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3158 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3159 */
3160
3161 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3162 }
3163
3164 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3165 {
3166 struct ni_private *devpriv = dev->private;
3167
3168 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3169
3170 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3171 #ifdef PCIDMA
3172 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3173 #else
3174 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3175 #endif
3176 /* NOTE: this is where use_onboard_memory=True would be implemented */
3177 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3178 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3179
3180 /* enable sending of ao fifo requests (dma request) */
3181 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3182
3183 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3184
3185 /* we are not supporting boards with virtual fifos */
3186 }
3187
3188 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3189 struct comedi_subdevice *s)
3190 {
3191 if (s->async->cmd.stop_src == TRIG_COUNT)
3192 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3193 NISTC_INTB_ENA_AO_BC_TC, 1);
3194
3195 s->async->inttrig = ni_ao_inttrig;
3196 }
3197
3198 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3199 {
3200 struct ni_private *devpriv = dev->private;
3201 const struct comedi_cmd *cmd = &s->async->cmd;
3202
3203 if (dev->irq == 0) {
3204 dev_err(dev->class_dev, "cannot run command without an irq");
3205 return -EIO;
3206 }
3207
3208 /* ni_ao_reset should have already been done */
3209 ni_ao_cmd_personalize(dev, cmd);
3210 /* clearing fifo and preload happens elsewhere */
3211
3212 ni_ao_cmd_set_trigger(dev, cmd);
3213 ni_ao_cmd_set_counters(dev, cmd);
3214 ni_ao_cmd_set_update(dev, cmd);
3215 ni_ao_cmd_set_channels(dev, s);
3216 ni_ao_cmd_set_stop_conditions(dev, cmd);
3217 ni_ao_cmd_set_fifo_mode(dev);
3218 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3219 ni_ao_cmd_set_interrupts(dev, s);
3220
3221 /*
3222 * arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be
3223 * called for ao commands since 1) TRIG_NOW is not supported and 2) DMA
3224 * must be setup and initially written to before arm/start happen.
3225 */
3226 return 0;
3227 }
3228
3229 /* end ni_ao_cmd */
3230
3231 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3232 struct comedi_cmd *cmd)
3233 {
3234 const struct ni_board_struct *board = dev->board_ptr;
3235 struct ni_private *devpriv = dev->private;
3236 int err = 0;
3237 unsigned int tmp;
3238
3239 /* Step 1 : check if triggers are trivially valid */
3240
3241 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3242 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3243 TRIG_TIMER | TRIG_EXT);
3244 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3245 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3246 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3247
3248 if (err)
3249 return 1;
3250
3251 /* Step 2a : make sure trigger sources are unique */
3252
3253 err |= comedi_check_trigger_is_unique(cmd->start_src);
3254 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3255 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3256
3257 /* Step 2b : and mutually compatible */
3258
3259 if (err)
3260 return 2;
3261
3262 /* Step 3: check if arguments are trivially valid */
3263
3264 switch (cmd->start_src) {
3265 case TRIG_INT:
3266 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3267 break;
3268 case TRIG_EXT:
3269 tmp = CR_CHAN(cmd->start_arg);
3270
3271 if (tmp > 18)
3272 tmp = 18;
3273 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3274 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3275 break;
3276 }
3277
3278 if (cmd->scan_begin_src == TRIG_TIMER) {
3279 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3280 board->ao_speed);
3281 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3282 devpriv->clock_ns *
3283 0xffffff);
3284 }
3285
3286 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3287 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3288 cmd->chanlist_len);
3289 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3290
3291 if (err)
3292 return 3;
3293
3294 /* step 4: fix up any arguments */
3295 if (cmd->scan_begin_src == TRIG_TIMER) {
3296 tmp = cmd->scan_begin_arg;
3297 cmd->scan_begin_arg =
3298 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3299 cmd->scan_begin_arg,
3300 cmd->flags));
3301 if (tmp != cmd->scan_begin_arg)
3302 err++;
3303 }
3304 if (err)
3305 return 4;
3306
3307 return 0;
3308 }
3309
3310 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3311 {
3312 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3313
3314 /*
3315 * In the following, the "--sync" comments are meant to denote
3316 * asynchronous boundaries for setting the registers as described in the
3317 * DAQ-STC mostly in the order also described in the DAQ-STC.
3318 */
3319
3320 struct ni_private *devpriv = dev->private;
3321
3322 ni_release_ao_mite_channel(dev);
3323
3324 /* --sync (reset AO) */
3325 if (devpriv->is_m_series)
3326 /* following example in mhddk for m-series */
3327 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3328
3329 /*--sync (start config) */
3330 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3331
3332 /*--sync (Disarm) */
3333 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3334
3335 /*
3336 * --sync
3337 * (clear bunch of registers--mseries mhddk examples do not include
3338 * this)
3339 */
3340 devpriv->ao_cmd1 = 0;
3341 devpriv->ao_cmd2 = 0;
3342 devpriv->ao_mode1 = 0;
3343 devpriv->ao_mode2 = 0;
3344 if (devpriv->is_m_series)
3345 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3346 else
3347 devpriv->ao_mode3 = 0;
3348
3349 ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3350 ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3351 ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3352 ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3353 ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3354 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3355 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3356 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3357 ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3358
3359 /*--sync (disable interrupts) */
3360 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3361
3362 /*--sync (ack) */
3363 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3364 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3365
3366 /*--not in DAQ-STC. which doc? */
3367 if (devpriv->is_6xxx) {
3368 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3369 NI671X_AO_IMMEDIATE_REG);
3370 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3371 NI611X_AO_MISC_REG);
3372 }
3373 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3374 /*--end */
3375
3376 return 0;
3377 }
3378
3379 /* digital io */
3380
3381 static int ni_dio_insn_config(struct comedi_device *dev,
3382 struct comedi_subdevice *s,
3383 struct comedi_insn *insn,
3384 unsigned int *data)
3385 {
3386 struct ni_private *devpriv = dev->private;
3387 int ret;
3388
3389 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3390 if (ret)
3391 return ret;
3392
3393 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3394 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3395 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3396
3397 return insn->n;
3398 }
3399
3400 static int ni_dio_insn_bits(struct comedi_device *dev,
3401 struct comedi_subdevice *s,
3402 struct comedi_insn *insn,
3403 unsigned int *data)
3404 {
3405 struct ni_private *devpriv = dev->private;
3406
3407 /* Make sure we're not using the serial part of the dio */
3408 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3409 devpriv->serial_interval_ns)
3410 return -EBUSY;
3411
3412 if (comedi_dio_update_state(s, data)) {
3413 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3414 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3415 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3416 }
3417
3418 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3419
3420 return insn->n;
3421 }
3422
3423 #ifdef PCIDMA
3424 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3425 struct comedi_subdevice *s,
3426 struct comedi_insn *insn,
3427 unsigned int *data)
3428 {
3429 int ret;
3430
3431 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3432 if (ret)
3433 return ret;
3434
3435 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3436
3437 return insn->n;
3438 }
3439
3440 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3441 struct comedi_subdevice *s,
3442 struct comedi_insn *insn,
3443 unsigned int *data)
3444 {
3445 if (comedi_dio_update_state(s, data))
3446 ni_writel(dev, s->state, NI_M_DIO_REG);
3447
3448 data[1] = ni_readl(dev, NI_M_DIO_REG);
3449
3450 return insn->n;
3451 }
3452
3453 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3454 struct comedi_subdevice *s,
3455 struct comedi_cmd *cmd)
3456 {
3457 int i;
3458
3459 for (i = 0; i < cmd->chanlist_len; ++i) {
3460 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3461
3462 if (chan != i)
3463 return -EINVAL;
3464 }
3465
3466 return 0;
3467 }
3468
3469 static int ni_cdio_cmdtest(struct comedi_device *dev,
3470 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3471 {
3472 int err = 0;
3473 int tmp;
3474
3475 /* Step 1 : check if triggers are trivially valid */
3476
3477 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3478 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3479 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3480 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3481 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3482
3483 if (err)
3484 return 1;
3485
3486 /* Step 2a : make sure trigger sources are unique */
3487 /* Step 2b : and mutually compatible */
3488
3489 /* Step 3: check if arguments are trivially valid */
3490
3491 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3492
3493 tmp = cmd->scan_begin_arg;
3494 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3495 if (tmp != cmd->scan_begin_arg)
3496 err |= -EINVAL;
3497
3498 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3499 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3500 cmd->chanlist_len);
3501 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3502 s->async->prealloc_bufsz /
3503 comedi_bytes_per_scan(s));
3504
3505 if (err)
3506 return 3;
3507
3508 /* Step 4: fix up any arguments */
3509
3510 /* Step 5: check channel list if it exists */
3511
3512 if (cmd->chanlist && cmd->chanlist_len > 0)
3513 err |= ni_cdio_check_chanlist(dev, s, cmd);
3514
3515 if (err)
3516 return 5;
3517
3518 return 0;
3519 }
3520
3521 static int ni_cdo_inttrig(struct comedi_device *dev,
3522 struct comedi_subdevice *s,
3523 unsigned int trig_num)
3524 {
3525 struct comedi_cmd *cmd = &s->async->cmd;
3526 const unsigned int timeout = 1000;
3527 int retval = 0;
3528 unsigned int i;
3529 struct ni_private *devpriv = dev->private;
3530 unsigned long flags;
3531
3532 if (trig_num != cmd->start_arg)
3533 return -EINVAL;
3534
3535 s->async->inttrig = NULL;
3536
3537 /* read alloc the entire buffer */
3538 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3539
3540 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3541 if (devpriv->cdo_mite_chan) {
3542 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3543 mite_dma_arm(devpriv->cdo_mite_chan);
3544 } else {
3545 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3546 retval = -EIO;
3547 }
3548 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3549 if (retval < 0)
3550 return retval;
3551
3552 /*
3553 * XXX not sure what interrupt C group does
3554 * wait for dma to fill output fifo
3555 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3556 */
3557 for (i = 0; i < timeout; ++i) {
3558 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3559 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3560 break;
3561 usleep_range(10, 100);
3562 }
3563 if (i == timeout) {
3564 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3565 s->cancel(dev, s);
3566 return -EIO;
3567 }
3568 ni_writel(dev, NI_M_CDO_CMD_ARM |
3569 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3570 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3571 NI_M_CDIO_CMD_REG);
3572 return retval;
3573 }
3574
3575 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3576 {
3577 struct ni_private *devpriv = dev->private;
3578 const struct comedi_cmd *cmd = &s->async->cmd;
3579 unsigned int cdo_mode_bits;
3580 int retval;
3581
3582 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3583 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3584 NI_M_CDO_MODE_HALT_ON_ERROR |
3585 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3586 if (cmd->scan_begin_arg & CR_INVERT)
3587 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3588 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3589 if (s->io_bits) {
3590 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3591 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3592 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3593 } else {
3594 dev_err(dev->class_dev,
3595 "attempted to run digital output command with no lines configured as outputs\n");
3596 return -EIO;
3597 }
3598 retval = ni_request_cdo_mite_channel(dev);
3599 if (retval < 0)
3600 return retval;
3601
3602 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3603 s->async->prealloc_bufsz /
3604 comedi_bytes_per_scan(s));
3605
3606 s->async->inttrig = ni_cdo_inttrig;
3607
3608 return 0;
3609 }
3610
3611 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3612 {
3613 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3614 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3615 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3616 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3617 NI_M_CDIO_CMD_REG);
3618 /*
3619 * XXX not sure what interrupt C group does
3620 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3621 */
3622 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3623 ni_release_cdo_mite_channel(dev);
3624 return 0;
3625 }
3626
3627 static void handle_cdio_interrupt(struct comedi_device *dev)
3628 {
3629 struct ni_private *devpriv = dev->private;
3630 unsigned int cdio_status;
3631 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3632 unsigned long flags;
3633
3634 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3635 if (devpriv->cdo_mite_chan)
3636 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3637 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3638
3639 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3640 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3641 /* XXX just guessing this is needed and does something useful */
3642 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3643 NI_M_CDIO_CMD_REG);
3644 s->async->events |= COMEDI_CB_OVERFLOW;
3645 }
3646 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3647 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3648 NI_M_CDIO_CMD_REG);
3649 /* s->async->events |= COMEDI_CB_EOA; */
3650 }
3651 comedi_handle_events(dev, s);
3652 }
3653 #endif /* PCIDMA */
3654
3655 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3656 struct comedi_subdevice *s,
3657 unsigned char data_out,
3658 unsigned char *data_in)
3659 {
3660 struct ni_private *devpriv = dev->private;
3661 unsigned int status1;
3662 int err = 0, count = 20;
3663
3664 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3665 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3666 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3667
3668 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3669 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3670 err = -EBUSY;
3671 goto error;
3672 }
3673
3674 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3675 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3676 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3677
3678 /* Wait until STC says we're done, but don't loop infinitely. */
3679 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3680 NISTC_STATUS1_SERIO_IN_PROG) {
3681 /* Delay one bit per loop */
3682 udelay((devpriv->serial_interval_ns + 999) / 1000);
3683 if (--count < 0) {
3684 dev_err(dev->class_dev,
3685 "SPI serial I/O didn't finish in time!\n");
3686 err = -ETIME;
3687 goto error;
3688 }
3689 }
3690
3691 /*
3692 * Delay for last bit. This delay is absolutely necessary, because
3693 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3694 */
3695 udelay((devpriv->serial_interval_ns + 999) / 1000);
3696
3697 if (data_in)
3698 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3699
3700 error:
3701 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3702
3703 return err;
3704 }
3705
3706 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3707 struct comedi_subdevice *s,
3708 unsigned char data_out,
3709 unsigned char *data_in)
3710 {
3711 struct ni_private *devpriv = dev->private;
3712 unsigned char mask, input = 0;
3713
3714 /* Wait for one bit before transfer */
3715 udelay((devpriv->serial_interval_ns + 999) / 1000);
3716
3717 for (mask = 0x80; mask; mask >>= 1) {
3718 /*
3719 * Output current bit; note that we cannot touch s->state
3720 * because it is a per-subdevice field, and serial is
3721 * a separate subdevice from DIO.
3722 */
3723 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3724 if (data_out & mask)
3725 devpriv->dio_output |= NISTC_DIO_SDOUT;
3726 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3727
3728 /*
3729 * Assert SDCLK (active low, inverted), wait for half of
3730 * the delay, deassert SDCLK, and wait for the other half.
3731 */
3732 devpriv->dio_control |= NISTC_DIO_SDCLK;
3733 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3734
3735 udelay((devpriv->serial_interval_ns + 999) / 2000);
3736
3737 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3738 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3739
3740 udelay((devpriv->serial_interval_ns + 999) / 2000);
3741
3742 /* Input current bit */
3743 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3744 input |= mask;
3745 }
3746
3747 if (data_in)
3748 *data_in = input;
3749
3750 return 0;
3751 }
3752
3753 static int ni_serial_insn_config(struct comedi_device *dev,
3754 struct comedi_subdevice *s,
3755 struct comedi_insn *insn,
3756 unsigned int *data)
3757 {
3758 struct ni_private *devpriv = dev->private;
3759 unsigned int clk_fout = devpriv->clock_and_fout;
3760 int err = insn->n;
3761 unsigned char byte_out, byte_in = 0;
3762
3763 if (insn->n != 2)
3764 return -EINVAL;
3765
3766 switch (data[0]) {
3767 case INSN_CONFIG_SERIAL_CLOCK:
3768 devpriv->serial_hw_mode = 1;
3769 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3770
3771 if (data[1] == SERIAL_DISABLED) {
3772 devpriv->serial_hw_mode = 0;
3773 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3774 NISTC_DIO_SDCLK);
3775 data[1] = SERIAL_DISABLED;
3776 devpriv->serial_interval_ns = data[1];
3777 } else if (data[1] <= SERIAL_600NS) {
3778 /*
3779 * Warning: this clock speed is too fast to reliably
3780 * control SCXI.
3781 */
3782 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3783 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3784 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3785 data[1] = SERIAL_600NS;
3786 devpriv->serial_interval_ns = data[1];
3787 } else if (data[1] <= SERIAL_1_2US) {
3788 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3789 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3790 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3791 data[1] = SERIAL_1_2US;
3792 devpriv->serial_interval_ns = data[1];
3793 } else if (data[1] <= SERIAL_10US) {
3794 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3795 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3796 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3797 /*
3798 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3799 * 600ns/1.2us. If you turn divide_by_2 off with the
3800 * slow clock, you will still get 10us, except then
3801 * all your delays are wrong.
3802 */
3803 data[1] = SERIAL_10US;
3804 devpriv->serial_interval_ns = data[1];
3805 } else {
3806 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3807 NISTC_DIO_SDCLK);
3808 devpriv->serial_hw_mode = 0;
3809 data[1] = (data[1] / 1000) * 1000;
3810 devpriv->serial_interval_ns = data[1];
3811 }
3812 devpriv->clock_and_fout = clk_fout;
3813
3814 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3815 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3816 return 1;
3817
3818 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3819
3820 if (devpriv->serial_interval_ns == 0)
3821 return -EINVAL;
3822
3823 byte_out = data[1] & 0xFF;
3824
3825 if (devpriv->serial_hw_mode) {
3826 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3827 &byte_in);
3828 } else if (devpriv->serial_interval_ns > 0) {
3829 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3830 &byte_in);
3831 } else {
3832 dev_err(dev->class_dev, "serial disabled!\n");
3833 return -EINVAL;
3834 }
3835 if (err < 0)
3836 return err;
3837 data[1] = byte_in & 0xFF;
3838 return insn->n;
3839
3840 break;
3841 default:
3842 return -EINVAL;
3843 }
3844 }
3845
3846 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3847 {
3848 int i;
3849
3850 for (i = 0; i < s->n_chan; i++) {
3851 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3852 NI67XX_AO_CFG2_REG);
3853 }
3854 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3855 }
3856
3857 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3858 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3859 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3860 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3861 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3862 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3863 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3864 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3865 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3866 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3867 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3868 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3869 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3870 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3871 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3872 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3873 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3874 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3875 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3876 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3877 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3878 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3879 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3880 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3881 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3882 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3883 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3884 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3885 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3886 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3887 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3888 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3889 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3890 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3891 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3892 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3893 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3894 };
3895
3896 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3897 enum ni_gpct_register reg)
3898 {
3899 const struct mio_regmap *regmap;
3900
3901 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3902 regmap = &ni_gpct_to_stc_regmap[reg];
3903 } else {
3904 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3905 __func__, reg);
3906 return 0;
3907 }
3908
3909 return regmap->mio_reg;
3910 }
3911
3912 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3913 enum ni_gpct_register reg)
3914 {
3915 struct comedi_device *dev = counter->counter_dev->dev;
3916 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3917
3918 if (stc_register == 0)
3919 return;
3920
3921 switch (reg) {
3922 /* m-series only registers */
3923 case NITIO_G0_CNT_MODE:
3924 case NITIO_G1_CNT_MODE:
3925 case NITIO_G0_GATE2:
3926 case NITIO_G1_GATE2:
3927 case NITIO_G0_DMA_CFG:
3928 case NITIO_G1_DMA_CFG:
3929 case NITIO_G0_ABZ:
3930 case NITIO_G1_ABZ:
3931 ni_writew(dev, bits, stc_register);
3932 break;
3933
3934 /* 32 bit registers */
3935 case NITIO_G0_LOADA:
3936 case NITIO_G1_LOADA:
3937 case NITIO_G0_LOADB:
3938 case NITIO_G1_LOADB:
3939 ni_stc_writel(dev, bits, stc_register);
3940 break;
3941
3942 /* 16 bit registers */
3943 case NITIO_G0_INT_ENA:
3944 ni_set_bitfield(dev, stc_register,
3945 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3946 bits);
3947 break;
3948 case NITIO_G1_INT_ENA:
3949 ni_set_bitfield(dev, stc_register,
3950 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
3951 bits);
3952 break;
3953 default:
3954 ni_stc_writew(dev, bits, stc_register);
3955 }
3956 }
3957
3958 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
3959 enum ni_gpct_register reg)
3960 {
3961 struct comedi_device *dev = counter->counter_dev->dev;
3962 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3963
3964 if (stc_register == 0)
3965 return 0;
3966
3967 switch (reg) {
3968 /* m-series only registers */
3969 case NITIO_G0_DMA_STATUS:
3970 case NITIO_G1_DMA_STATUS:
3971 return ni_readw(dev, stc_register);
3972
3973 /* 32 bit registers */
3974 case NITIO_G0_HW_SAVE:
3975 case NITIO_G1_HW_SAVE:
3976 case NITIO_G0_SW_SAVE:
3977 case NITIO_G1_SW_SAVE:
3978 return ni_stc_readl(dev, stc_register);
3979
3980 /* 16 bit registers */
3981 default:
3982 return ni_stc_readw(dev, stc_register);
3983 }
3984 }
3985
3986 static int ni_freq_out_insn_read(struct comedi_device *dev,
3987 struct comedi_subdevice *s,
3988 struct comedi_insn *insn,
3989 unsigned int *data)
3990 {
3991 struct ni_private *devpriv = dev->private;
3992 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3993 int i;
3994
3995 for (i = 0; i < insn->n; i++)
3996 data[i] = val;
3997
3998 return insn->n;
3999 }
4000
4001 static int ni_freq_out_insn_write(struct comedi_device *dev,
4002 struct comedi_subdevice *s,
4003 struct comedi_insn *insn,
4004 unsigned int *data)
4005 {
4006 struct ni_private *devpriv = dev->private;
4007
4008 if (insn->n) {
4009 unsigned int val = data[insn->n - 1];
4010
4011 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4012 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4013 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4014
4015 /* use the last data value to set the fout divider */
4016 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4017
4018 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4019 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4020 }
4021 return insn->n;
4022 }
4023
4024 static int ni_freq_out_insn_config(struct comedi_device *dev,
4025 struct comedi_subdevice *s,
4026 struct comedi_insn *insn,
4027 unsigned int *data)
4028 {
4029 struct ni_private *devpriv = dev->private;
4030
4031 switch (data[0]) {
4032 case INSN_CONFIG_SET_CLOCK_SRC:
4033 switch (data[1]) {
4034 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4035 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4036 break;
4037 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4038 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4039 break;
4040 default:
4041 return -EINVAL;
4042 }
4043 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4044 break;
4045 case INSN_CONFIG_GET_CLOCK_SRC:
4046 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4047 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4048 data[2] = TIMEBASE_2_NS;
4049 } else {
4050 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4051 data[2] = TIMEBASE_1_NS * 2;
4052 }
4053 break;
4054 default:
4055 return -EINVAL;
4056 }
4057 return insn->n;
4058 }
4059
4060 static int ni_8255_callback(struct comedi_device *dev,
4061 int dir, int port, int data, unsigned long iobase)
4062 {
4063 if (dir) {
4064 ni_writeb(dev, data, iobase + 2 * port);
4065 return 0;
4066 }
4067
4068 return ni_readb(dev, iobase + 2 * port);
4069 }
4070
4071 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4072 {
4073 struct ni_private *devpriv = dev->private;
4074
4075 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4076 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4077 return 3;
4078 }
4079
4080 static int ni_m_series_pwm_config(struct comedi_device *dev,
4081 struct comedi_subdevice *s,
4082 struct comedi_insn *insn,
4083 unsigned int *data)
4084 {
4085 struct ni_private *devpriv = dev->private;
4086 unsigned int up_count, down_count;
4087
4088 switch (data[0]) {
4089 case INSN_CONFIG_PWM_OUTPUT:
4090 switch (data[1]) {
4091 case CMDF_ROUND_NEAREST:
4092 up_count = DIV_ROUND_CLOSEST(data[2],
4093 devpriv->clock_ns);
4094 break;
4095 case CMDF_ROUND_DOWN:
4096 up_count = data[2] / devpriv->clock_ns;
4097 break;
4098 case CMDF_ROUND_UP:
4099 up_count =
4100 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4101 break;
4102 default:
4103 return -EINVAL;
4104 }
4105 switch (data[3]) {
4106 case CMDF_ROUND_NEAREST:
4107 down_count = DIV_ROUND_CLOSEST(data[4],
4108 devpriv->clock_ns);
4109 break;
4110 case CMDF_ROUND_DOWN:
4111 down_count = data[4] / devpriv->clock_ns;
4112 break;
4113 case CMDF_ROUND_UP:
4114 down_count =
4115 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4116 break;
4117 default:
4118 return -EINVAL;
4119 }
4120 if (up_count * devpriv->clock_ns != data[2] ||
4121 down_count * devpriv->clock_ns != data[4]) {
4122 data[2] = up_count * devpriv->clock_ns;
4123 data[4] = down_count * devpriv->clock_ns;
4124 return -EAGAIN;
4125 }
4126 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4127 NI_M_CAL_PWM_LOW_TIME(down_count),
4128 NI_M_CAL_PWM_REG);
4129 devpriv->pwm_up_count = up_count;
4130 devpriv->pwm_down_count = down_count;
4131 return 5;
4132 case INSN_CONFIG_GET_PWM_OUTPUT:
4133 return ni_get_pwm_config(dev, data);
4134 default:
4135 return -EINVAL;
4136 }
4137 return 0;
4138 }
4139
4140 static int ni_6143_pwm_config(struct comedi_device *dev,
4141 struct comedi_subdevice *s,
4142 struct comedi_insn *insn,
4143 unsigned int *data)
4144 {
4145 struct ni_private *devpriv = dev->private;
4146 unsigned int up_count, down_count;
4147
4148 switch (data[0]) {
4149 case INSN_CONFIG_PWM_OUTPUT:
4150 switch (data[1]) {
4151 case CMDF_ROUND_NEAREST:
4152 up_count = DIV_ROUND_CLOSEST(data[2],
4153 devpriv->clock_ns);
4154 break;
4155 case CMDF_ROUND_DOWN:
4156 up_count = data[2] / devpriv->clock_ns;
4157 break;
4158 case CMDF_ROUND_UP:
4159 up_count =
4160 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4161 break;
4162 default:
4163 return -EINVAL;
4164 }
4165 switch (data[3]) {
4166 case CMDF_ROUND_NEAREST:
4167 down_count = DIV_ROUND_CLOSEST(data[4],
4168 devpriv->clock_ns);
4169 break;
4170 case CMDF_ROUND_DOWN:
4171 down_count = data[4] / devpriv->clock_ns;
4172 break;
4173 case CMDF_ROUND_UP:
4174 down_count =
4175 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4176 break;
4177 default:
4178 return -EINVAL;
4179 }
4180 if (up_count * devpriv->clock_ns != data[2] ||
4181 down_count * devpriv->clock_ns != data[4]) {
4182 data[2] = up_count * devpriv->clock_ns;
4183 data[4] = down_count * devpriv->clock_ns;
4184 return -EAGAIN;
4185 }
4186 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4187 devpriv->pwm_up_count = up_count;
4188 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4189 devpriv->pwm_down_count = down_count;
4190 return 5;
4191 case INSN_CONFIG_GET_PWM_OUTPUT:
4192 return ni_get_pwm_config(dev, data);
4193 default:
4194 return -EINVAL;
4195 }
4196 return 0;
4197 }
4198
4199 static int pack_mb88341(int addr, int val, int *bitstring)
4200 {
4201 /*
4202 * Fujitsu MB 88341
4203 * Note that address bits are reversed. Thanks to
4204 * Ingo Keen for noticing this.
4205 *
4206 * Note also that the 88341 expects address values from
4207 * 1-12, whereas we use channel numbers 0-11. The NI
4208 * docs use 1-12, also, so be careful here.
4209 */
4210 addr++;
4211 *bitstring = ((addr & 0x1) << 11) |
4212 ((addr & 0x2) << 9) |
4213 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4214 return 12;
4215 }
4216
4217 static int pack_dac8800(int addr, int val, int *bitstring)
4218 {
4219 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4220 return 11;
4221 }
4222
4223 static int pack_dac8043(int addr, int val, int *bitstring)
4224 {
4225 *bitstring = val & 0xfff;
4226 return 12;
4227 }
4228
4229 static int pack_ad8522(int addr, int val, int *bitstring)
4230 {
4231 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4232 return 16;
4233 }
4234
4235 static int pack_ad8804(int addr, int val, int *bitstring)
4236 {
4237 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4238 return 12;
4239 }
4240
4241 static int pack_ad8842(int addr, int val, int *bitstring)
4242 {
4243 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4244 return 12;
4245 }
4246
4247 struct caldac_struct {
4248 int n_chans;
4249 int n_bits;
4250 int (*packbits)(int, int, int *);
4251 };
4252
4253 static struct caldac_struct caldacs[] = {
4254 [mb88341] = {12, 8, pack_mb88341},
4255 [dac8800] = {8, 8, pack_dac8800},
4256 [dac8043] = {1, 12, pack_dac8043},
4257 [ad8522] = {2, 12, pack_ad8522},
4258 [ad8804] = {12, 8, pack_ad8804},
4259 [ad8842] = {8, 8, pack_ad8842},
4260 [ad8804_debug] = {16, 8, pack_ad8804},
4261 };
4262
4263 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4264 {
4265 const struct ni_board_struct *board = dev->board_ptr;
4266 struct ni_private *devpriv = dev->private;
4267 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4268 unsigned int cmd;
4269 int i;
4270 int type;
4271
4272 if (devpriv->caldacs[addr] == val)
4273 return;
4274 devpriv->caldacs[addr] = val;
4275
4276 for (i = 0; i < 3; i++) {
4277 type = board->caldac[i];
4278 if (type == caldac_none)
4279 break;
4280 if (addr < caldacs[type].n_chans) {
4281 bits = caldacs[type].packbits(addr, val, &bitstring);
4282 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4283 break;
4284 }
4285 addr -= caldacs[type].n_chans;
4286 }
4287
4288 /* bits will be 0 if there is no caldac for the given addr */
4289 if (bits == 0)
4290 return;
4291
4292 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4293 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4294 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4295 udelay(1);
4296 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4297 udelay(1);
4298 }
4299 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4300 udelay(1);
4301 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4302 }
4303
4304 static int ni_calib_insn_write(struct comedi_device *dev,
4305 struct comedi_subdevice *s,
4306 struct comedi_insn *insn,
4307 unsigned int *data)
4308 {
4309 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4310
4311 return 1;
4312 }
4313
4314 static int ni_calib_insn_read(struct comedi_device *dev,
4315 struct comedi_subdevice *s,
4316 struct comedi_insn *insn,
4317 unsigned int *data)
4318 {
4319 struct ni_private *devpriv = dev->private;
4320
4321 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4322
4323 return 1;
4324 }
4325
4326 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4327 {
4328 const struct ni_board_struct *board = dev->board_ptr;
4329 struct ni_private *devpriv = dev->private;
4330 int i, j;
4331 int n_dacs;
4332 int n_chans = 0;
4333 int n_bits;
4334 int diffbits = 0;
4335 int type;
4336 int chan;
4337
4338 type = board->caldac[0];
4339 if (type == caldac_none)
4340 return;
4341 n_bits = caldacs[type].n_bits;
4342 for (i = 0; i < 3; i++) {
4343 type = board->caldac[i];
4344 if (type == caldac_none)
4345 break;
4346 if (caldacs[type].n_bits != n_bits)
4347 diffbits = 1;
4348 n_chans += caldacs[type].n_chans;
4349 }
4350 n_dacs = i;
4351 s->n_chan = n_chans;
4352
4353 if (diffbits) {
4354 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4355
4356 if (n_chans > MAX_N_CALDACS)
4357 dev_err(dev->class_dev,
4358 "BUG! MAX_N_CALDACS too small\n");
4359 s->maxdata_list = maxdata_list;
4360 chan = 0;
4361 for (i = 0; i < n_dacs; i++) {
4362 type = board->caldac[i];
4363 for (j = 0; j < caldacs[type].n_chans; j++) {
4364 maxdata_list[chan] =
4365 (1 << caldacs[type].n_bits) - 1;
4366 chan++;
4367 }
4368 }
4369
4370 for (chan = 0; chan < s->n_chan; chan++)
4371 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4372 } else {
4373 type = board->caldac[0];
4374 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4375
4376 for (chan = 0; chan < s->n_chan; chan++)
4377 ni_write_caldac(dev, i, s->maxdata / 2);
4378 }
4379 }
4380
4381 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4382 {
4383 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4384 int bit;
4385 int bitstring;
4386
4387 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4388 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4389 for (bit = 0x8000; bit; bit >>= 1) {
4390 if (bit & bitstring)
4391 cmd |= NI_E_SERIAL_CMD_SDATA;
4392 else
4393 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4394
4395 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4396 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4397 }
4398 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4399 bitstring = 0;
4400 for (bit = 0x80; bit; bit >>= 1) {
4401 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4402 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4403 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4404 bitstring |= bit;
4405 }
4406 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4407
4408 return bitstring;
4409 }
4410
4411 static int ni_eeprom_insn_read(struct comedi_device *dev,
4412 struct comedi_subdevice *s,
4413 struct comedi_insn *insn,
4414 unsigned int *data)
4415 {
4416 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4417
4418 return 1;
4419 }
4420
4421 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4422 struct comedi_subdevice *s,
4423 struct comedi_insn *insn,
4424 unsigned int *data)
4425 {
4426 struct ni_private *devpriv = dev->private;
4427
4428 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4429
4430 return 1;
4431 }
4432
4433 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4434 unsigned int chan)
4435 {
4436 /* pre-m-series boards have fixed signals on pfi pins */
4437 switch (chan) {
4438 case 0:
4439 return NI_PFI_OUTPUT_AI_START1;
4440 case 1:
4441 return NI_PFI_OUTPUT_AI_START2;
4442 case 2:
4443 return NI_PFI_OUTPUT_AI_CONVERT;
4444 case 3:
4445 return NI_PFI_OUTPUT_G_SRC1;
4446 case 4:
4447 return NI_PFI_OUTPUT_G_GATE1;
4448 case 5:
4449 return NI_PFI_OUTPUT_AO_UPDATE_N;
4450 case 6:
4451 return NI_PFI_OUTPUT_AO_START1;
4452 case 7:
4453 return NI_PFI_OUTPUT_AI_START_PULSE;
4454 case 8:
4455 return NI_PFI_OUTPUT_G_SRC0;
4456 case 9:
4457 return NI_PFI_OUTPUT_G_GATE0;
4458 default:
4459 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4460 break;
4461 }
4462 return 0;
4463 }
4464
4465 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4466 unsigned int chan, unsigned int source)
4467 {
4468 /* pre-m-series boards have fixed signals on pfi pins */
4469 if (source != ni_old_get_pfi_routing(dev, chan))
4470 return -EINVAL;
4471 return 2;
4472 }
4473
4474 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4475 unsigned int chan)
4476 {
4477 struct ni_private *devpriv = dev->private;
4478 const unsigned int array_offset = chan / 3;
4479
4480 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4481 devpriv->pfi_output_select_reg[array_offset]);
4482 }
4483
4484 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4485 unsigned int chan, unsigned int source)
4486 {
4487 struct ni_private *devpriv = dev->private;
4488 unsigned int index = chan / 3;
4489 unsigned short val = devpriv->pfi_output_select_reg[index];
4490
4491 if ((source & 0x1f) != source)
4492 return -EINVAL;
4493
4494 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4495 val |= NI_M_PFI_OUT_SEL(chan, source);
4496 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4497 devpriv->pfi_output_select_reg[index] = val;
4498
4499 return 2;
4500 }
4501
4502 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4503 unsigned int chan)
4504 {
4505 struct ni_private *devpriv = dev->private;
4506
4507 return (devpriv->is_m_series)
4508 ? ni_m_series_get_pfi_routing(dev, chan)
4509 : ni_old_get_pfi_routing(dev, chan);
4510 }
4511
4512 static int ni_set_pfi_routing(struct comedi_device *dev,
4513 unsigned int chan, unsigned int source)
4514 {
4515 struct ni_private *devpriv = dev->private;
4516
4517 return (devpriv->is_m_series)
4518 ? ni_m_series_set_pfi_routing(dev, chan, source)
4519 : ni_old_set_pfi_routing(dev, chan, source);
4520 }
4521
4522 static int ni_config_filter(struct comedi_device *dev,
4523 unsigned int pfi_channel,
4524 enum ni_pfi_filter_select filter)
4525 {
4526 struct ni_private *devpriv = dev->private;
4527 unsigned int bits;
4528
4529 if (!devpriv->is_m_series)
4530 return -ENOTSUPP;
4531
4532 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4533 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4534 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4535 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4536 return 0;
4537 }
4538
4539 static int ni_pfi_insn_config(struct comedi_device *dev,
4540 struct comedi_subdevice *s,
4541 struct comedi_insn *insn,
4542 unsigned int *data)
4543 {
4544 struct ni_private *devpriv = dev->private;
4545 unsigned int chan;
4546
4547 if (insn->n < 1)
4548 return -EINVAL;
4549
4550 chan = CR_CHAN(insn->chanspec);
4551
4552 switch (data[0]) {
4553 case COMEDI_OUTPUT:
4554 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4555 break;
4556 case COMEDI_INPUT:
4557 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4558 break;
4559 case INSN_CONFIG_DIO_QUERY:
4560 data[1] =
4561 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4562 COMEDI_OUTPUT : COMEDI_INPUT;
4563 return 0;
4564 case INSN_CONFIG_SET_ROUTING:
4565 return ni_set_pfi_routing(dev, chan, data[1]);
4566 case INSN_CONFIG_GET_ROUTING:
4567 data[1] = ni_get_pfi_routing(dev, chan);
4568 break;
4569 case INSN_CONFIG_FILTER:
4570 return ni_config_filter(dev, chan, data[1]);
4571 default:
4572 return -EINVAL;
4573 }
4574 return 0;
4575 }
4576
4577 static int ni_pfi_insn_bits(struct comedi_device *dev,
4578 struct comedi_subdevice *s,
4579 struct comedi_insn *insn,
4580 unsigned int *data)
4581 {
4582 struct ni_private *devpriv = dev->private;
4583
4584 if (!devpriv->is_m_series)
4585 return -ENOTSUPP;
4586
4587 if (comedi_dio_update_state(s, data))
4588 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4589
4590 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4591
4592 return insn->n;
4593 }
4594
4595 static int cs5529_wait_for_idle(struct comedi_device *dev)
4596 {
4597 unsigned short status;
4598 const int timeout = HZ;
4599 int i;
4600
4601 for (i = 0; i < timeout; i++) {
4602 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4603 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4604 break;
4605 set_current_state(TASK_INTERRUPTIBLE);
4606 if (schedule_timeout(1))
4607 return -EIO;
4608 }
4609 if (i == timeout) {
4610 dev_err(dev->class_dev, "timeout\n");
4611 return -ETIME;
4612 }
4613 return 0;
4614 }
4615
4616 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4617 {
4618 static const int timeout = 100;
4619 int i;
4620
4621 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4622 /* give time for command to start being serially clocked into cs5529.
4623 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4624 * set before we exit this function.
4625 */
4626 for (i = 0; i < timeout; i++) {
4627 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4628 NI67XX_CAL_STATUS_BUSY)
4629 break;
4630 udelay(1);
4631 }
4632 if (i == timeout)
4633 dev_err(dev->class_dev,
4634 "possible problem - never saw adc go busy?\n");
4635 }
4636
4637 static int cs5529_do_conversion(struct comedi_device *dev,
4638 unsigned short *data)
4639 {
4640 int retval;
4641 unsigned short status;
4642
4643 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4644 retval = cs5529_wait_for_idle(dev);
4645 if (retval) {
4646 dev_err(dev->class_dev,
4647 "timeout or signal in cs5529_do_conversion()\n");
4648 return -ETIME;
4649 }
4650 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4651 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4652 dev_err(dev->class_dev,
4653 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4654 return -EIO;
4655 }
4656 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4657 dev_err(dev->class_dev,
4658 "cs5529 conversion error, overrange (ignoring)\n");
4659 }
4660 if (data) {
4661 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4662 /* cs5529 returns 16 bit signed data in bipolar mode */
4663 *data ^= (1 << 15);
4664 }
4665 return 0;
4666 }
4667
4668 static int cs5529_ai_insn_read(struct comedi_device *dev,
4669 struct comedi_subdevice *s,
4670 struct comedi_insn *insn,
4671 unsigned int *data)
4672 {
4673 int n, retval;
4674 unsigned short sample;
4675 unsigned int channel_select;
4676 const unsigned int INTERNAL_REF = 0x1000;
4677
4678 /*
4679 * Set calibration adc source. Docs lie, reference select bits 8 to 11
4680 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4681 * 13 causes the adc input to go overrange (maybe reads external
4682 * reference?)
4683 */
4684 if (insn->chanspec & CR_ALT_SOURCE)
4685 channel_select = INTERNAL_REF;
4686 else
4687 channel_select = CR_CHAN(insn->chanspec);
4688 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4689
4690 for (n = 0; n < insn->n; n++) {
4691 retval = cs5529_do_conversion(dev, &sample);
4692 if (retval < 0)
4693 return retval;
4694 data[n] = sample;
4695 }
4696 return insn->n;
4697 }
4698
4699 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4700 unsigned int reg_select_bits)
4701 {
4702 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4703 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4704 reg_select_bits &= CS5529_CMD_REG_MASK;
4705 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4706 if (cs5529_wait_for_idle(dev))
4707 dev_err(dev->class_dev,
4708 "timeout or signal in %s\n", __func__);
4709 }
4710
4711 static int init_cs5529(struct comedi_device *dev)
4712 {
4713 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4714 CS5529_CFG_WORD_RATE_2180;
4715
4716 #if 1
4717 /* do self-calibration */
4718 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4719 CS5529_CFG_REG);
4720 /* need to force a conversion for calibration to run */
4721 cs5529_do_conversion(dev, NULL);
4722 #else
4723 /* force gain calibration to 1 */
4724 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4725 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4726 CS5529_CFG_REG);
4727 if (cs5529_wait_for_idle(dev))
4728 dev_err(dev->class_dev,
4729 "timeout or signal in %s\n", __func__);
4730 #endif
4731 return 0;
4732 }
4733
4734 /*
4735 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4736 * given an arbitrary frequency input clock.
4737 */
4738 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4739 unsigned int *freq_divider,
4740 unsigned int *freq_multiplier,
4741 unsigned int *actual_period_ns)
4742 {
4743 unsigned int div;
4744 unsigned int best_div = 1;
4745 unsigned int mult;
4746 unsigned int best_mult = 1;
4747 static const unsigned int pico_per_nano = 1000;
4748 const unsigned int reference_picosec = reference_period_ns *
4749 pico_per_nano;
4750 /*
4751 * m-series wants the phased-locked loop to output 80MHz, which is
4752 * divided by 4 to 20 MHz for most timing clocks
4753 */
4754 static const unsigned int target_picosec = 12500;
4755 int best_period_picosec = 0;
4756
4757 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4758 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4759 unsigned int new_period_ps =
4760 (reference_picosec * div) / mult;
4761 if (abs(new_period_ps - target_picosec) <
4762 abs(best_period_picosec - target_picosec)) {
4763 best_period_picosec = new_period_ps;
4764 best_div = div;
4765 best_mult = mult;
4766 }
4767 }
4768 }
4769 if (best_period_picosec == 0)
4770 return -EIO;
4771
4772 *freq_divider = best_div;
4773 *freq_multiplier = best_mult;
4774 /* return the actual period (* fudge factor for 80 to 20 MHz) */
4775 *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4776 pico_per_nano);
4777 return 0;
4778 }
4779
4780 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4781 unsigned int source,
4782 unsigned int period_ns)
4783 {
4784 struct ni_private *devpriv = dev->private;
4785 static const unsigned int min_period_ns = 50;
4786 static const unsigned int max_period_ns = 1000;
4787 static const unsigned int timeout = 1000;
4788 unsigned int pll_control_bits;
4789 unsigned int freq_divider;
4790 unsigned int freq_multiplier;
4791 unsigned int rtsi;
4792 unsigned int i;
4793 int retval;
4794
4795 if (source == NI_MIO_PLL_PXI10_CLOCK)
4796 period_ns = 100;
4797 /*
4798 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4799 * range so we'll use that.
4800 */
4801 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4802 dev_err(dev->class_dev,
4803 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4804 __func__, min_period_ns, max_period_ns);
4805 return -EINVAL;
4806 }
4807 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4808 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4809 NISTC_RTSI_TRIG_DIR_REG);
4810 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4811 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4812 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4813 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4814 switch (source) {
4815 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4816 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4817 break;
4818 case NI_MIO_PLL_PXI10_CLOCK:
4819 /* pxi clock is 10MHz */
4820 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4821 break;
4822 default:
4823 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4824 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4825 devpriv->clock_and_fout2 |=
4826 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4827 break;
4828 }
4829 }
4830 if (rtsi > NI_M_MAX_RTSI_CHAN)
4831 return -EINVAL;
4832 break;
4833 }
4834 retval = ni_mseries_get_pll_parameters(period_ns,
4835 &freq_divider,
4836 &freq_multiplier,
4837 &devpriv->clock_ns);
4838 if (retval < 0) {
4839 dev_err(dev->class_dev,
4840 "bug, failed to find pll parameters\n");
4841 return retval;
4842 }
4843
4844 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4845 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4846 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4847
4848 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4849 devpriv->clock_source = source;
4850 /* it takes a few hundred microseconds for PLL to lock */
4851 for (i = 0; i < timeout; ++i) {
4852 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4853 break;
4854 udelay(1);
4855 }
4856 if (i == timeout) {
4857 dev_err(dev->class_dev,
4858 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4859 __func__, source, period_ns);
4860 return -ETIMEDOUT;
4861 }
4862 return 3;
4863 }
4864
4865 static int ni_set_master_clock(struct comedi_device *dev,
4866 unsigned int source, unsigned int period_ns)
4867 {
4868 struct ni_private *devpriv = dev->private;
4869
4870 if (source == NI_MIO_INTERNAL_CLOCK) {
4871 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4872 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4873 NISTC_RTSI_TRIG_DIR_REG);
4874 devpriv->clock_ns = TIMEBASE_1_NS;
4875 if (devpriv->is_m_series) {
4876 devpriv->clock_and_fout2 &=
4877 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4878 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4879 ni_writew(dev, devpriv->clock_and_fout2,
4880 NI_M_CLK_FOUT2_REG);
4881 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4882 }
4883 devpriv->clock_source = source;
4884 } else {
4885 if (devpriv->is_m_series) {
4886 return ni_mseries_set_pll_master_clock(dev, source,
4887 period_ns);
4888 } else {
4889 if (source == NI_MIO_RTSI_CLOCK) {
4890 devpriv->rtsi_trig_direction_reg |=
4891 NISTC_RTSI_TRIG_USE_CLK;
4892 ni_stc_writew(dev,
4893 devpriv->rtsi_trig_direction_reg,
4894 NISTC_RTSI_TRIG_DIR_REG);
4895 if (period_ns == 0) {
4896 dev_err(dev->class_dev,
4897 "we don't handle an unspecified clock period correctly yet, returning error\n");
4898 return -EINVAL;
4899 }
4900 devpriv->clock_ns = period_ns;
4901 devpriv->clock_source = source;
4902 } else {
4903 return -EINVAL;
4904 }
4905 }
4906 }
4907 return 3;
4908 }
4909
4910 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4911 unsigned int chan, unsigned int source)
4912 {
4913 struct ni_private *devpriv = dev->private;
4914
4915 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4916 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4917 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4918 return 1;
4919
4920 dev_err(dev->class_dev,
4921 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4922 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4923 return 0;
4924 }
4925 return 0;
4926 }
4927 switch (source) {
4928 case NI_RTSI_OUTPUT_ADR_START1:
4929 case NI_RTSI_OUTPUT_ADR_START2:
4930 case NI_RTSI_OUTPUT_SCLKG:
4931 case NI_RTSI_OUTPUT_DACUPDN:
4932 case NI_RTSI_OUTPUT_DA_START1:
4933 case NI_RTSI_OUTPUT_G_SRC0:
4934 case NI_RTSI_OUTPUT_G_GATE0:
4935 case NI_RTSI_OUTPUT_RGOUT0:
4936 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4937 return 1;
4938 case NI_RTSI_OUTPUT_RTSI_OSC:
4939 return (devpriv->is_m_series) ? 1 : 0;
4940 default:
4941 return 0;
4942 }
4943 }
4944
4945 static int ni_set_rtsi_routing(struct comedi_device *dev,
4946 unsigned int chan, unsigned int src)
4947 {
4948 struct ni_private *devpriv = dev->private;
4949
4950 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4951 return -EINVAL;
4952 if (chan < 4) {
4953 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4954 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4955 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4956 NISTC_RTSI_TRIGA_OUT_REG);
4957 } else if (chan < 8) {
4958 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4959 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4960 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4961 NISTC_RTSI_TRIGB_OUT_REG);
4962 }
4963 return 2;
4964 }
4965
4966 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
4967 unsigned int chan)
4968 {
4969 struct ni_private *devpriv = dev->private;
4970
4971 if (chan < 4) {
4972 return NISTC_RTSI_TRIG_TO_SRC(chan,
4973 devpriv->rtsi_trig_a_output_reg);
4974 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4975 return NISTC_RTSI_TRIG_TO_SRC(chan,
4976 devpriv->rtsi_trig_b_output_reg);
4977 } else {
4978 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4979 return NI_RTSI_OUTPUT_RTSI_OSC;
4980 dev_err(dev->class_dev, "bug! should never get here?\n");
4981 return 0;
4982 }
4983 }
4984
4985 static int ni_rtsi_insn_config(struct comedi_device *dev,
4986 struct comedi_subdevice *s,
4987 struct comedi_insn *insn,
4988 unsigned int *data)
4989 {
4990 struct ni_private *devpriv = dev->private;
4991 unsigned int chan = CR_CHAN(insn->chanspec);
4992 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4993
4994 switch (data[0]) {
4995 case INSN_CONFIG_DIO_OUTPUT:
4996 if (chan < max_chan) {
4997 devpriv->rtsi_trig_direction_reg |=
4998 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4999 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5000 devpriv->rtsi_trig_direction_reg |=
5001 NISTC_RTSI_TRIG_DRV_CLK;
5002 }
5003 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5004 NISTC_RTSI_TRIG_DIR_REG);
5005 break;
5006 case INSN_CONFIG_DIO_INPUT:
5007 if (chan < max_chan) {
5008 devpriv->rtsi_trig_direction_reg &=
5009 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5010 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5011 devpriv->rtsi_trig_direction_reg &=
5012 ~NISTC_RTSI_TRIG_DRV_CLK;
5013 }
5014 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5015 NISTC_RTSI_TRIG_DIR_REG);
5016 break;
5017 case INSN_CONFIG_DIO_QUERY:
5018 if (chan < max_chan) {
5019 data[1] =
5020 (devpriv->rtsi_trig_direction_reg &
5021 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5022 ? INSN_CONFIG_DIO_OUTPUT
5023 : INSN_CONFIG_DIO_INPUT;
5024 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5025 data[1] = (devpriv->rtsi_trig_direction_reg &
5026 NISTC_RTSI_TRIG_DRV_CLK)
5027 ? INSN_CONFIG_DIO_OUTPUT
5028 : INSN_CONFIG_DIO_INPUT;
5029 }
5030 return 2;
5031 case INSN_CONFIG_SET_CLOCK_SRC:
5032 return ni_set_master_clock(dev, data[1], data[2]);
5033 case INSN_CONFIG_GET_CLOCK_SRC:
5034 data[1] = devpriv->clock_source;
5035 data[2] = devpriv->clock_ns;
5036 return 3;
5037 case INSN_CONFIG_SET_ROUTING:
5038 return ni_set_rtsi_routing(dev, chan, data[1]);
5039 case INSN_CONFIG_GET_ROUTING:
5040 data[1] = ni_get_rtsi_routing(dev, chan);
5041 return 2;
5042 default:
5043 return -EINVAL;
5044 }
5045 return 1;
5046 }
5047
5048 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5049 struct comedi_subdevice *s,
5050 struct comedi_insn *insn,
5051 unsigned int *data)
5052 {
5053 data[1] = 0;
5054
5055 return insn->n;
5056 }
5057
5058 static void ni_rtsi_init(struct comedi_device *dev)
5059 {
5060 struct ni_private *devpriv = dev->private;
5061
5062 /* Initialises the RTSI bus signal switch to a default state */
5063
5064 /*
5065 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5066 * to have no effect, at least on pxi-6281, which always uses
5067 * 20MHz rtsi clock frequency
5068 */
5069 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5070 /* Set clock mode to internal */
5071 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5072 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5073 /* default internal lines routing to RTSI bus lines */
5074 devpriv->rtsi_trig_a_output_reg =
5075 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5076 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5077 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5078 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5079 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5080 NISTC_RTSI_TRIGA_OUT_REG);
5081 devpriv->rtsi_trig_b_output_reg =
5082 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5083 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5084 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5085 if (devpriv->is_m_series)
5086 devpriv->rtsi_trig_b_output_reg |=
5087 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5088 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5089 NISTC_RTSI_TRIGB_OUT_REG);
5090
5091 /*
5092 * Sets the source and direction of the 4 on board lines
5093 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5094 */
5095 }
5096
5097 #ifdef PCIDMA
5098 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5099 {
5100 struct ni_gpct *counter = s->private;
5101 int retval;
5102
5103 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5104 COMEDI_INPUT);
5105 if (retval) {
5106 dev_err(dev->class_dev,
5107 "no dma channel available for use by counter\n");
5108 return retval;
5109 }
5110 ni_tio_acknowledge(counter);
5111 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5112
5113 return ni_tio_cmd(dev, s);
5114 }
5115
5116 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5117 {
5118 struct ni_gpct *counter = s->private;
5119 int retval;
5120
5121 retval = ni_tio_cancel(counter);
5122 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5123 ni_release_gpct_mite_channel(dev, counter->counter_index);
5124 return retval;
5125 }
5126 #endif
5127
5128 static irqreturn_t ni_E_interrupt(int irq, void *d)
5129 {
5130 struct comedi_device *dev = d;
5131 struct comedi_subdevice *s_ai = dev->read_subdev;
5132 struct comedi_subdevice *s_ao = dev->write_subdev;
5133 unsigned short a_status;
5134 unsigned short b_status;
5135 unsigned long flags;
5136 #ifdef PCIDMA
5137 struct ni_private *devpriv = dev->private;
5138 #endif
5139
5140 if (!dev->attached)
5141 return IRQ_NONE;
5142 smp_mb(); /* make sure dev->attached is checked */
5143
5144 /* lock to avoid race with comedi_poll */
5145 spin_lock_irqsave(&dev->spinlock, flags);
5146 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5147 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5148 #ifdef PCIDMA
5149 if (devpriv->mite) {
5150 unsigned long flags_too;
5151
5152 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5153 if (s_ai && devpriv->ai_mite_chan)
5154 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5155 if (s_ao && devpriv->ao_mite_chan)
5156 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5157 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5158 }
5159 #endif
5160 ack_a_interrupt(dev, a_status);
5161 ack_b_interrupt(dev, b_status);
5162 if (s_ai) {
5163 if (a_status & NISTC_AI_STATUS1_INTA)
5164 handle_a_interrupt(dev, s_ai, a_status);
5165 /* handle any interrupt or dma events */
5166 comedi_handle_events(dev, s_ai);
5167 }
5168 if (s_ao) {
5169 if (b_status & NISTC_AO_STATUS1_INTB)
5170 handle_b_interrupt(dev, s_ao, b_status);
5171 /* handle any interrupt or dma events */
5172 comedi_handle_events(dev, s_ao);
5173 }
5174 handle_gpct_interrupt(dev, 0);
5175 handle_gpct_interrupt(dev, 1);
5176 #ifdef PCIDMA
5177 if (devpriv->is_m_series)
5178 handle_cdio_interrupt(dev);
5179 #endif
5180
5181 spin_unlock_irqrestore(&dev->spinlock, flags);
5182 return IRQ_HANDLED;
5183 }
5184
5185 static int ni_alloc_private(struct comedi_device *dev)
5186 {
5187 struct ni_private *devpriv;
5188
5189 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5190 if (!devpriv)
5191 return -ENOMEM;
5192
5193 spin_lock_init(&devpriv->window_lock);
5194 spin_lock_init(&devpriv->soft_reg_copy_lock);
5195 spin_lock_init(&devpriv->mite_channel_lock);
5196
5197 return 0;
5198 }
5199
5200 static int ni_E_init(struct comedi_device *dev,
5201 unsigned int interrupt_pin, unsigned int irq_polarity)
5202 {
5203 const struct ni_board_struct *board = dev->board_ptr;
5204 struct ni_private *devpriv = dev->private;
5205 struct comedi_subdevice *s;
5206 int ret;
5207 int i;
5208
5209 if (board->n_aochan > MAX_N_AO_CHAN) {
5210 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5211 return -EINVAL;
5212 }
5213
5214 /* initialize clock dividers */
5215 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5216 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5217 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5218 NISTC_CLK_FOUT_TO_BOARD;
5219 if (!devpriv->is_6xxx) {
5220 /* BEAM is this needed for PCI-6143 ?? */
5221 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5222 NISTC_CLK_FOUT_AO_OUT_DIV2);
5223 }
5224 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5225
5226 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5227 if (ret)
5228 return ret;
5229
5230 /* Analog Input subdevice */
5231 s = &dev->subdevices[NI_AI_SUBDEV];
5232 if (board->n_adchan) {
5233 s->type = COMEDI_SUBD_AI;
5234 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5235 if (!devpriv->is_611x)
5236 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5237 if (board->ai_maxdata > 0xffff)
5238 s->subdev_flags |= SDF_LSAMPL;
5239 if (devpriv->is_m_series)
5240 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5241 s->n_chan = board->n_adchan;
5242 s->maxdata = board->ai_maxdata;
5243 s->range_table = ni_range_lkup[board->gainlkup];
5244 s->insn_read = ni_ai_insn_read;
5245 s->insn_config = ni_ai_insn_config;
5246 if (dev->irq) {
5247 dev->read_subdev = s;
5248 s->subdev_flags |= SDF_CMD_READ;
5249 s->len_chanlist = 512;
5250 s->do_cmdtest = ni_ai_cmdtest;
5251 s->do_cmd = ni_ai_cmd;
5252 s->cancel = ni_ai_reset;
5253 s->poll = ni_ai_poll;
5254 s->munge = ni_ai_munge;
5255
5256 if (devpriv->mite)
5257 s->async_dma_dir = DMA_FROM_DEVICE;
5258 }
5259
5260 /* reset the analog input configuration */
5261 ni_ai_reset(dev, s);
5262 } else {
5263 s->type = COMEDI_SUBD_UNUSED;
5264 }
5265
5266 /* Analog Output subdevice */
5267 s = &dev->subdevices[NI_AO_SUBDEV];
5268 if (board->n_aochan) {
5269 s->type = COMEDI_SUBD_AO;
5270 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5271 if (devpriv->is_m_series)
5272 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5273 s->n_chan = board->n_aochan;
5274 s->maxdata = board->ao_maxdata;
5275 s->range_table = board->ao_range_table;
5276 s->insn_config = ni_ao_insn_config;
5277 s->insn_write = ni_ao_insn_write;
5278
5279 ret = comedi_alloc_subdev_readback(s);
5280 if (ret)
5281 return ret;
5282
5283 /*
5284 * Along with the IRQ we need either a FIFO or DMA for
5285 * async command support.
5286 */
5287 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5288 dev->write_subdev = s;
5289 s->subdev_flags |= SDF_CMD_WRITE;
5290 s->len_chanlist = s->n_chan;
5291 s->do_cmdtest = ni_ao_cmdtest;
5292 s->do_cmd = ni_ao_cmd;
5293 s->cancel = ni_ao_reset;
5294 if (!devpriv->is_m_series)
5295 s->munge = ni_ao_munge;
5296
5297 if (devpriv->mite)
5298 s->async_dma_dir = DMA_TO_DEVICE;
5299 }
5300
5301 if (devpriv->is_67xx)
5302 init_ao_67xx(dev, s);
5303
5304 /* reset the analog output configuration */
5305 ni_ao_reset(dev, s);
5306 } else {
5307 s->type = COMEDI_SUBD_UNUSED;
5308 }
5309
5310 /* Digital I/O subdevice */
5311 s = &dev->subdevices[NI_DIO_SUBDEV];
5312 s->type = COMEDI_SUBD_DIO;
5313 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5314 s->n_chan = board->has_32dio_chan ? 32 : 8;
5315 s->maxdata = 1;
5316 s->range_table = &range_digital;
5317 if (devpriv->is_m_series) {
5318 #ifdef PCIDMA
5319 s->subdev_flags |= SDF_LSAMPL;
5320 s->insn_bits = ni_m_series_dio_insn_bits;
5321 s->insn_config = ni_m_series_dio_insn_config;
5322 if (dev->irq) {
5323 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5324 s->len_chanlist = s->n_chan;
5325 s->do_cmdtest = ni_cdio_cmdtest;
5326 s->do_cmd = ni_cdio_cmd;
5327 s->cancel = ni_cdio_cancel;
5328
5329 /* M-series boards use DMA */
5330 s->async_dma_dir = DMA_BIDIRECTIONAL;
5331 }
5332
5333 /* reset DIO and set all channels to inputs */
5334 ni_writel(dev, NI_M_CDO_CMD_RESET |
5335 NI_M_CDI_CMD_RESET,
5336 NI_M_CDIO_CMD_REG);
5337 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5338 #endif /* PCIDMA */
5339 } else {
5340 s->insn_bits = ni_dio_insn_bits;
5341 s->insn_config = ni_dio_insn_config;
5342
5343 /* set all channels to inputs */
5344 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5345 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5346 }
5347
5348 /* 8255 device */
5349 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5350 if (board->has_8255) {
5351 ret = subdev_8255_init(dev, s, ni_8255_callback,
5352 NI_E_8255_BASE);
5353 if (ret)
5354 return ret;
5355 } else {
5356 s->type = COMEDI_SUBD_UNUSED;
5357 }
5358
5359 /* formerly general purpose counter/timer device, but no longer used */
5360 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5361 s->type = COMEDI_SUBD_UNUSED;
5362
5363 /* Calibration subdevice */
5364 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5365 s->type = COMEDI_SUBD_CALIB;
5366 s->subdev_flags = SDF_INTERNAL;
5367 s->n_chan = 1;
5368 s->maxdata = 0;
5369 if (devpriv->is_m_series) {
5370 /* internal PWM output used for AI nonlinearity calibration */
5371 s->insn_config = ni_m_series_pwm_config;
5372
5373 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5374 } else if (devpriv->is_6143) {
5375 /* internal PWM output used for AI nonlinearity calibration */
5376 s->insn_config = ni_6143_pwm_config;
5377 } else {
5378 s->subdev_flags |= SDF_WRITABLE;
5379 s->insn_read = ni_calib_insn_read;
5380 s->insn_write = ni_calib_insn_write;
5381
5382 /* setup the caldacs and find the real n_chan and maxdata */
5383 caldac_setup(dev, s);
5384 }
5385
5386 /* EEPROM subdevice */
5387 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5388 s->type = COMEDI_SUBD_MEMORY;
5389 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5390 s->maxdata = 0xff;
5391 if (devpriv->is_m_series) {
5392 s->n_chan = M_SERIES_EEPROM_SIZE;
5393 s->insn_read = ni_m_series_eeprom_insn_read;
5394 } else {
5395 s->n_chan = 512;
5396 s->insn_read = ni_eeprom_insn_read;
5397 }
5398
5399 /* Digital I/O (PFI) subdevice */
5400 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5401 s->type = COMEDI_SUBD_DIO;
5402 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5403 s->maxdata = 1;
5404 if (devpriv->is_m_series) {
5405 s->n_chan = 16;
5406 s->insn_bits = ni_pfi_insn_bits;
5407
5408 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5409 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5410 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5411 NI_M_PFI_OUT_SEL_REG(i));
5412 }
5413 } else {
5414 s->n_chan = 10;
5415 }
5416 s->insn_config = ni_pfi_insn_config;
5417
5418 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5419
5420 /* cs5529 calibration adc */
5421 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5422 if (devpriv->is_67xx) {
5423 s->type = COMEDI_SUBD_AI;
5424 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5425 /* one channel for each analog output channel */
5426 s->n_chan = board->n_aochan;
5427 s->maxdata = (1 << 16) - 1;
5428 s->range_table = &range_unknown; /* XXX */
5429 s->insn_read = cs5529_ai_insn_read;
5430 s->insn_config = NULL;
5431 init_cs5529(dev);
5432 } else {
5433 s->type = COMEDI_SUBD_UNUSED;
5434 }
5435
5436 /* Serial */
5437 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5438 s->type = COMEDI_SUBD_SERIAL;
5439 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5440 s->n_chan = 1;
5441 s->maxdata = 0xff;
5442 s->insn_config = ni_serial_insn_config;
5443 devpriv->serial_interval_ns = 0;
5444 devpriv->serial_hw_mode = 0;
5445
5446 /* RTSI */
5447 s = &dev->subdevices[NI_RTSI_SUBDEV];
5448 s->type = COMEDI_SUBD_DIO;
5449 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5450 s->n_chan = 8;
5451 s->maxdata = 1;
5452 s->insn_bits = ni_rtsi_insn_bits;
5453 s->insn_config = ni_rtsi_insn_config;
5454 ni_rtsi_init(dev);
5455
5456 /* allocate and initialize the gpct counter device */
5457 devpriv->counter_dev = ni_gpct_device_construct(dev,
5458 ni_gpct_write_register,
5459 ni_gpct_read_register,
5460 (devpriv->is_m_series)
5461 ? ni_gpct_variant_m_series
5462 : ni_gpct_variant_e_series,
5463 NUM_GPCT);
5464 if (!devpriv->counter_dev)
5465 return -ENOMEM;
5466
5467 /* Counter (gpct) subdevices */
5468 for (i = 0; i < NUM_GPCT; ++i) {
5469 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5470
5471 /* setup and initialize the counter */
5472 gpct->chip_index = 0;
5473 gpct->counter_index = i;
5474 ni_tio_init_counter(gpct);
5475
5476 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5477 s->type = COMEDI_SUBD_COUNTER;
5478 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5479 s->n_chan = 3;
5480 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5481 : 0x00ffffff;
5482 s->insn_read = ni_tio_insn_read;
5483 s->insn_write = ni_tio_insn_read;
5484 s->insn_config = ni_tio_insn_config;
5485 #ifdef PCIDMA
5486 if (dev->irq && devpriv->mite) {
5487 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5488 s->len_chanlist = 1;
5489 s->do_cmdtest = ni_tio_cmdtest;
5490 s->do_cmd = ni_gpct_cmd;
5491 s->cancel = ni_gpct_cancel;
5492
5493 s->async_dma_dir = DMA_BIDIRECTIONAL;
5494 }
5495 #endif
5496 s->private = gpct;
5497 }
5498
5499 /* Frequency output subdevice */
5500 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5501 s->type = COMEDI_SUBD_COUNTER;
5502 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5503 s->n_chan = 1;
5504 s->maxdata = 0xf;
5505 s->insn_read = ni_freq_out_insn_read;
5506 s->insn_write = ni_freq_out_insn_write;
5507 s->insn_config = ni_freq_out_insn_config;
5508
5509 if (dev->irq) {
5510 ni_stc_writew(dev,
5511 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5512 (NISTC_INT_CTRL_3PIN_INT & 0) |
5513 NISTC_INT_CTRL_INTA_ENA |
5514 NISTC_INT_CTRL_INTB_ENA |
5515 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5516 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5517 NISTC_INT_CTRL_REG);
5518 }
5519
5520 /* DMA setup */
5521 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5522 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5523
5524 if (devpriv->is_6xxx) {
5525 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5526 } else if (devpriv->is_m_series) {
5527 int channel;
5528
5529 for (channel = 0; channel < board->n_aochan; ++channel) {
5530 ni_writeb(dev, 0xf,
5531 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5532 ni_writeb(dev, 0x0,
5533 NI_M_AO_REF_ATTENUATION_REG(channel));
5534 }
5535 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5536 }
5537
5538 return 0;
5539 }
5540
5541 static void mio_common_detach(struct comedi_device *dev)
5542 {
5543 struct ni_private *devpriv = dev->private;
5544
5545 if (devpriv)
5546 ni_gpct_device_destroy(devpriv->counter_dev);
5547 }
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