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[mirror_ubuntu-artful-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 * Hardware driver for DAQ-STC based boards
3 *
4 * COMEDI - Linux Control and Measurement Device Interface
5 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
6 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * This file is meant to be included by another file, e.g.,
21 * ni_atmio.c or ni_pcimio.c.
22 *
23 * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
24 *
25 * References (ftp://ftp.natinst.com/support/manuals):
26 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
27 * 341079b.pdf PCI E Series RLPM
28 * 340934b.pdf DAQ-STC reference manual
29 *
30 * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
31 * release_ni611x.pdf
32 * release_ni67xx.pdf
33 *
34 * Other possibly relevant info:
35 * 320517c.pdf User manual (obsolete)
36 * 320517f.pdf User manual (new)
37 * 320889a.pdf delete
38 * 320906c.pdf maximum signal ratings
39 * 321066a.pdf about 16x
40 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
41 * 321808a.pdf about at-mio-16e-10 rev P
42 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
43 * 321838a.pdf about at-mio-16de-10 rev N
44 *
45 * ISSUES:
46 * - the interrupt routine needs to be cleaned up
47 *
48 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
49 * fully tested as yet. Terry Barnaby, BEAM Ltd.
50 */
51
52 #include <linux/interrupt.h>
53 #include <linux/sched.h>
54 #include <linux/delay.h>
55 #include "8255.h"
56 #include "mite.h"
57
58 /* A timeout count */
59 #define NI_TIMEOUT 1000
60
61 /* Note: this table must match the ai_gain_* definitions */
62 static const short ni_gainlkup[][16] = {
63 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
64 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
65 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
66 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
67 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_4] = {0, 1, 4, 7},
69 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
70 0x003, 0x004, 0x005, 0x006},
71 [ai_gain_622x] = {0, 1, 4, 5},
72 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
73 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
74 };
75
76 static const struct comedi_lrange range_ni_E_ai = {
77 16, {
78 BIP_RANGE(10),
79 BIP_RANGE(5),
80 BIP_RANGE(2.5),
81 BIP_RANGE(1),
82 BIP_RANGE(0.5),
83 BIP_RANGE(0.25),
84 BIP_RANGE(0.1),
85 BIP_RANGE(0.05),
86 UNI_RANGE(20),
87 UNI_RANGE(10),
88 UNI_RANGE(5),
89 UNI_RANGE(2),
90 UNI_RANGE(1),
91 UNI_RANGE(0.5),
92 UNI_RANGE(0.2),
93 UNI_RANGE(0.1)
94 }
95 };
96
97 static const struct comedi_lrange range_ni_E_ai_limited = {
98 8, {
99 BIP_RANGE(10),
100 BIP_RANGE(5),
101 BIP_RANGE(1),
102 BIP_RANGE(0.1),
103 UNI_RANGE(10),
104 UNI_RANGE(5),
105 UNI_RANGE(1),
106 UNI_RANGE(0.1)
107 }
108 };
109
110 static const struct comedi_lrange range_ni_E_ai_limited14 = {
111 14, {
112 BIP_RANGE(10),
113 BIP_RANGE(5),
114 BIP_RANGE(2),
115 BIP_RANGE(1),
116 BIP_RANGE(0.5),
117 BIP_RANGE(0.2),
118 BIP_RANGE(0.1),
119 UNI_RANGE(10),
120 UNI_RANGE(5),
121 UNI_RANGE(2),
122 UNI_RANGE(1),
123 UNI_RANGE(0.5),
124 UNI_RANGE(0.2),
125 UNI_RANGE(0.1)
126 }
127 };
128
129 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
130 4, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 BIP_RANGE(0.5),
134 BIP_RANGE(0.05)
135 }
136 };
137
138 static const struct comedi_lrange range_ni_E_ai_611x = {
139 8, {
140 BIP_RANGE(50),
141 BIP_RANGE(20),
142 BIP_RANGE(10),
143 BIP_RANGE(5),
144 BIP_RANGE(2),
145 BIP_RANGE(1),
146 BIP_RANGE(0.5),
147 BIP_RANGE(0.2)
148 }
149 };
150
151 static const struct comedi_lrange range_ni_M_ai_622x = {
152 4, {
153 BIP_RANGE(10),
154 BIP_RANGE(5),
155 BIP_RANGE(1),
156 BIP_RANGE(0.2)
157 }
158 };
159
160 static const struct comedi_lrange range_ni_M_ai_628x = {
161 7, {
162 BIP_RANGE(10),
163 BIP_RANGE(5),
164 BIP_RANGE(2),
165 BIP_RANGE(1),
166 BIP_RANGE(0.5),
167 BIP_RANGE(0.2),
168 BIP_RANGE(0.1)
169 }
170 };
171
172 static const struct comedi_lrange range_ni_E_ao_ext = {
173 4, {
174 BIP_RANGE(10),
175 UNI_RANGE(10),
176 RANGE_ext(-1, 1),
177 RANGE_ext(0, 1)
178 }
179 };
180
181 static const struct comedi_lrange *const ni_range_lkup[] = {
182 [ai_gain_16] = &range_ni_E_ai,
183 [ai_gain_8] = &range_ni_E_ai_limited,
184 [ai_gain_14] = &range_ni_E_ai_limited14,
185 [ai_gain_4] = &range_ni_E_ai_bipolar4,
186 [ai_gain_611x] = &range_ni_E_ai_611x,
187 [ai_gain_622x] = &range_ni_M_ai_622x,
188 [ai_gain_628x] = &range_ni_M_ai_628x,
189 [ai_gain_6143] = &range_bipolar5
190 };
191
192 enum aimodes {
193 AIMODE_NONE = 0,
194 AIMODE_HALF_FULL = 1,
195 AIMODE_SCAN = 2,
196 AIMODE_SAMPLE = 3,
197 };
198
199 enum ni_common_subdevices {
200 NI_AI_SUBDEV,
201 NI_AO_SUBDEV,
202 NI_DIO_SUBDEV,
203 NI_8255_DIO_SUBDEV,
204 NI_UNUSED_SUBDEV,
205 NI_CALIBRATION_SUBDEV,
206 NI_EEPROM_SUBDEV,
207 NI_PFI_DIO_SUBDEV,
208 NI_CS5529_CALIBRATION_SUBDEV,
209 NI_SERIAL_SUBDEV,
210 NI_RTSI_SUBDEV,
211 NI_GPCT0_SUBDEV,
212 NI_GPCT1_SUBDEV,
213 NI_FREQ_OUT_SUBDEV,
214 NI_NUM_SUBDEVICES
215 };
216
217 #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x))
218
219 enum timebase_nanoseconds {
220 TIMEBASE_1_NS = 50,
221 TIMEBASE_2_NS = 10000
222 };
223
224 #define SERIAL_DISABLED 0
225 #define SERIAL_600NS 600
226 #define SERIAL_1_2US 1200
227 #define SERIAL_10US 10000
228
229 static const int num_adc_stages_611x = 3;
230
231 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
232 {
233 if (dev->mmio)
234 writel(data, dev->mmio + reg);
235 else
236 outl(data, dev->iobase + reg);
237 }
238
239 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
240 {
241 if (dev->mmio)
242 writew(data, dev->mmio + reg);
243 else
244 outw(data, dev->iobase + reg);
245 }
246
247 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
248 {
249 if (dev->mmio)
250 writeb(data, dev->mmio + reg);
251 else
252 outb(data, dev->iobase + reg);
253 }
254
255 static unsigned int ni_readl(struct comedi_device *dev, int reg)
256 {
257 if (dev->mmio)
258 return readl(dev->mmio + reg);
259
260 return inl(dev->iobase + reg);
261 }
262
263 static unsigned int ni_readw(struct comedi_device *dev, int reg)
264 {
265 if (dev->mmio)
266 return readw(dev->mmio + reg);
267
268 return inw(dev->iobase + reg);
269 }
270
271 static unsigned int ni_readb(struct comedi_device *dev, int reg)
272 {
273 if (dev->mmio)
274 return readb(dev->mmio + reg);
275
276 return inb(dev->iobase + reg);
277 }
278
279 /*
280 * We automatically take advantage of STC registers that can be
281 * read/written directly in the I/O space of the board.
282 *
283 * The AT-MIO and DAQCard devices map the low 8 STC registers to
284 * iobase+reg*2.
285 *
286 * Most PCIMIO devices also map the low 8 STC registers but the
287 * 611x devices map the read registers to iobase+(addr-1)*2.
288 * For now non-windowed STC access is disabled if a PCIMIO device
289 * is detected (devpriv->mite has been initialized).
290 *
291 * The M series devices do not used windowed registers for the
292 * STC registers. The functions below handle the mapping of the
293 * windowed STC registers to the m series register offsets.
294 */
295
296 struct mio_regmap {
297 unsigned int mio_reg;
298 int size;
299 };
300
301 static const struct mio_regmap m_series_stc_write_regmap[] = {
302 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
303 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
304 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
305 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
306 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
307 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
308 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
309 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
310 /*
311 * NISTC_DIO_OUT_REG maps to:
312 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
313 */
314 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
315 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
316 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
317 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
318 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
319 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
320 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
321 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
322 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
323 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
324 [NISTC_G0_MODE_REG] = { 0x134, 2 },
325 [NISTC_G1_MODE_REG] = { 0x136, 2 },
326 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
327 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
328 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
329 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
330 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
331 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
332 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
333 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
334 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
335 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
336 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
337 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
338 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
339 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
340 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
341 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
342 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
343 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
344 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
345 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
346 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
347 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
348 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
349 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
350 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
351 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
352 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
353 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
354 [NISTC_RESET_REG] = { 0x190, 2 },
355 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
356 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
357 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
358 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
359 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
360 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
361 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
362 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
363 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
364 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
365 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
366 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
367 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
368 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
369 };
370
371 static void m_series_stc_write(struct comedi_device *dev,
372 unsigned int data, unsigned int reg)
373 {
374 const struct mio_regmap *regmap;
375
376 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
377 regmap = &m_series_stc_write_regmap[reg];
378 } else {
379 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
380 __func__, reg);
381 return;
382 }
383
384 switch (regmap->size) {
385 case 4:
386 ni_writel(dev, data, regmap->mio_reg);
387 break;
388 case 2:
389 ni_writew(dev, data, regmap->mio_reg);
390 break;
391 default:
392 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
393 __func__, reg);
394 break;
395 }
396 }
397
398 static const struct mio_regmap m_series_stc_read_regmap[] = {
399 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
400 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
401 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
402 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
403 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
404 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
405 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
406 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
407 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
408 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
409 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
410 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
411 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
412 [NISTC_STATUS1_REG] = { 0x136, 2 },
413 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
414 [NISTC_STATUS2_REG] = { 0x13a, 2 },
415 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
416 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
417 };
418
419 static unsigned int m_series_stc_read(struct comedi_device *dev,
420 unsigned int reg)
421 {
422 const struct mio_regmap *regmap;
423
424 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
425 regmap = &m_series_stc_read_regmap[reg];
426 } else {
427 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
428 __func__, reg);
429 return 0;
430 }
431
432 switch (regmap->size) {
433 case 4:
434 return ni_readl(dev, regmap->mio_reg);
435 case 2:
436 return ni_readw(dev, regmap->mio_reg);
437 case 1:
438 return ni_readb(dev, regmap->mio_reg);
439 default:
440 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
441 __func__, reg);
442 return 0;
443 }
444 }
445
446 static void ni_stc_writew(struct comedi_device *dev,
447 unsigned int data, int reg)
448 {
449 struct ni_private *devpriv = dev->private;
450 unsigned long flags;
451
452 if (devpriv->is_m_series) {
453 m_series_stc_write(dev, data, reg);
454 } else {
455 spin_lock_irqsave(&devpriv->window_lock, flags);
456 if (!devpriv->mite && reg < 8) {
457 ni_writew(dev, data, reg * 2);
458 } else {
459 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
460 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
461 }
462 spin_unlock_irqrestore(&devpriv->window_lock, flags);
463 }
464 }
465
466 static void ni_stc_writel(struct comedi_device *dev,
467 unsigned int data, int reg)
468 {
469 struct ni_private *devpriv = dev->private;
470
471 if (devpriv->is_m_series) {
472 m_series_stc_write(dev, data, reg);
473 } else {
474 ni_stc_writew(dev, data >> 16, reg);
475 ni_stc_writew(dev, data & 0xffff, reg + 1);
476 }
477 }
478
479 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482 unsigned long flags;
483 unsigned int val;
484
485 if (devpriv->is_m_series) {
486 val = m_series_stc_read(dev, reg);
487 } else {
488 spin_lock_irqsave(&devpriv->window_lock, flags);
489 if (!devpriv->mite && reg < 8) {
490 val = ni_readw(dev, reg * 2);
491 } else {
492 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
493 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
494 }
495 spin_unlock_irqrestore(&devpriv->window_lock, flags);
496 }
497 return val;
498 }
499
500 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
501 {
502 struct ni_private *devpriv = dev->private;
503 unsigned int val;
504
505 if (devpriv->is_m_series) {
506 val = m_series_stc_read(dev, reg);
507 } else {
508 val = ni_stc_readw(dev, reg) << 16;
509 val |= ni_stc_readw(dev, reg + 1);
510 }
511 return val;
512 }
513
514 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
515 unsigned int bit_mask,
516 unsigned int bit_values)
517 {
518 struct ni_private *devpriv = dev->private;
519 unsigned long flags;
520
521 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
522 switch (reg) {
523 case NISTC_INTA_ENA_REG:
524 devpriv->int_a_enable_reg &= ~bit_mask;
525 devpriv->int_a_enable_reg |= bit_values & bit_mask;
526 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
527 break;
528 case NISTC_INTB_ENA_REG:
529 devpriv->int_b_enable_reg &= ~bit_mask;
530 devpriv->int_b_enable_reg |= bit_values & bit_mask;
531 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
532 break;
533 case NISTC_IO_BIDIR_PIN_REG:
534 devpriv->io_bidirection_pin_reg &= ~bit_mask;
535 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
536 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
537 break;
538 case NI_E_DMA_AI_AO_SEL_REG:
539 devpriv->ai_ao_select_reg &= ~bit_mask;
540 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
541 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
542 break;
543 case NI_E_DMA_G0_G1_SEL_REG:
544 devpriv->g0_g1_select_reg &= ~bit_mask;
545 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
546 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
547 break;
548 case NI_M_CDIO_DMA_SEL_REG:
549 devpriv->cdio_dma_select_reg &= ~bit_mask;
550 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
551 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
552 break;
553 default:
554 dev_err(dev->class_dev, "called with invalid register %d\n",
555 reg);
556 break;
557 }
558 mmiowb();
559 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
560 }
561
562 #ifdef PCIDMA
563
564 /* selects the MITE channel to use for DMA */
565 #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \
566 ((x) == 4) ? 0x3 : \
567 ((x) == 5) ? 0x5 : 0x0)
568
569 /* DMA channel setup */
570 static int ni_request_ai_mite_channel(struct comedi_device *dev)
571 {
572 struct ni_private *devpriv = dev->private;
573 struct mite_channel *mite_chan;
574 unsigned long flags;
575 unsigned int bits;
576
577 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
578 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
579 if (!mite_chan) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581 dev_err(dev->class_dev,
582 "failed to reserve mite dma channel for analog input\n");
583 return -EBUSY;
584 }
585 mite_chan->dir = COMEDI_INPUT;
586 devpriv->ai_mite_chan = mite_chan;
587
588 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
589 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
590 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
591
592 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
593 return 0;
594 }
595
596 static int ni_request_ao_mite_channel(struct comedi_device *dev)
597 {
598 struct ni_private *devpriv = dev->private;
599 struct mite_channel *mite_chan;
600 unsigned long flags;
601 unsigned int bits;
602
603 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
604 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
605 if (!mite_chan) {
606 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
607 dev_err(dev->class_dev,
608 "failed to reserve mite dma channel for analog outut\n");
609 return -EBUSY;
610 }
611 mite_chan->dir = COMEDI_OUTPUT;
612 devpriv->ao_mite_chan = mite_chan;
613
614 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
615 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
616 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
617
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
619 return 0;
620 }
621
622 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
623 unsigned int gpct_index,
624 enum comedi_io_direction direction)
625 {
626 struct ni_private *devpriv = dev->private;
627 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
628 struct mite_channel *mite_chan;
629 unsigned long flags;
630 unsigned int bits;
631
632 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
633 mite_chan = mite_request_channel(devpriv->mite,
634 devpriv->gpct_mite_ring[gpct_index]);
635 if (!mite_chan) {
636 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
637 dev_err(dev->class_dev,
638 "failed to reserve mite dma channel for counter\n");
639 return -EBUSY;
640 }
641 mite_chan->dir = direction;
642 ni_tio_set_mite_channel(counter, mite_chan);
643
644 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
645 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
646 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
647 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
648
649 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
650 return 0;
651 }
652
653 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
654 {
655 struct ni_private *devpriv = dev->private;
656 struct mite_channel *mite_chan;
657 unsigned long flags;
658 unsigned int bits;
659
660 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
661 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
662 if (!mite_chan) {
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
664 dev_err(dev->class_dev,
665 "failed to reserve mite dma channel for correlated digital output\n");
666 return -EBUSY;
667 }
668 mite_chan->dir = COMEDI_OUTPUT;
669 devpriv->cdo_mite_chan = mite_chan;
670
671 /*
672 * XXX just guessing NI_STC_DMA_CHAN_SEL()
673 * returns the right bits, under the assumption the cdio dma
674 * selection works just like ai/ao/gpct.
675 * Definitely works for dma channels 0 and 1.
676 */
677 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
678 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
679 NI_M_CDIO_DMA_SEL_CDO_MASK,
680 NI_M_CDIO_DMA_SEL_CDO(bits));
681
682 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
683 return 0;
684 }
685 #endif /* PCIDMA */
686
687 static void ni_release_ai_mite_channel(struct comedi_device *dev)
688 {
689 #ifdef PCIDMA
690 struct ni_private *devpriv = dev->private;
691 unsigned long flags;
692
693 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
694 if (devpriv->ai_mite_chan) {
695 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
696 NI_E_DMA_AI_SEL_MASK, 0);
697 mite_release_channel(devpriv->ai_mite_chan);
698 devpriv->ai_mite_chan = NULL;
699 }
700 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
701 #endif /* PCIDMA */
702 }
703
704 static void ni_release_ao_mite_channel(struct comedi_device *dev)
705 {
706 #ifdef PCIDMA
707 struct ni_private *devpriv = dev->private;
708 unsigned long flags;
709
710 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
711 if (devpriv->ao_mite_chan) {
712 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
713 NI_E_DMA_AO_SEL_MASK, 0);
714 mite_release_channel(devpriv->ao_mite_chan);
715 devpriv->ao_mite_chan = NULL;
716 }
717 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
718 #endif /* PCIDMA */
719 }
720
721 #ifdef PCIDMA
722 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
723 unsigned int gpct_index)
724 {
725 struct ni_private *devpriv = dev->private;
726 unsigned long flags;
727
728 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
729 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
730 struct mite_channel *mite_chan =
731 devpriv->counter_dev->counters[gpct_index].mite_chan;
732
733 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
734 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
735 ni_tio_set_mite_channel(&devpriv->
736 counter_dev->counters[gpct_index],
737 NULL);
738 mite_release_channel(mite_chan);
739 }
740 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
741 }
742
743 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
744 {
745 struct ni_private *devpriv = dev->private;
746 unsigned long flags;
747
748 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
749 if (devpriv->cdo_mite_chan) {
750 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
751 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
752 mite_release_channel(devpriv->cdo_mite_chan);
753 devpriv->cdo_mite_chan = NULL;
754 }
755 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
756 }
757
758 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
759 unsigned int gpct_index, short enable)
760 {
761 struct ni_private *devpriv = dev->private;
762 unsigned int val = 0;
763 int reg;
764
765 if (devpriv->is_m_series || gpct_index > 1)
766 return;
767
768 /*
769 * e-series boards use the second irq signals to generate
770 * dma requests for their counters
771 */
772 if (gpct_index == 0) {
773 reg = NISTC_INTA2_ENA_REG;
774 if (enable)
775 val = NISTC_INTA_ENA_G0_GATE;
776 } else {
777 reg = NISTC_INTB2_ENA_REG;
778 if (enable)
779 val = NISTC_INTB_ENA_G1_GATE;
780 }
781 ni_stc_writew(dev, val, reg);
782 }
783 #endif /* PCIDMA */
784
785 static void ni_clear_ai_fifo(struct comedi_device *dev)
786 {
787 struct ni_private *devpriv = dev->private;
788 static const int timeout = 10000;
789 int i;
790
791 if (devpriv->is_6143) {
792 /* Flush the 6143 data FIFO */
793 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
794 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
795 /* Wait for complete */
796 for (i = 0; i < timeout; i++) {
797 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
798 break;
799 udelay(1);
800 }
801 if (i == timeout)
802 dev_err(dev->class_dev, "FIFO flush timeout\n");
803 } else {
804 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
805 if (devpriv->is_625x) {
806 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
807 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
808 #if 0
809 /*
810 * The NI example code does 3 convert pulses for 625x
811 * boards, But that appears to be wrong in practice.
812 */
813 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
814 NISTC_AI_CMD1_REG);
815 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
816 NISTC_AI_CMD1_REG);
817 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
818 NISTC_AI_CMD1_REG);
819 #endif
820 }
821 }
822 }
823
824 static inline void ni_ao_win_outw(struct comedi_device *dev,
825 unsigned int data, int addr)
826 {
827 struct ni_private *devpriv = dev->private;
828 unsigned long flags;
829
830 spin_lock_irqsave(&devpriv->window_lock, flags);
831 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
832 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
833 spin_unlock_irqrestore(&devpriv->window_lock, flags);
834 }
835
836 static inline void ni_ao_win_outl(struct comedi_device *dev,
837 unsigned int data, int addr)
838 {
839 struct ni_private *devpriv = dev->private;
840 unsigned long flags;
841
842 spin_lock_irqsave(&devpriv->window_lock, flags);
843 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
844 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
845 spin_unlock_irqrestore(&devpriv->window_lock, flags);
846 }
847
848 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
849 {
850 struct ni_private *devpriv = dev->private;
851 unsigned long flags;
852 unsigned short data;
853
854 spin_lock_irqsave(&devpriv->window_lock, flags);
855 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
856 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
857 spin_unlock_irqrestore(&devpriv->window_lock, flags);
858 return data;
859 }
860
861 /*
862 * ni_set_bits( ) allows different parts of the ni_mio_common driver to
863 * share registers (such as Interrupt_A_Register) without interfering with
864 * each other.
865 *
866 * NOTE: the switch/case statements are optimized out for a constant argument
867 * so this is actually quite fast--- If you must wrap another function around
868 * this make it inline to avoid a large speed penalty.
869 *
870 * value should only be 1 or 0.
871 */
872 static inline void ni_set_bits(struct comedi_device *dev, int reg,
873 unsigned int bits, unsigned int value)
874 {
875 unsigned int bit_values;
876
877 if (value)
878 bit_values = bits;
879 else
880 bit_values = 0;
881 ni_set_bitfield(dev, reg, bits, bit_values);
882 }
883
884 #ifdef PCIDMA
885 static void ni_sync_ai_dma(struct comedi_device *dev)
886 {
887 struct ni_private *devpriv = dev->private;
888 struct comedi_subdevice *s = dev->read_subdev;
889 unsigned long flags;
890
891 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
892 if (devpriv->ai_mite_chan)
893 mite_sync_dma(devpriv->ai_mite_chan, s);
894 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
895 }
896
897 static int ni_ai_drain_dma(struct comedi_device *dev)
898 {
899 struct ni_private *devpriv = dev->private;
900 int i;
901 static const int timeout = 10000;
902 unsigned long flags;
903 int retval = 0;
904
905 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
906 if (devpriv->ai_mite_chan) {
907 for (i = 0; i < timeout; i++) {
908 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
909 NISTC_AI_STATUS1_FIFO_E) &&
910 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
911 break;
912 udelay(5);
913 }
914 if (i == timeout) {
915 dev_err(dev->class_dev, "timed out\n");
916 dev_err(dev->class_dev,
917 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
918 mite_bytes_in_transit(devpriv->ai_mite_chan),
919 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
920 retval = -1;
921 }
922 }
923 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
924
925 ni_sync_ai_dma(dev);
926
927 return retval;
928 }
929
930 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
931 {
932 static const int timeout = 10000;
933 int i;
934
935 for (i = 0; i < timeout; i++) {
936 unsigned short b_status;
937
938 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
939 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
940 break;
941 /*
942 * If we poll too often, the pci bus activity seems
943 * to slow the dma transfer down.
944 */
945 usleep_range(10, 100);
946 }
947 if (i == timeout) {
948 dev_err(dev->class_dev, "timed out waiting for dma load\n");
949 return -EPIPE;
950 }
951 return 0;
952 }
953 #endif /* PCIDMA */
954
955 #ifndef PCIDMA
956
957 static void ni_ao_fifo_load(struct comedi_device *dev,
958 struct comedi_subdevice *s, int n)
959 {
960 struct ni_private *devpriv = dev->private;
961 int i;
962 unsigned short d;
963 unsigned int packed_data;
964
965 for (i = 0; i < n; i++) {
966 comedi_buf_read_samples(s, &d, 1);
967
968 if (devpriv->is_6xxx) {
969 packed_data = d & 0xffff;
970 /* 6711 only has 16 bit wide ao fifo */
971 if (!devpriv->is_6711) {
972 comedi_buf_read_samples(s, &d, 1);
973 i++;
974 packed_data |= (d << 16) & 0xffff0000;
975 }
976 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
977 } else {
978 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
979 }
980 }
981 }
982
983 /*
984 * There's a small problem if the FIFO gets really low and we
985 * don't have the data to fill it. Basically, if after we fill
986 * the FIFO with all the data available, the FIFO is _still_
987 * less than half full, we never clear the interrupt. If the
988 * IRQ is in edge mode, we never get another interrupt, because
989 * this one wasn't cleared. If in level mode, we get flooded
990 * with interrupts that we can't fulfill, because nothing ever
991 * gets put into the buffer.
992 *
993 * This kind of situation is recoverable, but it is easier to
994 * just pretend we had a FIFO underrun, since there is a good
995 * chance it will happen anyway. This is _not_ the case for
996 * RT code, as RT code might purposely be running close to the
997 * metal. Needs to be fixed eventually.
998 */
999 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1000 struct comedi_subdevice *s)
1001 {
1002 const struct ni_board_struct *board = dev->board_ptr;
1003 unsigned int nbytes;
1004 unsigned int nsamples;
1005
1006 nbytes = comedi_buf_read_n_available(s);
1007 if (nbytes == 0) {
1008 s->async->events |= COMEDI_CB_OVERFLOW;
1009 return 0;
1010 }
1011
1012 nsamples = comedi_bytes_to_samples(s, nbytes);
1013 if (nsamples > board->ao_fifo_depth / 2)
1014 nsamples = board->ao_fifo_depth / 2;
1015
1016 ni_ao_fifo_load(dev, s, nsamples);
1017
1018 return 1;
1019 }
1020
1021 static int ni_ao_prep_fifo(struct comedi_device *dev,
1022 struct comedi_subdevice *s)
1023 {
1024 const struct ni_board_struct *board = dev->board_ptr;
1025 struct ni_private *devpriv = dev->private;
1026 unsigned int nbytes;
1027 unsigned int nsamples;
1028
1029 /* reset fifo */
1030 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1031 if (devpriv->is_6xxx)
1032 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1033
1034 /* load some data */
1035 nbytes = comedi_buf_read_n_available(s);
1036 if (nbytes == 0)
1037 return 0;
1038
1039 nsamples = comedi_bytes_to_samples(s, nbytes);
1040 if (nsamples > board->ao_fifo_depth)
1041 nsamples = board->ao_fifo_depth;
1042
1043 ni_ao_fifo_load(dev, s, nsamples);
1044
1045 return nsamples;
1046 }
1047
1048 static void ni_ai_fifo_read(struct comedi_device *dev,
1049 struct comedi_subdevice *s, int n)
1050 {
1051 struct ni_private *devpriv = dev->private;
1052 struct comedi_async *async = s->async;
1053 unsigned int dl;
1054 unsigned short data;
1055 int i;
1056
1057 if (devpriv->is_611x) {
1058 for (i = 0; i < n / 2; i++) {
1059 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1060 /* This may get the hi/lo data in the wrong order */
1061 data = (dl >> 16) & 0xffff;
1062 comedi_buf_write_samples(s, &data, 1);
1063 data = dl & 0xffff;
1064 comedi_buf_write_samples(s, &data, 1);
1065 }
1066 /* Check if there's a single sample stuck in the FIFO */
1067 if (n % 2) {
1068 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1069 data = dl & 0xffff;
1070 comedi_buf_write_samples(s, &data, 1);
1071 }
1072 } else if (devpriv->is_6143) {
1073 /*
1074 * This just reads the FIFO assuming the data is present,
1075 * no checks on the FIFO status are performed.
1076 */
1077 for (i = 0; i < n / 2; i++) {
1078 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1079
1080 data = (dl >> 16) & 0xffff;
1081 comedi_buf_write_samples(s, &data, 1);
1082 data = dl & 0xffff;
1083 comedi_buf_write_samples(s, &data, 1);
1084 }
1085 if (n % 2) {
1086 /* Assume there is a single sample stuck in the FIFO */
1087 /* Get stranded sample into FIFO */
1088 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1089 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1090 data = (dl >> 16) & 0xffff;
1091 comedi_buf_write_samples(s, &data, 1);
1092 }
1093 } else {
1094 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1095 dev_err(dev->class_dev,
1096 "bug! ai_fifo_buffer too small\n");
1097 async->events |= COMEDI_CB_ERROR;
1098 return;
1099 }
1100 for (i = 0; i < n; i++) {
1101 devpriv->ai_fifo_buffer[i] =
1102 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1103 }
1104 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1105 }
1106 }
1107
1108 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1109 {
1110 const struct ni_board_struct *board = dev->board_ptr;
1111 struct comedi_subdevice *s = dev->read_subdev;
1112 int n;
1113
1114 n = board->ai_fifo_depth / 2;
1115
1116 ni_ai_fifo_read(dev, s, n);
1117 }
1118 #endif
1119
1120 /* Empties the AI fifo */
1121 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1122 {
1123 struct ni_private *devpriv = dev->private;
1124 struct comedi_subdevice *s = dev->read_subdev;
1125 unsigned int dl;
1126 unsigned short data;
1127 int i;
1128
1129 if (devpriv->is_611x) {
1130 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1131 NISTC_AI_STATUS1_FIFO_E) == 0) {
1132 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1133
1134 /* This may get the hi/lo data in the wrong order */
1135 data = dl >> 16;
1136 comedi_buf_write_samples(s, &data, 1);
1137 data = dl & 0xffff;
1138 comedi_buf_write_samples(s, &data, 1);
1139 }
1140 } else if (devpriv->is_6143) {
1141 i = 0;
1142 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1143 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1144
1145 /* This may get the hi/lo data in the wrong order */
1146 data = dl >> 16;
1147 comedi_buf_write_samples(s, &data, 1);
1148 data = dl & 0xffff;
1149 comedi_buf_write_samples(s, &data, 1);
1150 i += 2;
1151 }
1152 /* Check if stranded sample is present */
1153 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1154 /* Get stranded sample into FIFO */
1155 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1156 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1157 data = (dl >> 16) & 0xffff;
1158 comedi_buf_write_samples(s, &data, 1);
1159 }
1160
1161 } else {
1162 unsigned short fe; /* fifo empty */
1163
1164 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1165 NISTC_AI_STATUS1_FIFO_E;
1166 while (fe == 0) {
1167 for (i = 0;
1168 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1169 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1170 NISTC_AI_STATUS1_FIFO_E;
1171 if (fe)
1172 break;
1173 devpriv->ai_fifo_buffer[i] =
1174 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1175 }
1176 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1177 }
1178 }
1179 }
1180
1181 static void get_last_sample_611x(struct comedi_device *dev)
1182 {
1183 struct ni_private *devpriv = dev->private;
1184 struct comedi_subdevice *s = dev->read_subdev;
1185 unsigned short data;
1186 unsigned int dl;
1187
1188 if (!devpriv->is_611x)
1189 return;
1190
1191 /* Check if there's a single sample stuck in the FIFO */
1192 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1193 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1194 data = dl & 0xffff;
1195 comedi_buf_write_samples(s, &data, 1);
1196 }
1197 }
1198
1199 static void get_last_sample_6143(struct comedi_device *dev)
1200 {
1201 struct ni_private *devpriv = dev->private;
1202 struct comedi_subdevice *s = dev->read_subdev;
1203 unsigned short data;
1204 unsigned int dl;
1205
1206 if (!devpriv->is_6143)
1207 return;
1208
1209 /* Check if there's a single sample stuck in the FIFO */
1210 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1211 /* Get stranded sample into FIFO */
1212 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1213 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1214
1215 /* This may get the hi/lo data in the wrong order */
1216 data = (dl >> 16) & 0xffff;
1217 comedi_buf_write_samples(s, &data, 1);
1218 }
1219 }
1220
1221 static void shutdown_ai_command(struct comedi_device *dev)
1222 {
1223 struct comedi_subdevice *s = dev->read_subdev;
1224
1225 #ifdef PCIDMA
1226 ni_ai_drain_dma(dev);
1227 #endif
1228 ni_handle_fifo_dregs(dev);
1229 get_last_sample_611x(dev);
1230 get_last_sample_6143(dev);
1231
1232 s->async->events |= COMEDI_CB_EOA;
1233 }
1234
1235 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1236 {
1237 struct ni_private *devpriv = dev->private;
1238
1239 if (devpriv->aimode == AIMODE_SCAN) {
1240 #ifdef PCIDMA
1241 static const int timeout = 10;
1242 int i;
1243
1244 for (i = 0; i < timeout; i++) {
1245 ni_sync_ai_dma(dev);
1246 if ((s->async->events & COMEDI_CB_EOS))
1247 break;
1248 udelay(1);
1249 }
1250 #else
1251 ni_handle_fifo_dregs(dev);
1252 s->async->events |= COMEDI_CB_EOS;
1253 #endif
1254 }
1255 /* handle special case of single scan */
1256 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1257 shutdown_ai_command(dev);
1258 }
1259
1260 static void handle_gpct_interrupt(struct comedi_device *dev,
1261 unsigned short counter_index)
1262 {
1263 #ifdef PCIDMA
1264 struct ni_private *devpriv = dev->private;
1265 struct comedi_subdevice *s;
1266
1267 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1268
1269 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1270 s);
1271 comedi_handle_events(dev, s);
1272 #endif
1273 }
1274
1275 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1276 {
1277 unsigned short ack = 0;
1278
1279 if (a_status & NISTC_AI_STATUS1_SC_TC)
1280 ack |= NISTC_INTA_ACK_AI_SC_TC;
1281 if (a_status & NISTC_AI_STATUS1_START1)
1282 ack |= NISTC_INTA_ACK_AI_START1;
1283 if (a_status & NISTC_AI_STATUS1_START)
1284 ack |= NISTC_INTA_ACK_AI_START;
1285 if (a_status & NISTC_AI_STATUS1_STOP)
1286 ack |= NISTC_INTA_ACK_AI_STOP;
1287 if (ack)
1288 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1289 }
1290
1291 static void handle_a_interrupt(struct comedi_device *dev,
1292 struct comedi_subdevice *s,
1293 unsigned short status)
1294 {
1295 struct comedi_cmd *cmd = &s->async->cmd;
1296
1297 /* test for all uncommon interrupt events at the same time */
1298 if (status & (NISTC_AI_STATUS1_ERR |
1299 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1300 if (status == 0xffff) {
1301 dev_err(dev->class_dev, "Card removed?\n");
1302 /*
1303 * We probably aren't even running a command now,
1304 * so it's a good idea to be careful.
1305 */
1306 if (comedi_is_subdevice_running(s))
1307 s->async->events |= COMEDI_CB_ERROR;
1308 return;
1309 }
1310 if (status & NISTC_AI_STATUS1_ERR) {
1311 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1312 status);
1313
1314 shutdown_ai_command(dev);
1315
1316 s->async->events |= COMEDI_CB_ERROR;
1317 if (status & NISTC_AI_STATUS1_OVER)
1318 s->async->events |= COMEDI_CB_OVERFLOW;
1319 return;
1320 }
1321 if (status & NISTC_AI_STATUS1_SC_TC) {
1322 if (cmd->stop_src == TRIG_COUNT)
1323 shutdown_ai_command(dev);
1324 }
1325 }
1326 #ifndef PCIDMA
1327 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1328 int i;
1329 static const int timeout = 10;
1330 /*
1331 * PCMCIA cards (at least 6036) seem to stop producing
1332 * interrupts if we fail to get the fifo less than half
1333 * full, so loop to be sure.
1334 */
1335 for (i = 0; i < timeout; ++i) {
1336 ni_handle_fifo_half_full(dev);
1337 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1338 NISTC_AI_STATUS1_FIFO_HF) == 0)
1339 break;
1340 }
1341 }
1342 #endif /* !PCIDMA */
1343
1344 if (status & NISTC_AI_STATUS1_STOP)
1345 ni_handle_eos(dev, s);
1346 }
1347
1348 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1349 {
1350 unsigned short ack = 0;
1351
1352 if (b_status & NISTC_AO_STATUS1_BC_TC)
1353 ack |= NISTC_INTB_ACK_AO_BC_TC;
1354 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1355 ack |= NISTC_INTB_ACK_AO_ERR;
1356 if (b_status & NISTC_AO_STATUS1_START)
1357 ack |= NISTC_INTB_ACK_AO_START;
1358 if (b_status & NISTC_AO_STATUS1_START1)
1359 ack |= NISTC_INTB_ACK_AO_START1;
1360 if (b_status & NISTC_AO_STATUS1_UC_TC)
1361 ack |= NISTC_INTB_ACK_AO_UC_TC;
1362 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1363 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1364 if (b_status & NISTC_AO_STATUS1_UPDATE)
1365 ack |= NISTC_INTB_ACK_AO_UPDATE;
1366 if (ack)
1367 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1368 }
1369
1370 static void handle_b_interrupt(struct comedi_device *dev,
1371 struct comedi_subdevice *s,
1372 unsigned short b_status)
1373 {
1374 if (b_status == 0xffff)
1375 return;
1376 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1377 dev_err(dev->class_dev,
1378 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1379 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1380 s->async->events |= COMEDI_CB_OVERFLOW;
1381 }
1382
1383 if (s->async->cmd.stop_src != TRIG_NONE &&
1384 b_status & NISTC_AO_STATUS1_BC_TC)
1385 s->async->events |= COMEDI_CB_EOA;
1386
1387 #ifndef PCIDMA
1388 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1389 int ret;
1390
1391 ret = ni_ao_fifo_half_empty(dev, s);
1392 if (!ret) {
1393 dev_err(dev->class_dev, "AO buffer underrun\n");
1394 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1395 NISTC_INTB_ENA_AO_FIFO |
1396 NISTC_INTB_ENA_AO_ERR, 0);
1397 s->async->events |= COMEDI_CB_OVERFLOW;
1398 }
1399 }
1400 #endif
1401 }
1402
1403 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1404 void *data, unsigned int num_bytes,
1405 unsigned int chan_index)
1406 {
1407 struct ni_private *devpriv = dev->private;
1408 struct comedi_async *async = s->async;
1409 struct comedi_cmd *cmd = &async->cmd;
1410 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1411 unsigned short *array = data;
1412 unsigned int *larray = data;
1413 unsigned int i;
1414 #ifdef PCIDMA
1415 __le16 *barray = data;
1416 __le32 *blarray = data;
1417 #endif
1418
1419 for (i = 0; i < nsamples; i++) {
1420 #ifdef PCIDMA
1421 if (s->subdev_flags & SDF_LSAMPL)
1422 larray[i] = le32_to_cpu(blarray[i]);
1423 else
1424 array[i] = le16_to_cpu(barray[i]);
1425 #endif
1426 if (s->subdev_flags & SDF_LSAMPL)
1427 larray[i] += devpriv->ai_offset[chan_index];
1428 else
1429 array[i] += devpriv->ai_offset[chan_index];
1430 chan_index++;
1431 chan_index %= cmd->chanlist_len;
1432 }
1433 }
1434
1435 #ifdef PCIDMA
1436
1437 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1438 {
1439 struct ni_private *devpriv = dev->private;
1440 struct comedi_subdevice *s = dev->read_subdev;
1441 int retval;
1442 unsigned long flags;
1443
1444 retval = ni_request_ai_mite_channel(dev);
1445 if (retval)
1446 return retval;
1447
1448 /* write alloc the entire buffer */
1449 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1450
1451 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1452 if (!devpriv->ai_mite_chan) {
1453 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1454 return -EIO;
1455 }
1456
1457 if (devpriv->is_611x || devpriv->is_6143)
1458 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1459 else if (devpriv->is_628x)
1460 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1461 else
1462 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1463
1464 /*start the MITE */
1465 mite_dma_arm(devpriv->ai_mite_chan);
1466 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1467
1468 return 0;
1469 }
1470
1471 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1472 {
1473 struct ni_private *devpriv = dev->private;
1474 struct comedi_subdevice *s = dev->write_subdev;
1475 int retval;
1476 unsigned long flags;
1477
1478 retval = ni_request_ao_mite_channel(dev);
1479 if (retval)
1480 return retval;
1481
1482 /* read alloc the entire buffer */
1483 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1484
1485 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1486 if (devpriv->ao_mite_chan) {
1487 if (devpriv->is_611x || devpriv->is_6713) {
1488 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1489 } else {
1490 /*
1491 * Doing 32 instead of 16 bit wide transfers from
1492 * memory makes the mite do 32 bit pci transfers,
1493 * doubling pci bandwidth.
1494 */
1495 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1496 }
1497 mite_dma_arm(devpriv->ao_mite_chan);
1498 } else {
1499 retval = -EIO;
1500 }
1501 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1502
1503 return retval;
1504 }
1505
1506 #endif /* PCIDMA */
1507
1508 /*
1509 * used for both cancel ioctl and board initialization
1510 *
1511 * this is pretty harsh for a cancel, but it works...
1512 */
1513 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1514 {
1515 struct ni_private *devpriv = dev->private;
1516 unsigned int ai_personal;
1517 unsigned int ai_out_ctrl;
1518
1519 ni_release_ai_mite_channel(dev);
1520 /* ai configuration */
1521 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1522 NISTC_RESET_REG);
1523
1524 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1525
1526 ni_clear_ai_fifo(dev);
1527
1528 if (!devpriv->is_6143)
1529 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1530
1531 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1532 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1533 NISTC_AI_MODE1_RSVD
1534 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1535 NISTC_AI_MODE1_REG);
1536 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1537 /* generate FIFO interrupts on non-empty */
1538 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1539 NISTC_AI_MODE3_REG);
1540
1541 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1542 NISTC_AI_PERSONAL_SOC_POLARITY |
1543 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1544 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1545 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1546 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1547 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1548 if (devpriv->is_611x) {
1549 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1550 } else if (devpriv->is_6143) {
1551 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1552 } else {
1553 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1554 if (devpriv->is_622x)
1555 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1556 else
1557 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1558 }
1559 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1560 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1561
1562 /* the following registers should not be changed, because there
1563 * are no backup registers in devpriv. If you want to change
1564 * any of these, add a backup register and other appropriate code:
1565 * NISTC_AI_MODE1_REG
1566 * NISTC_AI_MODE3_REG
1567 * NISTC_AI_PERSONAL_REG
1568 * NISTC_AI_OUT_CTRL_REG
1569 */
1570
1571 /* clear interrupts */
1572 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1573
1574 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1575
1576 return 0;
1577 }
1578
1579 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1580 {
1581 unsigned long flags;
1582 int count;
1583
1584 /* lock to avoid race with interrupt handler */
1585 spin_lock_irqsave(&dev->spinlock, flags);
1586 #ifndef PCIDMA
1587 ni_handle_fifo_dregs(dev);
1588 #else
1589 ni_sync_ai_dma(dev);
1590 #endif
1591 count = comedi_buf_n_bytes_ready(s);
1592 spin_unlock_irqrestore(&dev->spinlock, flags);
1593
1594 return count;
1595 }
1596
1597 static void ni_prime_channelgain_list(struct comedi_device *dev)
1598 {
1599 int i;
1600
1601 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1602 for (i = 0; i < NI_TIMEOUT; ++i) {
1603 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1604 NISTC_AI_STATUS1_FIFO_E)) {
1605 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1606 return;
1607 }
1608 udelay(1);
1609 }
1610 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1611 }
1612
1613 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1614 unsigned int n_chan,
1615 unsigned int *list)
1616 {
1617 const struct ni_board_struct *board = dev->board_ptr;
1618 struct ni_private *devpriv = dev->private;
1619 unsigned int chan, range, aref;
1620 unsigned int i;
1621 unsigned int dither;
1622 unsigned int range_code;
1623
1624 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1625
1626 if ((list[0] & CR_ALT_SOURCE)) {
1627 unsigned int bypass_bits;
1628
1629 chan = CR_CHAN(list[0]);
1630 range = CR_RANGE(list[0]);
1631 range_code = ni_gainlkup[board->gainlkup][range];
1632 dither = (list[0] & CR_ALT_FILTER) != 0;
1633 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1634 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1635 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1636 devpriv->ai_calib_source;
1637 if (dither)
1638 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1639 /* don't use 2's complement encoding */
1640 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1641 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1642 } else {
1643 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1644 }
1645 for (i = 0; i < n_chan; i++) {
1646 unsigned int config_bits = 0;
1647
1648 chan = CR_CHAN(list[i]);
1649 aref = CR_AREF(list[i]);
1650 range = CR_RANGE(list[i]);
1651 dither = (list[i] & CR_ALT_FILTER) != 0;
1652
1653 range_code = ni_gainlkup[board->gainlkup][range];
1654 devpriv->ai_offset[i] = 0;
1655 switch (aref) {
1656 case AREF_DIFF:
1657 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1658 break;
1659 case AREF_COMMON:
1660 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1661 break;
1662 case AREF_GROUND:
1663 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1664 break;
1665 case AREF_OTHER:
1666 break;
1667 }
1668 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1669 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1670 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1671 if (i == n_chan - 1)
1672 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1673 if (dither)
1674 config_bits |= NI_M_AI_CFG_DITHER;
1675 /* don't use 2's complement encoding */
1676 config_bits |= NI_M_AI_CFG_POLARITY;
1677 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1678 }
1679 ni_prime_channelgain_list(dev);
1680 }
1681
1682 /*
1683 * Notes on the 6110 and 6111:
1684 * These boards a slightly different than the rest of the series, since
1685 * they have multiple A/D converters.
1686 * From the driver side, the configuration memory is a
1687 * little different.
1688 * Configuration Memory Low:
1689 * bits 15-9: same
1690 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1691 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1692 * 1001 gain=0.1 (+/- 50)
1693 * 1010 0.2
1694 * 1011 0.1
1695 * 0001 1
1696 * 0010 2
1697 * 0011 5
1698 * 0100 10
1699 * 0101 20
1700 * 0110 50
1701 * Configuration Memory High:
1702 * bits 12-14: Channel Type
1703 * 001 for differential
1704 * 000 for calibration
1705 * bit 11: coupling (this is not currently handled)
1706 * 1 AC coupling
1707 * 0 DC coupling
1708 * bits 0-2: channel
1709 * valid channels are 0-3
1710 */
1711 static void ni_load_channelgain_list(struct comedi_device *dev,
1712 struct comedi_subdevice *s,
1713 unsigned int n_chan, unsigned int *list)
1714 {
1715 const struct ni_board_struct *board = dev->board_ptr;
1716 struct ni_private *devpriv = dev->private;
1717 unsigned int offset = (s->maxdata + 1) >> 1;
1718 unsigned int chan, range, aref;
1719 unsigned int i;
1720 unsigned int hi, lo;
1721 unsigned int dither;
1722
1723 if (devpriv->is_m_series) {
1724 ni_m_series_load_channelgain_list(dev, n_chan, list);
1725 return;
1726 }
1727 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1728 if (devpriv->changain_state &&
1729 devpriv->changain_spec == list[0]) {
1730 /* ready to go. */
1731 return;
1732 }
1733 devpriv->changain_state = 1;
1734 devpriv->changain_spec = list[0];
1735 } else {
1736 devpriv->changain_state = 0;
1737 }
1738
1739 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1740
1741 /* Set up Calibration mode if required */
1742 if (devpriv->is_6143) {
1743 if ((list[0] & CR_ALT_SOURCE) &&
1744 !devpriv->ai_calib_source_enabled) {
1745 /* Strobe Relay enable bit */
1746 ni_writew(dev, devpriv->ai_calib_source |
1747 NI6143_CALIB_CHAN_RELAY_ON,
1748 NI6143_CALIB_CHAN_REG);
1749 ni_writew(dev, devpriv->ai_calib_source,
1750 NI6143_CALIB_CHAN_REG);
1751 devpriv->ai_calib_source_enabled = 1;
1752 /* Allow relays to change */
1753 msleep_interruptible(100);
1754 } else if (!(list[0] & CR_ALT_SOURCE) &&
1755 devpriv->ai_calib_source_enabled) {
1756 /* Strobe Relay disable bit */
1757 ni_writew(dev, devpriv->ai_calib_source |
1758 NI6143_CALIB_CHAN_RELAY_OFF,
1759 NI6143_CALIB_CHAN_REG);
1760 ni_writew(dev, devpriv->ai_calib_source,
1761 NI6143_CALIB_CHAN_REG);
1762 devpriv->ai_calib_source_enabled = 0;
1763 /* Allow relays to change */
1764 msleep_interruptible(100);
1765 }
1766 }
1767
1768 for (i = 0; i < n_chan; i++) {
1769 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1770 chan = devpriv->ai_calib_source;
1771 else
1772 chan = CR_CHAN(list[i]);
1773 aref = CR_AREF(list[i]);
1774 range = CR_RANGE(list[i]);
1775 dither = (list[i] & CR_ALT_FILTER) != 0;
1776
1777 /* fix the external/internal range differences */
1778 range = ni_gainlkup[board->gainlkup][range];
1779 if (devpriv->is_611x)
1780 devpriv->ai_offset[i] = offset;
1781 else
1782 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1783
1784 hi = 0;
1785 if ((list[i] & CR_ALT_SOURCE)) {
1786 if (devpriv->is_611x)
1787 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1788 NI611X_CALIB_CHAN_SEL_REG);
1789 } else {
1790 if (devpriv->is_611x)
1791 aref = AREF_DIFF;
1792 else if (devpriv->is_6143)
1793 aref = AREF_OTHER;
1794 switch (aref) {
1795 case AREF_DIFF:
1796 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1797 break;
1798 case AREF_COMMON:
1799 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1800 break;
1801 case AREF_GROUND:
1802 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1803 break;
1804 case AREF_OTHER:
1805 break;
1806 }
1807 }
1808 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1809
1810 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1811
1812 if (!devpriv->is_6143) {
1813 lo = NI_E_AI_CFG_LO_GAIN(range);
1814
1815 if (i == n_chan - 1)
1816 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1817 if (dither)
1818 lo |= NI_E_AI_CFG_LO_DITHER;
1819
1820 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1821 }
1822 }
1823
1824 /* prime the channel/gain list */
1825 if (!devpriv->is_611x && !devpriv->is_6143)
1826 ni_prime_channelgain_list(dev);
1827 }
1828
1829 static int ni_ai_insn_read(struct comedi_device *dev,
1830 struct comedi_subdevice *s,
1831 struct comedi_insn *insn,
1832 unsigned int *data)
1833 {
1834 struct ni_private *devpriv = dev->private;
1835 unsigned int mask = s->maxdata;
1836 int i, n;
1837 unsigned int signbits;
1838 unsigned int d;
1839
1840 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1841
1842 ni_clear_ai_fifo(dev);
1843
1844 signbits = devpriv->ai_offset[0];
1845 if (devpriv->is_611x) {
1846 for (n = 0; n < num_adc_stages_611x; n++) {
1847 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1848 NISTC_AI_CMD1_REG);
1849 udelay(1);
1850 }
1851 for (n = 0; n < insn->n; n++) {
1852 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1853 NISTC_AI_CMD1_REG);
1854 /* The 611x has screwy 32-bit FIFOs. */
1855 d = 0;
1856 for (i = 0; i < NI_TIMEOUT; i++) {
1857 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1858 d = ni_readl(dev,
1859 NI611X_AI_FIFO_DATA_REG);
1860 d >>= 16;
1861 d &= 0xffff;
1862 break;
1863 }
1864 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1865 NISTC_AI_STATUS1_FIFO_E)) {
1866 d = ni_readl(dev,
1867 NI611X_AI_FIFO_DATA_REG);
1868 d &= 0xffff;
1869 break;
1870 }
1871 }
1872 if (i == NI_TIMEOUT) {
1873 dev_err(dev->class_dev, "timeout\n");
1874 return -ETIME;
1875 }
1876 d += signbits;
1877 data[n] = d & 0xffff;
1878 }
1879 } else if (devpriv->is_6143) {
1880 for (n = 0; n < insn->n; n++) {
1881 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1882 NISTC_AI_CMD1_REG);
1883
1884 /*
1885 * The 6143 has 32-bit FIFOs. You need to strobe a
1886 * bit to move a single 16bit stranded sample into
1887 * the FIFO.
1888 */
1889 d = 0;
1890 for (i = 0; i < NI_TIMEOUT; i++) {
1891 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1892 0x01) {
1893 /* Get stranded sample into FIFO */
1894 ni_writel(dev, 0x01,
1895 NI6143_AI_FIFO_CTRL_REG);
1896 d = ni_readl(dev,
1897 NI6143_AI_FIFO_DATA_REG);
1898 break;
1899 }
1900 }
1901 if (i == NI_TIMEOUT) {
1902 dev_err(dev->class_dev, "timeout\n");
1903 return -ETIME;
1904 }
1905 data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1906 }
1907 } else {
1908 for (n = 0; n < insn->n; n++) {
1909 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1910 NISTC_AI_CMD1_REG);
1911 for (i = 0; i < NI_TIMEOUT; i++) {
1912 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1913 NISTC_AI_STATUS1_FIFO_E))
1914 break;
1915 }
1916 if (i == NI_TIMEOUT) {
1917 dev_err(dev->class_dev, "timeout\n");
1918 return -ETIME;
1919 }
1920 if (devpriv->is_m_series) {
1921 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1922 d &= mask;
1923 data[n] = d;
1924 } else {
1925 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1926 d += signbits;
1927 data[n] = d & 0xffff;
1928 }
1929 }
1930 }
1931 return insn->n;
1932 }
1933
1934 static int ni_ns_to_timer(const struct comedi_device *dev,
1935 unsigned int nanosec, unsigned int flags)
1936 {
1937 struct ni_private *devpriv = dev->private;
1938 int divider;
1939
1940 switch (flags & CMDF_ROUND_MASK) {
1941 case CMDF_ROUND_NEAREST:
1942 default:
1943 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1944 break;
1945 case CMDF_ROUND_DOWN:
1946 divider = (nanosec) / devpriv->clock_ns;
1947 break;
1948 case CMDF_ROUND_UP:
1949 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1950 break;
1951 }
1952 return divider - 1;
1953 }
1954
1955 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1956 {
1957 struct ni_private *devpriv = dev->private;
1958
1959 return devpriv->clock_ns * (timer + 1);
1960 }
1961
1962 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1963 struct comedi_subdevice *sdev,
1964 const struct comedi_cmd *cmd,
1965 unsigned int max_count) {
1966 #ifdef PCIDMA
1967 unsigned int nbytes = max_count;
1968
1969 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1970 nbytes = cmd->stop_arg;
1971 nbytes *= comedi_bytes_per_scan(sdev);
1972
1973 if (nbytes > sdev->async->prealloc_bufsz) {
1974 if (cmd->stop_arg > 0)
1975 dev_err(sdev->device->class_dev,
1976 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
1977
1978 /*
1979 * we can only transfer up to the size of the buffer. In this
1980 * case, the user is expected to continue to write into the
1981 * comedi buffer (already implemented as a ring buffer).
1982 */
1983 nbytes = sdev->async->prealloc_bufsz;
1984 }
1985
1986 mite_init_ring_descriptors(ring, sdev, nbytes);
1987 #else
1988 dev_err(sdev->device->class_dev,
1989 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
1990 #endif
1991 }
1992
1993 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1994 unsigned int num_channels)
1995 {
1996 const struct ni_board_struct *board = dev->board_ptr;
1997 struct ni_private *devpriv = dev->private;
1998
1999 /* simultaneously-sampled inputs */
2000 if (devpriv->is_611x || devpriv->is_6143)
2001 return board->ai_speed;
2002
2003 /* multiplexed inputs */
2004 return board->ai_speed * num_channels;
2005 }
2006
2007 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2008 struct comedi_cmd *cmd)
2009 {
2010 const struct ni_board_struct *board = dev->board_ptr;
2011 struct ni_private *devpriv = dev->private;
2012 int err = 0;
2013 unsigned int tmp;
2014 unsigned int sources;
2015
2016 /* Step 1 : check if triggers are trivially valid */
2017
2018 err |= comedi_check_trigger_src(&cmd->start_src,
2019 TRIG_NOW | TRIG_INT | TRIG_EXT);
2020 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2021 TRIG_TIMER | TRIG_EXT);
2022
2023 sources = TRIG_TIMER | TRIG_EXT;
2024 if (devpriv->is_611x || devpriv->is_6143)
2025 sources |= TRIG_NOW;
2026 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2027
2028 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2029 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2030
2031 if (err)
2032 return 1;
2033
2034 /* Step 2a : make sure trigger sources are unique */
2035
2036 err |= comedi_check_trigger_is_unique(cmd->start_src);
2037 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2038 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2039 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2040
2041 /* Step 2b : and mutually compatible */
2042
2043 if (err)
2044 return 2;
2045
2046 /* Step 3: check if arguments are trivially valid */
2047
2048 switch (cmd->start_src) {
2049 case TRIG_NOW:
2050 case TRIG_INT:
2051 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2052 break;
2053 case TRIG_EXT:
2054 tmp = CR_CHAN(cmd->start_arg);
2055
2056 if (tmp > 16)
2057 tmp = 16;
2058 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2059 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2060 break;
2061 }
2062
2063 if (cmd->scan_begin_src == TRIG_TIMER) {
2064 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2065 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2066 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2067 devpriv->clock_ns *
2068 0xffffff);
2069 } else if (cmd->scan_begin_src == TRIG_EXT) {
2070 /* external trigger */
2071 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2072
2073 if (tmp > 16)
2074 tmp = 16;
2075 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2076 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2077 } else { /* TRIG_OTHER */
2078 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2079 }
2080
2081 if (cmd->convert_src == TRIG_TIMER) {
2082 if (devpriv->is_611x || devpriv->is_6143) {
2083 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2084 0);
2085 } else {
2086 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2087 board->ai_speed);
2088 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2089 devpriv->clock_ns *
2090 0xffff);
2091 }
2092 } else if (cmd->convert_src == TRIG_EXT) {
2093 /* external trigger */
2094 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2095
2096 if (tmp > 16)
2097 tmp = 16;
2098 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2099 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2100 } else if (cmd->convert_src == TRIG_NOW) {
2101 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2102 }
2103
2104 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2105 cmd->chanlist_len);
2106
2107 if (cmd->stop_src == TRIG_COUNT) {
2108 unsigned int max_count = 0x01000000;
2109
2110 if (devpriv->is_611x)
2111 max_count -= num_adc_stages_611x;
2112 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2113 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2114 } else {
2115 /* TRIG_NONE */
2116 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2117 }
2118
2119 if (err)
2120 return 3;
2121
2122 /* step 4: fix up any arguments */
2123
2124 if (cmd->scan_begin_src == TRIG_TIMER) {
2125 tmp = cmd->scan_begin_arg;
2126 cmd->scan_begin_arg =
2127 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2128 cmd->scan_begin_arg,
2129 cmd->flags));
2130 if (tmp != cmd->scan_begin_arg)
2131 err++;
2132 }
2133 if (cmd->convert_src == TRIG_TIMER) {
2134 if (!devpriv->is_611x && !devpriv->is_6143) {
2135 tmp = cmd->convert_arg;
2136 cmd->convert_arg =
2137 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2138 cmd->convert_arg,
2139 cmd->flags));
2140 if (tmp != cmd->convert_arg)
2141 err++;
2142 if (cmd->scan_begin_src == TRIG_TIMER &&
2143 cmd->scan_begin_arg <
2144 cmd->convert_arg * cmd->scan_end_arg) {
2145 cmd->scan_begin_arg =
2146 cmd->convert_arg * cmd->scan_end_arg;
2147 err++;
2148 }
2149 }
2150 }
2151
2152 if (err)
2153 return 4;
2154
2155 return 0;
2156 }
2157
2158 static int ni_ai_inttrig(struct comedi_device *dev,
2159 struct comedi_subdevice *s,
2160 unsigned int trig_num)
2161 {
2162 struct ni_private *devpriv = dev->private;
2163 struct comedi_cmd *cmd = &s->async->cmd;
2164
2165 if (trig_num != cmd->start_arg)
2166 return -EINVAL;
2167
2168 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2169 NISTC_AI_CMD2_REG);
2170 s->async->inttrig = NULL;
2171
2172 return 1;
2173 }
2174
2175 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2176 {
2177 struct ni_private *devpriv = dev->private;
2178 const struct comedi_cmd *cmd = &s->async->cmd;
2179 int timer;
2180 int mode1 = 0; /* mode1 is needed for both stop and convert */
2181 int mode2 = 0;
2182 int start_stop_select = 0;
2183 unsigned int stop_count;
2184 int interrupt_a_enable = 0;
2185 unsigned int ai_trig;
2186
2187 if (dev->irq == 0) {
2188 dev_err(dev->class_dev, "cannot run command without an irq\n");
2189 return -EIO;
2190 }
2191 ni_clear_ai_fifo(dev);
2192
2193 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2194
2195 /* start configuration */
2196 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2197
2198 /*
2199 * Disable analog triggering for now, since it interferes
2200 * with the use of pfi0.
2201 */
2202 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2203 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2204
2205 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2206 switch (cmd->start_src) {
2207 case TRIG_INT:
2208 case TRIG_NOW:
2209 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2210 NISTC_AI_TRIG_START1_SEL(0);
2211 break;
2212 case TRIG_EXT:
2213 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2214 1);
2215
2216 if (cmd->start_arg & CR_INVERT)
2217 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2218 if (cmd->start_arg & CR_EDGE)
2219 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2220 break;
2221 }
2222 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2223
2224 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2225 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2226 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2227 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2228
2229 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2230 /* logic low */
2231 start_stop_select |= NISTC_AI_STOP_POLARITY |
2232 NISTC_AI_STOP_SEL(31) |
2233 NISTC_AI_STOP_SYNC;
2234 } else {
2235 /* ai configuration memory */
2236 start_stop_select |= NISTC_AI_STOP_SEL(19);
2237 }
2238 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2239
2240 devpriv->ai_cmd2 = 0;
2241 switch (cmd->stop_src) {
2242 case TRIG_COUNT:
2243 stop_count = cmd->stop_arg - 1;
2244
2245 if (devpriv->is_611x) {
2246 /* have to take 3 stage adc pipeline into account */
2247 stop_count += num_adc_stages_611x;
2248 }
2249 /* stage number of scans */
2250 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2251
2252 mode1 |= NISTC_AI_MODE1_START_STOP |
2253 NISTC_AI_MODE1_RSVD |
2254 NISTC_AI_MODE1_TRIGGER_ONCE;
2255 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2256 /* load SC (Scan Count) */
2257 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2258
2259 if (stop_count == 0) {
2260 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2261 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2262 /*
2263 * This is required to get the last sample for
2264 * chanlist_len > 1, not sure why.
2265 */
2266 if (cmd->chanlist_len > 1)
2267 start_stop_select |= NISTC_AI_STOP_POLARITY |
2268 NISTC_AI_STOP_EDGE;
2269 }
2270 break;
2271 case TRIG_NONE:
2272 /* stage number of scans */
2273 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2274
2275 mode1 |= NISTC_AI_MODE1_START_STOP |
2276 NISTC_AI_MODE1_RSVD |
2277 NISTC_AI_MODE1_CONTINUOUS;
2278 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2279
2280 /* load SC (Scan Count) */
2281 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2282 break;
2283 }
2284
2285 switch (cmd->scan_begin_src) {
2286 case TRIG_TIMER:
2287 /*
2288 * stop bits for non 611x boards
2289 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2290 * NISTC_AI_MODE2_PRE_TRIGGER=0
2291 * NISTC_AI_START_STOP_REG:
2292 * NISTC_AI_START_POLARITY=0 (?) rising edge
2293 * NISTC_AI_START_EDGE=1 edge triggered
2294 * NISTC_AI_START_SYNC=1 (?)
2295 * NISTC_AI_START_SEL=0 SI_TC
2296 * NISTC_AI_STOP_POLARITY=0 rising edge
2297 * NISTC_AI_STOP_EDGE=0 level
2298 * NISTC_AI_STOP_SYNC=1
2299 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2300 */
2301 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2302 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2303
2304 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2305 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2306 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2307 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2308
2309 /* load SI */
2310 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2311 CMDF_ROUND_NEAREST);
2312 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2313 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2314 break;
2315 case TRIG_EXT:
2316 if (cmd->scan_begin_arg & CR_EDGE)
2317 start_stop_select |= NISTC_AI_START_EDGE;
2318 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2319 start_stop_select |= NISTC_AI_START_POLARITY;
2320 if (cmd->scan_begin_src != cmd->convert_src ||
2321 (cmd->scan_begin_arg & ~CR_EDGE) !=
2322 (cmd->convert_arg & ~CR_EDGE))
2323 start_stop_select |= NISTC_AI_START_SYNC;
2324 start_stop_select |=
2325 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2326 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2327 break;
2328 }
2329
2330 switch (cmd->convert_src) {
2331 case TRIG_TIMER:
2332 case TRIG_NOW:
2333 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2334 timer = 1;
2335 else
2336 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2337 CMDF_ROUND_NEAREST);
2338 /* 0,0 does not work */
2339 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2340 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2341
2342 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2343 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2344 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2345
2346 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2347
2348 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2349 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2350 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2351 break;
2352 case TRIG_EXT:
2353 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2354 CR_CHAN(cmd->convert_arg));
2355 if ((cmd->convert_arg & CR_INVERT) == 0)
2356 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2357 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2358
2359 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2360 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2361 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2362
2363 break;
2364 }
2365
2366 if (dev->irq) {
2367 /* interrupt on FIFO, errors, SC_TC */
2368 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2369 NISTC_INTA_ENA_AI_SC_TC;
2370
2371 #ifndef PCIDMA
2372 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2373 #endif
2374
2375 if ((cmd->flags & CMDF_WAKE_EOS) ||
2376 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2377 /* wake on end-of-scan */
2378 devpriv->aimode = AIMODE_SCAN;
2379 } else {
2380 devpriv->aimode = AIMODE_HALF_FULL;
2381 }
2382
2383 switch (devpriv->aimode) {
2384 case AIMODE_HALF_FULL:
2385 /* FIFO interrupts and DMA requests on half-full */
2386 #ifdef PCIDMA
2387 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2388 NISTC_AI_MODE3_REG);
2389 #else
2390 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2391 NISTC_AI_MODE3_REG);
2392 #endif
2393 break;
2394 case AIMODE_SAMPLE:
2395 /*generate FIFO interrupts on non-empty */
2396 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2397 NISTC_AI_MODE3_REG);
2398 break;
2399 case AIMODE_SCAN:
2400 #ifdef PCIDMA
2401 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2402 NISTC_AI_MODE3_REG);
2403 #else
2404 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2405 NISTC_AI_MODE3_REG);
2406 #endif
2407 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2408 break;
2409 default:
2410 break;
2411 }
2412
2413 /* clear interrupts */
2414 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2415
2416 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2417 } else {
2418 /* interrupt on nothing */
2419 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2420
2421 /* XXX start polling if necessary */
2422 }
2423
2424 /* end configuration */
2425 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2426
2427 switch (cmd->scan_begin_src) {
2428 case TRIG_TIMER:
2429 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2430 NISTC_AI_CMD1_SI_ARM |
2431 NISTC_AI_CMD1_DIV_ARM |
2432 NISTC_AI_CMD1_SC_ARM,
2433 NISTC_AI_CMD1_REG);
2434 break;
2435 case TRIG_EXT:
2436 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2437 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2438 NISTC_AI_CMD1_DIV_ARM |
2439 NISTC_AI_CMD1_SC_ARM,
2440 NISTC_AI_CMD1_REG);
2441 break;
2442 }
2443
2444 #ifdef PCIDMA
2445 {
2446 int retval = ni_ai_setup_MITE_dma(dev);
2447
2448 if (retval)
2449 return retval;
2450 }
2451 #endif
2452
2453 if (cmd->start_src == TRIG_NOW) {
2454 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2455 devpriv->ai_cmd2,
2456 NISTC_AI_CMD2_REG);
2457 s->async->inttrig = NULL;
2458 } else if (cmd->start_src == TRIG_EXT) {
2459 s->async->inttrig = NULL;
2460 } else { /* TRIG_INT */
2461 s->async->inttrig = ni_ai_inttrig;
2462 }
2463
2464 return 0;
2465 }
2466
2467 static int ni_ai_insn_config(struct comedi_device *dev,
2468 struct comedi_subdevice *s,
2469 struct comedi_insn *insn, unsigned int *data)
2470 {
2471 struct ni_private *devpriv = dev->private;
2472
2473 if (insn->n < 1)
2474 return -EINVAL;
2475
2476 switch (data[0]) {
2477 case INSN_CONFIG_ALT_SOURCE:
2478 if (devpriv->is_m_series) {
2479 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2480 return -EINVAL;
2481 devpriv->ai_calib_source = data[1];
2482 } else if (devpriv->is_6143) {
2483 unsigned int calib_source;
2484
2485 calib_source = data[1] & 0xf;
2486
2487 devpriv->ai_calib_source = calib_source;
2488 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2489 } else {
2490 unsigned int calib_source;
2491 unsigned int calib_source_adjust;
2492
2493 calib_source = data[1] & 0xf;
2494 calib_source_adjust = (data[1] >> 4) & 0xff;
2495
2496 if (calib_source >= 8)
2497 return -EINVAL;
2498 devpriv->ai_calib_source = calib_source;
2499 if (devpriv->is_611x) {
2500 ni_writeb(dev, calib_source_adjust,
2501 NI611X_CAL_GAIN_SEL_REG);
2502 }
2503 }
2504 return 2;
2505 default:
2506 break;
2507 }
2508
2509 return -EINVAL;
2510 }
2511
2512 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2513 void *data, unsigned int num_bytes,
2514 unsigned int chan_index)
2515 {
2516 struct comedi_cmd *cmd = &s->async->cmd;
2517 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2518 unsigned short *array = data;
2519 unsigned int i;
2520 #ifdef PCIDMA
2521 __le16 buf, *barray = data;
2522 #endif
2523
2524 for (i = 0; i < nsamples; i++) {
2525 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2526 unsigned short val = array[i];
2527
2528 /*
2529 * Munge data from unsigned to two's complement for
2530 * bipolar ranges.
2531 */
2532 if (comedi_range_is_bipolar(s, range))
2533 val = comedi_offset_munge(s, val);
2534 #ifdef PCIDMA
2535 buf = cpu_to_le16(val);
2536 barray[i] = buf;
2537 #else
2538 array[i] = val;
2539 #endif
2540 chan_index++;
2541 chan_index %= cmd->chanlist_len;
2542 }
2543 }
2544
2545 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2546 struct comedi_subdevice *s,
2547 unsigned int chanspec[],
2548 unsigned int n_chans, int timed)
2549 {
2550 struct ni_private *devpriv = dev->private;
2551 unsigned int range;
2552 unsigned int chan;
2553 unsigned int conf;
2554 int i;
2555 int invert = 0;
2556
2557 if (timed) {
2558 for (i = 0; i < s->n_chan; ++i) {
2559 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2560 ni_writeb(dev, devpriv->ao_conf[i],
2561 NI_M_AO_CFG_BANK_REG(i));
2562 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2563 }
2564 }
2565 for (i = 0; i < n_chans; i++) {
2566 const struct comedi_krange *krange;
2567
2568 chan = CR_CHAN(chanspec[i]);
2569 range = CR_RANGE(chanspec[i]);
2570 krange = s->range_table->range + range;
2571 invert = 0;
2572 conf = 0;
2573 switch (krange->max - krange->min) {
2574 case 20000000:
2575 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2576 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2577 break;
2578 case 10000000:
2579 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2580 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2581 break;
2582 case 4000000:
2583 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2584 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2585 NI_M_AO_REF_ATTENUATION_REG(chan));
2586 break;
2587 case 2000000:
2588 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2589 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2590 NI_M_AO_REF_ATTENUATION_REG(chan));
2591 break;
2592 default:
2593 dev_err(dev->class_dev,
2594 "bug! unhandled ao reference voltage\n");
2595 break;
2596 }
2597 switch (krange->max + krange->min) {
2598 case 0:
2599 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2600 break;
2601 case 10000000:
2602 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2603 break;
2604 default:
2605 dev_err(dev->class_dev,
2606 "bug! unhandled ao offset voltage\n");
2607 break;
2608 }
2609 if (timed)
2610 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2611 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2612 devpriv->ao_conf[chan] = conf;
2613 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2614 }
2615 return invert;
2616 }
2617
2618 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2619 struct comedi_subdevice *s,
2620 unsigned int chanspec[],
2621 unsigned int n_chans)
2622 {
2623 struct ni_private *devpriv = dev->private;
2624 unsigned int range;
2625 unsigned int chan;
2626 unsigned int conf;
2627 int i;
2628 int invert = 0;
2629
2630 for (i = 0; i < n_chans; i++) {
2631 chan = CR_CHAN(chanspec[i]);
2632 range = CR_RANGE(chanspec[i]);
2633 conf = NI_E_AO_DACSEL(chan);
2634
2635 if (comedi_range_is_bipolar(s, range)) {
2636 conf |= NI_E_AO_CFG_BIP;
2637 invert = (s->maxdata + 1) >> 1;
2638 } else {
2639 invert = 0;
2640 }
2641 if (comedi_range_is_external(s, range))
2642 conf |= NI_E_AO_EXT_REF;
2643
2644 /* not all boards can deglitch, but this shouldn't hurt */
2645 if (chanspec[i] & CR_DEGLITCH)
2646 conf |= NI_E_AO_DEGLITCH;
2647
2648 /* analog reference */
2649 /* AREF_OTHER connects AO ground to AI ground, i think */
2650 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2651 conf |= NI_E_AO_GROUND_REF;
2652
2653 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2654 devpriv->ao_conf[chan] = conf;
2655 }
2656 return invert;
2657 }
2658
2659 static int ni_ao_config_chanlist(struct comedi_device *dev,
2660 struct comedi_subdevice *s,
2661 unsigned int chanspec[], unsigned int n_chans,
2662 int timed)
2663 {
2664 struct ni_private *devpriv = dev->private;
2665
2666 if (devpriv->is_m_series)
2667 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2668 timed);
2669 else
2670 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2671 }
2672
2673 static int ni_ao_insn_write(struct comedi_device *dev,
2674 struct comedi_subdevice *s,
2675 struct comedi_insn *insn,
2676 unsigned int *data)
2677 {
2678 struct ni_private *devpriv = dev->private;
2679 unsigned int chan = CR_CHAN(insn->chanspec);
2680 unsigned int range = CR_RANGE(insn->chanspec);
2681 int reg;
2682 int i;
2683
2684 if (devpriv->is_6xxx) {
2685 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2686
2687 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2688 } else if (devpriv->is_m_series) {
2689 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2690 } else {
2691 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2692 }
2693
2694 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2695
2696 for (i = 0; i < insn->n; i++) {
2697 unsigned int val = data[i];
2698
2699 s->readback[chan] = val;
2700
2701 if (devpriv->is_6xxx) {
2702 /*
2703 * 6xxx boards have bipolar outputs, munge the
2704 * unsigned comedi values to 2's complement
2705 */
2706 val = comedi_offset_munge(s, val);
2707
2708 ni_ao_win_outw(dev, val, reg);
2709 } else if (devpriv->is_m_series) {
2710 /*
2711 * M-series boards use offset binary values for
2712 * bipolar and uinpolar outputs
2713 */
2714 ni_writew(dev, val, reg);
2715 } else {
2716 /*
2717 * Non-M series boards need two's complement values
2718 * for bipolar ranges.
2719 */
2720 if (comedi_range_is_bipolar(s, range))
2721 val = comedi_offset_munge(s, val);
2722
2723 ni_writew(dev, val, reg);
2724 }
2725 }
2726
2727 return insn->n;
2728 }
2729
2730 /*
2731 * Arms the AO device in preparation for a trigger event.
2732 * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2733 * not used). As a part of this preparation, this function preloads the DAC
2734 * registers with the first values of the output stream. This ensures that the
2735 * first clock cycle after the trigger can be used for output.
2736 *
2737 * Note that this function _must_ happen after a user has written data to the
2738 * output buffers via either mmap or write(fileno,...).
2739 */
2740 static int ni_ao_arm(struct comedi_device *dev,
2741 struct comedi_subdevice *s)
2742 {
2743 struct ni_private *devpriv = dev->private;
2744 int ret;
2745 int interrupt_b_bits;
2746 int i;
2747 static const int timeout = 1000;
2748
2749 /*
2750 * Prevent ao from doing things like trying to allocate the ao dma
2751 * channel multiple times.
2752 */
2753 if (!devpriv->ao_needs_arming) {
2754 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2755 __func__);
2756 return -EINVAL;
2757 }
2758
2759 devpriv->ao_needs_arming = 0;
2760
2761 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2762 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2763 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2764 #ifdef PCIDMA
2765 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2766 if (devpriv->is_6xxx)
2767 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2768 ret = ni_ao_setup_MITE_dma(dev);
2769 if (ret)
2770 return ret;
2771 ret = ni_ao_wait_for_dma_load(dev);
2772 if (ret < 0)
2773 return ret;
2774 #else
2775 ret = ni_ao_prep_fifo(dev, s);
2776 if (ret == 0)
2777 return -EPIPE;
2778
2779 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2780 #endif
2781
2782 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2783 NISTC_AO_MODE3_REG);
2784 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2785 /* wait for DACs to be loaded */
2786 for (i = 0; i < timeout; i++) {
2787 udelay(1);
2788 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2789 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2790 break;
2791 }
2792 if (i == timeout) {
2793 dev_err(dev->class_dev,
2794 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2795 return -EIO;
2796 }
2797 /*
2798 * stc manual says we are need to clear error interrupt after
2799 * AO_TMRDACWRs_In_Progress_St clears
2800 */
2801 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2802
2803 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2804
2805 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2806 NISTC_AO_CMD1_UC_ARM |
2807 NISTC_AO_CMD1_BC_ARM |
2808 devpriv->ao_cmd1,
2809 NISTC_AO_CMD1_REG);
2810
2811 return 0;
2812 }
2813
2814 static int ni_ao_insn_config(struct comedi_device *dev,
2815 struct comedi_subdevice *s,
2816 struct comedi_insn *insn, unsigned int *data)
2817 {
2818 const struct ni_board_struct *board = dev->board_ptr;
2819 struct ni_private *devpriv = dev->private;
2820 unsigned int nbytes;
2821
2822 switch (data[0]) {
2823 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2824 switch (data[1]) {
2825 case COMEDI_OUTPUT:
2826 nbytes = comedi_samples_to_bytes(s,
2827 board->ao_fifo_depth);
2828 data[2] = 1 + nbytes;
2829 if (devpriv->mite)
2830 data[2] += devpriv->mite->fifo_size;
2831 break;
2832 case COMEDI_INPUT:
2833 data[2] = 0;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838 return 0;
2839 case INSN_CONFIG_ARM:
2840 return ni_ao_arm(dev, s);
2841 default:
2842 break;
2843 }
2844
2845 return -EINVAL;
2846 }
2847
2848 static int ni_ao_inttrig(struct comedi_device *dev,
2849 struct comedi_subdevice *s,
2850 unsigned int trig_num)
2851 {
2852 struct ni_private *devpriv = dev->private;
2853 struct comedi_cmd *cmd = &s->async->cmd;
2854 int ret;
2855
2856 /*
2857 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2858 * For backwards compatibility, also allow trig_num == 0 when
2859 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2860 * in that case, the internal trigger is being used as a pre-trigger
2861 * before the external trigger.
2862 */
2863 if (!(trig_num == cmd->start_arg ||
2864 (trig_num == 0 && cmd->start_src != TRIG_INT)))
2865 return -EINVAL;
2866
2867 /*
2868 * Null trig at beginning prevent ao start trigger from executing more
2869 * than once per command.
2870 */
2871 s->async->inttrig = NULL;
2872
2873 if (devpriv->ao_needs_arming) {
2874 /* only arm this device if it still needs arming */
2875 ret = ni_ao_arm(dev, s);
2876 if (ret)
2877 return ret;
2878 }
2879
2880 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2881 NISTC_AO_CMD2_REG);
2882
2883 return 0;
2884 }
2885
2886 /*
2887 * begin ni_ao_cmd.
2888 * Organized similar to NI-STC and MHDDK examples.
2889 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2890 */
2891
2892 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2893 const struct comedi_cmd *cmd)
2894 {
2895 const struct ni_board_struct *board = dev->board_ptr;
2896 unsigned int bits;
2897
2898 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2899
2900 bits =
2901 /* fast CPU interface--only eseries */
2902 /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2903 NISTC_AO_PERSONAL_BC_SRC_SEL |
2904 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2905 /*
2906 * FIXME: start setting following bit when appropriate. Need to
2907 * determine whether board is E4 or E1.
2908 * FROM MHHDK:
2909 * if board is E4 or E1
2910 * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2911 * else
2912 * set it to 1
2913 */
2914 NISTC_AO_PERSONAL_UPDATE_PW |
2915 /* FIXME: when should we set following bit to zero? */
2916 NISTC_AO_PERSONAL_TMRDACWR_PW |
2917 (board->ao_fifo_depth ?
2918 NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2919 ;
2920 #if 0
2921 /*
2922 * FIXME:
2923 * add something like ".has_individual_dacs = 0" to ni_board_struct
2924 * since, as F Hess pointed out, not all in m series have singles. not
2925 * sure if e-series all have duals...
2926 */
2927
2928 /*
2929 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2930 * 6281, verified with bus analyzer.
2931 */
2932 if (devpriv->is_m_series)
2933 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2934 #endif
2935 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2936
2937 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2938 }
2939
2940 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2941 const struct comedi_cmd *cmd)
2942 {
2943 struct ni_private *devpriv = dev->private;
2944 unsigned int trigsel;
2945
2946 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2947
2948 /* sync */
2949 if (cmd->stop_src == TRIG_NONE) {
2950 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2951 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2952 } else {
2953 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2954 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2955 }
2956 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2957
2958 if (cmd->start_src == TRIG_INT) {
2959 trigsel = NISTC_AO_TRIG_START1_EDGE |
2960 NISTC_AO_TRIG_START1_SYNC;
2961 } else { /* TRIG_EXT */
2962 trigsel = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2963 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2964 if (cmd->start_arg & CR_INVERT)
2965 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2966 /* 0=edge detection disabled, 1=enabled */
2967 if (cmd->start_arg & CR_EDGE)
2968 trigsel |= NISTC_AO_TRIG_START1_EDGE;
2969 }
2970 ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2971
2972 /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2973
2974 /* sync */
2975 /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2976 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2977 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2978
2979 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2980 }
2981
2982 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2983 const struct comedi_cmd *cmd)
2984 {
2985 struct ni_private *devpriv = dev->private;
2986 /* Not supporting 'waveform staging' or 'local buffer with pauses' */
2987
2988 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2989 /*
2990 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
2991 * set_trigger above. It is unclear whether we really need to re-write
2992 * this register with these values. The mhddk examples for e-series
2993 * show writing this in both places, but the examples for m-series show
2994 * a single write in the set_counters function (here).
2995 */
2996 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2997
2998 /* sync (upload number of buffer iterations -1) */
2999 /* indicate that we want to use BC_Load_A_Register as the source */
3000 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3001 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3002
3003 /*
3004 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3005 * ignoring BC_TC, then we will need to find a way to ignore that
3006 * interrupt in continuous mode.
3007 */
3008 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3009
3010 /* sync (issue command to load number of buffer iterations -1) */
3011 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3012
3013 /* sync (upload number of updates in buffer) */
3014 /* indicate that we want to use UC_Load_A_Register as the source */
3015 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3016 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3017
3018 /*
3019 * if a user specifies '0', this automatically assumes the entire 24bit
3020 * address space is available for the (multiple iterations of single
3021 * buffer) MISB. Otherwise, stop_arg specifies the MISB length that
3022 * will be used, regardless of whether we are in continuous mode or not.
3023 * In continuous mode, the output will just iterate indefinitely over
3024 * the MISB.
3025 */
3026 {
3027 unsigned int stop_arg = cmd->stop_arg > 0 ?
3028 (cmd->stop_arg & 0xffffff) : 0xffffff;
3029
3030 if (devpriv->is_m_series) {
3031 /*
3032 * this is how the NI example code does it for m-series
3033 * boards, verified correct with 6259
3034 */
3035 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3036
3037 /* sync (issue cmd to load number of updates in MISB) */
3038 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3039 NISTC_AO_CMD1_REG);
3040 } else {
3041 ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3042
3043 /* sync (issue cmd to load number of updates in MISB) */
3044 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3045 NISTC_AO_CMD1_REG);
3046
3047 /*
3048 * sync (upload number of updates-1 in MISB)
3049 * --eseries only?
3050 */
3051 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3052 }
3053 }
3054
3055 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3056 }
3057
3058 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3059 const struct comedi_cmd *cmd)
3060 {
3061 struct ni_private *devpriv = dev->private;
3062
3063 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3064
3065 /*
3066 * zero out these bit fields to be set below. Does an ao-reset do this
3067 * automatically?
3068 */
3069 devpriv->ao_mode1 &= ~(
3070 NISTC_AO_MODE1_UI_SRC_MASK |
3071 NISTC_AO_MODE1_UI_SRC_POLARITY |
3072 NISTC_AO_MODE1_UPDATE_SRC_MASK |
3073 NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3074 );
3075
3076 if (cmd->scan_begin_src == TRIG_TIMER) {
3077 unsigned int trigvar;
3078
3079 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3080
3081 /*
3082 * NOTE: there are several other ways of configuring internal
3083 * updates, but we'll only support one for now: using
3084 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3085 * START1 and first update, and also w/o local buffer mode w/
3086 * pauses.
3087 */
3088
3089 /*
3090 * This is already done above:
3091 * devpriv->ao_mode1 &= ~(
3092 * // set UPDATE_Source to UI_TC:
3093 * NISTC_AO_MODE1_UPDATE_SRC_MASK |
3094 * // set UPDATE_Source_Polarity to rising (required?)
3095 * NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3096 * // set UI_Source to AO_IN_TIMEBASE1:
3097 * NISTC_AO_MODE1_UI_SRC_MASK |
3098 * // set UI_Source_Polarity to rising (required?)
3099 * NISTC_AO_MODE1_UI_SRC_POLARITY
3100 * );
3101 */
3102
3103 /*
3104 * TODO: use ao_ui_clock_source to allow all possible signals
3105 * to be routed to UI_Source_Select. See tSTC.h for
3106 * eseries/ni67xx and tMSeries.h for mseries.
3107 */
3108
3109 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3110 CMDF_ROUND_NEAREST);
3111
3112 /*
3113 * Wait N TB3 ticks after the start trigger before
3114 * clocking (N must be >=2).
3115 */
3116 /* following line: 2-1 per STC */
3117 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3118 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3119 /* following line: N-1 per STC */
3120 ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG);
3121 } else { /* TRIG_EXT */
3122 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
3123 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3124 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3125 CR_CHAN(cmd->scan_begin_arg));
3126 if (cmd->scan_begin_arg & CR_INVERT)
3127 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3128 }
3129
3130 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3131 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3132 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3133 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3134 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3135
3136 /* Configure DAQ-STC for Timed update mode */
3137 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3138 NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3139 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3140 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3141
3142 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3143 }
3144
3145 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3146 struct comedi_subdevice *s)
3147 {
3148 struct ni_private *devpriv = dev->private;
3149 const struct comedi_cmd *cmd = &s->async->cmd;
3150 unsigned int bits = 0;
3151
3152 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3153
3154 if (devpriv->is_6xxx) {
3155 unsigned int i;
3156
3157 bits = 0;
3158 for (i = 0; i < cmd->chanlist_len; ++i) {
3159 int chan = CR_CHAN(cmd->chanlist[i]);
3160
3161 bits |= 1 << chan;
3162 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3163 }
3164 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3165 }
3166
3167 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3168
3169 if (cmd->scan_end_arg > 1) {
3170 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3171 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3172 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3173
3174 } else {
3175 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3176 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3177 if (devpriv->is_m_series | devpriv->is_6xxx)
3178 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3179 else
3180 bits |= NISTC_AO_OUT_CTRL_CHANS(
3181 CR_CHAN(cmd->chanlist[0]));
3182 }
3183
3184 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3185 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3186
3187 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3188 }
3189
3190 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3191 const struct comedi_cmd *cmd)
3192 {
3193 struct ni_private *devpriv = dev->private;
3194
3195 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3196
3197 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3198 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3199
3200 /*
3201 * Since we are not supporting waveform staging, we ignore these errors:
3202 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3203 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3204 */
3205
3206 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3207 }
3208
3209 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3210 {
3211 struct ni_private *devpriv = dev->private;
3212
3213 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3214
3215 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3216 #ifdef PCIDMA
3217 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3218 #else
3219 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3220 #endif
3221 /* NOTE: this is where use_onboard_memory=True would be implemented */
3222 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3223 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3224
3225 /* enable sending of ao fifo requests (dma request) */
3226 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3227
3228 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3229
3230 /* we are not supporting boards with virtual fifos */
3231 }
3232
3233 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3234 struct comedi_subdevice *s)
3235 {
3236 if (s->async->cmd.stop_src == TRIG_COUNT)
3237 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3238 NISTC_INTB_ENA_AO_BC_TC, 1);
3239
3240 s->async->inttrig = ni_ao_inttrig;
3241 }
3242
3243 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3244 {
3245 struct ni_private *devpriv = dev->private;
3246 const struct comedi_cmd *cmd = &s->async->cmd;
3247
3248 if (dev->irq == 0) {
3249 dev_err(dev->class_dev, "cannot run command without an irq");
3250 return -EIO;
3251 }
3252
3253 /* ni_ao_reset should have already been done */
3254 ni_ao_cmd_personalize(dev, cmd);
3255 /* clearing fifo and preload happens elsewhere */
3256
3257 ni_ao_cmd_set_trigger(dev, cmd);
3258 ni_ao_cmd_set_counters(dev, cmd);
3259 ni_ao_cmd_set_update(dev, cmd);
3260 ni_ao_cmd_set_channels(dev, s);
3261 ni_ao_cmd_set_stop_conditions(dev, cmd);
3262 ni_ao_cmd_set_fifo_mode(dev);
3263 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3264 ni_ao_cmd_set_interrupts(dev, s);
3265
3266 /*
3267 * arm(ing) must happen later so that DMA can be setup and DACs
3268 * preloaded with the actual output buffer before starting.
3269 *
3270 * start(ing) must happen _after_ arming is completed. Starting can be
3271 * done either via ni_ao_inttrig, or via an external trigger.
3272 *
3273 * **Currently, ni_ao_inttrig will automatically attempt a call to
3274 * ni_ao_arm if the device still needs arming at that point. This
3275 * allows backwards compatibility.
3276 */
3277 devpriv->ao_needs_arming = 1;
3278 return 0;
3279 }
3280
3281 /* end ni_ao_cmd */
3282
3283 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3284 struct comedi_cmd *cmd)
3285 {
3286 const struct ni_board_struct *board = dev->board_ptr;
3287 struct ni_private *devpriv = dev->private;
3288 int err = 0;
3289 unsigned int tmp;
3290
3291 /* Step 1 : check if triggers are trivially valid */
3292
3293 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3294 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3295 TRIG_TIMER | TRIG_EXT);
3296 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3297 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3298 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3299
3300 if (err)
3301 return 1;
3302
3303 /* Step 2a : make sure trigger sources are unique */
3304
3305 err |= comedi_check_trigger_is_unique(cmd->start_src);
3306 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3307 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3308
3309 /* Step 2b : and mutually compatible */
3310
3311 if (err)
3312 return 2;
3313
3314 /* Step 3: check if arguments are trivially valid */
3315
3316 switch (cmd->start_src) {
3317 case TRIG_INT:
3318 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3319 break;
3320 case TRIG_EXT:
3321 tmp = CR_CHAN(cmd->start_arg);
3322
3323 if (tmp > 18)
3324 tmp = 18;
3325 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3326 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3327 break;
3328 }
3329
3330 if (cmd->scan_begin_src == TRIG_TIMER) {
3331 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3332 board->ao_speed);
3333 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3334 devpriv->clock_ns *
3335 0xffffff);
3336 }
3337
3338 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3339 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3340 cmd->chanlist_len);
3341 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3342
3343 if (err)
3344 return 3;
3345
3346 /* step 4: fix up any arguments */
3347 if (cmd->scan_begin_src == TRIG_TIMER) {
3348 tmp = cmd->scan_begin_arg;
3349 cmd->scan_begin_arg =
3350 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3351 cmd->scan_begin_arg,
3352 cmd->flags));
3353 if (tmp != cmd->scan_begin_arg)
3354 err++;
3355 }
3356 if (err)
3357 return 4;
3358
3359 return 0;
3360 }
3361
3362 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3363 {
3364 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3365
3366 /*
3367 * In the following, the "--sync" comments are meant to denote
3368 * asynchronous boundaries for setting the registers as described in the
3369 * DAQ-STC mostly in the order also described in the DAQ-STC.
3370 */
3371
3372 struct ni_private *devpriv = dev->private;
3373
3374 ni_release_ao_mite_channel(dev);
3375
3376 /* --sync (reset AO) */
3377 if (devpriv->is_m_series)
3378 /* following example in mhddk for m-series */
3379 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3380
3381 /*--sync (start config) */
3382 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3383
3384 /*--sync (Disarm) */
3385 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3386
3387 /*
3388 * --sync
3389 * (clear bunch of registers--mseries mhddk examples do not include
3390 * this)
3391 */
3392 devpriv->ao_cmd1 = 0;
3393 devpriv->ao_cmd2 = 0;
3394 devpriv->ao_mode1 = 0;
3395 devpriv->ao_mode2 = 0;
3396 if (devpriv->is_m_series)
3397 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3398 else
3399 devpriv->ao_mode3 = 0;
3400
3401 ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3402 ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3403 ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3404 ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3405 ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3406 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3407 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3408 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3409 ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3410
3411 /*--sync (disable interrupts) */
3412 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3413
3414 /*--sync (ack) */
3415 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3416 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3417
3418 /*--not in DAQ-STC. which doc? */
3419 if (devpriv->is_6xxx) {
3420 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3421 NI671X_AO_IMMEDIATE_REG);
3422 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3423 NI611X_AO_MISC_REG);
3424 }
3425 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3426 /*--end */
3427
3428 return 0;
3429 }
3430
3431 /* digital io */
3432
3433 static int ni_dio_insn_config(struct comedi_device *dev,
3434 struct comedi_subdevice *s,
3435 struct comedi_insn *insn,
3436 unsigned int *data)
3437 {
3438 struct ni_private *devpriv = dev->private;
3439 int ret;
3440
3441 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3442 if (ret)
3443 return ret;
3444
3445 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3446 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3447 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3448
3449 return insn->n;
3450 }
3451
3452 static int ni_dio_insn_bits(struct comedi_device *dev,
3453 struct comedi_subdevice *s,
3454 struct comedi_insn *insn,
3455 unsigned int *data)
3456 {
3457 struct ni_private *devpriv = dev->private;
3458
3459 /* Make sure we're not using the serial part of the dio */
3460 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3461 devpriv->serial_interval_ns)
3462 return -EBUSY;
3463
3464 if (comedi_dio_update_state(s, data)) {
3465 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3466 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3467 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3468 }
3469
3470 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3471
3472 return insn->n;
3473 }
3474
3475 #ifdef PCIDMA
3476 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3477 struct comedi_subdevice *s,
3478 struct comedi_insn *insn,
3479 unsigned int *data)
3480 {
3481 int ret;
3482
3483 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3484 if (ret)
3485 return ret;
3486
3487 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3488
3489 return insn->n;
3490 }
3491
3492 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3493 struct comedi_subdevice *s,
3494 struct comedi_insn *insn,
3495 unsigned int *data)
3496 {
3497 if (comedi_dio_update_state(s, data))
3498 ni_writel(dev, s->state, NI_M_DIO_REG);
3499
3500 data[1] = ni_readl(dev, NI_M_DIO_REG);
3501
3502 return insn->n;
3503 }
3504
3505 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3506 struct comedi_subdevice *s,
3507 struct comedi_cmd *cmd)
3508 {
3509 int i;
3510
3511 for (i = 0; i < cmd->chanlist_len; ++i) {
3512 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3513
3514 if (chan != i)
3515 return -EINVAL;
3516 }
3517
3518 return 0;
3519 }
3520
3521 static int ni_cdio_cmdtest(struct comedi_device *dev,
3522 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3523 {
3524 int err = 0;
3525 int tmp;
3526
3527 /* Step 1 : check if triggers are trivially valid */
3528
3529 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3530 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3531 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3532 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3533 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3534
3535 if (err)
3536 return 1;
3537
3538 /* Step 2a : make sure trigger sources are unique */
3539 /* Step 2b : and mutually compatible */
3540
3541 /* Step 3: check if arguments are trivially valid */
3542
3543 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3544
3545 tmp = cmd->scan_begin_arg;
3546 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3547 if (tmp != cmd->scan_begin_arg)
3548 err |= -EINVAL;
3549
3550 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3551 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3552 cmd->chanlist_len);
3553 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3554 s->async->prealloc_bufsz /
3555 comedi_bytes_per_scan(s));
3556
3557 if (err)
3558 return 3;
3559
3560 /* Step 4: fix up any arguments */
3561
3562 /* Step 5: check channel list if it exists */
3563
3564 if (cmd->chanlist && cmd->chanlist_len > 0)
3565 err |= ni_cdio_check_chanlist(dev, s, cmd);
3566
3567 if (err)
3568 return 5;
3569
3570 return 0;
3571 }
3572
3573 static int ni_cdo_inttrig(struct comedi_device *dev,
3574 struct comedi_subdevice *s,
3575 unsigned int trig_num)
3576 {
3577 struct comedi_cmd *cmd = &s->async->cmd;
3578 const unsigned int timeout = 1000;
3579 int retval = 0;
3580 unsigned int i;
3581 struct ni_private *devpriv = dev->private;
3582 unsigned long flags;
3583
3584 if (trig_num != cmd->start_arg)
3585 return -EINVAL;
3586
3587 s->async->inttrig = NULL;
3588
3589 /* read alloc the entire buffer */
3590 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3591
3592 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3593 if (devpriv->cdo_mite_chan) {
3594 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3595 mite_dma_arm(devpriv->cdo_mite_chan);
3596 } else {
3597 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3598 retval = -EIO;
3599 }
3600 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3601 if (retval < 0)
3602 return retval;
3603
3604 /*
3605 * XXX not sure what interrupt C group does
3606 * wait for dma to fill output fifo
3607 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3608 */
3609 for (i = 0; i < timeout; ++i) {
3610 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3611 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3612 break;
3613 usleep_range(10, 100);
3614 }
3615 if (i == timeout) {
3616 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3617 s->cancel(dev, s);
3618 return -EIO;
3619 }
3620 ni_writel(dev, NI_M_CDO_CMD_ARM |
3621 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3622 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3623 NI_M_CDIO_CMD_REG);
3624 return retval;
3625 }
3626
3627 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3628 {
3629 struct ni_private *devpriv = dev->private;
3630 const struct comedi_cmd *cmd = &s->async->cmd;
3631 unsigned int cdo_mode_bits;
3632 int retval;
3633
3634 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3635 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3636 NI_M_CDO_MODE_HALT_ON_ERROR |
3637 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3638 if (cmd->scan_begin_arg & CR_INVERT)
3639 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3640 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3641 if (s->io_bits) {
3642 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3643 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3644 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3645 } else {
3646 dev_err(dev->class_dev,
3647 "attempted to run digital output command with no lines configured as outputs\n");
3648 return -EIO;
3649 }
3650 retval = ni_request_cdo_mite_channel(dev);
3651 if (retval < 0)
3652 return retval;
3653
3654 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3655 s->async->prealloc_bufsz /
3656 comedi_bytes_per_scan(s));
3657
3658 s->async->inttrig = ni_cdo_inttrig;
3659
3660 return 0;
3661 }
3662
3663 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3664 {
3665 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3666 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3667 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3668 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3669 NI_M_CDIO_CMD_REG);
3670 /*
3671 * XXX not sure what interrupt C group does
3672 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3673 */
3674 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3675 ni_release_cdo_mite_channel(dev);
3676 return 0;
3677 }
3678
3679 static void handle_cdio_interrupt(struct comedi_device *dev)
3680 {
3681 struct ni_private *devpriv = dev->private;
3682 unsigned int cdio_status;
3683 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3684 unsigned long flags;
3685
3686 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3687 if (devpriv->cdo_mite_chan)
3688 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3689 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3690
3691 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3692 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3693 /* XXX just guessing this is needed and does something useful */
3694 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3695 NI_M_CDIO_CMD_REG);
3696 s->async->events |= COMEDI_CB_OVERFLOW;
3697 }
3698 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3699 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3700 NI_M_CDIO_CMD_REG);
3701 /* s->async->events |= COMEDI_CB_EOA; */
3702 }
3703 comedi_handle_events(dev, s);
3704 }
3705 #endif /* PCIDMA */
3706
3707 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3708 struct comedi_subdevice *s,
3709 unsigned char data_out,
3710 unsigned char *data_in)
3711 {
3712 struct ni_private *devpriv = dev->private;
3713 unsigned int status1;
3714 int err = 0, count = 20;
3715
3716 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3717 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3718 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3719
3720 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3721 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3722 err = -EBUSY;
3723 goto error;
3724 }
3725
3726 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3727 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3728 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3729
3730 /* Wait until STC says we're done, but don't loop infinitely. */
3731 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3732 NISTC_STATUS1_SERIO_IN_PROG) {
3733 /* Delay one bit per loop */
3734 udelay((devpriv->serial_interval_ns + 999) / 1000);
3735 if (--count < 0) {
3736 dev_err(dev->class_dev,
3737 "SPI serial I/O didn't finish in time!\n");
3738 err = -ETIME;
3739 goto error;
3740 }
3741 }
3742
3743 /*
3744 * Delay for last bit. This delay is absolutely necessary, because
3745 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3746 */
3747 udelay((devpriv->serial_interval_ns + 999) / 1000);
3748
3749 if (data_in)
3750 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3751
3752 error:
3753 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3754
3755 return err;
3756 }
3757
3758 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3759 struct comedi_subdevice *s,
3760 unsigned char data_out,
3761 unsigned char *data_in)
3762 {
3763 struct ni_private *devpriv = dev->private;
3764 unsigned char mask, input = 0;
3765
3766 /* Wait for one bit before transfer */
3767 udelay((devpriv->serial_interval_ns + 999) / 1000);
3768
3769 for (mask = 0x80; mask; mask >>= 1) {
3770 /*
3771 * Output current bit; note that we cannot touch s->state
3772 * because it is a per-subdevice field, and serial is
3773 * a separate subdevice from DIO.
3774 */
3775 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3776 if (data_out & mask)
3777 devpriv->dio_output |= NISTC_DIO_SDOUT;
3778 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3779
3780 /*
3781 * Assert SDCLK (active low, inverted), wait for half of
3782 * the delay, deassert SDCLK, and wait for the other half.
3783 */
3784 devpriv->dio_control |= NISTC_DIO_SDCLK;
3785 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3786
3787 udelay((devpriv->serial_interval_ns + 999) / 2000);
3788
3789 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3790 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3791
3792 udelay((devpriv->serial_interval_ns + 999) / 2000);
3793
3794 /* Input current bit */
3795 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3796 input |= mask;
3797 }
3798
3799 if (data_in)
3800 *data_in = input;
3801
3802 return 0;
3803 }
3804
3805 static int ni_serial_insn_config(struct comedi_device *dev,
3806 struct comedi_subdevice *s,
3807 struct comedi_insn *insn,
3808 unsigned int *data)
3809 {
3810 struct ni_private *devpriv = dev->private;
3811 unsigned int clk_fout = devpriv->clock_and_fout;
3812 int err = insn->n;
3813 unsigned char byte_out, byte_in = 0;
3814
3815 if (insn->n != 2)
3816 return -EINVAL;
3817
3818 switch (data[0]) {
3819 case INSN_CONFIG_SERIAL_CLOCK:
3820 devpriv->serial_hw_mode = 1;
3821 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3822
3823 if (data[1] == SERIAL_DISABLED) {
3824 devpriv->serial_hw_mode = 0;
3825 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3826 NISTC_DIO_SDCLK);
3827 data[1] = SERIAL_DISABLED;
3828 devpriv->serial_interval_ns = data[1];
3829 } else if (data[1] <= SERIAL_600NS) {
3830 /*
3831 * Warning: this clock speed is too fast to reliably
3832 * control SCXI.
3833 */
3834 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3835 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3836 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3837 data[1] = SERIAL_600NS;
3838 devpriv->serial_interval_ns = data[1];
3839 } else if (data[1] <= SERIAL_1_2US) {
3840 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3841 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3842 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3843 data[1] = SERIAL_1_2US;
3844 devpriv->serial_interval_ns = data[1];
3845 } else if (data[1] <= SERIAL_10US) {
3846 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3847 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3848 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3849 /*
3850 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3851 * 600ns/1.2us. If you turn divide_by_2 off with the
3852 * slow clock, you will still get 10us, except then
3853 * all your delays are wrong.
3854 */
3855 data[1] = SERIAL_10US;
3856 devpriv->serial_interval_ns = data[1];
3857 } else {
3858 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3859 NISTC_DIO_SDCLK);
3860 devpriv->serial_hw_mode = 0;
3861 data[1] = (data[1] / 1000) * 1000;
3862 devpriv->serial_interval_ns = data[1];
3863 }
3864 devpriv->clock_and_fout = clk_fout;
3865
3866 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3867 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3868 return 1;
3869
3870 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3871
3872 if (devpriv->serial_interval_ns == 0)
3873 return -EINVAL;
3874
3875 byte_out = data[1] & 0xFF;
3876
3877 if (devpriv->serial_hw_mode) {
3878 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3879 &byte_in);
3880 } else if (devpriv->serial_interval_ns > 0) {
3881 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3882 &byte_in);
3883 } else {
3884 dev_err(dev->class_dev, "serial disabled!\n");
3885 return -EINVAL;
3886 }
3887 if (err < 0)
3888 return err;
3889 data[1] = byte_in & 0xFF;
3890 return insn->n;
3891
3892 break;
3893 default:
3894 return -EINVAL;
3895 }
3896 }
3897
3898 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3899 {
3900 int i;
3901
3902 for (i = 0; i < s->n_chan; i++) {
3903 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3904 NI67XX_AO_CFG2_REG);
3905 }
3906 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3907 }
3908
3909 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3910 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3911 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3912 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3913 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3914 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3915 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3916 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3917 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3918 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3919 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3920 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3921 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3922 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3923 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3924 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3925 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3926 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3927 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3928 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3929 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3930 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3931 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3932 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3933 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3934 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3935 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3936 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3937 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3938 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3939 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3940 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3941 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3942 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3943 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3944 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3945 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3946 };
3947
3948 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3949 enum ni_gpct_register reg)
3950 {
3951 const struct mio_regmap *regmap;
3952
3953 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3954 regmap = &ni_gpct_to_stc_regmap[reg];
3955 } else {
3956 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3957 __func__, reg);
3958 return 0;
3959 }
3960
3961 return regmap->mio_reg;
3962 }
3963
3964 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
3965 enum ni_gpct_register reg)
3966 {
3967 struct comedi_device *dev = counter->counter_dev->dev;
3968 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3969
3970 if (stc_register == 0)
3971 return;
3972
3973 switch (reg) {
3974 /* m-series only registers */
3975 case NITIO_G0_CNT_MODE:
3976 case NITIO_G1_CNT_MODE:
3977 case NITIO_G0_GATE2:
3978 case NITIO_G1_GATE2:
3979 case NITIO_G0_DMA_CFG:
3980 case NITIO_G1_DMA_CFG:
3981 case NITIO_G0_ABZ:
3982 case NITIO_G1_ABZ:
3983 ni_writew(dev, bits, stc_register);
3984 break;
3985
3986 /* 32 bit registers */
3987 case NITIO_G0_LOADA:
3988 case NITIO_G1_LOADA:
3989 case NITIO_G0_LOADB:
3990 case NITIO_G1_LOADB:
3991 ni_stc_writel(dev, bits, stc_register);
3992 break;
3993
3994 /* 16 bit registers */
3995 case NITIO_G0_INT_ENA:
3996 ni_set_bitfield(dev, stc_register,
3997 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
3998 bits);
3999 break;
4000 case NITIO_G1_INT_ENA:
4001 ni_set_bitfield(dev, stc_register,
4002 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4003 bits);
4004 break;
4005 default:
4006 ni_stc_writew(dev, bits, stc_register);
4007 }
4008 }
4009
4010 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4011 enum ni_gpct_register reg)
4012 {
4013 struct comedi_device *dev = counter->counter_dev->dev;
4014 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4015
4016 if (stc_register == 0)
4017 return 0;
4018
4019 switch (reg) {
4020 /* m-series only registers */
4021 case NITIO_G0_DMA_STATUS:
4022 case NITIO_G1_DMA_STATUS:
4023 return ni_readw(dev, stc_register);
4024
4025 /* 32 bit registers */
4026 case NITIO_G0_HW_SAVE:
4027 case NITIO_G1_HW_SAVE:
4028 case NITIO_G0_SW_SAVE:
4029 case NITIO_G1_SW_SAVE:
4030 return ni_stc_readl(dev, stc_register);
4031
4032 /* 16 bit registers */
4033 default:
4034 return ni_stc_readw(dev, stc_register);
4035 }
4036 }
4037
4038 static int ni_freq_out_insn_read(struct comedi_device *dev,
4039 struct comedi_subdevice *s,
4040 struct comedi_insn *insn,
4041 unsigned int *data)
4042 {
4043 struct ni_private *devpriv = dev->private;
4044 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4045 int i;
4046
4047 for (i = 0; i < insn->n; i++)
4048 data[i] = val;
4049
4050 return insn->n;
4051 }
4052
4053 static int ni_freq_out_insn_write(struct comedi_device *dev,
4054 struct comedi_subdevice *s,
4055 struct comedi_insn *insn,
4056 unsigned int *data)
4057 {
4058 struct ni_private *devpriv = dev->private;
4059
4060 if (insn->n) {
4061 unsigned int val = data[insn->n - 1];
4062
4063 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4064 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4065 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4066
4067 /* use the last data value to set the fout divider */
4068 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4069
4070 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4071 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4072 }
4073 return insn->n;
4074 }
4075
4076 static int ni_freq_out_insn_config(struct comedi_device *dev,
4077 struct comedi_subdevice *s,
4078 struct comedi_insn *insn,
4079 unsigned int *data)
4080 {
4081 struct ni_private *devpriv = dev->private;
4082
4083 switch (data[0]) {
4084 case INSN_CONFIG_SET_CLOCK_SRC:
4085 switch (data[1]) {
4086 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4087 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4088 break;
4089 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4090 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4091 break;
4092 default:
4093 return -EINVAL;
4094 }
4095 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4096 break;
4097 case INSN_CONFIG_GET_CLOCK_SRC:
4098 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4099 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4100 data[2] = TIMEBASE_2_NS;
4101 } else {
4102 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4103 data[2] = TIMEBASE_1_NS * 2;
4104 }
4105 break;
4106 default:
4107 return -EINVAL;
4108 }
4109 return insn->n;
4110 }
4111
4112 static int ni_8255_callback(struct comedi_device *dev,
4113 int dir, int port, int data, unsigned long iobase)
4114 {
4115 if (dir) {
4116 ni_writeb(dev, data, iobase + 2 * port);
4117 return 0;
4118 }
4119
4120 return ni_readb(dev, iobase + 2 * port);
4121 }
4122
4123 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4124 {
4125 struct ni_private *devpriv = dev->private;
4126
4127 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4128 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4129 return 3;
4130 }
4131
4132 static int ni_m_series_pwm_config(struct comedi_device *dev,
4133 struct comedi_subdevice *s,
4134 struct comedi_insn *insn,
4135 unsigned int *data)
4136 {
4137 struct ni_private *devpriv = dev->private;
4138 unsigned int up_count, down_count;
4139
4140 switch (data[0]) {
4141 case INSN_CONFIG_PWM_OUTPUT:
4142 switch (data[1]) {
4143 case CMDF_ROUND_NEAREST:
4144 up_count = DIV_ROUND_CLOSEST(data[2],
4145 devpriv->clock_ns);
4146 break;
4147 case CMDF_ROUND_DOWN:
4148 up_count = data[2] / devpriv->clock_ns;
4149 break;
4150 case CMDF_ROUND_UP:
4151 up_count =
4152 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4153 break;
4154 default:
4155 return -EINVAL;
4156 }
4157 switch (data[3]) {
4158 case CMDF_ROUND_NEAREST:
4159 down_count = DIV_ROUND_CLOSEST(data[4],
4160 devpriv->clock_ns);
4161 break;
4162 case CMDF_ROUND_DOWN:
4163 down_count = data[4] / devpriv->clock_ns;
4164 break;
4165 case CMDF_ROUND_UP:
4166 down_count =
4167 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4168 break;
4169 default:
4170 return -EINVAL;
4171 }
4172 if (up_count * devpriv->clock_ns != data[2] ||
4173 down_count * devpriv->clock_ns != data[4]) {
4174 data[2] = up_count * devpriv->clock_ns;
4175 data[4] = down_count * devpriv->clock_ns;
4176 return -EAGAIN;
4177 }
4178 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4179 NI_M_CAL_PWM_LOW_TIME(down_count),
4180 NI_M_CAL_PWM_REG);
4181 devpriv->pwm_up_count = up_count;
4182 devpriv->pwm_down_count = down_count;
4183 return 5;
4184 case INSN_CONFIG_GET_PWM_OUTPUT:
4185 return ni_get_pwm_config(dev, data);
4186 default:
4187 return -EINVAL;
4188 }
4189 return 0;
4190 }
4191
4192 static int ni_6143_pwm_config(struct comedi_device *dev,
4193 struct comedi_subdevice *s,
4194 struct comedi_insn *insn,
4195 unsigned int *data)
4196 {
4197 struct ni_private *devpriv = dev->private;
4198 unsigned int up_count, down_count;
4199
4200 switch (data[0]) {
4201 case INSN_CONFIG_PWM_OUTPUT:
4202 switch (data[1]) {
4203 case CMDF_ROUND_NEAREST:
4204 up_count = DIV_ROUND_CLOSEST(data[2],
4205 devpriv->clock_ns);
4206 break;
4207 case CMDF_ROUND_DOWN:
4208 up_count = data[2] / devpriv->clock_ns;
4209 break;
4210 case CMDF_ROUND_UP:
4211 up_count =
4212 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4213 break;
4214 default:
4215 return -EINVAL;
4216 }
4217 switch (data[3]) {
4218 case CMDF_ROUND_NEAREST:
4219 down_count = DIV_ROUND_CLOSEST(data[4],
4220 devpriv->clock_ns);
4221 break;
4222 case CMDF_ROUND_DOWN:
4223 down_count = data[4] / devpriv->clock_ns;
4224 break;
4225 case CMDF_ROUND_UP:
4226 down_count =
4227 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4228 break;
4229 default:
4230 return -EINVAL;
4231 }
4232 if (up_count * devpriv->clock_ns != data[2] ||
4233 down_count * devpriv->clock_ns != data[4]) {
4234 data[2] = up_count * devpriv->clock_ns;
4235 data[4] = down_count * devpriv->clock_ns;
4236 return -EAGAIN;
4237 }
4238 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4239 devpriv->pwm_up_count = up_count;
4240 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4241 devpriv->pwm_down_count = down_count;
4242 return 5;
4243 case INSN_CONFIG_GET_PWM_OUTPUT:
4244 return ni_get_pwm_config(dev, data);
4245 default:
4246 return -EINVAL;
4247 }
4248 return 0;
4249 }
4250
4251 static int pack_mb88341(int addr, int val, int *bitstring)
4252 {
4253 /*
4254 * Fujitsu MB 88341
4255 * Note that address bits are reversed. Thanks to
4256 * Ingo Keen for noticing this.
4257 *
4258 * Note also that the 88341 expects address values from
4259 * 1-12, whereas we use channel numbers 0-11. The NI
4260 * docs use 1-12, also, so be careful here.
4261 */
4262 addr++;
4263 *bitstring = ((addr & 0x1) << 11) |
4264 ((addr & 0x2) << 9) |
4265 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4266 return 12;
4267 }
4268
4269 static int pack_dac8800(int addr, int val, int *bitstring)
4270 {
4271 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4272 return 11;
4273 }
4274
4275 static int pack_dac8043(int addr, int val, int *bitstring)
4276 {
4277 *bitstring = val & 0xfff;
4278 return 12;
4279 }
4280
4281 static int pack_ad8522(int addr, int val, int *bitstring)
4282 {
4283 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4284 return 16;
4285 }
4286
4287 static int pack_ad8804(int addr, int val, int *bitstring)
4288 {
4289 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4290 return 12;
4291 }
4292
4293 static int pack_ad8842(int addr, int val, int *bitstring)
4294 {
4295 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4296 return 12;
4297 }
4298
4299 struct caldac_struct {
4300 int n_chans;
4301 int n_bits;
4302 int (*packbits)(int, int, int *);
4303 };
4304
4305 static struct caldac_struct caldacs[] = {
4306 [mb88341] = {12, 8, pack_mb88341},
4307 [dac8800] = {8, 8, pack_dac8800},
4308 [dac8043] = {1, 12, pack_dac8043},
4309 [ad8522] = {2, 12, pack_ad8522},
4310 [ad8804] = {12, 8, pack_ad8804},
4311 [ad8842] = {8, 8, pack_ad8842},
4312 [ad8804_debug] = {16, 8, pack_ad8804},
4313 };
4314
4315 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4316 {
4317 const struct ni_board_struct *board = dev->board_ptr;
4318 struct ni_private *devpriv = dev->private;
4319 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4320 unsigned int cmd;
4321 int i;
4322 int type;
4323
4324 if (devpriv->caldacs[addr] == val)
4325 return;
4326 devpriv->caldacs[addr] = val;
4327
4328 for (i = 0; i < 3; i++) {
4329 type = board->caldac[i];
4330 if (type == caldac_none)
4331 break;
4332 if (addr < caldacs[type].n_chans) {
4333 bits = caldacs[type].packbits(addr, val, &bitstring);
4334 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4335 break;
4336 }
4337 addr -= caldacs[type].n_chans;
4338 }
4339
4340 /* bits will be 0 if there is no caldac for the given addr */
4341 if (bits == 0)
4342 return;
4343
4344 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4345 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4346 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4347 udelay(1);
4348 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4349 udelay(1);
4350 }
4351 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4352 udelay(1);
4353 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4354 }
4355
4356 static int ni_calib_insn_write(struct comedi_device *dev,
4357 struct comedi_subdevice *s,
4358 struct comedi_insn *insn,
4359 unsigned int *data)
4360 {
4361 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4362
4363 return 1;
4364 }
4365
4366 static int ni_calib_insn_read(struct comedi_device *dev,
4367 struct comedi_subdevice *s,
4368 struct comedi_insn *insn,
4369 unsigned int *data)
4370 {
4371 struct ni_private *devpriv = dev->private;
4372
4373 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4374
4375 return 1;
4376 }
4377
4378 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4379 {
4380 const struct ni_board_struct *board = dev->board_ptr;
4381 struct ni_private *devpriv = dev->private;
4382 int i, j;
4383 int n_dacs;
4384 int n_chans = 0;
4385 int n_bits;
4386 int diffbits = 0;
4387 int type;
4388 int chan;
4389
4390 type = board->caldac[0];
4391 if (type == caldac_none)
4392 return;
4393 n_bits = caldacs[type].n_bits;
4394 for (i = 0; i < 3; i++) {
4395 type = board->caldac[i];
4396 if (type == caldac_none)
4397 break;
4398 if (caldacs[type].n_bits != n_bits)
4399 diffbits = 1;
4400 n_chans += caldacs[type].n_chans;
4401 }
4402 n_dacs = i;
4403 s->n_chan = n_chans;
4404
4405 if (diffbits) {
4406 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4407
4408 if (n_chans > MAX_N_CALDACS)
4409 dev_err(dev->class_dev,
4410 "BUG! MAX_N_CALDACS too small\n");
4411 s->maxdata_list = maxdata_list;
4412 chan = 0;
4413 for (i = 0; i < n_dacs; i++) {
4414 type = board->caldac[i];
4415 for (j = 0; j < caldacs[type].n_chans; j++) {
4416 maxdata_list[chan] =
4417 (1 << caldacs[type].n_bits) - 1;
4418 chan++;
4419 }
4420 }
4421
4422 for (chan = 0; chan < s->n_chan; chan++)
4423 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4424 } else {
4425 type = board->caldac[0];
4426 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4427
4428 for (chan = 0; chan < s->n_chan; chan++)
4429 ni_write_caldac(dev, i, s->maxdata / 2);
4430 }
4431 }
4432
4433 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4434 {
4435 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4436 int bit;
4437 int bitstring;
4438
4439 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4440 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4441 for (bit = 0x8000; bit; bit >>= 1) {
4442 if (bit & bitstring)
4443 cmd |= NI_E_SERIAL_CMD_SDATA;
4444 else
4445 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4446
4447 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4448 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4449 }
4450 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4451 bitstring = 0;
4452 for (bit = 0x80; bit; bit >>= 1) {
4453 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4454 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4455 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4456 bitstring |= bit;
4457 }
4458 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4459
4460 return bitstring;
4461 }
4462
4463 static int ni_eeprom_insn_read(struct comedi_device *dev,
4464 struct comedi_subdevice *s,
4465 struct comedi_insn *insn,
4466 unsigned int *data)
4467 {
4468 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4469
4470 return 1;
4471 }
4472
4473 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4474 struct comedi_subdevice *s,
4475 struct comedi_insn *insn,
4476 unsigned int *data)
4477 {
4478 struct ni_private *devpriv = dev->private;
4479
4480 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4481
4482 return 1;
4483 }
4484
4485 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4486 unsigned int chan)
4487 {
4488 /* pre-m-series boards have fixed signals on pfi pins */
4489 switch (chan) {
4490 case 0:
4491 return NI_PFI_OUTPUT_AI_START1;
4492 case 1:
4493 return NI_PFI_OUTPUT_AI_START2;
4494 case 2:
4495 return NI_PFI_OUTPUT_AI_CONVERT;
4496 case 3:
4497 return NI_PFI_OUTPUT_G_SRC1;
4498 case 4:
4499 return NI_PFI_OUTPUT_G_GATE1;
4500 case 5:
4501 return NI_PFI_OUTPUT_AO_UPDATE_N;
4502 case 6:
4503 return NI_PFI_OUTPUT_AO_START1;
4504 case 7:
4505 return NI_PFI_OUTPUT_AI_START_PULSE;
4506 case 8:
4507 return NI_PFI_OUTPUT_G_SRC0;
4508 case 9:
4509 return NI_PFI_OUTPUT_G_GATE0;
4510 default:
4511 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4512 break;
4513 }
4514 return 0;
4515 }
4516
4517 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4518 unsigned int chan, unsigned int source)
4519 {
4520 /* pre-m-series boards have fixed signals on pfi pins */
4521 if (source != ni_old_get_pfi_routing(dev, chan))
4522 return -EINVAL;
4523 return 2;
4524 }
4525
4526 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4527 unsigned int chan)
4528 {
4529 struct ni_private *devpriv = dev->private;
4530 const unsigned int array_offset = chan / 3;
4531
4532 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4533 devpriv->pfi_output_select_reg[array_offset]);
4534 }
4535
4536 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4537 unsigned int chan, unsigned int source)
4538 {
4539 struct ni_private *devpriv = dev->private;
4540 unsigned int index = chan / 3;
4541 unsigned short val = devpriv->pfi_output_select_reg[index];
4542
4543 if ((source & 0x1f) != source)
4544 return -EINVAL;
4545
4546 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4547 val |= NI_M_PFI_OUT_SEL(chan, source);
4548 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4549 devpriv->pfi_output_select_reg[index] = val;
4550
4551 return 2;
4552 }
4553
4554 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4555 unsigned int chan)
4556 {
4557 struct ni_private *devpriv = dev->private;
4558
4559 return (devpriv->is_m_series)
4560 ? ni_m_series_get_pfi_routing(dev, chan)
4561 : ni_old_get_pfi_routing(dev, chan);
4562 }
4563
4564 static int ni_set_pfi_routing(struct comedi_device *dev,
4565 unsigned int chan, unsigned int source)
4566 {
4567 struct ni_private *devpriv = dev->private;
4568
4569 return (devpriv->is_m_series)
4570 ? ni_m_series_set_pfi_routing(dev, chan, source)
4571 : ni_old_set_pfi_routing(dev, chan, source);
4572 }
4573
4574 static int ni_config_filter(struct comedi_device *dev,
4575 unsigned int pfi_channel,
4576 enum ni_pfi_filter_select filter)
4577 {
4578 struct ni_private *devpriv = dev->private;
4579 unsigned int bits;
4580
4581 if (!devpriv->is_m_series)
4582 return -ENOTSUPP;
4583
4584 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4585 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4586 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4587 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4588 return 0;
4589 }
4590
4591 static int ni_pfi_insn_config(struct comedi_device *dev,
4592 struct comedi_subdevice *s,
4593 struct comedi_insn *insn,
4594 unsigned int *data)
4595 {
4596 struct ni_private *devpriv = dev->private;
4597 unsigned int chan;
4598
4599 if (insn->n < 1)
4600 return -EINVAL;
4601
4602 chan = CR_CHAN(insn->chanspec);
4603
4604 switch (data[0]) {
4605 case COMEDI_OUTPUT:
4606 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4607 break;
4608 case COMEDI_INPUT:
4609 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4610 break;
4611 case INSN_CONFIG_DIO_QUERY:
4612 data[1] =
4613 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4614 COMEDI_OUTPUT : COMEDI_INPUT;
4615 return 0;
4616 case INSN_CONFIG_SET_ROUTING:
4617 return ni_set_pfi_routing(dev, chan, data[1]);
4618 case INSN_CONFIG_GET_ROUTING:
4619 data[1] = ni_get_pfi_routing(dev, chan);
4620 break;
4621 case INSN_CONFIG_FILTER:
4622 return ni_config_filter(dev, chan, data[1]);
4623 default:
4624 return -EINVAL;
4625 }
4626 return 0;
4627 }
4628
4629 static int ni_pfi_insn_bits(struct comedi_device *dev,
4630 struct comedi_subdevice *s,
4631 struct comedi_insn *insn,
4632 unsigned int *data)
4633 {
4634 struct ni_private *devpriv = dev->private;
4635
4636 if (!devpriv->is_m_series)
4637 return -ENOTSUPP;
4638
4639 if (comedi_dio_update_state(s, data))
4640 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4641
4642 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4643
4644 return insn->n;
4645 }
4646
4647 static int cs5529_wait_for_idle(struct comedi_device *dev)
4648 {
4649 unsigned short status;
4650 const int timeout = HZ;
4651 int i;
4652
4653 for (i = 0; i < timeout; i++) {
4654 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4655 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4656 break;
4657 set_current_state(TASK_INTERRUPTIBLE);
4658 if (schedule_timeout(1))
4659 return -EIO;
4660 }
4661 if (i == timeout) {
4662 dev_err(dev->class_dev, "timeout\n");
4663 return -ETIME;
4664 }
4665 return 0;
4666 }
4667
4668 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4669 {
4670 static const int timeout = 100;
4671 int i;
4672
4673 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4674 /* give time for command to start being serially clocked into cs5529.
4675 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4676 * set before we exit this function.
4677 */
4678 for (i = 0; i < timeout; i++) {
4679 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4680 NI67XX_CAL_STATUS_BUSY)
4681 break;
4682 udelay(1);
4683 }
4684 if (i == timeout)
4685 dev_err(dev->class_dev,
4686 "possible problem - never saw adc go busy?\n");
4687 }
4688
4689 static int cs5529_do_conversion(struct comedi_device *dev,
4690 unsigned short *data)
4691 {
4692 int retval;
4693 unsigned short status;
4694
4695 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4696 retval = cs5529_wait_for_idle(dev);
4697 if (retval) {
4698 dev_err(dev->class_dev,
4699 "timeout or signal in cs5529_do_conversion()\n");
4700 return -ETIME;
4701 }
4702 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4703 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4704 dev_err(dev->class_dev,
4705 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4706 return -EIO;
4707 }
4708 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4709 dev_err(dev->class_dev,
4710 "cs5529 conversion error, overrange (ignoring)\n");
4711 }
4712 if (data) {
4713 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4714 /* cs5529 returns 16 bit signed data in bipolar mode */
4715 *data ^= (1 << 15);
4716 }
4717 return 0;
4718 }
4719
4720 static int cs5529_ai_insn_read(struct comedi_device *dev,
4721 struct comedi_subdevice *s,
4722 struct comedi_insn *insn,
4723 unsigned int *data)
4724 {
4725 int n, retval;
4726 unsigned short sample;
4727 unsigned int channel_select;
4728 const unsigned int INTERNAL_REF = 0x1000;
4729
4730 /*
4731 * Set calibration adc source. Docs lie, reference select bits 8 to 11
4732 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4733 * 13 causes the adc input to go overrange (maybe reads external
4734 * reference?)
4735 */
4736 if (insn->chanspec & CR_ALT_SOURCE)
4737 channel_select = INTERNAL_REF;
4738 else
4739 channel_select = CR_CHAN(insn->chanspec);
4740 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4741
4742 for (n = 0; n < insn->n; n++) {
4743 retval = cs5529_do_conversion(dev, &sample);
4744 if (retval < 0)
4745 return retval;
4746 data[n] = sample;
4747 }
4748 return insn->n;
4749 }
4750
4751 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4752 unsigned int reg_select_bits)
4753 {
4754 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4755 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4756 reg_select_bits &= CS5529_CMD_REG_MASK;
4757 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4758 if (cs5529_wait_for_idle(dev))
4759 dev_err(dev->class_dev,
4760 "timeout or signal in %s\n", __func__);
4761 }
4762
4763 static int init_cs5529(struct comedi_device *dev)
4764 {
4765 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4766 CS5529_CFG_WORD_RATE_2180;
4767
4768 #if 1
4769 /* do self-calibration */
4770 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4771 CS5529_CFG_REG);
4772 /* need to force a conversion for calibration to run */
4773 cs5529_do_conversion(dev, NULL);
4774 #else
4775 /* force gain calibration to 1 */
4776 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4777 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4778 CS5529_CFG_REG);
4779 if (cs5529_wait_for_idle(dev))
4780 dev_err(dev->class_dev,
4781 "timeout or signal in %s\n", __func__);
4782 #endif
4783 return 0;
4784 }
4785
4786 /*
4787 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4788 * given an arbitrary frequency input clock.
4789 */
4790 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4791 unsigned int *freq_divider,
4792 unsigned int *freq_multiplier,
4793 unsigned int *actual_period_ns)
4794 {
4795 unsigned int div;
4796 unsigned int best_div = 1;
4797 unsigned int mult;
4798 unsigned int best_mult = 1;
4799 static const unsigned int pico_per_nano = 1000;
4800 const unsigned int reference_picosec = reference_period_ns *
4801 pico_per_nano;
4802 /*
4803 * m-series wants the phased-locked loop to output 80MHz, which is
4804 * divided by 4 to 20 MHz for most timing clocks
4805 */
4806 static const unsigned int target_picosec = 12500;
4807 int best_period_picosec = 0;
4808
4809 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4810 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4811 unsigned int new_period_ps =
4812 (reference_picosec * div) / mult;
4813 if (abs(new_period_ps - target_picosec) <
4814 abs(best_period_picosec - target_picosec)) {
4815 best_period_picosec = new_period_ps;
4816 best_div = div;
4817 best_mult = mult;
4818 }
4819 }
4820 }
4821 if (best_period_picosec == 0)
4822 return -EIO;
4823
4824 *freq_divider = best_div;
4825 *freq_multiplier = best_mult;
4826 /* return the actual period (* fudge factor for 80 to 20 MHz) */
4827 *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4828 pico_per_nano);
4829 return 0;
4830 }
4831
4832 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4833 unsigned int source,
4834 unsigned int period_ns)
4835 {
4836 struct ni_private *devpriv = dev->private;
4837 static const unsigned int min_period_ns = 50;
4838 static const unsigned int max_period_ns = 1000;
4839 static const unsigned int timeout = 1000;
4840 unsigned int pll_control_bits;
4841 unsigned int freq_divider;
4842 unsigned int freq_multiplier;
4843 unsigned int rtsi;
4844 unsigned int i;
4845 int retval;
4846
4847 if (source == NI_MIO_PLL_PXI10_CLOCK)
4848 period_ns = 100;
4849 /*
4850 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4851 * range so we'll use that.
4852 */
4853 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4854 dev_err(dev->class_dev,
4855 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4856 __func__, min_period_ns, max_period_ns);
4857 return -EINVAL;
4858 }
4859 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4860 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4861 NISTC_RTSI_TRIG_DIR_REG);
4862 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4863 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4864 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4865 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4866 switch (source) {
4867 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4868 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4869 break;
4870 case NI_MIO_PLL_PXI10_CLOCK:
4871 /* pxi clock is 10MHz */
4872 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4873 break;
4874 default:
4875 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4876 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4877 devpriv->clock_and_fout2 |=
4878 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4879 break;
4880 }
4881 }
4882 if (rtsi > NI_M_MAX_RTSI_CHAN)
4883 return -EINVAL;
4884 break;
4885 }
4886 retval = ni_mseries_get_pll_parameters(period_ns,
4887 &freq_divider,
4888 &freq_multiplier,
4889 &devpriv->clock_ns);
4890 if (retval < 0) {
4891 dev_err(dev->class_dev,
4892 "bug, failed to find pll parameters\n");
4893 return retval;
4894 }
4895
4896 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4897 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4898 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4899
4900 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4901 devpriv->clock_source = source;
4902 /* it takes a few hundred microseconds for PLL to lock */
4903 for (i = 0; i < timeout; ++i) {
4904 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4905 break;
4906 udelay(1);
4907 }
4908 if (i == timeout) {
4909 dev_err(dev->class_dev,
4910 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4911 __func__, source, period_ns);
4912 return -ETIMEDOUT;
4913 }
4914 return 3;
4915 }
4916
4917 static int ni_set_master_clock(struct comedi_device *dev,
4918 unsigned int source, unsigned int period_ns)
4919 {
4920 struct ni_private *devpriv = dev->private;
4921
4922 if (source == NI_MIO_INTERNAL_CLOCK) {
4923 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4924 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4925 NISTC_RTSI_TRIG_DIR_REG);
4926 devpriv->clock_ns = TIMEBASE_1_NS;
4927 if (devpriv->is_m_series) {
4928 devpriv->clock_and_fout2 &=
4929 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4930 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4931 ni_writew(dev, devpriv->clock_and_fout2,
4932 NI_M_CLK_FOUT2_REG);
4933 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4934 }
4935 devpriv->clock_source = source;
4936 } else {
4937 if (devpriv->is_m_series) {
4938 return ni_mseries_set_pll_master_clock(dev, source,
4939 period_ns);
4940 } else {
4941 if (source == NI_MIO_RTSI_CLOCK) {
4942 devpriv->rtsi_trig_direction_reg |=
4943 NISTC_RTSI_TRIG_USE_CLK;
4944 ni_stc_writew(dev,
4945 devpriv->rtsi_trig_direction_reg,
4946 NISTC_RTSI_TRIG_DIR_REG);
4947 if (period_ns == 0) {
4948 dev_err(dev->class_dev,
4949 "we don't handle an unspecified clock period correctly yet, returning error\n");
4950 return -EINVAL;
4951 }
4952 devpriv->clock_ns = period_ns;
4953 devpriv->clock_source = source;
4954 } else {
4955 return -EINVAL;
4956 }
4957 }
4958 }
4959 return 3;
4960 }
4961
4962 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4963 unsigned int chan, unsigned int source)
4964 {
4965 struct ni_private *devpriv = dev->private;
4966
4967 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4968 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4969 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4970 return 1;
4971
4972 dev_err(dev->class_dev,
4973 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4974 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4975 return 0;
4976 }
4977 return 0;
4978 }
4979 switch (source) {
4980 case NI_RTSI_OUTPUT_ADR_START1:
4981 case NI_RTSI_OUTPUT_ADR_START2:
4982 case NI_RTSI_OUTPUT_SCLKG:
4983 case NI_RTSI_OUTPUT_DACUPDN:
4984 case NI_RTSI_OUTPUT_DA_START1:
4985 case NI_RTSI_OUTPUT_G_SRC0:
4986 case NI_RTSI_OUTPUT_G_GATE0:
4987 case NI_RTSI_OUTPUT_RGOUT0:
4988 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4989 return 1;
4990 case NI_RTSI_OUTPUT_RTSI_OSC:
4991 return (devpriv->is_m_series) ? 1 : 0;
4992 default:
4993 return 0;
4994 }
4995 }
4996
4997 static int ni_set_rtsi_routing(struct comedi_device *dev,
4998 unsigned int chan, unsigned int src)
4999 {
5000 struct ni_private *devpriv = dev->private;
5001
5002 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5003 return -EINVAL;
5004 if (chan < 4) {
5005 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5006 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5007 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5008 NISTC_RTSI_TRIGA_OUT_REG);
5009 } else if (chan < 8) {
5010 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5011 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5012 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5013 NISTC_RTSI_TRIGB_OUT_REG);
5014 }
5015 return 2;
5016 }
5017
5018 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5019 unsigned int chan)
5020 {
5021 struct ni_private *devpriv = dev->private;
5022
5023 if (chan < 4) {
5024 return NISTC_RTSI_TRIG_TO_SRC(chan,
5025 devpriv->rtsi_trig_a_output_reg);
5026 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5027 return NISTC_RTSI_TRIG_TO_SRC(chan,
5028 devpriv->rtsi_trig_b_output_reg);
5029 } else {
5030 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
5031 return NI_RTSI_OUTPUT_RTSI_OSC;
5032 dev_err(dev->class_dev, "bug! should never get here?\n");
5033 return 0;
5034 }
5035 }
5036
5037 static int ni_rtsi_insn_config(struct comedi_device *dev,
5038 struct comedi_subdevice *s,
5039 struct comedi_insn *insn,
5040 unsigned int *data)
5041 {
5042 struct ni_private *devpriv = dev->private;
5043 unsigned int chan = CR_CHAN(insn->chanspec);
5044 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5045
5046 switch (data[0]) {
5047 case INSN_CONFIG_DIO_OUTPUT:
5048 if (chan < max_chan) {
5049 devpriv->rtsi_trig_direction_reg |=
5050 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5051 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5052 devpriv->rtsi_trig_direction_reg |=
5053 NISTC_RTSI_TRIG_DRV_CLK;
5054 }
5055 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5056 NISTC_RTSI_TRIG_DIR_REG);
5057 break;
5058 case INSN_CONFIG_DIO_INPUT:
5059 if (chan < max_chan) {
5060 devpriv->rtsi_trig_direction_reg &=
5061 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5062 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5063 devpriv->rtsi_trig_direction_reg &=
5064 ~NISTC_RTSI_TRIG_DRV_CLK;
5065 }
5066 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5067 NISTC_RTSI_TRIG_DIR_REG);
5068 break;
5069 case INSN_CONFIG_DIO_QUERY:
5070 if (chan < max_chan) {
5071 data[1] =
5072 (devpriv->rtsi_trig_direction_reg &
5073 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5074 ? INSN_CONFIG_DIO_OUTPUT
5075 : INSN_CONFIG_DIO_INPUT;
5076 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5077 data[1] = (devpriv->rtsi_trig_direction_reg &
5078 NISTC_RTSI_TRIG_DRV_CLK)
5079 ? INSN_CONFIG_DIO_OUTPUT
5080 : INSN_CONFIG_DIO_INPUT;
5081 }
5082 return 2;
5083 case INSN_CONFIG_SET_CLOCK_SRC:
5084 return ni_set_master_clock(dev, data[1], data[2]);
5085 case INSN_CONFIG_GET_CLOCK_SRC:
5086 data[1] = devpriv->clock_source;
5087 data[2] = devpriv->clock_ns;
5088 return 3;
5089 case INSN_CONFIG_SET_ROUTING:
5090 return ni_set_rtsi_routing(dev, chan, data[1]);
5091 case INSN_CONFIG_GET_ROUTING:
5092 data[1] = ni_get_rtsi_routing(dev, chan);
5093 return 2;
5094 default:
5095 return -EINVAL;
5096 }
5097 return 1;
5098 }
5099
5100 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5101 struct comedi_subdevice *s,
5102 struct comedi_insn *insn,
5103 unsigned int *data)
5104 {
5105 data[1] = 0;
5106
5107 return insn->n;
5108 }
5109
5110 static void ni_rtsi_init(struct comedi_device *dev)
5111 {
5112 struct ni_private *devpriv = dev->private;
5113
5114 /* Initialises the RTSI bus signal switch to a default state */
5115
5116 /*
5117 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5118 * to have no effect, at least on pxi-6281, which always uses
5119 * 20MHz rtsi clock frequency
5120 */
5121 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5122 /* Set clock mode to internal */
5123 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5124 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5125 /* default internal lines routing to RTSI bus lines */
5126 devpriv->rtsi_trig_a_output_reg =
5127 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5128 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5129 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5130 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5131 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5132 NISTC_RTSI_TRIGA_OUT_REG);
5133 devpriv->rtsi_trig_b_output_reg =
5134 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5135 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5136 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5137 if (devpriv->is_m_series)
5138 devpriv->rtsi_trig_b_output_reg |=
5139 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5140 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5141 NISTC_RTSI_TRIGB_OUT_REG);
5142
5143 /*
5144 * Sets the source and direction of the 4 on board lines
5145 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5146 */
5147 }
5148
5149 #ifdef PCIDMA
5150 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5151 {
5152 struct ni_gpct *counter = s->private;
5153 int retval;
5154
5155 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5156 COMEDI_INPUT);
5157 if (retval) {
5158 dev_err(dev->class_dev,
5159 "no dma channel available for use by counter\n");
5160 return retval;
5161 }
5162 ni_tio_acknowledge(counter);
5163 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5164
5165 return ni_tio_cmd(dev, s);
5166 }
5167
5168 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5169 {
5170 struct ni_gpct *counter = s->private;
5171 int retval;
5172
5173 retval = ni_tio_cancel(counter);
5174 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5175 ni_release_gpct_mite_channel(dev, counter->counter_index);
5176 return retval;
5177 }
5178 #endif
5179
5180 static irqreturn_t ni_E_interrupt(int irq, void *d)
5181 {
5182 struct comedi_device *dev = d;
5183 struct comedi_subdevice *s_ai = dev->read_subdev;
5184 struct comedi_subdevice *s_ao = dev->write_subdev;
5185 unsigned short a_status;
5186 unsigned short b_status;
5187 unsigned long flags;
5188 #ifdef PCIDMA
5189 struct ni_private *devpriv = dev->private;
5190 #endif
5191
5192 if (!dev->attached)
5193 return IRQ_NONE;
5194 smp_mb(); /* make sure dev->attached is checked */
5195
5196 /* lock to avoid race with comedi_poll */
5197 spin_lock_irqsave(&dev->spinlock, flags);
5198 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5199 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5200 #ifdef PCIDMA
5201 if (devpriv->mite) {
5202 unsigned long flags_too;
5203
5204 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5205 if (s_ai && devpriv->ai_mite_chan)
5206 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5207 if (s_ao && devpriv->ao_mite_chan)
5208 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5209 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5210 }
5211 #endif
5212 ack_a_interrupt(dev, a_status);
5213 ack_b_interrupt(dev, b_status);
5214 if (s_ai) {
5215 if (a_status & NISTC_AI_STATUS1_INTA)
5216 handle_a_interrupt(dev, s_ai, a_status);
5217 /* handle any interrupt or dma events */
5218 comedi_handle_events(dev, s_ai);
5219 }
5220 if (s_ao) {
5221 if (b_status & NISTC_AO_STATUS1_INTB)
5222 handle_b_interrupt(dev, s_ao, b_status);
5223 /* handle any interrupt or dma events */
5224 comedi_handle_events(dev, s_ao);
5225 }
5226 handle_gpct_interrupt(dev, 0);
5227 handle_gpct_interrupt(dev, 1);
5228 #ifdef PCIDMA
5229 if (devpriv->is_m_series)
5230 handle_cdio_interrupt(dev);
5231 #endif
5232
5233 spin_unlock_irqrestore(&dev->spinlock, flags);
5234 return IRQ_HANDLED;
5235 }
5236
5237 static int ni_alloc_private(struct comedi_device *dev)
5238 {
5239 struct ni_private *devpriv;
5240
5241 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5242 if (!devpriv)
5243 return -ENOMEM;
5244
5245 spin_lock_init(&devpriv->window_lock);
5246 spin_lock_init(&devpriv->soft_reg_copy_lock);
5247 spin_lock_init(&devpriv->mite_channel_lock);
5248
5249 return 0;
5250 }
5251
5252 static int ni_E_init(struct comedi_device *dev,
5253 unsigned int interrupt_pin, unsigned int irq_polarity)
5254 {
5255 const struct ni_board_struct *board = dev->board_ptr;
5256 struct ni_private *devpriv = dev->private;
5257 struct comedi_subdevice *s;
5258 int ret;
5259 int i;
5260
5261 if (board->n_aochan > MAX_N_AO_CHAN) {
5262 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5263 return -EINVAL;
5264 }
5265
5266 /* initialize clock dividers */
5267 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5268 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5269 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5270 NISTC_CLK_FOUT_TO_BOARD;
5271 if (!devpriv->is_6xxx) {
5272 /* BEAM is this needed for PCI-6143 ?? */
5273 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5274 NISTC_CLK_FOUT_AO_OUT_DIV2);
5275 }
5276 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5277
5278 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5279 if (ret)
5280 return ret;
5281
5282 /* Analog Input subdevice */
5283 s = &dev->subdevices[NI_AI_SUBDEV];
5284 if (board->n_adchan) {
5285 s->type = COMEDI_SUBD_AI;
5286 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5287 if (!devpriv->is_611x)
5288 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5289 if (board->ai_maxdata > 0xffff)
5290 s->subdev_flags |= SDF_LSAMPL;
5291 if (devpriv->is_m_series)
5292 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5293 s->n_chan = board->n_adchan;
5294 s->maxdata = board->ai_maxdata;
5295 s->range_table = ni_range_lkup[board->gainlkup];
5296 s->insn_read = ni_ai_insn_read;
5297 s->insn_config = ni_ai_insn_config;
5298 if (dev->irq) {
5299 dev->read_subdev = s;
5300 s->subdev_flags |= SDF_CMD_READ;
5301 s->len_chanlist = 512;
5302 s->do_cmdtest = ni_ai_cmdtest;
5303 s->do_cmd = ni_ai_cmd;
5304 s->cancel = ni_ai_reset;
5305 s->poll = ni_ai_poll;
5306 s->munge = ni_ai_munge;
5307
5308 if (devpriv->mite)
5309 s->async_dma_dir = DMA_FROM_DEVICE;
5310 }
5311
5312 /* reset the analog input configuration */
5313 ni_ai_reset(dev, s);
5314 } else {
5315 s->type = COMEDI_SUBD_UNUSED;
5316 }
5317
5318 /* Analog Output subdevice */
5319 s = &dev->subdevices[NI_AO_SUBDEV];
5320 if (board->n_aochan) {
5321 s->type = COMEDI_SUBD_AO;
5322 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5323 if (devpriv->is_m_series)
5324 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5325 s->n_chan = board->n_aochan;
5326 s->maxdata = board->ao_maxdata;
5327 s->range_table = board->ao_range_table;
5328 s->insn_config = ni_ao_insn_config;
5329 s->insn_write = ni_ao_insn_write;
5330
5331 ret = comedi_alloc_subdev_readback(s);
5332 if (ret)
5333 return ret;
5334
5335 /*
5336 * Along with the IRQ we need either a FIFO or DMA for
5337 * async command support.
5338 */
5339 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5340 dev->write_subdev = s;
5341 s->subdev_flags |= SDF_CMD_WRITE;
5342 s->len_chanlist = s->n_chan;
5343 s->do_cmdtest = ni_ao_cmdtest;
5344 s->do_cmd = ni_ao_cmd;
5345 s->cancel = ni_ao_reset;
5346 if (!devpriv->is_m_series)
5347 s->munge = ni_ao_munge;
5348
5349 if (devpriv->mite)
5350 s->async_dma_dir = DMA_TO_DEVICE;
5351 }
5352
5353 if (devpriv->is_67xx)
5354 init_ao_67xx(dev, s);
5355
5356 /* reset the analog output configuration */
5357 ni_ao_reset(dev, s);
5358 } else {
5359 s->type = COMEDI_SUBD_UNUSED;
5360 }
5361
5362 /* Digital I/O subdevice */
5363 s = &dev->subdevices[NI_DIO_SUBDEV];
5364 s->type = COMEDI_SUBD_DIO;
5365 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5366 s->n_chan = board->has_32dio_chan ? 32 : 8;
5367 s->maxdata = 1;
5368 s->range_table = &range_digital;
5369 if (devpriv->is_m_series) {
5370 #ifdef PCIDMA
5371 s->subdev_flags |= SDF_LSAMPL;
5372 s->insn_bits = ni_m_series_dio_insn_bits;
5373 s->insn_config = ni_m_series_dio_insn_config;
5374 if (dev->irq) {
5375 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5376 s->len_chanlist = s->n_chan;
5377 s->do_cmdtest = ni_cdio_cmdtest;
5378 s->do_cmd = ni_cdio_cmd;
5379 s->cancel = ni_cdio_cancel;
5380
5381 /* M-series boards use DMA */
5382 s->async_dma_dir = DMA_BIDIRECTIONAL;
5383 }
5384
5385 /* reset DIO and set all channels to inputs */
5386 ni_writel(dev, NI_M_CDO_CMD_RESET |
5387 NI_M_CDI_CMD_RESET,
5388 NI_M_CDIO_CMD_REG);
5389 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5390 #endif /* PCIDMA */
5391 } else {
5392 s->insn_bits = ni_dio_insn_bits;
5393 s->insn_config = ni_dio_insn_config;
5394
5395 /* set all channels to inputs */
5396 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5397 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5398 }
5399
5400 /* 8255 device */
5401 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5402 if (board->has_8255) {
5403 ret = subdev_8255_init(dev, s, ni_8255_callback,
5404 NI_E_8255_BASE);
5405 if (ret)
5406 return ret;
5407 } else {
5408 s->type = COMEDI_SUBD_UNUSED;
5409 }
5410
5411 /* formerly general purpose counter/timer device, but no longer used */
5412 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5413 s->type = COMEDI_SUBD_UNUSED;
5414
5415 /* Calibration subdevice */
5416 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5417 s->type = COMEDI_SUBD_CALIB;
5418 s->subdev_flags = SDF_INTERNAL;
5419 s->n_chan = 1;
5420 s->maxdata = 0;
5421 if (devpriv->is_m_series) {
5422 /* internal PWM output used for AI nonlinearity calibration */
5423 s->insn_config = ni_m_series_pwm_config;
5424
5425 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5426 } else if (devpriv->is_6143) {
5427 /* internal PWM output used for AI nonlinearity calibration */
5428 s->insn_config = ni_6143_pwm_config;
5429 } else {
5430 s->subdev_flags |= SDF_WRITABLE;
5431 s->insn_read = ni_calib_insn_read;
5432 s->insn_write = ni_calib_insn_write;
5433
5434 /* setup the caldacs and find the real n_chan and maxdata */
5435 caldac_setup(dev, s);
5436 }
5437
5438 /* EEPROM subdevice */
5439 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5440 s->type = COMEDI_SUBD_MEMORY;
5441 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5442 s->maxdata = 0xff;
5443 if (devpriv->is_m_series) {
5444 s->n_chan = M_SERIES_EEPROM_SIZE;
5445 s->insn_read = ni_m_series_eeprom_insn_read;
5446 } else {
5447 s->n_chan = 512;
5448 s->insn_read = ni_eeprom_insn_read;
5449 }
5450
5451 /* Digital I/O (PFI) subdevice */
5452 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5453 s->type = COMEDI_SUBD_DIO;
5454 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5455 s->maxdata = 1;
5456 if (devpriv->is_m_series) {
5457 s->n_chan = 16;
5458 s->insn_bits = ni_pfi_insn_bits;
5459
5460 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5461 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5462 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5463 NI_M_PFI_OUT_SEL_REG(i));
5464 }
5465 } else {
5466 s->n_chan = 10;
5467 }
5468 s->insn_config = ni_pfi_insn_config;
5469
5470 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5471
5472 /* cs5529 calibration adc */
5473 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5474 if (devpriv->is_67xx) {
5475 s->type = COMEDI_SUBD_AI;
5476 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5477 /* one channel for each analog output channel */
5478 s->n_chan = board->n_aochan;
5479 s->maxdata = (1 << 16) - 1;
5480 s->range_table = &range_unknown; /* XXX */
5481 s->insn_read = cs5529_ai_insn_read;
5482 s->insn_config = NULL;
5483 init_cs5529(dev);
5484 } else {
5485 s->type = COMEDI_SUBD_UNUSED;
5486 }
5487
5488 /* Serial */
5489 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5490 s->type = COMEDI_SUBD_SERIAL;
5491 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5492 s->n_chan = 1;
5493 s->maxdata = 0xff;
5494 s->insn_config = ni_serial_insn_config;
5495 devpriv->serial_interval_ns = 0;
5496 devpriv->serial_hw_mode = 0;
5497
5498 /* RTSI */
5499 s = &dev->subdevices[NI_RTSI_SUBDEV];
5500 s->type = COMEDI_SUBD_DIO;
5501 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5502 s->n_chan = 8;
5503 s->maxdata = 1;
5504 s->insn_bits = ni_rtsi_insn_bits;
5505 s->insn_config = ni_rtsi_insn_config;
5506 ni_rtsi_init(dev);
5507
5508 /* allocate and initialize the gpct counter device */
5509 devpriv->counter_dev = ni_gpct_device_construct(dev,
5510 ni_gpct_write_register,
5511 ni_gpct_read_register,
5512 (devpriv->is_m_series)
5513 ? ni_gpct_variant_m_series
5514 : ni_gpct_variant_e_series,
5515 NUM_GPCT);
5516 if (!devpriv->counter_dev)
5517 return -ENOMEM;
5518
5519 /* Counter (gpct) subdevices */
5520 for (i = 0; i < NUM_GPCT; ++i) {
5521 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5522
5523 /* setup and initialize the counter */
5524 gpct->chip_index = 0;
5525 gpct->counter_index = i;
5526 ni_tio_init_counter(gpct);
5527
5528 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5529 s->type = COMEDI_SUBD_COUNTER;
5530 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5531 s->n_chan = 3;
5532 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5533 : 0x00ffffff;
5534 s->insn_read = ni_tio_insn_read;
5535 s->insn_write = ni_tio_insn_write;
5536 s->insn_config = ni_tio_insn_config;
5537 #ifdef PCIDMA
5538 if (dev->irq && devpriv->mite) {
5539 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5540 s->len_chanlist = 1;
5541 s->do_cmdtest = ni_tio_cmdtest;
5542 s->do_cmd = ni_gpct_cmd;
5543 s->cancel = ni_gpct_cancel;
5544
5545 s->async_dma_dir = DMA_BIDIRECTIONAL;
5546 }
5547 #endif
5548 s->private = gpct;
5549 }
5550
5551 /* Frequency output subdevice */
5552 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5553 s->type = COMEDI_SUBD_COUNTER;
5554 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5555 s->n_chan = 1;
5556 s->maxdata = 0xf;
5557 s->insn_read = ni_freq_out_insn_read;
5558 s->insn_write = ni_freq_out_insn_write;
5559 s->insn_config = ni_freq_out_insn_config;
5560
5561 if (dev->irq) {
5562 ni_stc_writew(dev,
5563 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5564 (NISTC_INT_CTRL_3PIN_INT & 0) |
5565 NISTC_INT_CTRL_INTA_ENA |
5566 NISTC_INT_CTRL_INTB_ENA |
5567 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5568 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5569 NISTC_INT_CTRL_REG);
5570 }
5571
5572 /* DMA setup */
5573 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5574 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5575
5576 if (devpriv->is_6xxx) {
5577 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5578 } else if (devpriv->is_m_series) {
5579 int channel;
5580
5581 for (channel = 0; channel < board->n_aochan; ++channel) {
5582 ni_writeb(dev, 0xf,
5583 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5584 ni_writeb(dev, 0x0,
5585 NI_M_AO_REF_ATTENUATION_REG(channel));
5586 }
5587 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5588 }
5589
5590 return 0;
5591 }
5592
5593 static void mio_common_detach(struct comedi_device *dev)
5594 {
5595 struct ni_private *devpriv = dev->private;
5596
5597 if (devpriv)
5598 ni_gpct_device_destroy(devpriv->counter_dev);
5599 }
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