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staging: comedi: make 'dev->attached' a bool bit-field
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23 */
24
25 /*
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
28
29 Interrupt support originally added by Truxton Fulton
30 <trux@truxton.com>
31
32 References (from ftp://ftp.natinst.com/support/manuals):
33
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
38 release_ni611x.pdf
39 release_ni67xx.pdf
40 Other possibly relevant info:
41
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
44 320889a.pdf delete
45 320906c.pdf maximum signal ratings
46 321066a.pdf about 16x
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
51
52 ISSUES:
53
54 - the interrupt routine needs to be cleaned up
55
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
58 */
59
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
63
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
66 #include "8255.h"
67 #include "mite.h"
68 #include "comedi_fc.h"
69
70 #ifndef MDPRINTK
71 #define MDPRINTK(format, args...)
72 #endif
73
74 /* A timeout count */
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
77
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 };
92
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
94 RANGE(-10, 10),
95 RANGE(-5, 5),
96 RANGE(-2.5, 2.5),
97 RANGE(-1, 1),
98 RANGE(-0.5, 0.5),
99 RANGE(-0.25, 0.25),
100 RANGE(-0.1, 0.1),
101 RANGE(-0.05, 0.05),
102 RANGE(0, 20),
103 RANGE(0, 10),
104 RANGE(0, 5),
105 RANGE(0, 2),
106 RANGE(0, 1),
107 RANGE(0, 0.5),
108 RANGE(0, 0.2),
109 RANGE(0, 0.1),
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
114 RANGE(-10, 10),
115 RANGE(-5, 5),
116 RANGE(-1, 1),
117 RANGE(-0.1,
118 0.1),
119 RANGE(0, 10),
120 RANGE(0, 5),
121 RANGE(0, 1),
122 RANGE(0, 0.1),
123 }
124 };
125
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
127 RANGE(-10,
128 10),
129 RANGE(-5, 5),
130 RANGE(-2, 2),
131 RANGE(-1, 1),
132 RANGE(-0.5,
133 0.5),
134 RANGE(-0.2,
135 0.2),
136 RANGE(-0.1,
137 0.1),
138 RANGE(0, 10),
139 RANGE(0, 5),
140 RANGE(0, 2),
141 RANGE(0, 1),
142 RANGE(0,
143 0.5),
144 RANGE(0,
145 0.2),
146 RANGE(0,
147 0.1),
148 }
149 };
150
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
152 RANGE(-10, 10),
153 RANGE(-5, 5),
154 RANGE(-0.5,
155 0.5),
156 RANGE(-0.05,
157 0.05),
158 }
159 };
160
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
162 RANGE(-50, 50),
163 RANGE(-20, 20),
164 RANGE(-10, 10),
165 RANGE(-5, 5),
166 RANGE(-2, 2),
167 RANGE(-1, 1),
168 RANGE(-0.5, 0.5),
169 RANGE(-0.2, 0.2),
170 }
171 };
172
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
174 RANGE(-10, 10),
175 RANGE(-5, 5),
176 RANGE(-1, 1),
177 RANGE(-0.2, 0.2),
178 }
179 };
180
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
182 RANGE(-10, 10),
183 RANGE(-5, 5),
184 RANGE(-2, 2),
185 RANGE(-1, 1),
186 RANGE(-0.5, 0.5),
187 RANGE(-0.2, 0.2),
188 RANGE(-0.1, 0.1),
189 }
190 };
191
192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
193 RANGE(-5, +5),
194 }
195 };
196
197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
198 RANGE(-10, 10),
199 RANGE(0, 10),
200 RANGE_ext(-1, 1),
201 RANGE_ext(0, 1),
202 }
203 };
204
205 static const struct comedi_lrange *const ni_range_lkup[] = {
206 [ai_gain_16] = &range_ni_E_ai,
207 [ai_gain_8] = &range_ni_E_ai_limited,
208 [ai_gain_14] = &range_ni_E_ai_limited14,
209 [ai_gain_4] = &range_ni_E_ai_bipolar4,
210 [ai_gain_611x] = &range_ni_E_ai_611x,
211 [ai_gain_622x] = &range_ni_M_ai_622x,
212 [ai_gain_628x] = &range_ni_M_ai_628x,
213 [ai_gain_6143] = &range_ni_S_ai_6143
214 };
215
216 static int ni_dio_insn_config(struct comedi_device *dev,
217 struct comedi_subdevice *s,
218 struct comedi_insn *insn, unsigned int *data);
219 static int ni_dio_insn_bits(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_insn *insn, unsigned int *data);
222 static int ni_cdio_cmdtest(struct comedi_device *dev,
223 struct comedi_subdevice *s, struct comedi_cmd *cmd);
224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
225 static int ni_cdio_cancel(struct comedi_device *dev,
226 struct comedi_subdevice *s);
227 static void handle_cdio_interrupt(struct comedi_device *dev);
228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
229 unsigned int trignum);
230
231 static int ni_serial_insn_config(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn, unsigned int *data);
234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 unsigned char data_out,
237 unsigned char *data_in);
238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 unsigned char data_out,
241 unsigned char *data_in);
242
243 static int ni_calib_insn_read(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn, unsigned int *data);
246 static int ni_calib_insn_write(struct comedi_device *dev,
247 struct comedi_subdevice *s,
248 struct comedi_insn *insn, unsigned int *data);
249
250 static int ni_eeprom_insn_read(struct comedi_device *dev,
251 struct comedi_subdevice *s,
252 struct comedi_insn *insn, unsigned int *data);
253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn,
256 unsigned int *data);
257
258 static int ni_pfi_insn_bits(struct comedi_device *dev,
259 struct comedi_subdevice *s,
260 struct comedi_insn *insn, unsigned int *data);
261 static int ni_pfi_insn_config(struct comedi_device *dev,
262 struct comedi_subdevice *s,
263 struct comedi_insn *insn, unsigned int *data);
264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
265 unsigned chan);
266
267 static void ni_rtsi_init(struct comedi_device *dev);
268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
269 struct comedi_subdevice *s,
270 struct comedi_insn *insn, unsigned int *data);
271 static int ni_rtsi_insn_config(struct comedi_device *dev,
272 struct comedi_subdevice *s,
273 struct comedi_insn *insn, unsigned int *data);
274
275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
277
278 #ifdef DEBUG_STATUS_A
279 static void ni_mio_print_status_a(int status);
280 #else
281 #define ni_mio_print_status_a(a)
282 #endif
283 #ifdef DEBUG_STATUS_B
284 static void ni_mio_print_status_b(int status);
285 #else
286 #define ni_mio_print_status_b(a)
287 #endif
288
289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
290 #ifndef PCIDMA
291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
293 struct comedi_subdevice *s);
294 #endif
295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
297 unsigned int trignum);
298 static void ni_load_channelgain_list(struct comedi_device *dev,
299 unsigned int n_chan, unsigned int *list);
300 static void shutdown_ai_command(struct comedi_device *dev);
301
302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
303 unsigned int trignum);
304
305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
306
307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
308
309 static int ni_gpct_insn_write(struct comedi_device *dev,
310 struct comedi_subdevice *s,
311 struct comedi_insn *insn, unsigned int *data);
312 static int ni_gpct_insn_read(struct comedi_device *dev,
313 struct comedi_subdevice *s,
314 struct comedi_insn *insn, unsigned int *data);
315 static int ni_gpct_insn_config(struct comedi_device *dev,
316 struct comedi_subdevice *s,
317 struct comedi_insn *insn, unsigned int *data);
318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
319 static int ni_gpct_cmdtest(struct comedi_device *dev,
320 struct comedi_subdevice *s, struct comedi_cmd *cmd);
321 static int ni_gpct_cancel(struct comedi_device *dev,
322 struct comedi_subdevice *s);
323 static void handle_gpct_interrupt(struct comedi_device *dev,
324 unsigned short counter_index);
325
326 static int init_cs5529(struct comedi_device *dev);
327 static int cs5529_do_conversion(struct comedi_device *dev,
328 unsigned short *data);
329 static int cs5529_ai_insn_read(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data);
332 #ifdef NI_CS5529_DEBUG
333 static unsigned int cs5529_config_read(struct comedi_device *dev,
334 unsigned int reg_select_bits);
335 #endif
336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
337 unsigned int reg_select_bits);
338
339 static int ni_m_series_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
342 static int ni_6143_pwm_config(struct comedi_device *dev,
343 struct comedi_subdevice *s,
344 struct comedi_insn *insn, unsigned int *data);
345
346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
347 unsigned period_ns);
348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
350
351 enum aimodes {
352 AIMODE_NONE = 0,
353 AIMODE_HALF_FULL = 1,
354 AIMODE_SCAN = 2,
355 AIMODE_SAMPLE = 3,
356 };
357
358 enum ni_common_subdevices {
359 NI_AI_SUBDEV,
360 NI_AO_SUBDEV,
361 NI_DIO_SUBDEV,
362 NI_8255_DIO_SUBDEV,
363 NI_UNUSED_SUBDEV,
364 NI_CALIBRATION_SUBDEV,
365 NI_EEPROM_SUBDEV,
366 NI_PFI_DIO_SUBDEV,
367 NI_CS5529_CALIBRATION_SUBDEV,
368 NI_SERIAL_SUBDEV,
369 NI_RTSI_SUBDEV,
370 NI_GPCT0_SUBDEV,
371 NI_GPCT1_SUBDEV,
372 NI_FREQ_OUT_SUBDEV,
373 NI_NUM_SUBDEVICES
374 };
375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
376 {
377 switch (counter_index) {
378 case 0:
379 return NI_GPCT0_SUBDEV;
380 break;
381 case 1:
382 return NI_GPCT1_SUBDEV;
383 break;
384 default:
385 break;
386 }
387 BUG();
388 return NI_GPCT0_SUBDEV;
389 }
390
391 enum timebase_nanoseconds {
392 TIMEBASE_1_NS = 50,
393 TIMEBASE_2_NS = 10000
394 };
395
396 #define SERIAL_DISABLED 0
397 #define SERIAL_600NS 600
398 #define SERIAL_1_2US 1200
399 #define SERIAL_10US 10000
400
401 static const int num_adc_stages_611x = 3;
402
403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
404 unsigned ai_mite_status);
405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
406 unsigned ao_mite_status);
407 static void get_last_sample_611x(struct comedi_device *dev);
408 static void get_last_sample_6143(struct comedi_device *dev);
409
410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
411 unsigned bit_mask, unsigned bit_values)
412 {
413 struct ni_private *devpriv = dev->private;
414 unsigned long flags;
415
416 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
417 switch (reg) {
418 case Interrupt_A_Enable_Register:
419 devpriv->int_a_enable_reg &= ~bit_mask;
420 devpriv->int_a_enable_reg |= bit_values & bit_mask;
421 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
422 Interrupt_A_Enable_Register);
423 break;
424 case Interrupt_B_Enable_Register:
425 devpriv->int_b_enable_reg &= ~bit_mask;
426 devpriv->int_b_enable_reg |= bit_values & bit_mask;
427 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
428 Interrupt_B_Enable_Register);
429 break;
430 case IO_Bidirection_Pin_Register:
431 devpriv->io_bidirection_pin_reg &= ~bit_mask;
432 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
433 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
434 IO_Bidirection_Pin_Register);
435 break;
436 case AI_AO_Select:
437 devpriv->ai_ao_select_reg &= ~bit_mask;
438 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
439 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
440 break;
441 case G0_G1_Select:
442 devpriv->g0_g1_select_reg &= ~bit_mask;
443 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
444 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
445 break;
446 default:
447 printk("Warning %s() called with invalid register\n", __func__);
448 printk("reg is %d\n", reg);
449 break;
450 }
451 mmiowb();
452 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
453 }
454
455 #ifdef PCIDMA
456 static int ni_ai_drain_dma(struct comedi_device *dev);
457
458 /* DMA channel setup */
459
460 /* negative channel means no channel */
461 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
462 {
463 unsigned bitfield;
464
465 if (channel >= 0) {
466 bitfield =
467 (ni_stc_dma_channel_select_bitfield(channel) <<
468 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
469 } else {
470 bitfield = 0;
471 }
472 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
473 }
474
475 /* negative channel means no channel */
476 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
477 {
478 unsigned bitfield;
479
480 if (channel >= 0) {
481 bitfield =
482 (ni_stc_dma_channel_select_bitfield(channel) <<
483 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
484 } else {
485 bitfield = 0;
486 }
487 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
488 }
489
490 /* negative mite_channel means no channel */
491 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
492 unsigned gpct_index,
493 int mite_channel)
494 {
495 unsigned bitfield;
496
497 if (mite_channel >= 0) {
498 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
499 } else {
500 bitfield = 0;
501 }
502 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
503 bitfield);
504 }
505
506 /* negative mite_channel means no channel */
507 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
508 int mite_channel)
509 {
510 struct ni_private *devpriv = dev->private;
511 unsigned long flags;
512
513 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
514 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
515 if (mite_channel >= 0) {
516 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
517 under the assumption the cdio dma selection works just like ai/ao/gpct.
518 Definitely works for dma channels 0 and 1. */
519 devpriv->cdio_dma_select_reg |=
520 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
521 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
522 }
523 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
524 mmiowb();
525 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
526 }
527
528 static int ni_request_ai_mite_channel(struct comedi_device *dev)
529 {
530 struct ni_private *devpriv = dev->private;
531 unsigned long flags;
532
533 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
534 BUG_ON(devpriv->ai_mite_chan);
535 devpriv->ai_mite_chan =
536 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
537 if (devpriv->ai_mite_chan == NULL) {
538 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
539 comedi_error(dev,
540 "failed to reserve mite dma channel for analog input.");
541 return -EBUSY;
542 }
543 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
544 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
545 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
546 return 0;
547 }
548
549 static int ni_request_ao_mite_channel(struct comedi_device *dev)
550 {
551 struct ni_private *devpriv = dev->private;
552 unsigned long flags;
553
554 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
555 BUG_ON(devpriv->ao_mite_chan);
556 devpriv->ao_mite_chan =
557 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
558 if (devpriv->ao_mite_chan == NULL) {
559 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
560 comedi_error(dev,
561 "failed to reserve mite dma channel for analog outut.");
562 return -EBUSY;
563 }
564 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
565 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
566 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
567 return 0;
568 }
569
570 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
571 unsigned gpct_index,
572 enum comedi_io_direction direction)
573 {
574 struct ni_private *devpriv = dev->private;
575 unsigned long flags;
576 struct mite_channel *mite_chan;
577
578 BUG_ON(gpct_index >= NUM_GPCT);
579 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
580 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
581 mite_chan =
582 mite_request_channel(devpriv->mite,
583 devpriv->gpct_mite_ring[gpct_index]);
584 if (mite_chan == NULL) {
585 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
586 comedi_error(dev,
587 "failed to reserve mite dma channel for counter.");
588 return -EBUSY;
589 }
590 mite_chan->dir = direction;
591 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
592 mite_chan);
593 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
594 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
595 return 0;
596 }
597
598 #endif /* PCIDMA */
599
600 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
601 {
602 #ifdef PCIDMA
603 struct ni_private *devpriv = dev->private;
604 unsigned long flags;
605
606 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
607 BUG_ON(devpriv->cdo_mite_chan);
608 devpriv->cdo_mite_chan =
609 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
610 if (devpriv->cdo_mite_chan == NULL) {
611 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
612 comedi_error(dev,
613 "failed to reserve mite dma channel for correlated digital outut.");
614 return -EBUSY;
615 }
616 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
617 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
618 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
619 #endif /* PCIDMA */
620 return 0;
621 }
622
623 static void ni_release_ai_mite_channel(struct comedi_device *dev)
624 {
625 #ifdef PCIDMA
626 struct ni_private *devpriv = dev->private;
627 unsigned long flags;
628
629 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
630 if (devpriv->ai_mite_chan) {
631 ni_set_ai_dma_channel(dev, -1);
632 mite_release_channel(devpriv->ai_mite_chan);
633 devpriv->ai_mite_chan = NULL;
634 }
635 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
636 #endif /* PCIDMA */
637 }
638
639 static void ni_release_ao_mite_channel(struct comedi_device *dev)
640 {
641 #ifdef PCIDMA
642 struct ni_private *devpriv = dev->private;
643 unsigned long flags;
644
645 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
646 if (devpriv->ao_mite_chan) {
647 ni_set_ao_dma_channel(dev, -1);
648 mite_release_channel(devpriv->ao_mite_chan);
649 devpriv->ao_mite_chan = NULL;
650 }
651 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
652 #endif /* PCIDMA */
653 }
654
655 #ifdef PCIDMA
656 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
657 unsigned gpct_index)
658 {
659 struct ni_private *devpriv = dev->private;
660 unsigned long flags;
661
662 BUG_ON(gpct_index >= NUM_GPCT);
663 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
664 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
665 struct mite_channel *mite_chan =
666 devpriv->counter_dev->counters[gpct_index].mite_chan;
667
668 ni_set_gpct_dma_channel(dev, gpct_index, -1);
669 ni_tio_set_mite_channel(&devpriv->
670 counter_dev->counters[gpct_index],
671 NULL);
672 mite_release_channel(mite_chan);
673 }
674 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
675 }
676 #endif /* PCIDMA */
677
678 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
679 {
680 #ifdef PCIDMA
681 struct ni_private *devpriv = dev->private;
682 unsigned long flags;
683
684 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
685 if (devpriv->cdo_mite_chan) {
686 ni_set_cdo_dma_channel(dev, -1);
687 mite_release_channel(devpriv->cdo_mite_chan);
688 devpriv->cdo_mite_chan = NULL;
689 }
690 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
691 #endif /* PCIDMA */
692 }
693
694 /* e-series boards use the second irq signals to generate dma requests for their counters */
695 #ifdef PCIDMA
696 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
697 unsigned gpct_index, short enable)
698 {
699 const struct ni_board_struct *board = comedi_board(dev);
700 struct ni_private *devpriv = dev->private;
701
702 if (board->reg_type & ni_reg_m_series_mask)
703 return;
704 switch (gpct_index) {
705 case 0:
706 if (enable) {
707 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
708 Second_IRQ_A_Enable_Register);
709 } else {
710 devpriv->stc_writew(dev, 0,
711 Second_IRQ_A_Enable_Register);
712 }
713 break;
714 case 1:
715 if (enable) {
716 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
717 Second_IRQ_B_Enable_Register);
718 } else {
719 devpriv->stc_writew(dev, 0,
720 Second_IRQ_B_Enable_Register);
721 }
722 break;
723 default:
724 BUG();
725 break;
726 }
727 }
728 #endif /* PCIDMA */
729
730 static void ni_clear_ai_fifo(struct comedi_device *dev)
731 {
732 const struct ni_board_struct *board = comedi_board(dev);
733 struct ni_private *devpriv = dev->private;
734
735 if (board->reg_type == ni_reg_6143) {
736 /* Flush the 6143 data FIFO */
737 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
738 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
739 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
740 } else {
741 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
742 if (board->reg_type == ni_reg_625x) {
743 ni_writeb(0, M_Offset_Static_AI_Control(0));
744 ni_writeb(1, M_Offset_Static_AI_Control(0));
745 #if 0
746 /* the NI example code does 3 convert pulses for 625x boards,
747 but that appears to be wrong in practice. */
748 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
749 AI_Command_1_Register);
750 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
751 AI_Command_1_Register);
752 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
753 AI_Command_1_Register);
754 #endif
755 }
756 }
757 }
758
759 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
760 {
761 struct ni_private *devpriv = dev->private;
762
763 devpriv->stc_writew(dev, data >> 16, reg);
764 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
765 }
766
767 static uint32_t win_in2(struct comedi_device *dev, int reg)
768 {
769 struct ni_private *devpriv = dev->private;
770 uint32_t bits;
771
772 bits = devpriv->stc_readw(dev, reg) << 16;
773 bits |= devpriv->stc_readw(dev, reg + 1);
774 return bits;
775 }
776
777 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
778 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
779 int addr)
780 {
781 struct ni_private *devpriv = dev->private;
782 unsigned long flags;
783
784 spin_lock_irqsave(&devpriv->window_lock, flags);
785 ni_writew(addr, AO_Window_Address_611x);
786 ni_writew(data, AO_Window_Data_611x);
787 spin_unlock_irqrestore(&devpriv->window_lock, flags);
788 }
789
790 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
791 int addr)
792 {
793 struct ni_private *devpriv = dev->private;
794 unsigned long flags;
795
796 spin_lock_irqsave(&devpriv->window_lock, flags);
797 ni_writew(addr, AO_Window_Address_611x);
798 ni_writel(data, AO_Window_Data_611x);
799 spin_unlock_irqrestore(&devpriv->window_lock, flags);
800 }
801
802 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
803 {
804 struct ni_private *devpriv = dev->private;
805 unsigned long flags;
806 unsigned short data;
807
808 spin_lock_irqsave(&devpriv->window_lock, flags);
809 ni_writew(addr, AO_Window_Address_611x);
810 data = ni_readw(AO_Window_Data_611x);
811 spin_unlock_irqrestore(&devpriv->window_lock, flags);
812 return data;
813 }
814
815 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
816 * share registers (such as Interrupt_A_Register) without interfering with
817 * each other.
818 *
819 * NOTE: the switch/case statements are optimized out for a constant argument
820 * so this is actually quite fast--- If you must wrap another function around this
821 * make it inline to avoid a large speed penalty.
822 *
823 * value should only be 1 or 0.
824 */
825 static inline void ni_set_bits(struct comedi_device *dev, int reg,
826 unsigned bits, unsigned value)
827 {
828 unsigned bit_values;
829
830 if (value)
831 bit_values = bits;
832 else
833 bit_values = 0;
834 ni_set_bitfield(dev, reg, bits, bit_values);
835 }
836
837 static irqreturn_t ni_E_interrupt(int irq, void *d)
838 {
839 struct comedi_device *dev = d;
840 struct ni_private *devpriv = dev->private;
841 unsigned short a_status;
842 unsigned short b_status;
843 unsigned int ai_mite_status = 0;
844 unsigned int ao_mite_status = 0;
845 unsigned long flags;
846 #ifdef PCIDMA
847 struct mite_struct *mite = devpriv->mite;
848 #endif
849
850 if (!dev->attached)
851 return IRQ_NONE;
852 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
853
854 /* lock to avoid race with comedi_poll */
855 spin_lock_irqsave(&dev->spinlock, flags);
856 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
857 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
858 #ifdef PCIDMA
859 if (mite) {
860 unsigned long flags_too;
861
862 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
863 if (devpriv->ai_mite_chan) {
864 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
865 if (ai_mite_status & CHSR_LINKC)
866 writel(CHOR_CLRLC,
867 devpriv->mite->mite_io_addr +
868 MITE_CHOR(devpriv->
869 ai_mite_chan->channel));
870 }
871 if (devpriv->ao_mite_chan) {
872 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
873 if (ao_mite_status & CHSR_LINKC)
874 writel(CHOR_CLRLC,
875 mite->mite_io_addr +
876 MITE_CHOR(devpriv->
877 ao_mite_chan->channel));
878 }
879 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
880 }
881 #endif
882 ack_a_interrupt(dev, a_status);
883 ack_b_interrupt(dev, b_status);
884 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
885 handle_a_interrupt(dev, a_status, ai_mite_status);
886 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
887 handle_b_interrupt(dev, b_status, ao_mite_status);
888 handle_gpct_interrupt(dev, 0);
889 handle_gpct_interrupt(dev, 1);
890 handle_cdio_interrupt(dev);
891
892 spin_unlock_irqrestore(&dev->spinlock, flags);
893 return IRQ_HANDLED;
894 }
895
896 #ifdef PCIDMA
897 static void ni_sync_ai_dma(struct comedi_device *dev)
898 {
899 struct ni_private *devpriv = dev->private;
900 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
901 unsigned long flags;
902
903 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
904 if (devpriv->ai_mite_chan)
905 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
906 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
907 }
908
909 static void mite_handle_b_linkc(struct mite_struct *mite,
910 struct comedi_device *dev)
911 {
912 struct ni_private *devpriv = dev->private;
913 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
914 unsigned long flags;
915
916 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
917 if (devpriv->ao_mite_chan) {
918 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
919 }
920 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
921 }
922
923 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
924 {
925 struct ni_private *devpriv = dev->private;
926 static const int timeout = 10000;
927 int i;
928 for (i = 0; i < timeout; i++) {
929 unsigned short b_status;
930
931 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
932 if (b_status & AO_FIFO_Half_Full_St)
933 break;
934 /* if we poll too often, the pci bus activity seems
935 to slow the dma transfer down */
936 udelay(10);
937 }
938 if (i == timeout) {
939 comedi_error(dev, "timed out waiting for dma load");
940 return -EPIPE;
941 }
942 return 0;
943 }
944
945 #endif /* PCIDMA */
946 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
947 {
948 struct ni_private *devpriv = dev->private;
949
950 if (devpriv->aimode == AIMODE_SCAN) {
951 #ifdef PCIDMA
952 static const int timeout = 10;
953 int i;
954
955 for (i = 0; i < timeout; i++) {
956 ni_sync_ai_dma(dev);
957 if ((s->async->events & COMEDI_CB_EOS))
958 break;
959 udelay(1);
960 }
961 #else
962 ni_handle_fifo_dregs(dev);
963 s->async->events |= COMEDI_CB_EOS;
964 #endif
965 }
966 /* handle special case of single scan using AI_End_On_End_Of_Scan */
967 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
968 shutdown_ai_command(dev);
969 }
970 }
971
972 static void shutdown_ai_command(struct comedi_device *dev)
973 {
974 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
975
976 #ifdef PCIDMA
977 ni_ai_drain_dma(dev);
978 #endif
979 ni_handle_fifo_dregs(dev);
980 get_last_sample_611x(dev);
981 get_last_sample_6143(dev);
982
983 s->async->events |= COMEDI_CB_EOA;
984 }
985
986 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
987 {
988 if (s->
989 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
990 COMEDI_CB_EOA)) {
991 switch (s->index) {
992 case NI_AI_SUBDEV:
993 ni_ai_reset(dev, s);
994 break;
995 case NI_AO_SUBDEV:
996 ni_ao_reset(dev, s);
997 break;
998 case NI_GPCT0_SUBDEV:
999 case NI_GPCT1_SUBDEV:
1000 ni_gpct_cancel(dev, s);
1001 break;
1002 case NI_DIO_SUBDEV:
1003 ni_cdio_cancel(dev, s);
1004 break;
1005 default:
1006 break;
1007 }
1008 }
1009 comedi_event(dev, s);
1010 }
1011
1012 static void handle_gpct_interrupt(struct comedi_device *dev,
1013 unsigned short counter_index)
1014 {
1015 #ifdef PCIDMA
1016 struct ni_private *devpriv = dev->private;
1017 struct comedi_subdevice *s;
1018
1019 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1020
1021 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1022 s);
1023 if (s->async->events)
1024 ni_event(dev, s);
1025 #endif
1026 }
1027
1028 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1029 {
1030 struct ni_private *devpriv = dev->private;
1031 unsigned short ack = 0;
1032
1033 if (a_status & AI_SC_TC_St) {
1034 ack |= AI_SC_TC_Interrupt_Ack;
1035 }
1036 if (a_status & AI_START1_St) {
1037 ack |= AI_START1_Interrupt_Ack;
1038 }
1039 if (a_status & AI_START_St) {
1040 ack |= AI_START_Interrupt_Ack;
1041 }
1042 if (a_status & AI_STOP_St) {
1043 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1044 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1045 }
1046 if (ack)
1047 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1048 }
1049
1050 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1051 unsigned ai_mite_status)
1052 {
1053 struct ni_private *devpriv = dev->private;
1054 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1055
1056 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1057 if (s->type == COMEDI_SUBD_UNUSED)
1058 return;
1059
1060 #ifdef DEBUG_INTERRUPT
1061 printk
1062 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1063 status, ai_mite_status);
1064 ni_mio_print_status_a(status);
1065 #endif
1066 #ifdef PCIDMA
1067 if (ai_mite_status & CHSR_LINKC) {
1068 ni_sync_ai_dma(dev);
1069 }
1070
1071 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1072 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1073 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1074 printk
1075 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1076 ai_mite_status);
1077 /* mite_print_chsr(ai_mite_status); */
1078 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1079 /* disable_irq(dev->irq); */
1080 }
1081 #endif
1082
1083 /* test for all uncommon interrupt events at the same time */
1084 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1085 AI_SC_TC_St | AI_START1_St)) {
1086 if (status == 0xffff) {
1087 printk
1088 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1089 /* we probably aren't even running a command now,
1090 * so it's a good idea to be careful. */
1091 if (comedi_is_subdevice_running(s)) {
1092 s->async->events |=
1093 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1094 ni_event(dev, s);
1095 }
1096 return;
1097 }
1098 if (status & (AI_Overrun_St | AI_Overflow_St |
1099 AI_SC_TC_Error_St)) {
1100 printk("ni_mio_common: ai error a_status=%04x\n",
1101 status);
1102 ni_mio_print_status_a(status);
1103
1104 shutdown_ai_command(dev);
1105
1106 s->async->events |= COMEDI_CB_ERROR;
1107 if (status & (AI_Overrun_St | AI_Overflow_St))
1108 s->async->events |= COMEDI_CB_OVERFLOW;
1109
1110 ni_event(dev, s);
1111
1112 return;
1113 }
1114 if (status & AI_SC_TC_St) {
1115 #ifdef DEBUG_INTERRUPT
1116 printk("ni_mio_common: SC_TC interrupt\n");
1117 #endif
1118 if (!devpriv->ai_continuous) {
1119 shutdown_ai_command(dev);
1120 }
1121 }
1122 }
1123 #ifndef PCIDMA
1124 if (status & AI_FIFO_Half_Full_St) {
1125 int i;
1126 static const int timeout = 10;
1127 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1128 *fail to get the fifo less than half full, so loop to be sure.*/
1129 for (i = 0; i < timeout; ++i) {
1130 ni_handle_fifo_half_full(dev);
1131 if ((devpriv->stc_readw(dev,
1132 AI_Status_1_Register) &
1133 AI_FIFO_Half_Full_St) == 0)
1134 break;
1135 }
1136 }
1137 #endif /* !PCIDMA */
1138
1139 if ((status & AI_STOP_St)) {
1140 ni_handle_eos(dev, s);
1141 }
1142
1143 ni_event(dev, s);
1144
1145 #ifdef DEBUG_INTERRUPT
1146 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1147 if (status & Interrupt_A_St) {
1148 printk
1149 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1150 status);
1151 }
1152 #endif
1153 }
1154
1155 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1156 {
1157 struct ni_private *devpriv = dev->private;
1158 unsigned short ack = 0;
1159
1160 if (b_status & AO_BC_TC_St) {
1161 ack |= AO_BC_TC_Interrupt_Ack;
1162 }
1163 if (b_status & AO_Overrun_St) {
1164 ack |= AO_Error_Interrupt_Ack;
1165 }
1166 if (b_status & AO_START_St) {
1167 ack |= AO_START_Interrupt_Ack;
1168 }
1169 if (b_status & AO_START1_St) {
1170 ack |= AO_START1_Interrupt_Ack;
1171 }
1172 if (b_status & AO_UC_TC_St) {
1173 ack |= AO_UC_TC_Interrupt_Ack;
1174 }
1175 if (b_status & AO_UI2_TC_St) {
1176 ack |= AO_UI2_TC_Interrupt_Ack;
1177 }
1178 if (b_status & AO_UPDATE_St) {
1179 ack |= AO_UPDATE_Interrupt_Ack;
1180 }
1181 if (ack)
1182 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1183 }
1184
1185 static void handle_b_interrupt(struct comedi_device *dev,
1186 unsigned short b_status, unsigned ao_mite_status)
1187 {
1188 struct ni_private *devpriv = dev->private;
1189 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1190 /* unsigned short ack=0; */
1191
1192 #ifdef DEBUG_INTERRUPT
1193 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1194 b_status, ao_mite_status);
1195 ni_mio_print_status_b(b_status);
1196 #endif
1197
1198 #ifdef PCIDMA
1199 /* Currently, mite.c requires us to handle LINKC */
1200 if (ao_mite_status & CHSR_LINKC) {
1201 mite_handle_b_linkc(devpriv->mite, dev);
1202 }
1203
1204 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1205 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1206 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1207 printk
1208 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1209 ao_mite_status);
1210 /* mite_print_chsr(ao_mite_status); */
1211 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1212 }
1213 #endif
1214
1215 if (b_status == 0xffff)
1216 return;
1217 if (b_status & AO_Overrun_St) {
1218 printk
1219 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1220 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1221 s->async->events |= COMEDI_CB_OVERFLOW;
1222 }
1223
1224 if (b_status & AO_BC_TC_St) {
1225 MDPRINTK
1226 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1227 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1228 s->async->events |= COMEDI_CB_EOA;
1229 }
1230 #ifndef PCIDMA
1231 if (b_status & AO_FIFO_Request_St) {
1232 int ret;
1233
1234 ret = ni_ao_fifo_half_empty(dev, s);
1235 if (!ret) {
1236 printk("ni_mio_common: AO buffer underrun\n");
1237 ni_set_bits(dev, Interrupt_B_Enable_Register,
1238 AO_FIFO_Interrupt_Enable |
1239 AO_Error_Interrupt_Enable, 0);
1240 s->async->events |= COMEDI_CB_OVERFLOW;
1241 }
1242 }
1243 #endif
1244
1245 ni_event(dev, s);
1246 }
1247
1248 #ifdef DEBUG_STATUS_A
1249 static const char *const status_a_strings[] = {
1250 "passthru0", "fifo", "G0_gate", "G0_TC",
1251 "stop", "start", "sc_tc", "start1",
1252 "start2", "sc_tc_error", "overflow", "overrun",
1253 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1254 };
1255
1256 static void ni_mio_print_status_a(int status)
1257 {
1258 int i;
1259
1260 printk("A status:");
1261 for (i = 15; i >= 0; i--) {
1262 if (status & (1 << i)) {
1263 printk(" %s", status_a_strings[i]);
1264 }
1265 }
1266 printk("\n");
1267 }
1268 #endif
1269
1270 #ifdef DEBUG_STATUS_B
1271 static const char *const status_b_strings[] = {
1272 "passthru1", "fifo", "G1_gate", "G1_TC",
1273 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1274 "start1", "overrun", "start", "bc_tc_error",
1275 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1276 };
1277
1278 static void ni_mio_print_status_b(int status)
1279 {
1280 int i;
1281
1282 printk("B status:");
1283 for (i = 15; i >= 0; i--) {
1284 if (status & (1 << i)) {
1285 printk(" %s", status_b_strings[i]);
1286 }
1287 }
1288 printk("\n");
1289 }
1290 #endif
1291
1292 #ifndef PCIDMA
1293
1294 static void ni_ao_fifo_load(struct comedi_device *dev,
1295 struct comedi_subdevice *s, int n)
1296 {
1297 const struct ni_board_struct *board = comedi_board(dev);
1298 struct comedi_async *async = s->async;
1299 struct comedi_cmd *cmd = &async->cmd;
1300 int chan;
1301 int i;
1302 short d;
1303 u32 packed_data;
1304 int range;
1305 int err = 1;
1306
1307 chan = async->cur_chan;
1308 for (i = 0; i < n; i++) {
1309 err &= comedi_buf_get(async, &d);
1310 if (err == 0)
1311 break;
1312
1313 range = CR_RANGE(cmd->chanlist[chan]);
1314
1315 if (board->reg_type & ni_reg_6xxx_mask) {
1316 packed_data = d & 0xffff;
1317 /* 6711 only has 16 bit wide ao fifo */
1318 if (board->reg_type != ni_reg_6711) {
1319 err &= comedi_buf_get(async, &d);
1320 if (err == 0)
1321 break;
1322 chan++;
1323 i++;
1324 packed_data |= (d << 16) & 0xffff0000;
1325 }
1326 ni_writel(packed_data, DAC_FIFO_Data_611x);
1327 } else {
1328 ni_writew(d, DAC_FIFO_Data);
1329 }
1330 chan++;
1331 chan %= cmd->chanlist_len;
1332 }
1333 async->cur_chan = chan;
1334 if (err == 0) {
1335 async->events |= COMEDI_CB_OVERFLOW;
1336 }
1337 }
1338
1339 /*
1340 * There's a small problem if the FIFO gets really low and we
1341 * don't have the data to fill it. Basically, if after we fill
1342 * the FIFO with all the data available, the FIFO is _still_
1343 * less than half full, we never clear the interrupt. If the
1344 * IRQ is in edge mode, we never get another interrupt, because
1345 * this one wasn't cleared. If in level mode, we get flooded
1346 * with interrupts that we can't fulfill, because nothing ever
1347 * gets put into the buffer.
1348 *
1349 * This kind of situation is recoverable, but it is easier to
1350 * just pretend we had a FIFO underrun, since there is a good
1351 * chance it will happen anyway. This is _not_ the case for
1352 * RT code, as RT code might purposely be running close to the
1353 * metal. Needs to be fixed eventually.
1354 */
1355 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1356 struct comedi_subdevice *s)
1357 {
1358 const struct ni_board_struct *board = comedi_board(dev);
1359 int n;
1360
1361 n = comedi_buf_read_n_available(s->async);
1362 if (n == 0) {
1363 s->async->events |= COMEDI_CB_OVERFLOW;
1364 return 0;
1365 }
1366
1367 n /= sizeof(short);
1368 if (n > board->ao_fifo_depth / 2)
1369 n = board->ao_fifo_depth / 2;
1370
1371 ni_ao_fifo_load(dev, s, n);
1372
1373 s->async->events |= COMEDI_CB_BLOCK;
1374
1375 return 1;
1376 }
1377
1378 static int ni_ao_prep_fifo(struct comedi_device *dev,
1379 struct comedi_subdevice *s)
1380 {
1381 const struct ni_board_struct *board = comedi_board(dev);
1382 struct ni_private *devpriv = dev->private;
1383 int n;
1384
1385 /* reset fifo */
1386 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1387 if (board->reg_type & ni_reg_6xxx_mask)
1388 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1389
1390 /* load some data */
1391 n = comedi_buf_read_n_available(s->async);
1392 if (n == 0)
1393 return 0;
1394
1395 n /= sizeof(short);
1396 if (n > board->ao_fifo_depth)
1397 n = board->ao_fifo_depth;
1398
1399 ni_ao_fifo_load(dev, s, n);
1400
1401 return n;
1402 }
1403
1404 static void ni_ai_fifo_read(struct comedi_device *dev,
1405 struct comedi_subdevice *s, int n)
1406 {
1407 const struct ni_board_struct *board = comedi_board(dev);
1408 struct ni_private *devpriv = dev->private;
1409 struct comedi_async *async = s->async;
1410 int i;
1411
1412 if (board->reg_type == ni_reg_611x) {
1413 short data[2];
1414 u32 dl;
1415
1416 for (i = 0; i < n / 2; i++) {
1417 dl = ni_readl(ADC_FIFO_Data_611x);
1418 /* This may get the hi/lo data in the wrong order */
1419 data[0] = (dl >> 16) & 0xffff;
1420 data[1] = dl & 0xffff;
1421 cfc_write_array_to_buffer(s, data, sizeof(data));
1422 }
1423 /* Check if there's a single sample stuck in the FIFO */
1424 if (n % 2) {
1425 dl = ni_readl(ADC_FIFO_Data_611x);
1426 data[0] = dl & 0xffff;
1427 cfc_write_to_buffer(s, data[0]);
1428 }
1429 } else if (board->reg_type == ni_reg_6143) {
1430 short data[2];
1431 u32 dl;
1432
1433 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1434 for (i = 0; i < n / 2; i++) {
1435 dl = ni_readl(AIFIFO_Data_6143);
1436
1437 data[0] = (dl >> 16) & 0xffff;
1438 data[1] = dl & 0xffff;
1439 cfc_write_array_to_buffer(s, data, sizeof(data));
1440 }
1441 if (n % 2) {
1442 /* Assume there is a single sample stuck in the FIFO */
1443 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1444 dl = ni_readl(AIFIFO_Data_6143);
1445 data[0] = (dl >> 16) & 0xffff;
1446 cfc_write_to_buffer(s, data[0]);
1447 }
1448 } else {
1449 if (n > sizeof(devpriv->ai_fifo_buffer) /
1450 sizeof(devpriv->ai_fifo_buffer[0])) {
1451 comedi_error(dev, "bug! ai_fifo_buffer too small");
1452 async->events |= COMEDI_CB_ERROR;
1453 return;
1454 }
1455 for (i = 0; i < n; i++) {
1456 devpriv->ai_fifo_buffer[i] =
1457 ni_readw(ADC_FIFO_Data_Register);
1458 }
1459 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1460 n *
1461 sizeof(devpriv->ai_fifo_buffer[0]));
1462 }
1463 }
1464
1465 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1466 {
1467 const struct ni_board_struct *board = comedi_board(dev);
1468 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1469 int n;
1470
1471 n = board->ai_fifo_depth / 2;
1472
1473 ni_ai_fifo_read(dev, s, n);
1474 }
1475 #endif
1476
1477 #ifdef PCIDMA
1478 static int ni_ai_drain_dma(struct comedi_device *dev)
1479 {
1480 struct ni_private *devpriv = dev->private;
1481 int i;
1482 static const int timeout = 10000;
1483 unsigned long flags;
1484 int retval = 0;
1485
1486 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1487 if (devpriv->ai_mite_chan) {
1488 for (i = 0; i < timeout; i++) {
1489 if ((devpriv->stc_readw(dev,
1490 AI_Status_1_Register) &
1491 AI_FIFO_Empty_St)
1492 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1493 0)
1494 break;
1495 udelay(5);
1496 }
1497 if (i == timeout) {
1498 printk("ni_mio_common: wait for dma drain timed out\n");
1499 printk
1500 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1501 mite_bytes_in_transit(devpriv->ai_mite_chan),
1502 devpriv->stc_readw(dev, AI_Status_1_Register));
1503 retval = -1;
1504 }
1505 }
1506 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1507
1508 ni_sync_ai_dma(dev);
1509
1510 return retval;
1511 }
1512 #endif
1513 /*
1514 Empties the AI fifo
1515 */
1516 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1517 {
1518 const struct ni_board_struct *board = comedi_board(dev);
1519 struct ni_private *devpriv = dev->private;
1520 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1521 short data[2];
1522 u32 dl;
1523 short fifo_empty;
1524 int i;
1525
1526 if (board->reg_type == ni_reg_611x) {
1527 while ((devpriv->stc_readw(dev,
1528 AI_Status_1_Register) &
1529 AI_FIFO_Empty_St) == 0) {
1530 dl = ni_readl(ADC_FIFO_Data_611x);
1531
1532 /* This may get the hi/lo data in the wrong order */
1533 data[0] = (dl >> 16);
1534 data[1] = (dl & 0xffff);
1535 cfc_write_array_to_buffer(s, data, sizeof(data));
1536 }
1537 } else if (board->reg_type == ni_reg_6143) {
1538 i = 0;
1539 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1540 dl = ni_readl(AIFIFO_Data_6143);
1541
1542 /* This may get the hi/lo data in the wrong order */
1543 data[0] = (dl >> 16);
1544 data[1] = (dl & 0xffff);
1545 cfc_write_array_to_buffer(s, data, sizeof(data));
1546 i += 2;
1547 }
1548 /* Check if stranded sample is present */
1549 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1550 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1551 dl = ni_readl(AIFIFO_Data_6143);
1552 data[0] = (dl >> 16) & 0xffff;
1553 cfc_write_to_buffer(s, data[0]);
1554 }
1555
1556 } else {
1557 fifo_empty =
1558 devpriv->stc_readw(dev,
1559 AI_Status_1_Register) & AI_FIFO_Empty_St;
1560 while (fifo_empty == 0) {
1561 for (i = 0;
1562 i <
1563 sizeof(devpriv->ai_fifo_buffer) /
1564 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1565 fifo_empty =
1566 devpriv->stc_readw(dev,
1567 AI_Status_1_Register) &
1568 AI_FIFO_Empty_St;
1569 if (fifo_empty)
1570 break;
1571 devpriv->ai_fifo_buffer[i] =
1572 ni_readw(ADC_FIFO_Data_Register);
1573 }
1574 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1575 i *
1576 sizeof(devpriv->
1577 ai_fifo_buffer[0]));
1578 }
1579 }
1580 }
1581
1582 static void get_last_sample_611x(struct comedi_device *dev)
1583 {
1584 const struct ni_board_struct *board = comedi_board(dev);
1585 struct ni_private *devpriv __maybe_unused = dev->private;
1586 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1587 short data;
1588 u32 dl;
1589
1590 if (board->reg_type != ni_reg_611x)
1591 return;
1592
1593 /* Check if there's a single sample stuck in the FIFO */
1594 if (ni_readb(XXX_Status) & 0x80) {
1595 dl = ni_readl(ADC_FIFO_Data_611x);
1596 data = (dl & 0xffff);
1597 cfc_write_to_buffer(s, data);
1598 }
1599 }
1600
1601 static void get_last_sample_6143(struct comedi_device *dev)
1602 {
1603 const struct ni_board_struct *board = comedi_board(dev);
1604 struct ni_private *devpriv __maybe_unused = dev->private;
1605 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1606 short data;
1607 u32 dl;
1608
1609 if (board->reg_type != ni_reg_6143)
1610 return;
1611
1612 /* Check if there's a single sample stuck in the FIFO */
1613 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1614 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1615 dl = ni_readl(AIFIFO_Data_6143);
1616
1617 /* This may get the hi/lo data in the wrong order */
1618 data = (dl >> 16) & 0xffff;
1619 cfc_write_to_buffer(s, data);
1620 }
1621 }
1622
1623 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1624 void *data, unsigned int num_bytes,
1625 unsigned int chan_index)
1626 {
1627 struct ni_private *devpriv = dev->private;
1628 struct comedi_async *async = s->async;
1629 unsigned int i;
1630 unsigned int length = num_bytes / bytes_per_sample(s);
1631 short *array = data;
1632 unsigned int *larray = data;
1633
1634 for (i = 0; i < length; i++) {
1635 #ifdef PCIDMA
1636 if (s->subdev_flags & SDF_LSAMPL)
1637 larray[i] = le32_to_cpu(larray[i]);
1638 else
1639 array[i] = le16_to_cpu(array[i]);
1640 #endif
1641 if (s->subdev_flags & SDF_LSAMPL)
1642 larray[i] += devpriv->ai_offset[chan_index];
1643 else
1644 array[i] += devpriv->ai_offset[chan_index];
1645 chan_index++;
1646 chan_index %= async->cmd.chanlist_len;
1647 }
1648 }
1649
1650 #ifdef PCIDMA
1651
1652 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1653 {
1654 const struct ni_board_struct *board = comedi_board(dev);
1655 struct ni_private *devpriv = dev->private;
1656 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1657 int retval;
1658 unsigned long flags;
1659
1660 retval = ni_request_ai_mite_channel(dev);
1661 if (retval)
1662 return retval;
1663 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1664
1665 /* write alloc the entire buffer */
1666 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1667
1668 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1669 if (devpriv->ai_mite_chan == NULL) {
1670 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1671 return -EIO;
1672 }
1673
1674 switch (board->reg_type) {
1675 case ni_reg_611x:
1676 case ni_reg_6143:
1677 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1678 break;
1679 case ni_reg_628x:
1680 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1681 break;
1682 default:
1683 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1684 break;
1685 }
1686 /*start the MITE */
1687 mite_dma_arm(devpriv->ai_mite_chan);
1688 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1689
1690 return 0;
1691 }
1692
1693 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1694 {
1695 const struct ni_board_struct *board = comedi_board(dev);
1696 struct ni_private *devpriv = dev->private;
1697 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1698 int retval;
1699 unsigned long flags;
1700
1701 retval = ni_request_ao_mite_channel(dev);
1702 if (retval)
1703 return retval;
1704
1705 /* read alloc the entire buffer */
1706 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1707
1708 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1709 if (devpriv->ao_mite_chan) {
1710 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1711 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1712 } else {
1713 /* doing 32 instead of 16 bit wide transfers from memory
1714 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1715 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1716 }
1717 mite_dma_arm(devpriv->ao_mite_chan);
1718 } else
1719 retval = -EIO;
1720 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1721
1722 return retval;
1723 }
1724
1725 #endif /* PCIDMA */
1726
1727 /*
1728 used for both cancel ioctl and board initialization
1729
1730 this is pretty harsh for a cancel, but it works...
1731 */
1732
1733 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1734 {
1735 const struct ni_board_struct *board = comedi_board(dev);
1736 struct ni_private *devpriv = dev->private;
1737
1738 ni_release_ai_mite_channel(dev);
1739 /* ai configuration */
1740 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1741 Joint_Reset_Register);
1742
1743 ni_set_bits(dev, Interrupt_A_Enable_Register,
1744 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1745 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1746 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1747 AI_FIFO_Interrupt_Enable, 0);
1748
1749 ni_clear_ai_fifo(dev);
1750
1751 if (board->reg_type != ni_reg_6143)
1752 ni_writeb(0, Misc_Command);
1753
1754 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1755 devpriv->stc_writew(dev,
1756 AI_Start_Stop | AI_Mode_1_Reserved
1757 /*| AI_Trigger_Once */ ,
1758 AI_Mode_1_Register);
1759 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1760 /* generate FIFO interrupts on non-empty */
1761 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1762 if (board->reg_type == ni_reg_611x) {
1763 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1764 AI_SOC_Polarity |
1765 AI_LOCALMUX_CLK_Pulse_Width,
1766 AI_Personal_Register);
1767 devpriv->stc_writew(dev,
1768 AI_SCAN_IN_PROG_Output_Select(3) |
1769 AI_EXTMUX_CLK_Output_Select(0) |
1770 AI_LOCALMUX_CLK_Output_Select(2) |
1771 AI_SC_TC_Output_Select(3) |
1772 AI_CONVERT_Output_Select
1773 (AI_CONVERT_Output_Enable_High),
1774 AI_Output_Control_Register);
1775 } else if (board->reg_type == ni_reg_6143) {
1776 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1777 AI_SOC_Polarity |
1778 AI_LOCALMUX_CLK_Pulse_Width,
1779 AI_Personal_Register);
1780 devpriv->stc_writew(dev,
1781 AI_SCAN_IN_PROG_Output_Select(3) |
1782 AI_EXTMUX_CLK_Output_Select(0) |
1783 AI_LOCALMUX_CLK_Output_Select(2) |
1784 AI_SC_TC_Output_Select(3) |
1785 AI_CONVERT_Output_Select
1786 (AI_CONVERT_Output_Enable_Low),
1787 AI_Output_Control_Register);
1788 } else {
1789 unsigned ai_output_control_bits;
1790 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1791 AI_SOC_Polarity |
1792 AI_CONVERT_Pulse_Width |
1793 AI_LOCALMUX_CLK_Pulse_Width,
1794 AI_Personal_Register);
1795 ai_output_control_bits =
1796 AI_SCAN_IN_PROG_Output_Select(3) |
1797 AI_EXTMUX_CLK_Output_Select(0) |
1798 AI_LOCALMUX_CLK_Output_Select(2) |
1799 AI_SC_TC_Output_Select(3);
1800 if (board->reg_type == ni_reg_622x)
1801 ai_output_control_bits |=
1802 AI_CONVERT_Output_Select
1803 (AI_CONVERT_Output_Enable_High);
1804 else
1805 ai_output_control_bits |=
1806 AI_CONVERT_Output_Select
1807 (AI_CONVERT_Output_Enable_Low);
1808 devpriv->stc_writew(dev, ai_output_control_bits,
1809 AI_Output_Control_Register);
1810 }
1811 /* the following registers should not be changed, because there
1812 * are no backup registers in devpriv. If you want to change
1813 * any of these, add a backup register and other appropriate code:
1814 * AI_Mode_1_Register
1815 * AI_Mode_3_Register
1816 * AI_Personal_Register
1817 * AI_Output_Control_Register
1818 */
1819 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1820
1821 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1822
1823 return 0;
1824 }
1825
1826 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1827 {
1828 unsigned long flags;
1829 int count;
1830
1831 /* lock to avoid race with interrupt handler */
1832 spin_lock_irqsave(&dev->spinlock, flags);
1833 #ifndef PCIDMA
1834 ni_handle_fifo_dregs(dev);
1835 #else
1836 ni_sync_ai_dma(dev);
1837 #endif
1838 count = s->async->buf_write_count - s->async->buf_read_count;
1839 spin_unlock_irqrestore(&dev->spinlock, flags);
1840
1841 return count;
1842 }
1843
1844 static int ni_ai_insn_read(struct comedi_device *dev,
1845 struct comedi_subdevice *s, struct comedi_insn *insn,
1846 unsigned int *data)
1847 {
1848 const struct ni_board_struct *board = comedi_board(dev);
1849 struct ni_private *devpriv = dev->private;
1850 int i, n;
1851 const unsigned int mask = (1 << board->adbits) - 1;
1852 unsigned signbits;
1853 unsigned short d;
1854 unsigned long dl;
1855
1856 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1857
1858 ni_clear_ai_fifo(dev);
1859
1860 signbits = devpriv->ai_offset[0];
1861 if (board->reg_type == ni_reg_611x) {
1862 for (n = 0; n < num_adc_stages_611x; n++) {
1863 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1864 AI_Command_1_Register);
1865 udelay(1);
1866 }
1867 for (n = 0; n < insn->n; n++) {
1868 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1869 AI_Command_1_Register);
1870 /* The 611x has screwy 32-bit FIFOs. */
1871 d = 0;
1872 for (i = 0; i < NI_TIMEOUT; i++) {
1873 if (ni_readb(XXX_Status) & 0x80) {
1874 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1875 & 0xffff;
1876 break;
1877 }
1878 if (!(devpriv->stc_readw(dev,
1879 AI_Status_1_Register) &
1880 AI_FIFO_Empty_St)) {
1881 d = ni_readl(ADC_FIFO_Data_611x) &
1882 0xffff;
1883 break;
1884 }
1885 }
1886 if (i == NI_TIMEOUT) {
1887 printk
1888 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1889 return -ETIME;
1890 }
1891 d += signbits;
1892 data[n] = d;
1893 }
1894 } else if (board->reg_type == ni_reg_6143) {
1895 for (n = 0; n < insn->n; n++) {
1896 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1897 AI_Command_1_Register);
1898
1899 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1900 dl = 0;
1901 for (i = 0; i < NI_TIMEOUT; i++) {
1902 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1903 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1904 dl = ni_readl(AIFIFO_Data_6143);
1905 break;
1906 }
1907 }
1908 if (i == NI_TIMEOUT) {
1909 printk
1910 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1911 return -ETIME;
1912 }
1913 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1914 }
1915 } else {
1916 for (n = 0; n < insn->n; n++) {
1917 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1918 AI_Command_1_Register);
1919 for (i = 0; i < NI_TIMEOUT; i++) {
1920 if (!(devpriv->stc_readw(dev,
1921 AI_Status_1_Register) &
1922 AI_FIFO_Empty_St))
1923 break;
1924 }
1925 if (i == NI_TIMEOUT) {
1926 printk
1927 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1928 return -ETIME;
1929 }
1930 if (board->reg_type & ni_reg_m_series_mask) {
1931 data[n] =
1932 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1933 } else {
1934 d = ni_readw(ADC_FIFO_Data_Register);
1935 d += signbits; /* subtle: needs to be short addition */
1936 data[n] = d;
1937 }
1938 }
1939 }
1940 return insn->n;
1941 }
1942
1943 static void ni_prime_channelgain_list(struct comedi_device *dev)
1944 {
1945 struct ni_private *devpriv = dev->private;
1946 int i;
1947
1948 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1949 for (i = 0; i < NI_TIMEOUT; ++i) {
1950 if (!(devpriv->stc_readw(dev,
1951 AI_Status_1_Register) &
1952 AI_FIFO_Empty_St)) {
1953 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1954 return;
1955 }
1956 udelay(1);
1957 }
1958 printk("ni_mio_common: timeout loading channel/gain list\n");
1959 }
1960
1961 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1962 unsigned int n_chan,
1963 unsigned int *list)
1964 {
1965 const struct ni_board_struct *board = comedi_board(dev);
1966 struct ni_private *devpriv = dev->private;
1967 unsigned int chan, range, aref;
1968 unsigned int i;
1969 unsigned offset;
1970 unsigned int dither;
1971 unsigned range_code;
1972
1973 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1974
1975 /* offset = 1 << (board->adbits - 1); */
1976 if ((list[0] & CR_ALT_SOURCE)) {
1977 unsigned bypass_bits;
1978 chan = CR_CHAN(list[0]);
1979 range = CR_RANGE(list[0]);
1980 range_code = ni_gainlkup[board->gainlkup][range];
1981 dither = ((list[0] & CR_ALT_FILTER) != 0);
1982 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1983 bypass_bits |= chan;
1984 bypass_bits |=
1985 (devpriv->ai_calib_source) &
1986 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1987 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1988 MSeries_AI_Bypass_Mode_Mux_Mask |
1989 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1990 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1991 if (dither)
1992 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1993 /* don't use 2's complement encoding */
1994 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1995 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1996 } else {
1997 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1998 }
1999 offset = 0;
2000 for (i = 0; i < n_chan; i++) {
2001 unsigned config_bits = 0;
2002 chan = CR_CHAN(list[i]);
2003 aref = CR_AREF(list[i]);
2004 range = CR_RANGE(list[i]);
2005 dither = ((list[i] & CR_ALT_FILTER) != 0);
2006
2007 range_code = ni_gainlkup[board->gainlkup][range];
2008 devpriv->ai_offset[i] = offset;
2009 switch (aref) {
2010 case AREF_DIFF:
2011 config_bits |=
2012 MSeries_AI_Config_Channel_Type_Differential_Bits;
2013 break;
2014 case AREF_COMMON:
2015 config_bits |=
2016 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2017 break;
2018 case AREF_GROUND:
2019 config_bits |=
2020 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2021 break;
2022 case AREF_OTHER:
2023 break;
2024 }
2025 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2026 config_bits |=
2027 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2028 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2029 if (i == n_chan - 1)
2030 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2031 if (dither)
2032 config_bits |= MSeries_AI_Config_Dither_Bit;
2033 /* don't use 2's complement encoding */
2034 config_bits |= MSeries_AI_Config_Polarity_Bit;
2035 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2036 }
2037 ni_prime_channelgain_list(dev);
2038 }
2039
2040 /*
2041 * Notes on the 6110 and 6111:
2042 * These boards a slightly different than the rest of the series, since
2043 * they have multiple A/D converters.
2044 * From the driver side, the configuration memory is a
2045 * little different.
2046 * Configuration Memory Low:
2047 * bits 15-9: same
2048 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2049 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2050 * 1001 gain=0.1 (+/- 50)
2051 * 1010 0.2
2052 * 1011 0.1
2053 * 0001 1
2054 * 0010 2
2055 * 0011 5
2056 * 0100 10
2057 * 0101 20
2058 * 0110 50
2059 * Configuration Memory High:
2060 * bits 12-14: Channel Type
2061 * 001 for differential
2062 * 000 for calibration
2063 * bit 11: coupling (this is not currently handled)
2064 * 1 AC coupling
2065 * 0 DC coupling
2066 * bits 0-2: channel
2067 * valid channels are 0-3
2068 */
2069 static void ni_load_channelgain_list(struct comedi_device *dev,
2070 unsigned int n_chan, unsigned int *list)
2071 {
2072 const struct ni_board_struct *board = comedi_board(dev);
2073 struct ni_private *devpriv = dev->private;
2074 unsigned int chan, range, aref;
2075 unsigned int i;
2076 unsigned int hi, lo;
2077 unsigned offset;
2078 unsigned int dither;
2079
2080 if (board->reg_type & ni_reg_m_series_mask) {
2081 ni_m_series_load_channelgain_list(dev, n_chan, list);
2082 return;
2083 }
2084 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2085 && (board->reg_type != ni_reg_6143)) {
2086 if (devpriv->changain_state
2087 && devpriv->changain_spec == list[0]) {
2088 /* ready to go. */
2089 return;
2090 }
2091 devpriv->changain_state = 1;
2092 devpriv->changain_spec = list[0];
2093 } else {
2094 devpriv->changain_state = 0;
2095 }
2096
2097 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2098
2099 /* Set up Calibration mode if required */
2100 if (board->reg_type == ni_reg_6143) {
2101 if ((list[0] & CR_ALT_SOURCE)
2102 && !devpriv->ai_calib_source_enabled) {
2103 /* Strobe Relay enable bit */
2104 ni_writew(devpriv->ai_calib_source |
2105 Calibration_Channel_6143_RelayOn,
2106 Calibration_Channel_6143);
2107 ni_writew(devpriv->ai_calib_source,
2108 Calibration_Channel_6143);
2109 devpriv->ai_calib_source_enabled = 1;
2110 msleep_interruptible(100); /* Allow relays to change */
2111 } else if (!(list[0] & CR_ALT_SOURCE)
2112 && devpriv->ai_calib_source_enabled) {
2113 /* Strobe Relay disable bit */
2114 ni_writew(devpriv->ai_calib_source |
2115 Calibration_Channel_6143_RelayOff,
2116 Calibration_Channel_6143);
2117 ni_writew(devpriv->ai_calib_source,
2118 Calibration_Channel_6143);
2119 devpriv->ai_calib_source_enabled = 0;
2120 msleep_interruptible(100); /* Allow relays to change */
2121 }
2122 }
2123
2124 offset = 1 << (board->adbits - 1);
2125 for (i = 0; i < n_chan; i++) {
2126 if ((board->reg_type != ni_reg_6143)
2127 && (list[i] & CR_ALT_SOURCE)) {
2128 chan = devpriv->ai_calib_source;
2129 } else {
2130 chan = CR_CHAN(list[i]);
2131 }
2132 aref = CR_AREF(list[i]);
2133 range = CR_RANGE(list[i]);
2134 dither = ((list[i] & CR_ALT_FILTER) != 0);
2135
2136 /* fix the external/internal range differences */
2137 range = ni_gainlkup[board->gainlkup][range];
2138 if (board->reg_type == ni_reg_611x)
2139 devpriv->ai_offset[i] = offset;
2140 else
2141 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2142
2143 hi = 0;
2144 if ((list[i] & CR_ALT_SOURCE)) {
2145 if (board->reg_type == ni_reg_611x)
2146 ni_writew(CR_CHAN(list[i]) & 0x0003,
2147 Calibration_Channel_Select_611x);
2148 } else {
2149 if (board->reg_type == ni_reg_611x)
2150 aref = AREF_DIFF;
2151 else if (board->reg_type == ni_reg_6143)
2152 aref = AREF_OTHER;
2153 switch (aref) {
2154 case AREF_DIFF:
2155 hi |= AI_DIFFERENTIAL;
2156 break;
2157 case AREF_COMMON:
2158 hi |= AI_COMMON;
2159 break;
2160 case AREF_GROUND:
2161 hi |= AI_GROUND;
2162 break;
2163 case AREF_OTHER:
2164 break;
2165 }
2166 }
2167 hi |= AI_CONFIG_CHANNEL(chan);
2168
2169 ni_writew(hi, Configuration_Memory_High);
2170
2171 if (board->reg_type != ni_reg_6143) {
2172 lo = range;
2173 if (i == n_chan - 1)
2174 lo |= AI_LAST_CHANNEL;
2175 if (dither)
2176 lo |= AI_DITHER;
2177
2178 ni_writew(lo, Configuration_Memory_Low);
2179 }
2180 }
2181
2182 /* prime the channel/gain list */
2183 if ((board->reg_type != ni_reg_611x)
2184 && (board->reg_type != ni_reg_6143)) {
2185 ni_prime_channelgain_list(dev);
2186 }
2187 }
2188
2189 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2190 int round_mode)
2191 {
2192 struct ni_private *devpriv = dev->private;
2193 int divider;
2194
2195 switch (round_mode) {
2196 case TRIG_ROUND_NEAREST:
2197 default:
2198 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2199 break;
2200 case TRIG_ROUND_DOWN:
2201 divider = (nanosec) / devpriv->clock_ns;
2202 break;
2203 case TRIG_ROUND_UP:
2204 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2205 break;
2206 }
2207 return divider - 1;
2208 }
2209
2210 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2211 {
2212 struct ni_private *devpriv = dev->private;
2213
2214 return devpriv->clock_ns * (timer + 1);
2215 }
2216
2217 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2218 unsigned num_channels)
2219 {
2220 const struct ni_board_struct *board = comedi_board(dev);
2221
2222 switch (board->reg_type) {
2223 case ni_reg_611x:
2224 case ni_reg_6143:
2225 /* simultaneously-sampled inputs */
2226 return board->ai_speed;
2227 break;
2228 default:
2229 /* multiplexed inputs */
2230 break;
2231 }
2232 return board->ai_speed * num_channels;
2233 }
2234
2235 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2236 struct comedi_cmd *cmd)
2237 {
2238 const struct ni_board_struct *board = comedi_board(dev);
2239 struct ni_private *devpriv = dev->private;
2240 int err = 0;
2241 int tmp;
2242 unsigned int sources;
2243
2244 /* Step 1 : check if triggers are trivially valid */
2245
2246 if ((cmd->flags & CMDF_WRITE))
2247 cmd->flags &= ~CMDF_WRITE;
2248
2249 err |= cfc_check_trigger_src(&cmd->start_src,
2250 TRIG_NOW | TRIG_INT | TRIG_EXT);
2251 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2252 TRIG_TIMER | TRIG_EXT);
2253
2254 sources = TRIG_TIMER | TRIG_EXT;
2255 if (board->reg_type == ni_reg_611x ||
2256 board->reg_type == ni_reg_6143)
2257 sources |= TRIG_NOW;
2258 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2259
2260 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2261 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2262
2263 if (err)
2264 return 1;
2265
2266 /* Step 2a : make sure trigger sources are unique */
2267
2268 err |= cfc_check_trigger_is_unique(cmd->start_src);
2269 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2270 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2271 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2272
2273 /* Step 2b : and mutually compatible */
2274
2275 if (err)
2276 return 2;
2277
2278 /* Step 3: check if arguments are trivially valid */
2279
2280 if (cmd->start_src == TRIG_EXT) {
2281 /* external trigger */
2282 unsigned int tmp = CR_CHAN(cmd->start_arg);
2283
2284 if (tmp > 16)
2285 tmp = 16;
2286 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2287 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2288 } else {
2289 /* true for both TRIG_NOW and TRIG_INT */
2290 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2291 }
2292
2293 if (cmd->scan_begin_src == TRIG_TIMER) {
2294 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2295 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2296 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2297 devpriv->clock_ns * 0xffffff);
2298 } else if (cmd->scan_begin_src == TRIG_EXT) {
2299 /* external trigger */
2300 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2301
2302 if (tmp > 16)
2303 tmp = 16;
2304 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2305 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2306 } else { /* TRIG_OTHER */
2307 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2308 }
2309
2310 if (cmd->convert_src == TRIG_TIMER) {
2311 if ((board->reg_type == ni_reg_611x)
2312 || (board->reg_type == ni_reg_6143)) {
2313 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2314 } else {
2315 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2316 board->ai_speed);
2317 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2318 devpriv->clock_ns * 0xffff);
2319 }
2320 } else if (cmd->convert_src == TRIG_EXT) {
2321 /* external trigger */
2322 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2323
2324 if (tmp > 16)
2325 tmp = 16;
2326 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2327 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2328 } else if (cmd->convert_src == TRIG_NOW) {
2329 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2330 }
2331
2332 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2333
2334 if (cmd->stop_src == TRIG_COUNT) {
2335 unsigned int max_count = 0x01000000;
2336
2337 if (board->reg_type == ni_reg_611x)
2338 max_count -= num_adc_stages_611x;
2339 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2340 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2341 } else {
2342 /* TRIG_NONE */
2343 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2344 }
2345
2346 if (err)
2347 return 3;
2348
2349 /* step 4: fix up any arguments */
2350
2351 if (cmd->scan_begin_src == TRIG_TIMER) {
2352 tmp = cmd->scan_begin_arg;
2353 cmd->scan_begin_arg =
2354 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2355 cmd->scan_begin_arg,
2356 cmd->
2357 flags &
2358 TRIG_ROUND_MASK));
2359 if (tmp != cmd->scan_begin_arg)
2360 err++;
2361 }
2362 if (cmd->convert_src == TRIG_TIMER) {
2363 if ((board->reg_type != ni_reg_611x)
2364 && (board->reg_type != ni_reg_6143)) {
2365 tmp = cmd->convert_arg;
2366 cmd->convert_arg =
2367 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2368 cmd->convert_arg,
2369 cmd->
2370 flags &
2371 TRIG_ROUND_MASK));
2372 if (tmp != cmd->convert_arg)
2373 err++;
2374 if (cmd->scan_begin_src == TRIG_TIMER &&
2375 cmd->scan_begin_arg <
2376 cmd->convert_arg * cmd->scan_end_arg) {
2377 cmd->scan_begin_arg =
2378 cmd->convert_arg * cmd->scan_end_arg;
2379 err++;
2380 }
2381 }
2382 }
2383
2384 if (err)
2385 return 4;
2386
2387 return 0;
2388 }
2389
2390 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2391 {
2392 const struct ni_board_struct *board = comedi_board(dev);
2393 struct ni_private *devpriv = dev->private;
2394 const struct comedi_cmd *cmd = &s->async->cmd;
2395 int timer;
2396 int mode1 = 0; /* mode1 is needed for both stop and convert */
2397 int mode2 = 0;
2398 int start_stop_select = 0;
2399 unsigned int stop_count;
2400 int interrupt_a_enable = 0;
2401
2402 MDPRINTK("ni_ai_cmd\n");
2403 if (dev->irq == 0) {
2404 comedi_error(dev, "cannot run command without an irq");
2405 return -EIO;
2406 }
2407 ni_clear_ai_fifo(dev);
2408
2409 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2410
2411 /* start configuration */
2412 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2413
2414 /* disable analog triggering for now, since it
2415 * interferes with the use of pfi0 */
2416 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2417 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2418 Analog_Trigger_Etc_Register);
2419
2420 switch (cmd->start_src) {
2421 case TRIG_INT:
2422 case TRIG_NOW:
2423 devpriv->stc_writew(dev, AI_START2_Select(0) |
2424 AI_START1_Sync | AI_START1_Edge |
2425 AI_START1_Select(0),
2426 AI_Trigger_Select_Register);
2427 break;
2428 case TRIG_EXT:
2429 {
2430 int chan = CR_CHAN(cmd->start_arg);
2431 unsigned int bits = AI_START2_Select(0) |
2432 AI_START1_Sync | AI_START1_Select(chan + 1);
2433
2434 if (cmd->start_arg & CR_INVERT)
2435 bits |= AI_START1_Polarity;
2436 if (cmd->start_arg & CR_EDGE)
2437 bits |= AI_START1_Edge;
2438 devpriv->stc_writew(dev, bits,
2439 AI_Trigger_Select_Register);
2440 break;
2441 }
2442 }
2443
2444 mode2 &= ~AI_Pre_Trigger;
2445 mode2 &= ~AI_SC_Initial_Load_Source;
2446 mode2 &= ~AI_SC_Reload_Mode;
2447 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2448
2449 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2450 || (board->reg_type == ni_reg_6143)) {
2451 start_stop_select |= AI_STOP_Polarity;
2452 start_stop_select |= AI_STOP_Select(31); /* logic low */
2453 start_stop_select |= AI_STOP_Sync;
2454 } else {
2455 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2456 }
2457 devpriv->stc_writew(dev, start_stop_select,
2458 AI_START_STOP_Select_Register);
2459
2460 devpriv->ai_cmd2 = 0;
2461 switch (cmd->stop_src) {
2462 case TRIG_COUNT:
2463 stop_count = cmd->stop_arg - 1;
2464
2465 if (board->reg_type == ni_reg_611x) {
2466 /* have to take 3 stage adc pipeline into account */
2467 stop_count += num_adc_stages_611x;
2468 }
2469 /* stage number of scans */
2470 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2471
2472 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2473 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2474 /* load SC (Scan Count) */
2475 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2476
2477 devpriv->ai_continuous = 0;
2478 if (stop_count == 0) {
2479 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2480 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2481 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2482 if (cmd->chanlist_len > 1)
2483 start_stop_select |=
2484 AI_STOP_Polarity | AI_STOP_Edge;
2485 }
2486 break;
2487 case TRIG_NONE:
2488 /* stage number of scans */
2489 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2490
2491 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2492 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2493
2494 /* load SC (Scan Count) */
2495 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2496
2497 devpriv->ai_continuous = 1;
2498
2499 break;
2500 }
2501
2502 switch (cmd->scan_begin_src) {
2503 case TRIG_TIMER:
2504 /*
2505 stop bits for non 611x boards
2506 AI_SI_Special_Trigger_Delay=0
2507 AI_Pre_Trigger=0
2508 AI_START_STOP_Select_Register:
2509 AI_START_Polarity=0 (?) rising edge
2510 AI_START_Edge=1 edge triggered
2511 AI_START_Sync=1 (?)
2512 AI_START_Select=0 SI_TC
2513 AI_STOP_Polarity=0 rising edge
2514 AI_STOP_Edge=0 level
2515 AI_STOP_Sync=1
2516 AI_STOP_Select=19 external pin (configuration mem)
2517 */
2518 start_stop_select |= AI_START_Edge | AI_START_Sync;
2519 devpriv->stc_writew(dev, start_stop_select,
2520 AI_START_STOP_Select_Register);
2521
2522 mode2 |= AI_SI_Reload_Mode(0);
2523 /* AI_SI_Initial_Load_Source=A */
2524 mode2 &= ~AI_SI_Initial_Load_Source;
2525 /* mode2 |= AI_SC_Reload_Mode; */
2526 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2527
2528 /* load SI */
2529 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2530 TRIG_ROUND_NEAREST);
2531 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2532 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2533 break;
2534 case TRIG_EXT:
2535 if (cmd->scan_begin_arg & CR_EDGE)
2536 start_stop_select |= AI_START_Edge;
2537 /* AI_START_Polarity==1 is falling edge */
2538 if (cmd->scan_begin_arg & CR_INVERT)
2539 start_stop_select |= AI_START_Polarity;
2540 if (cmd->scan_begin_src != cmd->convert_src ||
2541 (cmd->scan_begin_arg & ~CR_EDGE) !=
2542 (cmd->convert_arg & ~CR_EDGE))
2543 start_stop_select |= AI_START_Sync;
2544 start_stop_select |=
2545 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2546 devpriv->stc_writew(dev, start_stop_select,
2547 AI_START_STOP_Select_Register);
2548 break;
2549 }
2550
2551 switch (cmd->convert_src) {
2552 case TRIG_TIMER:
2553 case TRIG_NOW:
2554 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2555 timer = 1;
2556 else
2557 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2558 TRIG_ROUND_NEAREST);
2559 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2560 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2561
2562 /* AI_SI2_Reload_Mode = alternate */
2563 /* AI_SI2_Initial_Load_Source = A */
2564 mode2 &= ~AI_SI2_Initial_Load_Source;
2565 mode2 |= AI_SI2_Reload_Mode;
2566 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2567
2568 /* AI_SI2_Load */
2569 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2570
2571 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2572 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2573
2574 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2575 break;
2576 case TRIG_EXT:
2577 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2578 if ((cmd->convert_arg & CR_INVERT) == 0)
2579 mode1 |= AI_CONVERT_Source_Polarity;
2580 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2581
2582 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2583 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2584
2585 break;
2586 }
2587
2588 if (dev->irq) {
2589
2590 /* interrupt on FIFO, errors, SC_TC */
2591 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2592 AI_SC_TC_Interrupt_Enable;
2593
2594 #ifndef PCIDMA
2595 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2596 #endif
2597
2598 if (cmd->flags & TRIG_WAKE_EOS
2599 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2600 /* wake on end-of-scan */
2601 devpriv->aimode = AIMODE_SCAN;
2602 } else {
2603 devpriv->aimode = AIMODE_HALF_FULL;
2604 }
2605
2606 switch (devpriv->aimode) {
2607 case AIMODE_HALF_FULL:
2608 /*generate FIFO interrupts and DMA requests on half-full */
2609 #ifdef PCIDMA
2610 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2611 AI_Mode_3_Register);
2612 #else
2613 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2614 AI_Mode_3_Register);
2615 #endif
2616 break;
2617 case AIMODE_SAMPLE:
2618 /*generate FIFO interrupts on non-empty */
2619 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2620 AI_Mode_3_Register);
2621 break;
2622 case AIMODE_SCAN:
2623 #ifdef PCIDMA
2624 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2625 AI_Mode_3_Register);
2626 #else
2627 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2628 AI_Mode_3_Register);
2629 #endif
2630 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2631 break;
2632 default:
2633 break;
2634 }
2635
2636 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2637
2638 ni_set_bits(dev, Interrupt_A_Enable_Register,
2639 interrupt_a_enable, 1);
2640
2641 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2642 devpriv->int_a_enable_reg);
2643 } else {
2644 /* interrupt on nothing */
2645 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2646
2647 /* XXX start polling if necessary */
2648 MDPRINTK("interrupting on nothing\n");
2649 }
2650
2651 /* end configuration */
2652 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2653
2654 switch (cmd->scan_begin_src) {
2655 case TRIG_TIMER:
2656 devpriv->stc_writew(dev,
2657 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2658 AI_SC_Arm, AI_Command_1_Register);
2659 break;
2660 case TRIG_EXT:
2661 /* XXX AI_SI_Arm? */
2662 devpriv->stc_writew(dev,
2663 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2664 AI_SC_Arm, AI_Command_1_Register);
2665 break;
2666 }
2667
2668 #ifdef PCIDMA
2669 {
2670 int retval = ni_ai_setup_MITE_dma(dev);
2671 if (retval)
2672 return retval;
2673 }
2674 /* mite_dump_regs(devpriv->mite); */
2675 #endif
2676
2677 switch (cmd->start_src) {
2678 case TRIG_NOW:
2679 /* AI_START1_Pulse */
2680 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2681 AI_Command_2_Register);
2682 s->async->inttrig = NULL;
2683 break;
2684 case TRIG_EXT:
2685 s->async->inttrig = NULL;
2686 break;
2687 case TRIG_INT:
2688 s->async->inttrig = &ni_ai_inttrig;
2689 break;
2690 }
2691
2692 MDPRINTK("exit ni_ai_cmd\n");
2693
2694 return 0;
2695 }
2696
2697 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2698 unsigned int trignum)
2699 {
2700 struct ni_private *devpriv = dev->private;
2701
2702 if (trignum != 0)
2703 return -EINVAL;
2704
2705 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2706 AI_Command_2_Register);
2707 s->async->inttrig = NULL;
2708
2709 return 1;
2710 }
2711
2712 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2713 struct comedi_subdevice *s,
2714 struct comedi_insn *insn,
2715 unsigned int *data);
2716
2717 static int ni_ai_insn_config(struct comedi_device *dev,
2718 struct comedi_subdevice *s,
2719 struct comedi_insn *insn, unsigned int *data)
2720 {
2721 const struct ni_board_struct *board = comedi_board(dev);
2722 struct ni_private *devpriv = dev->private;
2723
2724 if (insn->n < 1)
2725 return -EINVAL;
2726
2727 switch (data[0]) {
2728 case INSN_CONFIG_ANALOG_TRIG:
2729 return ni_ai_config_analog_trig(dev, s, insn, data);
2730 case INSN_CONFIG_ALT_SOURCE:
2731 if (board->reg_type & ni_reg_m_series_mask) {
2732 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2733 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2734 MSeries_AI_Bypass_Mode_Mux_Mask |
2735 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2736 return -EINVAL;
2737 }
2738 devpriv->ai_calib_source = data[1];
2739 } else if (board->reg_type == ni_reg_6143) {
2740 unsigned int calib_source;
2741
2742 calib_source = data[1] & 0xf;
2743
2744 if (calib_source > 0xF)
2745 return -EINVAL;
2746
2747 devpriv->ai_calib_source = calib_source;
2748 ni_writew(calib_source, Calibration_Channel_6143);
2749 } else {
2750 unsigned int calib_source;
2751 unsigned int calib_source_adjust;
2752
2753 calib_source = data[1] & 0xf;
2754 calib_source_adjust = (data[1] >> 4) & 0xff;
2755
2756 if (calib_source >= 8)
2757 return -EINVAL;
2758 devpriv->ai_calib_source = calib_source;
2759 if (board->reg_type == ni_reg_611x) {
2760 ni_writeb(calib_source_adjust,
2761 Cal_Gain_Select_611x);
2762 }
2763 }
2764 return 2;
2765 default:
2766 break;
2767 }
2768
2769 return -EINVAL;
2770 }
2771
2772 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2773 struct comedi_subdevice *s,
2774 struct comedi_insn *insn,
2775 unsigned int *data)
2776 {
2777 const struct ni_board_struct *board = comedi_board(dev);
2778 struct ni_private *devpriv = dev->private;
2779 unsigned int a, b, modebits;
2780 int err = 0;
2781
2782 /* data[1] is flags
2783 * data[2] is analog line
2784 * data[3] is set level
2785 * data[4] is reset level */
2786 if (!board->has_analog_trig)
2787 return -EINVAL;
2788 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2789 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2790 err++;
2791 }
2792 if (data[2] >= board->n_adchan) {
2793 data[2] = board->n_adchan - 1;
2794 err++;
2795 }
2796 if (data[3] > 255) { /* a */
2797 data[3] = 255;
2798 err++;
2799 }
2800 if (data[4] > 255) { /* b */
2801 data[4] = 255;
2802 err++;
2803 }
2804 /*
2805 * 00 ignore
2806 * 01 set
2807 * 10 reset
2808 *
2809 * modes:
2810 * 1 level: +b- +a-
2811 * high mode 00 00 01 10
2812 * low mode 00 00 10 01
2813 * 2 level: (a<b)
2814 * hysteresis low mode 10 00 00 01
2815 * hysteresis high mode 01 00 00 10
2816 * middle mode 10 01 01 10
2817 */
2818
2819 a = data[3];
2820 b = data[4];
2821 modebits = data[1] & 0xff;
2822 if (modebits & 0xf0) {
2823 /* two level mode */
2824 if (b < a) {
2825 /* swap order */
2826 a = data[4];
2827 b = data[3];
2828 modebits =
2829 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2830 }
2831 devpriv->atrig_low = a;
2832 devpriv->atrig_high = b;
2833 switch (modebits) {
2834 case 0x81: /* low hysteresis mode */
2835 devpriv->atrig_mode = 6;
2836 break;
2837 case 0x42: /* high hysteresis mode */
2838 devpriv->atrig_mode = 3;
2839 break;
2840 case 0x96: /* middle window mode */
2841 devpriv->atrig_mode = 2;
2842 break;
2843 default:
2844 data[1] &= ~0xff;
2845 err++;
2846 }
2847 } else {
2848 /* one level mode */
2849 if (b != 0) {
2850 data[4] = 0;
2851 err++;
2852 }
2853 switch (modebits) {
2854 case 0x06: /* high window mode */
2855 devpriv->atrig_high = a;
2856 devpriv->atrig_mode = 0;
2857 break;
2858 case 0x09: /* low window mode */
2859 devpriv->atrig_low = a;
2860 devpriv->atrig_mode = 1;
2861 break;
2862 default:
2863 data[1] &= ~0xff;
2864 err++;
2865 }
2866 }
2867 if (err)
2868 return -EAGAIN;
2869 return 5;
2870 }
2871
2872 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2873 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2874 void *data, unsigned int num_bytes,
2875 unsigned int chan_index)
2876 {
2877 const struct ni_board_struct *board = comedi_board(dev);
2878 struct comedi_async *async = s->async;
2879 unsigned int range;
2880 unsigned int i;
2881 unsigned int offset;
2882 unsigned int length = num_bytes / sizeof(short);
2883 short *array = data;
2884
2885 offset = 1 << (board->aobits - 1);
2886 for (i = 0; i < length; i++) {
2887 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2888 if (board->ao_unipolar == 0 || (range & 1) == 0)
2889 array[i] -= offset;
2890 #ifdef PCIDMA
2891 array[i] = cpu_to_le16(array[i]);
2892 #endif
2893 chan_index++;
2894 chan_index %= async->cmd.chanlist_len;
2895 }
2896 }
2897
2898 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2899 struct comedi_subdevice *s,
2900 unsigned int chanspec[],
2901 unsigned int n_chans, int timed)
2902 {
2903 const struct ni_board_struct *board = comedi_board(dev);
2904 struct ni_private *devpriv = dev->private;
2905 unsigned int range;
2906 unsigned int chan;
2907 unsigned int conf;
2908 int i;
2909 int invert = 0;
2910
2911 if (timed) {
2912 for (i = 0; i < board->n_aochan; ++i) {
2913 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2914 ni_writeb(devpriv->ao_conf[i],
2915 M_Offset_AO_Config_Bank(i));
2916 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2917 }
2918 }
2919 for (i = 0; i < n_chans; i++) {
2920 const struct comedi_krange *krange;
2921 chan = CR_CHAN(chanspec[i]);
2922 range = CR_RANGE(chanspec[i]);
2923 krange = s->range_table->range + range;
2924 invert = 0;
2925 conf = 0;
2926 switch (krange->max - krange->min) {
2927 case 20000000:
2928 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2929 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2930 break;
2931 case 10000000:
2932 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2933 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2934 break;
2935 case 4000000:
2936 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2937 ni_writeb(MSeries_Attenuate_x5_Bit,
2938 M_Offset_AO_Reference_Attenuation(chan));
2939 break;
2940 case 2000000:
2941 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2942 ni_writeb(MSeries_Attenuate_x5_Bit,
2943 M_Offset_AO_Reference_Attenuation(chan));
2944 break;
2945 default:
2946 printk("%s: bug! unhandled ao reference voltage\n",
2947 __func__);
2948 break;
2949 }
2950 switch (krange->max + krange->min) {
2951 case 0:
2952 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2953 break;
2954 case 10000000:
2955 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2956 break;
2957 default:
2958 printk("%s: bug! unhandled ao offset voltage\n",
2959 __func__);
2960 break;
2961 }
2962 if (timed)
2963 conf |= MSeries_AO_Update_Timed_Bit;
2964 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2965 devpriv->ao_conf[chan] = conf;
2966 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2967 }
2968 return invert;
2969 }
2970
2971 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2972 struct comedi_subdevice *s,
2973 unsigned int chanspec[],
2974 unsigned int n_chans)
2975 {
2976 const struct ni_board_struct *board = comedi_board(dev);
2977 struct ni_private *devpriv = dev->private;
2978 unsigned int range;
2979 unsigned int chan;
2980 unsigned int conf;
2981 int i;
2982 int invert = 0;
2983
2984 for (i = 0; i < n_chans; i++) {
2985 chan = CR_CHAN(chanspec[i]);
2986 range = CR_RANGE(chanspec[i]);
2987 conf = AO_Channel(chan);
2988
2989 if (board->ao_unipolar) {
2990 if ((range & 1) == 0) {
2991 conf |= AO_Bipolar;
2992 invert = (1 << (board->aobits - 1));
2993 } else {
2994 invert = 0;
2995 }
2996 if (range & 2)
2997 conf |= AO_Ext_Ref;
2998 } else {
2999 conf |= AO_Bipolar;
3000 invert = (1 << (board->aobits - 1));
3001 }
3002
3003 /* not all boards can deglitch, but this shouldn't hurt */
3004 if (chanspec[i] & CR_DEGLITCH)
3005 conf |= AO_Deglitch;
3006
3007 /* analog reference */
3008 /* AREF_OTHER connects AO ground to AI ground, i think */
3009 conf |= (CR_AREF(chanspec[i]) ==
3010 AREF_OTHER) ? AO_Ground_Ref : 0;
3011
3012 ni_writew(conf, AO_Configuration);
3013 devpriv->ao_conf[chan] = conf;
3014 }
3015 return invert;
3016 }
3017
3018 static int ni_ao_config_chanlist(struct comedi_device *dev,
3019 struct comedi_subdevice *s,
3020 unsigned int chanspec[], unsigned int n_chans,
3021 int timed)
3022 {
3023 const struct ni_board_struct *board = comedi_board(dev);
3024
3025 if (board->reg_type & ni_reg_m_series_mask)
3026 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3027 timed);
3028 else
3029 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3030 }
3031
3032 static int ni_ao_insn_read(struct comedi_device *dev,
3033 struct comedi_subdevice *s, struct comedi_insn *insn,
3034 unsigned int *data)
3035 {
3036 struct ni_private *devpriv = dev->private;
3037
3038 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3039
3040 return 1;
3041 }
3042
3043 static int ni_ao_insn_write(struct comedi_device *dev,
3044 struct comedi_subdevice *s,
3045 struct comedi_insn *insn, unsigned int *data)
3046 {
3047 const struct ni_board_struct *board = comedi_board(dev);
3048 struct ni_private *devpriv = dev->private;
3049 unsigned int chan = CR_CHAN(insn->chanspec);
3050 unsigned int invert;
3051
3052 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3053
3054 devpriv->ao[chan] = data[0];
3055
3056 if (board->reg_type & ni_reg_m_series_mask) {
3057 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3058 } else
3059 ni_writew(data[0] ^ invert,
3060 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3061
3062 return 1;
3063 }
3064
3065 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3066 struct comedi_subdevice *s,
3067 struct comedi_insn *insn, unsigned int *data)
3068 {
3069 const struct ni_board_struct *board = comedi_board(dev);
3070 struct ni_private *devpriv = dev->private;
3071 unsigned int chan = CR_CHAN(insn->chanspec);
3072 unsigned int invert;
3073
3074 ao_win_out(1 << chan, AO_Immediate_671x);
3075 invert = 1 << (board->aobits - 1);
3076
3077 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3078
3079 devpriv->ao[chan] = data[0];
3080 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3081
3082 return 1;
3083 }
3084
3085 static int ni_ao_insn_config(struct comedi_device *dev,
3086 struct comedi_subdevice *s,
3087 struct comedi_insn *insn, unsigned int *data)
3088 {
3089 const struct ni_board_struct *board = comedi_board(dev);
3090 struct ni_private *devpriv = dev->private;
3091
3092 switch (data[0]) {
3093 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3094 switch (data[1]) {
3095 case COMEDI_OUTPUT:
3096 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3097 if (devpriv->mite)
3098 data[2] += devpriv->mite->fifo_size;
3099 break;
3100 case COMEDI_INPUT:
3101 data[2] = 0;
3102 break;
3103 default:
3104 return -EINVAL;
3105 break;
3106 }
3107 return 0;
3108 default:
3109 break;
3110 }
3111
3112 return -EINVAL;
3113 }
3114
3115 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3116 unsigned int trignum)
3117 {
3118 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3119 struct ni_private *devpriv = dev->private;
3120 int ret;
3121 int interrupt_b_bits;
3122 int i;
3123 static const int timeout = 1000;
3124
3125 if (trignum != 0)
3126 return -EINVAL;
3127
3128 /* Null trig at beginning prevent ao start trigger from executing more than
3129 once per command (and doing things like trying to allocate the ao dma channel
3130 multiple times) */
3131 s->async->inttrig = NULL;
3132
3133 ni_set_bits(dev, Interrupt_B_Enable_Register,
3134 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3135 interrupt_b_bits = AO_Error_Interrupt_Enable;
3136 #ifdef PCIDMA
3137 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3138 if (board->reg_type & ni_reg_6xxx_mask)
3139 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3140 ret = ni_ao_setup_MITE_dma(dev);
3141 if (ret)
3142 return ret;
3143 ret = ni_ao_wait_for_dma_load(dev);
3144 if (ret < 0)
3145 return ret;
3146 #else
3147 ret = ni_ao_prep_fifo(dev, s);
3148 if (ret == 0)
3149 return -EPIPE;
3150
3151 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3152 #endif
3153
3154 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3155 AO_Mode_3_Register);
3156 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3157 /* wait for DACs to be loaded */
3158 for (i = 0; i < timeout; i++) {
3159 udelay(1);
3160 if ((devpriv->stc_readw(dev,
3161 Joint_Status_2_Register) &
3162 AO_TMRDACWRs_In_Progress_St) == 0)
3163 break;
3164 }
3165 if (i == timeout) {
3166 comedi_error(dev,
3167 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3168 return -EIO;
3169 }
3170 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3171 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3172 Interrupt_B_Ack_Register);
3173
3174 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3175
3176 devpriv->stc_writew(dev,
3177 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3178 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3179 AO_Command_1_Register);
3180
3181 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3182 AO_Command_2_Register);
3183
3184 return 0;
3185 }
3186
3187 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3188 {
3189 const struct ni_board_struct *board = comedi_board(dev);
3190 struct ni_private *devpriv = dev->private;
3191 const struct comedi_cmd *cmd = &s->async->cmd;
3192 int bits;
3193 int i;
3194 unsigned trigvar;
3195
3196 if (dev->irq == 0) {
3197 comedi_error(dev, "cannot run command without an irq");
3198 return -EIO;
3199 }
3200
3201 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3202
3203 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3204
3205 if (board->reg_type & ni_reg_6xxx_mask) {
3206 ao_win_out(CLEAR_WG, AO_Misc_611x);
3207
3208 bits = 0;
3209 for (i = 0; i < cmd->chanlist_len; i++) {
3210 int chan;
3211
3212 chan = CR_CHAN(cmd->chanlist[i]);
3213 bits |= 1 << chan;
3214 ao_win_out(chan, AO_Waveform_Generation_611x);
3215 }
3216 ao_win_out(bits, AO_Timed_611x);
3217 }
3218
3219 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3220
3221 if (cmd->stop_src == TRIG_NONE) {
3222 devpriv->ao_mode1 |= AO_Continuous;
3223 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3224 } else {
3225 devpriv->ao_mode1 &= ~AO_Continuous;
3226 devpriv->ao_mode1 |= AO_Trigger_Once;
3227 }
3228 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3229 switch (cmd->start_src) {
3230 case TRIG_INT:
3231 case TRIG_NOW:
3232 devpriv->ao_trigger_select &=
3233 ~(AO_START1_Polarity | AO_START1_Select(-1));
3234 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3235 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3236 AO_Trigger_Select_Register);
3237 break;
3238 case TRIG_EXT:
3239 devpriv->ao_trigger_select =
3240 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3241 if (cmd->start_arg & CR_INVERT)
3242 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3243 if (cmd->start_arg & CR_EDGE)
3244 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3245 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3246 AO_Trigger_Select_Register);
3247 break;
3248 default:
3249 BUG();
3250 break;
3251 }
3252 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3253 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3254
3255 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3256 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3257 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3258 if (cmd->stop_src == TRIG_NONE) {
3259 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3260 } else {
3261 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3262 }
3263 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3264 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3265 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3266 switch (cmd->stop_src) {
3267 case TRIG_COUNT:
3268 if (board->reg_type & ni_reg_m_series_mask) {
3269 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3270 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3271 AO_UC_Load_A_Register);
3272 devpriv->stc_writew(dev, AO_UC_Load,
3273 AO_Command_1_Register);
3274 } else {
3275 devpriv->stc_writel(dev, cmd->stop_arg,
3276 AO_UC_Load_A_Register);
3277 devpriv->stc_writew(dev, AO_UC_Load,
3278 AO_Command_1_Register);
3279 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3280 AO_UC_Load_A_Register);
3281 }
3282 break;
3283 case TRIG_NONE:
3284 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3285 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3286 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3287 break;
3288 default:
3289 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3290 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3291 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3292 }
3293
3294 devpriv->ao_mode1 &=
3295 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3296 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3297 switch (cmd->scan_begin_src) {
3298 case TRIG_TIMER:
3299 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3300 trigvar =
3301 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3302 TRIG_ROUND_NEAREST);
3303 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3304 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3305 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3306 break;
3307 case TRIG_EXT:
3308 devpriv->ao_mode1 |=
3309 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3310 if (cmd->scan_begin_arg & CR_INVERT)
3311 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3312 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3313 break;
3314 default:
3315 BUG();
3316 break;
3317 }
3318 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3319 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3320 devpriv->ao_mode2 &=
3321 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3322 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3323
3324 if (cmd->scan_end_arg > 1) {
3325 devpriv->ao_mode1 |= AO_Multiple_Channels;
3326 devpriv->stc_writew(dev,
3327 AO_Number_Of_Channels(cmd->scan_end_arg -
3328 1) |
3329 AO_UPDATE_Output_Select
3330 (AO_Update_Output_High_Z),
3331 AO_Output_Control_Register);
3332 } else {
3333 unsigned bits;
3334 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3335 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3336 if (board->reg_type &
3337 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3338 bits |= AO_Number_Of_Channels(0);
3339 } else {
3340 bits |=
3341 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3342 }
3343 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3344 }
3345 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3346
3347 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3348 AO_Command_1_Register);
3349
3350 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3351 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3352
3353 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3354 #ifdef PCIDMA
3355 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3356 #else
3357 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3358 #endif
3359 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3360 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3361
3362 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3363 AO_TMRDACWR_Pulse_Width;
3364 if (board->ao_fifo_depth)
3365 bits |= AO_FIFO_Enable;
3366 else
3367 bits |= AO_DMA_PIO_Control;
3368 #if 0
3369 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3370 verified with bus analyzer. */
3371 if (board->reg_type & ni_reg_m_series_mask)
3372 bits |= AO_Number_Of_DAC_Packages;
3373 #endif
3374 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3375 /* enable sending of ao dma requests */
3376 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3377
3378 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3379
3380 if (cmd->stop_src == TRIG_COUNT) {
3381 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3382 Interrupt_B_Ack_Register);
3383 ni_set_bits(dev, Interrupt_B_Enable_Register,
3384 AO_BC_TC_Interrupt_Enable, 1);
3385 }
3386
3387 s->async->inttrig = &ni_ao_inttrig;
3388
3389 return 0;
3390 }
3391
3392 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3393 struct comedi_cmd *cmd)
3394 {
3395 const struct ni_board_struct *board = comedi_board(dev);
3396 struct ni_private *devpriv = dev->private;
3397 int err = 0;
3398 int tmp;
3399
3400 /* Step 1 : check if triggers are trivially valid */
3401
3402 if ((cmd->flags & CMDF_WRITE) == 0)
3403 cmd->flags |= CMDF_WRITE;
3404
3405 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3406 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3407 TRIG_TIMER | TRIG_EXT);
3408 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3409 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3410 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3411
3412 if (err)
3413 return 1;
3414
3415 /* Step 2a : make sure trigger sources are unique */
3416
3417 err |= cfc_check_trigger_is_unique(cmd->start_src);
3418 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3419 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3420
3421 /* Step 2b : and mutually compatible */
3422
3423 if (err)
3424 return 2;
3425
3426 /* Step 3: check if arguments are trivially valid */
3427
3428 if (cmd->start_src == TRIG_EXT) {
3429 /* external trigger */
3430 unsigned int tmp = CR_CHAN(cmd->start_arg);
3431
3432 if (tmp > 18)
3433 tmp = 18;
3434 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3435 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3436 } else {
3437 /* true for both TRIG_NOW and TRIG_INT */
3438 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3439 }
3440
3441 if (cmd->scan_begin_src == TRIG_TIMER) {
3442 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3443 board->ao_speed);
3444 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3445 devpriv->clock_ns * 0xffffff);
3446 }
3447
3448 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3449 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3450
3451 if (cmd->stop_src == TRIG_COUNT)
3452 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3453 else /* TRIG_NONE */
3454 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3455
3456 if (err)
3457 return 3;
3458
3459 /* step 4: fix up any arguments */
3460 if (cmd->scan_begin_src == TRIG_TIMER) {
3461 tmp = cmd->scan_begin_arg;
3462 cmd->scan_begin_arg =
3463 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3464 cmd->scan_begin_arg,
3465 cmd->
3466 flags &
3467 TRIG_ROUND_MASK));
3468 if (tmp != cmd->scan_begin_arg)
3469 err++;
3470 }
3471 if (err)
3472 return 4;
3473
3474 /* step 5: fix up chanlist */
3475
3476 if (err)
3477 return 5;
3478
3479 return 0;
3480 }
3481
3482 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3483 {
3484 const struct ni_board_struct *board = comedi_board(dev);
3485 struct ni_private *devpriv = dev->private;
3486
3487 /* devpriv->ao0p=0x0000; */
3488 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3489
3490 /* devpriv->ao1p=AO_Channel(1); */
3491 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3492
3493 ni_release_ao_mite_channel(dev);
3494
3495 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3496 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3497 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3498 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3499 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3500 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3501 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3502 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3503 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3504 devpriv->ao_cmd1 = 0;
3505 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3506 devpriv->ao_cmd2 = 0;
3507 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3508 devpriv->ao_mode1 = 0;
3509 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3510 devpriv->ao_mode2 = 0;
3511 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3512 if (board->reg_type & ni_reg_m_series_mask)
3513 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3514 else
3515 devpriv->ao_mode3 = 0;
3516 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3517 devpriv->ao_trigger_select = 0;
3518 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3519 AO_Trigger_Select_Register);
3520 if (board->reg_type & ni_reg_6xxx_mask) {
3521 unsigned immediate_bits = 0;
3522 unsigned i;
3523 for (i = 0; i < s->n_chan; ++i) {
3524 immediate_bits |= 1 << i;
3525 }
3526 ao_win_out(immediate_bits, AO_Immediate_671x);
3527 ao_win_out(CLEAR_WG, AO_Misc_611x);
3528 }
3529 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3530
3531 return 0;
3532 }
3533
3534 /* digital io */
3535
3536 static int ni_dio_insn_config(struct comedi_device *dev,
3537 struct comedi_subdevice *s,
3538 struct comedi_insn *insn, unsigned int *data)
3539 {
3540 struct ni_private *devpriv = dev->private;
3541
3542 #ifdef DEBUG_DIO
3543 printk("ni_dio_insn_config() chan=%d io=%d\n",
3544 CR_CHAN(insn->chanspec), data[0]);
3545 #endif
3546 switch (data[0]) {
3547 case INSN_CONFIG_DIO_OUTPUT:
3548 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3549 break;
3550 case INSN_CONFIG_DIO_INPUT:
3551 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3552 break;
3553 case INSN_CONFIG_DIO_QUERY:
3554 data[1] =
3555 (s->
3556 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3557 COMEDI_INPUT;
3558 return insn->n;
3559 break;
3560 default:
3561 return -EINVAL;
3562 }
3563
3564 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3565 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3566 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3567
3568 return 1;
3569 }
3570
3571 static int ni_dio_insn_bits(struct comedi_device *dev,
3572 struct comedi_subdevice *s,
3573 struct comedi_insn *insn, unsigned int *data)
3574 {
3575 struct ni_private *devpriv = dev->private;
3576
3577 #ifdef DEBUG_DIO
3578 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3579 #endif
3580
3581 if (data[0]) {
3582 /* Perform check to make sure we're not using the
3583 serial part of the dio */
3584 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3585 && devpriv->serial_interval_ns)
3586 return -EBUSY;
3587
3588 s->state &= ~data[0];
3589 s->state |= (data[0] & data[1]);
3590 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3591 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3592 devpriv->stc_writew(dev, devpriv->dio_output,
3593 DIO_Output_Register);
3594 }
3595 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3596
3597 return insn->n;
3598 }
3599
3600 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3601 struct comedi_subdevice *s,
3602 struct comedi_insn *insn,
3603 unsigned int *data)
3604 {
3605 struct ni_private *devpriv __maybe_unused = dev->private;
3606
3607 #ifdef DEBUG_DIO
3608 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3609 CR_CHAN(insn->chanspec), data[0]);
3610 #endif
3611 switch (data[0]) {
3612 case INSN_CONFIG_DIO_OUTPUT:
3613 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3614 break;
3615 case INSN_CONFIG_DIO_INPUT:
3616 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3617 break;
3618 case INSN_CONFIG_DIO_QUERY:
3619 data[1] =
3620 (s->
3621 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3622 COMEDI_INPUT;
3623 return insn->n;
3624 break;
3625 default:
3626 return -EINVAL;
3627 }
3628
3629 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3630
3631 return 1;
3632 }
3633
3634 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3635 struct comedi_subdevice *s,
3636 struct comedi_insn *insn,
3637 unsigned int *data)
3638 {
3639 struct ni_private *devpriv __maybe_unused = dev->private;
3640
3641 #ifdef DEBUG_DIO
3642 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3643 data[1]);
3644 #endif
3645
3646 if (data[0]) {
3647 s->state &= ~data[0];
3648 s->state |= (data[0] & data[1]);
3649 ni_writel(s->state, M_Offset_Static_Digital_Output);
3650 }
3651 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3652
3653 return insn->n;
3654 }
3655
3656 static int ni_cdio_cmdtest(struct comedi_device *dev,
3657 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3658 {
3659 int err = 0;
3660 int tmp;
3661 unsigned i;
3662
3663 /* Step 1 : check if triggers are trivially valid */
3664
3665 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3666 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3667 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3668 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3669 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3670
3671 if (err)
3672 return 1;
3673
3674 /* Step 2a : make sure trigger sources are unique */
3675 /* Step 2b : and mutually compatible */
3676
3677 if (err)
3678 return 2;
3679
3680 /* Step 3: check if arguments are trivially valid */
3681
3682 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3683
3684 tmp = cmd->scan_begin_arg;
3685 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3686 if (tmp != cmd->scan_begin_arg)
3687 err |= -EINVAL;
3688
3689 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3690 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3691 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3692
3693 if (err)
3694 return 3;
3695
3696 /* step 4: fix up any arguments */
3697
3698 if (err)
3699 return 4;
3700
3701 /* step 5: check chanlist */
3702
3703 for (i = 0; i < cmd->chanlist_len; ++i) {
3704 if (cmd->chanlist[i] != i)
3705 err = 1;
3706 }
3707
3708 if (err)
3709 return 5;
3710
3711 return 0;
3712 }
3713
3714 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3715 {
3716 struct ni_private *devpriv __maybe_unused = dev->private;
3717 const struct comedi_cmd *cmd = &s->async->cmd;
3718 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3719 int retval;
3720
3721 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3722 switch (cmd->scan_begin_src) {
3723 case TRIG_EXT:
3724 cdo_mode_bits |=
3725 CR_CHAN(cmd->scan_begin_arg) &
3726 CDO_Sample_Source_Select_Mask;
3727 break;
3728 default:
3729 BUG();
3730 break;
3731 }
3732 if (cmd->scan_begin_arg & CR_INVERT)
3733 cdo_mode_bits |= CDO_Polarity_Bit;
3734 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3735 if (s->io_bits) {
3736 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3737 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3738 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3739 } else {
3740 comedi_error(dev,
3741 "attempted to run digital output command with no lines configured as outputs");
3742 return -EIO;
3743 }
3744 retval = ni_request_cdo_mite_channel(dev);
3745 if (retval < 0) {
3746 return retval;
3747 }
3748 s->async->inttrig = &ni_cdo_inttrig;
3749 return 0;
3750 }
3751
3752 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3753 unsigned int trignum)
3754 {
3755 #ifdef PCIDMA
3756 struct ni_private *devpriv = dev->private;
3757 unsigned long flags;
3758 #endif
3759 int retval = 0;
3760 unsigned i;
3761 const unsigned timeout = 1000;
3762
3763 s->async->inttrig = NULL;
3764
3765 /* read alloc the entire buffer */
3766 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3767
3768 #ifdef PCIDMA
3769 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3770 if (devpriv->cdo_mite_chan) {
3771 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3772 mite_dma_arm(devpriv->cdo_mite_chan);
3773 } else {
3774 comedi_error(dev, "BUG: no cdo mite channel?");
3775 retval = -EIO;
3776 }
3777 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3778 if (retval < 0)
3779 return retval;
3780 #endif
3781 /*
3782 * XXX not sure what interrupt C group does
3783 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3784 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3785 */
3786 for (i = 0; i < timeout; ++i) {
3787 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3788 break;
3789 udelay(10);
3790 }
3791 if (i == timeout) {
3792 comedi_error(dev, "dma failed to fill cdo fifo!");
3793 ni_cdio_cancel(dev, s);
3794 return -EIO;
3795 }
3796 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3797 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3798 M_Offset_CDIO_Command);
3799 return retval;
3800 }
3801
3802 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3803 {
3804 struct ni_private *devpriv __maybe_unused = dev->private;
3805
3806 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3807 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3808 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3809 M_Offset_CDIO_Command);
3810 /*
3811 * XXX not sure what interrupt C group does ni_writeb(0,
3812 * M_Offset_Interrupt_C_Enable);
3813 */
3814 ni_writel(0, M_Offset_CDO_Mask_Enable);
3815 ni_release_cdo_mite_channel(dev);
3816 return 0;
3817 }
3818
3819 static void handle_cdio_interrupt(struct comedi_device *dev)
3820 {
3821 const struct ni_board_struct *board = comedi_board(dev);
3822 struct ni_private *devpriv __maybe_unused = dev->private;
3823 unsigned cdio_status;
3824 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3825 #ifdef PCIDMA
3826 unsigned long flags;
3827 #endif
3828
3829 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3830 return;
3831 }
3832 #ifdef PCIDMA
3833 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3834 if (devpriv->cdo_mite_chan) {
3835 unsigned cdo_mite_status =
3836 mite_get_status(devpriv->cdo_mite_chan);
3837 if (cdo_mite_status & CHSR_LINKC) {
3838 writel(CHOR_CLRLC,
3839 devpriv->mite->mite_io_addr +
3840 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3841 }
3842 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3843 }
3844 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3845 #endif
3846
3847 cdio_status = ni_readl(M_Offset_CDIO_Status);
3848 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3849 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3850 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3851 s->async->events |= COMEDI_CB_OVERFLOW;
3852 }
3853 if (cdio_status & CDO_FIFO_Empty_Bit) {
3854 /* printk("cdio fifo empty\n"); */
3855 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3856 M_Offset_CDIO_Command);
3857 /* s->async->events |= COMEDI_CB_EOA; */
3858 }
3859 ni_event(dev, s);
3860 }
3861
3862 static int ni_serial_insn_config(struct comedi_device *dev,
3863 struct comedi_subdevice *s,
3864 struct comedi_insn *insn, unsigned int *data)
3865 {
3866 struct ni_private *devpriv = dev->private;
3867 int err = insn->n;
3868 unsigned char byte_out, byte_in = 0;
3869
3870 if (insn->n != 2)
3871 return -EINVAL;
3872
3873 switch (data[0]) {
3874 case INSN_CONFIG_SERIAL_CLOCK:
3875
3876 #ifdef DEBUG_DIO
3877 printk("SPI serial clock Config cd\n", data[1]);
3878 #endif
3879 devpriv->serial_hw_mode = 1;
3880 devpriv->dio_control |= DIO_HW_Serial_Enable;
3881
3882 if (data[1] == SERIAL_DISABLED) {
3883 devpriv->serial_hw_mode = 0;
3884 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3885 DIO_Software_Serial_Control);
3886 data[1] = SERIAL_DISABLED;
3887 devpriv->serial_interval_ns = data[1];
3888 } else if (data[1] <= SERIAL_600NS) {
3889 /* Warning: this clock speed is too fast to reliably
3890 control SCXI. */
3891 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3892 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3893 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3894 data[1] = SERIAL_600NS;
3895 devpriv->serial_interval_ns = data[1];
3896 } else if (data[1] <= SERIAL_1_2US) {
3897 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3898 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3899 DIO_Serial_Out_Divide_By_2;
3900 data[1] = SERIAL_1_2US;
3901 devpriv->serial_interval_ns = data[1];
3902 } else if (data[1] <= SERIAL_10US) {
3903 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3904 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3905 DIO_Serial_Out_Divide_By_2;
3906 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3907 600ns/1.2us. If you turn divide_by_2 off with the
3908 slow clock, you will still get 10us, except then
3909 all your delays are wrong. */
3910 data[1] = SERIAL_10US;
3911 devpriv->serial_interval_ns = data[1];
3912 } else {
3913 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3914 DIO_Software_Serial_Control);
3915 devpriv->serial_hw_mode = 0;
3916 data[1] = (data[1] / 1000) * 1000;
3917 devpriv->serial_interval_ns = data[1];
3918 }
3919
3920 devpriv->stc_writew(dev, devpriv->dio_control,
3921 DIO_Control_Register);
3922 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3923 Clock_and_FOUT_Register);
3924 return 1;
3925
3926 break;
3927
3928 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3929
3930 if (devpriv->serial_interval_ns == 0) {
3931 return -EINVAL;
3932 }
3933
3934 byte_out = data[1] & 0xFF;
3935
3936 if (devpriv->serial_hw_mode) {
3937 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3938 &byte_in);
3939 } else if (devpriv->serial_interval_ns > 0) {
3940 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3941 &byte_in);
3942 } else {
3943 printk("ni_serial_insn_config: serial disabled!\n");
3944 return -EINVAL;
3945 }
3946 if (err < 0)
3947 return err;
3948 data[1] = byte_in & 0xFF;
3949 return insn->n;
3950
3951 break;
3952 default:
3953 return -EINVAL;
3954 }
3955
3956 }
3957
3958 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3959 struct comedi_subdevice *s,
3960 unsigned char data_out,
3961 unsigned char *data_in)
3962 {
3963 struct ni_private *devpriv = dev->private;
3964 unsigned int status1;
3965 int err = 0, count = 20;
3966
3967 #ifdef DEBUG_DIO
3968 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3969 #endif
3970
3971 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3972 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3973 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3974
3975 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3976 if (status1 & DIO_Serial_IO_In_Progress_St) {
3977 err = -EBUSY;
3978 goto Error;
3979 }
3980
3981 devpriv->dio_control |= DIO_HW_Serial_Start;
3982 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3983 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3984
3985 /* Wait until STC says we're done, but don't loop infinitely. */
3986 while ((status1 =
3987 devpriv->stc_readw(dev,
3988 Joint_Status_1_Register)) &
3989 DIO_Serial_IO_In_Progress_St) {
3990 /* Delay one bit per loop */
3991 udelay((devpriv->serial_interval_ns + 999) / 1000);
3992 if (--count < 0) {
3993 printk
3994 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3995 err = -ETIME;
3996 goto Error;
3997 }
3998 }
3999
4000 /* Delay for last bit. This delay is absolutely necessary, because
4001 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
4002 udelay((devpriv->serial_interval_ns + 999) / 1000);
4003
4004 if (data_in != NULL) {
4005 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4006 #ifdef DEBUG_DIO
4007 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4008 #endif
4009 }
4010
4011 Error:
4012 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4013
4014 return err;
4015 }
4016
4017 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4018 struct comedi_subdevice *s,
4019 unsigned char data_out,
4020 unsigned char *data_in)
4021 {
4022 struct ni_private *devpriv = dev->private;
4023 unsigned char mask, input = 0;
4024
4025 #ifdef DEBUG_DIO
4026 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4027 #endif
4028
4029 /* Wait for one bit before transfer */
4030 udelay((devpriv->serial_interval_ns + 999) / 1000);
4031
4032 for (mask = 0x80; mask; mask >>= 1) {
4033 /* Output current bit; note that we cannot touch s->state
4034 because it is a per-subdevice field, and serial is
4035 a separate subdevice from DIO. */
4036 devpriv->dio_output &= ~DIO_SDOUT;
4037 if (data_out & mask) {
4038 devpriv->dio_output |= DIO_SDOUT;
4039 }
4040 devpriv->stc_writew(dev, devpriv->dio_output,
4041 DIO_Output_Register);
4042
4043 /* Assert SDCLK (active low, inverted), wait for half of
4044 the delay, deassert SDCLK, and wait for the other half. */
4045 devpriv->dio_control |= DIO_Software_Serial_Control;
4046 devpriv->stc_writew(dev, devpriv->dio_control,
4047 DIO_Control_Register);
4048
4049 udelay((devpriv->serial_interval_ns + 999) / 2000);
4050
4051 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4052 devpriv->stc_writew(dev, devpriv->dio_control,
4053 DIO_Control_Register);
4054
4055 udelay((devpriv->serial_interval_ns + 999) / 2000);
4056
4057 /* Input current bit */
4058 if (devpriv->stc_readw(dev,
4059 DIO_Parallel_Input_Register) & DIO_SDIN)
4060 {
4061 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4062 input |= mask;
4063 }
4064 }
4065 #ifdef DEBUG_DIO
4066 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4067 #endif
4068 if (data_in)
4069 *data_in = input;
4070
4071 return 0;
4072 }
4073
4074 static void mio_common_detach(struct comedi_device *dev)
4075 {
4076 const struct ni_board_struct *board = comedi_board(dev);
4077 struct ni_private *devpriv = dev->private;
4078 struct comedi_subdevice *s;
4079
4080 if (devpriv) {
4081 if (devpriv->counter_dev) {
4082 ni_gpct_device_destroy(devpriv->counter_dev);
4083 }
4084 }
4085 if (dev->subdevices && board->has_8255) {
4086 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4087 subdev_8255_cleanup(dev, s);
4088 }
4089 }
4090
4091 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4092 {
4093 int i;
4094
4095 for (i = 0; i < s->n_chan; i++) {
4096 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4097 AO_Configuration_2_67xx);
4098 }
4099 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4100 }
4101
4102 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4103 {
4104 unsigned stc_register;
4105 switch (reg) {
4106 case NITIO_G0_Autoincrement_Reg:
4107 stc_register = G_Autoincrement_Register(0);
4108 break;
4109 case NITIO_G1_Autoincrement_Reg:
4110 stc_register = G_Autoincrement_Register(1);
4111 break;
4112 case NITIO_G0_Command_Reg:
4113 stc_register = G_Command_Register(0);
4114 break;
4115 case NITIO_G1_Command_Reg:
4116 stc_register = G_Command_Register(1);
4117 break;
4118 case NITIO_G0_HW_Save_Reg:
4119 stc_register = G_HW_Save_Register(0);
4120 break;
4121 case NITIO_G1_HW_Save_Reg:
4122 stc_register = G_HW_Save_Register(1);
4123 break;
4124 case NITIO_G0_SW_Save_Reg:
4125 stc_register = G_Save_Register(0);
4126 break;
4127 case NITIO_G1_SW_Save_Reg:
4128 stc_register = G_Save_Register(1);
4129 break;
4130 case NITIO_G0_Mode_Reg:
4131 stc_register = G_Mode_Register(0);
4132 break;
4133 case NITIO_G1_Mode_Reg:
4134 stc_register = G_Mode_Register(1);
4135 break;
4136 case NITIO_G0_LoadA_Reg:
4137 stc_register = G_Load_A_Register(0);
4138 break;
4139 case NITIO_G1_LoadA_Reg:
4140 stc_register = G_Load_A_Register(1);
4141 break;
4142 case NITIO_G0_LoadB_Reg:
4143 stc_register = G_Load_B_Register(0);
4144 break;
4145 case NITIO_G1_LoadB_Reg:
4146 stc_register = G_Load_B_Register(1);
4147 break;
4148 case NITIO_G0_Input_Select_Reg:
4149 stc_register = G_Input_Select_Register(0);
4150 break;
4151 case NITIO_G1_Input_Select_Reg:
4152 stc_register = G_Input_Select_Register(1);
4153 break;
4154 case NITIO_G01_Status_Reg:
4155 stc_register = G_Status_Register;
4156 break;
4157 case NITIO_G01_Joint_Reset_Reg:
4158 stc_register = Joint_Reset_Register;
4159 break;
4160 case NITIO_G01_Joint_Status1_Reg:
4161 stc_register = Joint_Status_1_Register;
4162 break;
4163 case NITIO_G01_Joint_Status2_Reg:
4164 stc_register = Joint_Status_2_Register;
4165 break;
4166 case NITIO_G0_Interrupt_Acknowledge_Reg:
4167 stc_register = Interrupt_A_Ack_Register;
4168 break;
4169 case NITIO_G1_Interrupt_Acknowledge_Reg:
4170 stc_register = Interrupt_B_Ack_Register;
4171 break;
4172 case NITIO_G0_Status_Reg:
4173 stc_register = AI_Status_1_Register;
4174 break;
4175 case NITIO_G1_Status_Reg:
4176 stc_register = AO_Status_1_Register;
4177 break;
4178 case NITIO_G0_Interrupt_Enable_Reg:
4179 stc_register = Interrupt_A_Enable_Register;
4180 break;
4181 case NITIO_G1_Interrupt_Enable_Reg:
4182 stc_register = Interrupt_B_Enable_Register;
4183 break;
4184 default:
4185 printk("%s: unhandled register 0x%x in switch.\n",
4186 __func__, reg);
4187 BUG();
4188 return 0;
4189 break;
4190 }
4191 return stc_register;
4192 }
4193
4194 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4195 enum ni_gpct_register reg)
4196 {
4197 struct comedi_device *dev = counter->counter_dev->dev;
4198 struct ni_private *devpriv = dev->private;
4199 unsigned stc_register;
4200 /* bits in the join reset register which are relevant to counters */
4201 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4202 static const unsigned gpct_interrupt_a_enable_mask =
4203 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4204 static const unsigned gpct_interrupt_b_enable_mask =
4205 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4206
4207 switch (reg) {
4208 /* m-series-only registers */
4209 case NITIO_G0_Counting_Mode_Reg:
4210 ni_writew(bits, M_Offset_G0_Counting_Mode);
4211 break;
4212 case NITIO_G1_Counting_Mode_Reg:
4213 ni_writew(bits, M_Offset_G1_Counting_Mode);
4214 break;
4215 case NITIO_G0_Second_Gate_Reg:
4216 ni_writew(bits, M_Offset_G0_Second_Gate);
4217 break;
4218 case NITIO_G1_Second_Gate_Reg:
4219 ni_writew(bits, M_Offset_G1_Second_Gate);
4220 break;
4221 case NITIO_G0_DMA_Config_Reg:
4222 ni_writew(bits, M_Offset_G0_DMA_Config);
4223 break;
4224 case NITIO_G1_DMA_Config_Reg:
4225 ni_writew(bits, M_Offset_G1_DMA_Config);
4226 break;
4227 case NITIO_G0_ABZ_Reg:
4228 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4229 break;
4230 case NITIO_G1_ABZ_Reg:
4231 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4232 break;
4233
4234 /* 32 bit registers */
4235 case NITIO_G0_LoadA_Reg:
4236 case NITIO_G1_LoadA_Reg:
4237 case NITIO_G0_LoadB_Reg:
4238 case NITIO_G1_LoadB_Reg:
4239 stc_register = ni_gpct_to_stc_register(reg);
4240 devpriv->stc_writel(dev, bits, stc_register);
4241 break;
4242
4243 /* 16 bit registers */
4244 case NITIO_G0_Interrupt_Enable_Reg:
4245 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4246 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4247 gpct_interrupt_a_enable_mask, bits);
4248 break;
4249 case NITIO_G1_Interrupt_Enable_Reg:
4250 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4251 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4252 gpct_interrupt_b_enable_mask, bits);
4253 break;
4254 case NITIO_G01_Joint_Reset_Reg:
4255 BUG_ON(bits & ~gpct_joint_reset_mask);
4256 /* fall-through */
4257 default:
4258 stc_register = ni_gpct_to_stc_register(reg);
4259 devpriv->stc_writew(dev, bits, stc_register);
4260 }
4261 }
4262
4263 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4264 enum ni_gpct_register reg)
4265 {
4266 struct comedi_device *dev = counter->counter_dev->dev;
4267 struct ni_private *devpriv = dev->private;
4268 unsigned stc_register;
4269
4270 switch (reg) {
4271 /* m-series only registers */
4272 case NITIO_G0_DMA_Status_Reg:
4273 return ni_readw(M_Offset_G0_DMA_Status);
4274 break;
4275 case NITIO_G1_DMA_Status_Reg:
4276 return ni_readw(M_Offset_G1_DMA_Status);
4277 break;
4278
4279 /* 32 bit registers */
4280 case NITIO_G0_HW_Save_Reg:
4281 case NITIO_G1_HW_Save_Reg:
4282 case NITIO_G0_SW_Save_Reg:
4283 case NITIO_G1_SW_Save_Reg:
4284 stc_register = ni_gpct_to_stc_register(reg);
4285 return devpriv->stc_readl(dev, stc_register);
4286 break;
4287
4288 /* 16 bit registers */
4289 default:
4290 stc_register = ni_gpct_to_stc_register(reg);
4291 return devpriv->stc_readw(dev, stc_register);
4292 break;
4293 }
4294 return 0;
4295 }
4296
4297 static int ni_freq_out_insn_read(struct comedi_device *dev,
4298 struct comedi_subdevice *s,
4299 struct comedi_insn *insn, unsigned int *data)
4300 {
4301 struct ni_private *devpriv = dev->private;
4302
4303 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4304 return 1;
4305 }
4306
4307 static int ni_freq_out_insn_write(struct comedi_device *dev,
4308 struct comedi_subdevice *s,
4309 struct comedi_insn *insn, unsigned int *data)
4310 {
4311 struct ni_private *devpriv = dev->private;
4312
4313 devpriv->clock_and_fout &= ~FOUT_Enable;
4314 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4315 Clock_and_FOUT_Register);
4316 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4317 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4318 devpriv->clock_and_fout |= FOUT_Enable;
4319 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4320 Clock_and_FOUT_Register);
4321 return insn->n;
4322 }
4323
4324 static int ni_set_freq_out_clock(struct comedi_device *dev,
4325 unsigned int clock_source)
4326 {
4327 struct ni_private *devpriv = dev->private;
4328
4329 switch (clock_source) {
4330 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4331 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4332 break;
4333 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4334 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4335 break;
4336 default:
4337 return -EINVAL;
4338 }
4339 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4340 Clock_and_FOUT_Register);
4341 return 3;
4342 }
4343
4344 static void ni_get_freq_out_clock(struct comedi_device *dev,
4345 unsigned int *clock_source,
4346 unsigned int *clock_period_ns)
4347 {
4348 struct ni_private *devpriv = dev->private;
4349
4350 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4351 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4352 *clock_period_ns = TIMEBASE_2_NS;
4353 } else {
4354 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4355 *clock_period_ns = TIMEBASE_1_NS * 2;
4356 }
4357 }
4358
4359 static int ni_freq_out_insn_config(struct comedi_device *dev,
4360 struct comedi_subdevice *s,
4361 struct comedi_insn *insn, unsigned int *data)
4362 {
4363 switch (data[0]) {
4364 case INSN_CONFIG_SET_CLOCK_SRC:
4365 return ni_set_freq_out_clock(dev, data[1]);
4366 break;
4367 case INSN_CONFIG_GET_CLOCK_SRC:
4368 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4369 return 3;
4370 default:
4371 break;
4372 }
4373 return -EINVAL;
4374 }
4375
4376 static int ni_alloc_private(struct comedi_device *dev)
4377 {
4378 struct ni_private *devpriv;
4379
4380 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4381 if (!devpriv)
4382 return -ENOMEM;
4383 dev->private = devpriv;
4384
4385 spin_lock_init(&devpriv->window_lock);
4386 spin_lock_init(&devpriv->soft_reg_copy_lock);
4387 spin_lock_init(&devpriv->mite_channel_lock);
4388
4389 return 0;
4390 };
4391
4392 static int ni_E_init(struct comedi_device *dev)
4393 {
4394 const struct ni_board_struct *board = comedi_board(dev);
4395 struct ni_private *devpriv = dev->private;
4396 struct comedi_subdevice *s;
4397 unsigned j;
4398 enum ni_gpct_variant counter_variant;
4399 int ret;
4400
4401 if (board->n_aochan > MAX_N_AO_CHAN) {
4402 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4403 return -EINVAL;
4404 }
4405
4406 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4407 if (ret)
4408 return ret;
4409
4410 /* analog input subdevice */
4411
4412 s = &dev->subdevices[NI_AI_SUBDEV];
4413 dev->read_subdev = s;
4414 if (board->n_adchan) {
4415 s->type = COMEDI_SUBD_AI;
4416 s->subdev_flags =
4417 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4418 if (board->reg_type != ni_reg_611x)
4419 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4420 if (board->adbits > 16)
4421 s->subdev_flags |= SDF_LSAMPL;
4422 if (board->reg_type & ni_reg_m_series_mask)
4423 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4424 s->n_chan = board->n_adchan;
4425 s->len_chanlist = 512;
4426 s->maxdata = (1 << board->adbits) - 1;
4427 s->range_table = ni_range_lkup[board->gainlkup];
4428 s->insn_read = &ni_ai_insn_read;
4429 s->insn_config = &ni_ai_insn_config;
4430 s->do_cmdtest = &ni_ai_cmdtest;
4431 s->do_cmd = &ni_ai_cmd;
4432 s->cancel = &ni_ai_reset;
4433 s->poll = &ni_ai_poll;
4434 s->munge = &ni_ai_munge;
4435 #ifdef PCIDMA
4436 s->async_dma_dir = DMA_FROM_DEVICE;
4437 #endif
4438 } else {
4439 s->type = COMEDI_SUBD_UNUSED;
4440 }
4441
4442 /* analog output subdevice */
4443
4444 s = &dev->subdevices[NI_AO_SUBDEV];
4445 if (board->n_aochan) {
4446 s->type = COMEDI_SUBD_AO;
4447 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4448 if (board->reg_type & ni_reg_m_series_mask)
4449 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4450 s->n_chan = board->n_aochan;
4451 s->maxdata = (1 << board->aobits) - 1;
4452 s->range_table = board->ao_range_table;
4453 s->insn_read = &ni_ao_insn_read;
4454 if (board->reg_type & ni_reg_6xxx_mask) {
4455 s->insn_write = &ni_ao_insn_write_671x;
4456 } else {
4457 s->insn_write = &ni_ao_insn_write;
4458 }
4459 s->insn_config = &ni_ao_insn_config;
4460 #ifdef PCIDMA
4461 if (board->n_aochan) {
4462 s->async_dma_dir = DMA_TO_DEVICE;
4463 #else
4464 if (board->ao_fifo_depth) {
4465 #endif
4466 dev->write_subdev = s;
4467 s->subdev_flags |= SDF_CMD_WRITE;
4468 s->do_cmd = &ni_ao_cmd;
4469 s->do_cmdtest = &ni_ao_cmdtest;
4470 s->len_chanlist = board->n_aochan;
4471 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4472 s->munge = ni_ao_munge;
4473 }
4474 s->cancel = &ni_ao_reset;
4475 } else {
4476 s->type = COMEDI_SUBD_UNUSED;
4477 }
4478 if ((board->reg_type & ni_reg_67xx_mask))
4479 init_ao_67xx(dev, s);
4480
4481 /* digital i/o subdevice */
4482
4483 s = &dev->subdevices[NI_DIO_SUBDEV];
4484 s->type = COMEDI_SUBD_DIO;
4485 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4486 s->maxdata = 1;
4487 s->io_bits = 0; /* all bits input */
4488 s->range_table = &range_digital;
4489 s->n_chan = board->num_p0_dio_channels;
4490 if (board->reg_type & ni_reg_m_series_mask) {
4491 s->subdev_flags |=
4492 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4493 s->insn_bits = &ni_m_series_dio_insn_bits;
4494 s->insn_config = &ni_m_series_dio_insn_config;
4495 s->do_cmd = &ni_cdio_cmd;
4496 s->do_cmdtest = &ni_cdio_cmdtest;
4497 s->cancel = &ni_cdio_cancel;
4498 s->async_dma_dir = DMA_BIDIRECTIONAL;
4499 s->len_chanlist = s->n_chan;
4500
4501 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4502 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4503 } else {
4504 s->insn_bits = &ni_dio_insn_bits;
4505 s->insn_config = &ni_dio_insn_config;
4506 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4507 ni_writew(devpriv->dio_control, DIO_Control_Register);
4508 }
4509
4510 /* 8255 device */
4511 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4512 if (board->has_8255) {
4513 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4514 } else {
4515 s->type = COMEDI_SUBD_UNUSED;
4516 }
4517
4518 /* formerly general purpose counter/timer device, but no longer used */
4519 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4520 s->type = COMEDI_SUBD_UNUSED;
4521
4522 /* calibration subdevice -- ai and ao */
4523 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4524 s->type = COMEDI_SUBD_CALIB;
4525 if (board->reg_type & ni_reg_m_series_mask) {
4526 /* internal PWM analog output used for AI nonlinearity calibration */
4527 s->subdev_flags = SDF_INTERNAL;
4528 s->insn_config = &ni_m_series_pwm_config;
4529 s->n_chan = 1;
4530 s->maxdata = 0;
4531 ni_writel(0x0, M_Offset_Cal_PWM);
4532 } else if (board->reg_type == ni_reg_6143) {
4533 /* internal PWM analog output used for AI nonlinearity calibration */
4534 s->subdev_flags = SDF_INTERNAL;
4535 s->insn_config = &ni_6143_pwm_config;
4536 s->n_chan = 1;
4537 s->maxdata = 0;
4538 } else {
4539 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4540 s->insn_read = &ni_calib_insn_read;
4541 s->insn_write = &ni_calib_insn_write;
4542 caldac_setup(dev, s);
4543 }
4544
4545 /* EEPROM */
4546 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4547 s->type = COMEDI_SUBD_MEMORY;
4548 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4549 s->maxdata = 0xff;
4550 if (board->reg_type & ni_reg_m_series_mask) {
4551 s->n_chan = M_SERIES_EEPROM_SIZE;
4552 s->insn_read = &ni_m_series_eeprom_insn_read;
4553 } else {
4554 s->n_chan = 512;
4555 s->insn_read = &ni_eeprom_insn_read;
4556 }
4557
4558 /* PFI */
4559 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4560 s->type = COMEDI_SUBD_DIO;
4561 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4562 if (board->reg_type & ni_reg_m_series_mask) {
4563 unsigned i;
4564 s->n_chan = 16;
4565 ni_writew(s->state, M_Offset_PFI_DO);
4566 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4567 ni_writew(devpriv->pfi_output_select_reg[i],
4568 M_Offset_PFI_Output_Select(i + 1));
4569 }
4570 } else {
4571 s->n_chan = 10;
4572 }
4573 s->maxdata = 1;
4574 if (board->reg_type & ni_reg_m_series_mask) {
4575 s->insn_bits = &ni_pfi_insn_bits;
4576 }
4577 s->insn_config = &ni_pfi_insn_config;
4578 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4579
4580 /* cs5529 calibration adc */
4581 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4582 if (board->reg_type & ni_reg_67xx_mask) {
4583 s->type = COMEDI_SUBD_AI;
4584 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4585 /* one channel for each analog output channel */
4586 s->n_chan = board->n_aochan;
4587 s->maxdata = (1 << 16) - 1;
4588 s->range_table = &range_unknown; /* XXX */
4589 s->insn_read = cs5529_ai_insn_read;
4590 s->insn_config = NULL;
4591 init_cs5529(dev);
4592 } else {
4593 s->type = COMEDI_SUBD_UNUSED;
4594 }
4595
4596 /* Serial */
4597 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4598 s->type = COMEDI_SUBD_SERIAL;
4599 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4600 s->n_chan = 1;
4601 s->maxdata = 0xff;
4602 s->insn_config = ni_serial_insn_config;
4603 devpriv->serial_interval_ns = 0;
4604 devpriv->serial_hw_mode = 0;
4605
4606 /* RTSI */
4607 s = &dev->subdevices[NI_RTSI_SUBDEV];
4608 s->type = COMEDI_SUBD_DIO;
4609 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4610 s->n_chan = 8;
4611 s->maxdata = 1;
4612 s->insn_bits = ni_rtsi_insn_bits;
4613 s->insn_config = ni_rtsi_insn_config;
4614 ni_rtsi_init(dev);
4615
4616 if (board->reg_type & ni_reg_m_series_mask) {
4617 counter_variant = ni_gpct_variant_m_series;
4618 } else {
4619 counter_variant = ni_gpct_variant_e_series;
4620 }
4621 devpriv->counter_dev = ni_gpct_device_construct(dev,
4622 &ni_gpct_write_register,
4623 &ni_gpct_read_register,
4624 counter_variant,
4625 NUM_GPCT);
4626 /* General purpose counters */
4627 for (j = 0; j < NUM_GPCT; ++j) {
4628 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4629 s->type = COMEDI_SUBD_COUNTER;
4630 s->subdev_flags =
4631 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4632 /* | SDF_CMD_WRITE */ ;
4633 s->n_chan = 3;
4634 if (board->reg_type & ni_reg_m_series_mask)
4635 s->maxdata = 0xffffffff;
4636 else
4637 s->maxdata = 0xffffff;
4638 s->insn_read = &ni_gpct_insn_read;
4639 s->insn_write = &ni_gpct_insn_write;
4640 s->insn_config = &ni_gpct_insn_config;
4641 s->do_cmd = &ni_gpct_cmd;
4642 s->len_chanlist = 1;
4643 s->do_cmdtest = &ni_gpct_cmdtest;
4644 s->cancel = &ni_gpct_cancel;
4645 s->async_dma_dir = DMA_BIDIRECTIONAL;
4646 s->private = &devpriv->counter_dev->counters[j];
4647
4648 devpriv->counter_dev->counters[j].chip_index = 0;
4649 devpriv->counter_dev->counters[j].counter_index = j;
4650 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4651 }
4652
4653 /* Frequency output */
4654 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4655 s->type = COMEDI_SUBD_COUNTER;
4656 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4657 s->n_chan = 1;
4658 s->maxdata = 0xf;
4659 s->insn_read = &ni_freq_out_insn_read;
4660 s->insn_write = &ni_freq_out_insn_write;
4661 s->insn_config = &ni_freq_out_insn_config;
4662
4663 /* ai configuration */
4664 s = &dev->subdevices[NI_AI_SUBDEV];
4665 ni_ai_reset(dev, s);
4666 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4667 /* BEAM is this needed for PCI-6143 ?? */
4668 devpriv->clock_and_fout =
4669 Slow_Internal_Time_Divide_By_2 |
4670 Slow_Internal_Timebase |
4671 Clock_To_Board_Divide_By_2 |
4672 Clock_To_Board |
4673 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4674 } else {
4675 devpriv->clock_and_fout =
4676 Slow_Internal_Time_Divide_By_2 |
4677 Slow_Internal_Timebase |
4678 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4679 }
4680 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4681 Clock_and_FOUT_Register);
4682
4683 /* analog output configuration */
4684 s = &dev->subdevices[NI_AO_SUBDEV];
4685 ni_ao_reset(dev, s);
4686
4687 if (dev->irq) {
4688 devpriv->stc_writew(dev,
4689 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4690 0) | (Interrupt_Output_On_3_Pins & 0) |
4691 Interrupt_A_Enable | Interrupt_B_Enable |
4692 Interrupt_A_Output_Select(interrupt_pin
4693 (dev->irq)) |
4694 Interrupt_B_Output_Select(interrupt_pin
4695 (dev->irq)),
4696 Interrupt_Control_Register);
4697 }
4698
4699 /* DMA setup */
4700 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4701 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4702
4703 if (board->reg_type & ni_reg_6xxx_mask) {
4704 ni_writeb(0, Magic_611x);
4705 } else if (board->reg_type & ni_reg_m_series_mask) {
4706 int channel;
4707 for (channel = 0; channel < board->n_aochan; ++channel) {
4708 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4709 ni_writeb(0x0,
4710 M_Offset_AO_Reference_Attenuation(channel));
4711 }
4712 ni_writeb(0x0, M_Offset_AO_Calibration);
4713 }
4714
4715 printk("\n");
4716 return 0;
4717 }
4718
4719 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4720 {
4721 struct comedi_device *dev = (struct comedi_device *)arg;
4722 struct ni_private *devpriv __maybe_unused = dev->private;
4723
4724 if (dir) {
4725 ni_writeb(data, Port_A + 2 * port);
4726 return 0;
4727 } else {
4728 return ni_readb(Port_A + 2 * port);
4729 }
4730 }
4731
4732 /*
4733 presents the EEPROM as a subdevice
4734 */
4735
4736 static int ni_eeprom_insn_read(struct comedi_device *dev,
4737 struct comedi_subdevice *s,
4738 struct comedi_insn *insn, unsigned int *data)
4739 {
4740 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4741
4742 return 1;
4743 }
4744
4745 /*
4746 reads bytes out of eeprom
4747 */
4748
4749 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4750 {
4751 struct ni_private *devpriv __maybe_unused = dev->private;
4752 int bit;
4753 int bitstring;
4754
4755 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4756 ni_writeb(0x04, Serial_Command);
4757 for (bit = 0x8000; bit; bit >>= 1) {
4758 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4759 Serial_Command);
4760 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4761 Serial_Command);
4762 }
4763 bitstring = 0;
4764 for (bit = 0x80; bit; bit >>= 1) {
4765 ni_writeb(0x04, Serial_Command);
4766 ni_writeb(0x05, Serial_Command);
4767 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4768 }
4769 ni_writeb(0x00, Serial_Command);
4770
4771 return bitstring;
4772 }
4773
4774 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4775 struct comedi_subdevice *s,
4776 struct comedi_insn *insn,
4777 unsigned int *data)
4778 {
4779 struct ni_private *devpriv = dev->private;
4780
4781 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4782
4783 return 1;
4784 }
4785
4786 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4787 {
4788 struct ni_private *devpriv = dev->private;
4789
4790 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4791 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4792 return 3;
4793 }
4794
4795 static int ni_m_series_pwm_config(struct comedi_device *dev,
4796 struct comedi_subdevice *s,
4797 struct comedi_insn *insn, unsigned int *data)
4798 {
4799 struct ni_private *devpriv = dev->private;
4800 unsigned up_count, down_count;
4801
4802 switch (data[0]) {
4803 case INSN_CONFIG_PWM_OUTPUT:
4804 switch (data[1]) {
4805 case TRIG_ROUND_NEAREST:
4806 up_count =
4807 (data[2] +
4808 devpriv->clock_ns / 2) / devpriv->clock_ns;
4809 break;
4810 case TRIG_ROUND_DOWN:
4811 up_count = data[2] / devpriv->clock_ns;
4812 break;
4813 case TRIG_ROUND_UP:
4814 up_count =
4815 (data[2] + devpriv->clock_ns -
4816 1) / devpriv->clock_ns;
4817 break;
4818 default:
4819 return -EINVAL;
4820 break;
4821 }
4822 switch (data[3]) {
4823 case TRIG_ROUND_NEAREST:
4824 down_count =
4825 (data[4] +
4826 devpriv->clock_ns / 2) / devpriv->clock_ns;
4827 break;
4828 case TRIG_ROUND_DOWN:
4829 down_count = data[4] / devpriv->clock_ns;
4830 break;
4831 case TRIG_ROUND_UP:
4832 down_count =
4833 (data[4] + devpriv->clock_ns -
4834 1) / devpriv->clock_ns;
4835 break;
4836 default:
4837 return -EINVAL;
4838 break;
4839 }
4840 if (up_count * devpriv->clock_ns != data[2] ||
4841 down_count * devpriv->clock_ns != data[4]) {
4842 data[2] = up_count * devpriv->clock_ns;
4843 data[4] = down_count * devpriv->clock_ns;
4844 return -EAGAIN;
4845 }
4846 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4847 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4848 M_Offset_Cal_PWM);
4849 devpriv->pwm_up_count = up_count;
4850 devpriv->pwm_down_count = down_count;
4851 return 5;
4852 break;
4853 case INSN_CONFIG_GET_PWM_OUTPUT:
4854 return ni_get_pwm_config(dev, data);
4855 break;
4856 default:
4857 return -EINVAL;
4858 break;
4859 }
4860 return 0;
4861 }
4862
4863 static int ni_6143_pwm_config(struct comedi_device *dev,
4864 struct comedi_subdevice *s,
4865 struct comedi_insn *insn, unsigned int *data)
4866 {
4867 struct ni_private *devpriv = dev->private;
4868 unsigned up_count, down_count;
4869
4870 switch (data[0]) {
4871 case INSN_CONFIG_PWM_OUTPUT:
4872 switch (data[1]) {
4873 case TRIG_ROUND_NEAREST:
4874 up_count =
4875 (data[2] +
4876 devpriv->clock_ns / 2) / devpriv->clock_ns;
4877 break;
4878 case TRIG_ROUND_DOWN:
4879 up_count = data[2] / devpriv->clock_ns;
4880 break;
4881 case TRIG_ROUND_UP:
4882 up_count =
4883 (data[2] + devpriv->clock_ns -
4884 1) / devpriv->clock_ns;
4885 break;
4886 default:
4887 return -EINVAL;
4888 break;
4889 }
4890 switch (data[3]) {
4891 case TRIG_ROUND_NEAREST:
4892 down_count =
4893 (data[4] +
4894 devpriv->clock_ns / 2) / devpriv->clock_ns;
4895 break;
4896 case TRIG_ROUND_DOWN:
4897 down_count = data[4] / devpriv->clock_ns;
4898 break;
4899 case TRIG_ROUND_UP:
4900 down_count =
4901 (data[4] + devpriv->clock_ns -
4902 1) / devpriv->clock_ns;
4903 break;
4904 default:
4905 return -EINVAL;
4906 break;
4907 }
4908 if (up_count * devpriv->clock_ns != data[2] ||
4909 down_count * devpriv->clock_ns != data[4]) {
4910 data[2] = up_count * devpriv->clock_ns;
4911 data[4] = down_count * devpriv->clock_ns;
4912 return -EAGAIN;
4913 }
4914 ni_writel(up_count, Calibration_HighTime_6143);
4915 devpriv->pwm_up_count = up_count;
4916 ni_writel(down_count, Calibration_LowTime_6143);
4917 devpriv->pwm_down_count = down_count;
4918 return 5;
4919 break;
4920 case INSN_CONFIG_GET_PWM_OUTPUT:
4921 return ni_get_pwm_config(dev, data);
4922 default:
4923 return -EINVAL;
4924 break;
4925 }
4926 return 0;
4927 }
4928
4929 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4930 /*
4931 calibration subdevice
4932 */
4933 static int ni_calib_insn_write(struct comedi_device *dev,
4934 struct comedi_subdevice *s,
4935 struct comedi_insn *insn, unsigned int *data)
4936 {
4937 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4938
4939 return 1;
4940 }
4941
4942 static int ni_calib_insn_read(struct comedi_device *dev,
4943 struct comedi_subdevice *s,
4944 struct comedi_insn *insn, unsigned int *data)
4945 {
4946 struct ni_private *devpriv = dev->private;
4947
4948 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4949
4950 return 1;
4951 }
4952
4953 static int pack_mb88341(int addr, int val, int *bitstring);
4954 static int pack_dac8800(int addr, int val, int *bitstring);
4955 static int pack_dac8043(int addr, int val, int *bitstring);
4956 static int pack_ad8522(int addr, int val, int *bitstring);
4957 static int pack_ad8804(int addr, int val, int *bitstring);
4958 static int pack_ad8842(int addr, int val, int *bitstring);
4959
4960 struct caldac_struct {
4961 int n_chans;
4962 int n_bits;
4963 int (*packbits) (int, int, int *);
4964 };
4965
4966 static struct caldac_struct caldacs[] = {
4967 [mb88341] = {12, 8, pack_mb88341},
4968 [dac8800] = {8, 8, pack_dac8800},
4969 [dac8043] = {1, 12, pack_dac8043},
4970 [ad8522] = {2, 12, pack_ad8522},
4971 [ad8804] = {12, 8, pack_ad8804},
4972 [ad8842] = {8, 8, pack_ad8842},
4973 [ad8804_debug] = {16, 8, pack_ad8804},
4974 };
4975
4976 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4977 {
4978 const struct ni_board_struct *board = comedi_board(dev);
4979 struct ni_private *devpriv = dev->private;
4980 int i, j;
4981 int n_dacs;
4982 int n_chans = 0;
4983 int n_bits;
4984 int diffbits = 0;
4985 int type;
4986 int chan;
4987
4988 type = board->caldac[0];
4989 if (type == caldac_none)
4990 return;
4991 n_bits = caldacs[type].n_bits;
4992 for (i = 0; i < 3; i++) {
4993 type = board->caldac[i];
4994 if (type == caldac_none)
4995 break;
4996 if (caldacs[type].n_bits != n_bits)
4997 diffbits = 1;
4998 n_chans += caldacs[type].n_chans;
4999 }
5000 n_dacs = i;
5001 s->n_chan = n_chans;
5002
5003 if (diffbits) {
5004 unsigned int *maxdata_list;
5005
5006 if (n_chans > MAX_N_CALDACS) {
5007 printk("BUG! MAX_N_CALDACS too small\n");
5008 }
5009 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5010 chan = 0;
5011 for (i = 0; i < n_dacs; i++) {
5012 type = board->caldac[i];
5013 for (j = 0; j < caldacs[type].n_chans; j++) {
5014 maxdata_list[chan] =
5015 (1 << caldacs[type].n_bits) - 1;
5016 chan++;
5017 }
5018 }
5019
5020 for (chan = 0; chan < s->n_chan; chan++)
5021 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5022 } else {
5023 type = board->caldac[0];
5024 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5025
5026 for (chan = 0; chan < s->n_chan; chan++)
5027 ni_write_caldac(dev, i, s->maxdata / 2);
5028 }
5029 }
5030
5031 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5032 {
5033 const struct ni_board_struct *board = comedi_board(dev);
5034 struct ni_private *devpriv = dev->private;
5035 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5036 int i;
5037 int type;
5038
5039 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5040 if (devpriv->caldacs[addr] == val)
5041 return;
5042 devpriv->caldacs[addr] = val;
5043
5044 for (i = 0; i < 3; i++) {
5045 type = board->caldac[i];
5046 if (type == caldac_none)
5047 break;
5048 if (addr < caldacs[type].n_chans) {
5049 bits = caldacs[type].packbits(addr, val, &bitstring);
5050 loadbit = SerDacLd(i);
5051 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5052 break;
5053 }
5054 addr -= caldacs[type].n_chans;
5055 }
5056
5057 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5058 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5059 udelay(1);
5060 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5061 udelay(1);
5062 }
5063 ni_writeb(loadbit, Serial_Command);
5064 udelay(1);
5065 ni_writeb(0, Serial_Command);
5066 }
5067
5068 static int pack_mb88341(int addr, int val, int *bitstring)
5069 {
5070 /*
5071 Fujitsu MB 88341
5072 Note that address bits are reversed. Thanks to
5073 Ingo Keen for noticing this.
5074
5075 Note also that the 88341 expects address values from
5076 1-12, whereas we use channel numbers 0-11. The NI
5077 docs use 1-12, also, so be careful here.
5078 */
5079 addr++;
5080 *bitstring = ((addr & 0x1) << 11) |
5081 ((addr & 0x2) << 9) |
5082 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5083 return 12;
5084 }
5085
5086 static int pack_dac8800(int addr, int val, int *bitstring)
5087 {
5088 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5089 return 11;
5090 }
5091
5092 static int pack_dac8043(int addr, int val, int *bitstring)
5093 {
5094 *bitstring = val & 0xfff;
5095 return 12;
5096 }
5097
5098 static int pack_ad8522(int addr, int val, int *bitstring)
5099 {
5100 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5101 return 16;
5102 }
5103
5104 static int pack_ad8804(int addr, int val, int *bitstring)
5105 {
5106 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5107 return 12;
5108 }
5109
5110 static int pack_ad8842(int addr, int val, int *bitstring)
5111 {
5112 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5113 return 12;
5114 }
5115
5116 #if 0
5117 /*
5118 * Read the GPCTs current value.
5119 */
5120 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5121 {
5122 unsigned int hi1, hi2, lo;
5123
5124 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5125 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5126 G_Command_Register(chan));
5127
5128 devpriv->gpct_command[chan] |= G_Save_Trace;
5129 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5130 G_Command_Register(chan));
5131
5132 /* This procedure is used because the two registers cannot
5133 * be read atomically. */
5134 do {
5135 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5136 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5137 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5138 } while (hi1 != hi2);
5139
5140 return (hi1 << 16) | lo;
5141 }
5142
5143 static void GPCT_Reset(struct comedi_device *dev, int chan)
5144 {
5145 int temp_ack_reg = 0;
5146
5147 /* printk("GPCT_Reset..."); */
5148 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5149
5150 switch (chan) {
5151 case 0:
5152 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5153 ni_set_bits(dev, Interrupt_A_Enable_Register,
5154 G0_TC_Interrupt_Enable, 0);
5155 ni_set_bits(dev, Interrupt_A_Enable_Register,
5156 G0_Gate_Interrupt_Enable, 0);
5157 temp_ack_reg |= G0_Gate_Error_Confirm;
5158 temp_ack_reg |= G0_TC_Error_Confirm;
5159 temp_ack_reg |= G0_TC_Interrupt_Ack;
5160 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5161 devpriv->stc_writew(dev, temp_ack_reg,
5162 Interrupt_A_Ack_Register);
5163
5164 /* problem...this interferes with the other ctr... */
5165 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5166 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5167 Analog_Trigger_Etc_Register);
5168 break;
5169 case 1:
5170 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5171 ni_set_bits(dev, Interrupt_B_Enable_Register,
5172 G1_TC_Interrupt_Enable, 0);
5173 ni_set_bits(dev, Interrupt_B_Enable_Register,
5174 G0_Gate_Interrupt_Enable, 0);
5175 temp_ack_reg |= G1_Gate_Error_Confirm;
5176 temp_ack_reg |= G1_TC_Error_Confirm;
5177 temp_ack_reg |= G1_TC_Interrupt_Ack;
5178 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5179 devpriv->stc_writew(dev, temp_ack_reg,
5180 Interrupt_B_Ack_Register);
5181
5182 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5183 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5184 Analog_Trigger_Etc_Register);
5185 break;
5186 }
5187
5188 devpriv->gpct_mode[chan] = 0;
5189 devpriv->gpct_input_select[chan] = 0;
5190 devpriv->gpct_command[chan] = 0;
5191
5192 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5193
5194 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5195 G_Mode_Register(chan));
5196 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5197 G_Input_Select_Register(chan));
5198 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5199
5200 /* printk("exit GPCT_Reset\n"); */
5201 }
5202
5203 #endif
5204
5205 static int ni_gpct_insn_config(struct comedi_device *dev,
5206 struct comedi_subdevice *s,
5207 struct comedi_insn *insn, unsigned int *data)
5208 {
5209 struct ni_gpct *counter = s->private;
5210 return ni_tio_insn_config(counter, insn, data);
5211 }
5212
5213 static int ni_gpct_insn_read(struct comedi_device *dev,
5214 struct comedi_subdevice *s,
5215 struct comedi_insn *insn, unsigned int *data)
5216 {
5217 struct ni_gpct *counter = s->private;
5218 return ni_tio_rinsn(counter, insn, data);
5219 }
5220
5221 static int ni_gpct_insn_write(struct comedi_device *dev,
5222 struct comedi_subdevice *s,
5223 struct comedi_insn *insn, unsigned int *data)
5224 {
5225 struct ni_gpct *counter = s->private;
5226 return ni_tio_winsn(counter, insn, data);
5227 }
5228
5229 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5230 {
5231 int retval;
5232 #ifdef PCIDMA
5233 struct ni_gpct *counter = s->private;
5234 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5235
5236 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5237 COMEDI_INPUT);
5238 if (retval) {
5239 comedi_error(dev,
5240 "no dma channel available for use by counter");
5241 return retval;
5242 }
5243 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5244 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5245 retval = ni_tio_cmd(counter, s->async);
5246 #else
5247 retval = -ENOTSUPP;
5248 #endif
5249 return retval;
5250 }
5251
5252 static int ni_gpct_cmdtest(struct comedi_device *dev,
5253 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5254 {
5255 #ifdef PCIDMA
5256 struct ni_gpct *counter = s->private;
5257
5258 return ni_tio_cmdtest(counter, cmd);
5259 #else
5260 return -ENOTSUPP;
5261 #endif
5262 }
5263
5264 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5265 {
5266 #ifdef PCIDMA
5267 struct ni_gpct *counter = s->private;
5268 int retval;
5269
5270 retval = ni_tio_cancel(counter);
5271 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5272 ni_release_gpct_mite_channel(dev, counter->counter_index);
5273 return retval;
5274 #else
5275 return 0;
5276 #endif
5277 }
5278
5279 /*
5280 *
5281 * Programmable Function Inputs
5282 *
5283 */
5284
5285 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5286 unsigned source)
5287 {
5288 struct ni_private *devpriv = dev->private;
5289 unsigned pfi_reg_index;
5290 unsigned array_offset;
5291
5292 if ((source & 0x1f) != source)
5293 return -EINVAL;
5294 pfi_reg_index = 1 + chan / 3;
5295 array_offset = pfi_reg_index - 1;
5296 devpriv->pfi_output_select_reg[array_offset] &=
5297 ~MSeries_PFI_Output_Select_Mask(chan);
5298 devpriv->pfi_output_select_reg[array_offset] |=
5299 MSeries_PFI_Output_Select_Bits(chan, source);
5300 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5301 M_Offset_PFI_Output_Select(pfi_reg_index));
5302 return 2;
5303 }
5304
5305 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5306 unsigned source)
5307 {
5308 /* pre-m-series boards have fixed signals on pfi pins */
5309 if (source != ni_old_get_pfi_routing(dev, chan))
5310 return -EINVAL;
5311 return 2;
5312 }
5313
5314 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5315 unsigned source)
5316 {
5317 const struct ni_board_struct *board = comedi_board(dev);
5318
5319 if (board->reg_type & ni_reg_m_series_mask)
5320 return ni_m_series_set_pfi_routing(dev, chan, source);
5321 else
5322 return ni_old_set_pfi_routing(dev, chan, source);
5323 }
5324
5325 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5326 unsigned chan)
5327 {
5328 struct ni_private *devpriv = dev->private;
5329 const unsigned array_offset = chan / 3;
5330
5331 return MSeries_PFI_Output_Select_Source(chan,
5332 devpriv->
5333 pfi_output_select_reg
5334 [array_offset]);
5335 }
5336
5337 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5338 {
5339 /* pre-m-series boards have fixed signals on pfi pins */
5340 switch (chan) {
5341 case 0:
5342 return NI_PFI_OUTPUT_AI_START1;
5343 break;
5344 case 1:
5345 return NI_PFI_OUTPUT_AI_START2;
5346 break;
5347 case 2:
5348 return NI_PFI_OUTPUT_AI_CONVERT;
5349 break;
5350 case 3:
5351 return NI_PFI_OUTPUT_G_SRC1;
5352 break;
5353 case 4:
5354 return NI_PFI_OUTPUT_G_GATE1;
5355 break;
5356 case 5:
5357 return NI_PFI_OUTPUT_AO_UPDATE_N;
5358 break;
5359 case 6:
5360 return NI_PFI_OUTPUT_AO_START1;
5361 break;
5362 case 7:
5363 return NI_PFI_OUTPUT_AI_START_PULSE;
5364 break;
5365 case 8:
5366 return NI_PFI_OUTPUT_G_SRC0;
5367 break;
5368 case 9:
5369 return NI_PFI_OUTPUT_G_GATE0;
5370 break;
5371 default:
5372 printk("%s: bug, unhandled case in switch.\n", __func__);
5373 break;
5374 }
5375 return 0;
5376 }
5377
5378 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5379 {
5380 const struct ni_board_struct *board = comedi_board(dev);
5381
5382 if (board->reg_type & ni_reg_m_series_mask)
5383 return ni_m_series_get_pfi_routing(dev, chan);
5384 else
5385 return ni_old_get_pfi_routing(dev, chan);
5386 }
5387
5388 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5389 enum ni_pfi_filter_select filter)
5390 {
5391 const struct ni_board_struct *board = comedi_board(dev);
5392 struct ni_private *devpriv __maybe_unused = dev->private;
5393 unsigned bits;
5394
5395 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5396 return -ENOTSUPP;
5397 }
5398 bits = ni_readl(M_Offset_PFI_Filter);
5399 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5400 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5401 ni_writel(bits, M_Offset_PFI_Filter);
5402 return 0;
5403 }
5404
5405 static int ni_pfi_insn_bits(struct comedi_device *dev,
5406 struct comedi_subdevice *s,
5407 struct comedi_insn *insn, unsigned int *data)
5408 {
5409 const struct ni_board_struct *board = comedi_board(dev);
5410 struct ni_private *devpriv __maybe_unused = dev->private;
5411
5412 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5413 return -ENOTSUPP;
5414 }
5415 if (data[0]) {
5416 s->state &= ~data[0];
5417 s->state |= (data[0] & data[1]);
5418 ni_writew(s->state, M_Offset_PFI_DO);
5419 }
5420 data[1] = ni_readw(M_Offset_PFI_DI);
5421 return insn->n;
5422 }
5423
5424 static int ni_pfi_insn_config(struct comedi_device *dev,
5425 struct comedi_subdevice *s,
5426 struct comedi_insn *insn, unsigned int *data)
5427 {
5428 struct ni_private *devpriv = dev->private;
5429 unsigned int chan;
5430
5431 if (insn->n < 1)
5432 return -EINVAL;
5433
5434 chan = CR_CHAN(insn->chanspec);
5435
5436 switch (data[0]) {
5437 case COMEDI_OUTPUT:
5438 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5439 break;
5440 case COMEDI_INPUT:
5441 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5442 break;
5443 case INSN_CONFIG_DIO_QUERY:
5444 data[1] =
5445 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5446 COMEDI_OUTPUT : COMEDI_INPUT;
5447 return 0;
5448 break;
5449 case INSN_CONFIG_SET_ROUTING:
5450 return ni_set_pfi_routing(dev, chan, data[1]);
5451 break;
5452 case INSN_CONFIG_GET_ROUTING:
5453 data[1] = ni_get_pfi_routing(dev, chan);
5454 break;
5455 case INSN_CONFIG_FILTER:
5456 return ni_config_filter(dev, chan, data[1]);
5457 break;
5458 default:
5459 return -EINVAL;
5460 }
5461 return 0;
5462 }
5463
5464 /*
5465 *
5466 * NI RTSI Bus Functions
5467 *
5468 */
5469 static void ni_rtsi_init(struct comedi_device *dev)
5470 {
5471 const struct ni_board_struct *board = comedi_board(dev);
5472 struct ni_private *devpriv = dev->private;
5473
5474 /* Initialises the RTSI bus signal switch to a default state */
5475
5476 /* Set clock mode to internal */
5477 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5478 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5479 printk("ni_set_master_clock failed, bug?");
5480 }
5481 /* default internal lines routing to RTSI bus lines */
5482 devpriv->rtsi_trig_a_output_reg =
5483 RTSI_Trig_Output_Bits(0,
5484 NI_RTSI_OUTPUT_ADR_START1) |
5485 RTSI_Trig_Output_Bits(1,
5486 NI_RTSI_OUTPUT_ADR_START2) |
5487 RTSI_Trig_Output_Bits(2,
5488 NI_RTSI_OUTPUT_SCLKG) |
5489 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5490 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5491 RTSI_Trig_A_Output_Register);
5492 devpriv->rtsi_trig_b_output_reg =
5493 RTSI_Trig_Output_Bits(4,
5494 NI_RTSI_OUTPUT_DA_START1) |
5495 RTSI_Trig_Output_Bits(5,
5496 NI_RTSI_OUTPUT_G_SRC0) |
5497 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5498 if (board->reg_type & ni_reg_m_series_mask)
5499 devpriv->rtsi_trig_b_output_reg |=
5500 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5501 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5502 RTSI_Trig_B_Output_Register);
5503
5504 /*
5505 * Sets the source and direction of the 4 on board lines
5506 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5507 */
5508 }
5509
5510 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5511 struct comedi_subdevice *s,
5512 struct comedi_insn *insn, unsigned int *data)
5513 {
5514 data[1] = 0;
5515
5516 return insn->n;
5517 }
5518
5519 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5520 * given an arbitrary frequency input clock */
5521 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5522 unsigned *freq_divider,
5523 unsigned *freq_multiplier,
5524 unsigned *actual_period_ns)
5525 {
5526 unsigned div;
5527 unsigned best_div = 1;
5528 static const unsigned max_div = 0x10;
5529 unsigned mult;
5530 unsigned best_mult = 1;
5531 static const unsigned max_mult = 0x100;
5532 static const unsigned pico_per_nano = 1000;
5533
5534 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5535 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5536 * 20 MHz for most timing clocks */
5537 static const unsigned target_picosec = 12500;
5538 static const unsigned fudge_factor_80_to_20Mhz = 4;
5539 int best_period_picosec = 0;
5540 for (div = 1; div <= max_div; ++div) {
5541 for (mult = 1; mult <= max_mult; ++mult) {
5542 unsigned new_period_ps =
5543 (reference_picosec * div) / mult;
5544 if (abs(new_period_ps - target_picosec) <
5545 abs(best_period_picosec - target_picosec)) {
5546 best_period_picosec = new_period_ps;
5547 best_div = div;
5548 best_mult = mult;
5549 }
5550 }
5551 }
5552 if (best_period_picosec == 0) {
5553 printk("%s: bug, failed to find pll parameters\n", __func__);
5554 return -EIO;
5555 }
5556 *freq_divider = best_div;
5557 *freq_multiplier = best_mult;
5558 *actual_period_ns =
5559 (best_period_picosec * fudge_factor_80_to_20Mhz +
5560 (pico_per_nano / 2)) / pico_per_nano;
5561 return 0;
5562 }
5563
5564 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5565 {
5566 const struct ni_board_struct *board = comedi_board(dev);
5567
5568 if (board->reg_type & ni_reg_m_series_mask)
5569 return 8;
5570 else
5571 return 7;
5572 }
5573
5574 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5575 unsigned source, unsigned period_ns)
5576 {
5577 struct ni_private *devpriv = dev->private;
5578 static const unsigned min_period_ns = 50;
5579 static const unsigned max_period_ns = 1000;
5580 static const unsigned timeout = 1000;
5581 unsigned pll_control_bits;
5582 unsigned freq_divider;
5583 unsigned freq_multiplier;
5584 unsigned i;
5585 int retval;
5586
5587 if (source == NI_MIO_PLL_PXI10_CLOCK)
5588 period_ns = 100;
5589 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5590 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5591 printk
5592 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5593 "for the phased-lock loop.\n", __func__,
5594 min_period_ns, max_period_ns);
5595 return -EINVAL;
5596 }
5597 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5598 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5599 RTSI_Trig_Direction_Register);
5600 pll_control_bits =
5601 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5602 devpriv->clock_and_fout2 |=
5603 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5604 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5605 switch (source) {
5606 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5607 devpriv->clock_and_fout2 |=
5608 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5609 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5610 &freq_multiplier,
5611 &devpriv->clock_ns);
5612 if (retval < 0)
5613 return retval;
5614 break;
5615 case NI_MIO_PLL_PXI10_CLOCK:
5616 /* pxi clock is 10MHz */
5617 devpriv->clock_and_fout2 |=
5618 MSeries_PLL_In_Source_Select_PXI_Clock10;
5619 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5620 &freq_multiplier,
5621 &devpriv->clock_ns);
5622 if (retval < 0)
5623 return retval;
5624 break;
5625 default:
5626 {
5627 unsigned rtsi_channel;
5628 static const unsigned max_rtsi_channel = 7;
5629 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5630 ++rtsi_channel) {
5631 if (source ==
5632 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5633 devpriv->clock_and_fout2 |=
5634 MSeries_PLL_In_Source_Select_RTSI_Bits
5635 (rtsi_channel);
5636 break;
5637 }
5638 }
5639 if (rtsi_channel > max_rtsi_channel)
5640 return -EINVAL;
5641 retval = ni_mseries_get_pll_parameters(period_ns,
5642 &freq_divider,
5643 &freq_multiplier,
5644 &devpriv->
5645 clock_ns);
5646 if (retval < 0)
5647 return retval;
5648 }
5649 break;
5650 }
5651 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5652 pll_control_bits |=
5653 MSeries_PLL_Divisor_Bits(freq_divider) |
5654 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5655
5656 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5657 * freq_divider, freq_multiplier, pll_control_bits); */
5658 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5659 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5660 devpriv->clock_source = source;
5661 /* it seems to typically take a few hundred microseconds for PLL to lock */
5662 for (i = 0; i < timeout; ++i) {
5663 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5664 break;
5665 }
5666 udelay(1);
5667 }
5668 if (i == timeout) {
5669 printk
5670 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5671 __func__, source, period_ns);
5672 return -ETIMEDOUT;
5673 }
5674 return 3;
5675 }
5676
5677 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5678 unsigned period_ns)
5679 {
5680 const struct ni_board_struct *board = comedi_board(dev);
5681 struct ni_private *devpriv = dev->private;
5682
5683 if (source == NI_MIO_INTERNAL_CLOCK) {
5684 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5685 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5686 RTSI_Trig_Direction_Register);
5687 devpriv->clock_ns = TIMEBASE_1_NS;
5688 if (board->reg_type & ni_reg_m_series_mask) {
5689 devpriv->clock_and_fout2 &=
5690 ~(MSeries_Timebase1_Select_Bit |
5691 MSeries_Timebase3_Select_Bit);
5692 ni_writew(devpriv->clock_and_fout2,
5693 M_Offset_Clock_and_Fout2);
5694 ni_writew(0, M_Offset_PLL_Control);
5695 }
5696 devpriv->clock_source = source;
5697 } else {
5698 if (board->reg_type & ni_reg_m_series_mask) {
5699 return ni_mseries_set_pll_master_clock(dev, source,
5700 period_ns);
5701 } else {
5702 if (source == NI_MIO_RTSI_CLOCK) {
5703 devpriv->rtsi_trig_direction_reg |=
5704 Use_RTSI_Clock_Bit;
5705 devpriv->stc_writew(dev,
5706 devpriv->
5707 rtsi_trig_direction_reg,
5708 RTSI_Trig_Direction_Register);
5709 if (period_ns == 0) {
5710 printk
5711 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5712 __func__);
5713 return -EINVAL;
5714 } else {
5715 devpriv->clock_ns = period_ns;
5716 }
5717 devpriv->clock_source = source;
5718 } else
5719 return -EINVAL;
5720 }
5721 }
5722 return 3;
5723 }
5724
5725 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5726 unsigned source)
5727 {
5728 const struct ni_board_struct *board = comedi_board(dev);
5729
5730 if (chan >= num_configurable_rtsi_channels(dev)) {
5731 if (chan == old_RTSI_clock_channel) {
5732 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5733 return 1;
5734 else {
5735 printk
5736 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5737 __func__, chan, old_RTSI_clock_channel);
5738 return 0;
5739 }
5740 }
5741 return 0;
5742 }
5743 switch (source) {
5744 case NI_RTSI_OUTPUT_ADR_START1:
5745 case NI_RTSI_OUTPUT_ADR_START2:
5746 case NI_RTSI_OUTPUT_SCLKG:
5747 case NI_RTSI_OUTPUT_DACUPDN:
5748 case NI_RTSI_OUTPUT_DA_START1:
5749 case NI_RTSI_OUTPUT_G_SRC0:
5750 case NI_RTSI_OUTPUT_G_GATE0:
5751 case NI_RTSI_OUTPUT_RGOUT0:
5752 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5753 return 1;
5754 break;
5755 case NI_RTSI_OUTPUT_RTSI_OSC:
5756 if (board->reg_type & ni_reg_m_series_mask)
5757 return 1;
5758 else
5759 return 0;
5760 break;
5761 default:
5762 return 0;
5763 break;
5764 }
5765 }
5766
5767 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5768 unsigned source)
5769 {
5770 struct ni_private *devpriv = dev->private;
5771
5772 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5773 return -EINVAL;
5774 if (chan < 4) {
5775 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5776 devpriv->rtsi_trig_a_output_reg |=
5777 RTSI_Trig_Output_Bits(chan, source);
5778 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5779 RTSI_Trig_A_Output_Register);
5780 } else if (chan < 8) {
5781 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5782 devpriv->rtsi_trig_b_output_reg |=
5783 RTSI_Trig_Output_Bits(chan, source);
5784 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5785 RTSI_Trig_B_Output_Register);
5786 }
5787 return 2;
5788 }
5789
5790 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5791 {
5792 struct ni_private *devpriv = dev->private;
5793
5794 if (chan < 4) {
5795 return RTSI_Trig_Output_Source(chan,
5796 devpriv->rtsi_trig_a_output_reg);
5797 } else if (chan < num_configurable_rtsi_channels(dev)) {
5798 return RTSI_Trig_Output_Source(chan,
5799 devpriv->rtsi_trig_b_output_reg);
5800 } else {
5801 if (chan == old_RTSI_clock_channel)
5802 return NI_RTSI_OUTPUT_RTSI_OSC;
5803 printk("%s: bug! should never get here?\n", __func__);
5804 return 0;
5805 }
5806 }
5807
5808 static int ni_rtsi_insn_config(struct comedi_device *dev,
5809 struct comedi_subdevice *s,
5810 struct comedi_insn *insn, unsigned int *data)
5811 {
5812 const struct ni_board_struct *board = comedi_board(dev);
5813 struct ni_private *devpriv = dev->private;
5814 unsigned int chan = CR_CHAN(insn->chanspec);
5815
5816 switch (data[0]) {
5817 case INSN_CONFIG_DIO_OUTPUT:
5818 if (chan < num_configurable_rtsi_channels(dev)) {
5819 devpriv->rtsi_trig_direction_reg |=
5820 RTSI_Output_Bit(chan,
5821 (board->reg_type & ni_reg_m_series_mask) != 0);
5822 } else if (chan == old_RTSI_clock_channel) {
5823 devpriv->rtsi_trig_direction_reg |=
5824 Drive_RTSI_Clock_Bit;
5825 }
5826 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5827 RTSI_Trig_Direction_Register);
5828 break;
5829 case INSN_CONFIG_DIO_INPUT:
5830 if (chan < num_configurable_rtsi_channels(dev)) {
5831 devpriv->rtsi_trig_direction_reg &=
5832 ~RTSI_Output_Bit(chan,
5833 (board->reg_type & ni_reg_m_series_mask) != 0);
5834 } else if (chan == old_RTSI_clock_channel) {
5835 devpriv->rtsi_trig_direction_reg &=
5836 ~Drive_RTSI_Clock_Bit;
5837 }
5838 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5839 RTSI_Trig_Direction_Register);
5840 break;
5841 case INSN_CONFIG_DIO_QUERY:
5842 if (chan < num_configurable_rtsi_channels(dev)) {
5843 data[1] =
5844 (devpriv->rtsi_trig_direction_reg &
5845 RTSI_Output_Bit(chan,
5846 (board->reg_type & ni_reg_m_series_mask) != 0))
5847 ? INSN_CONFIG_DIO_OUTPUT
5848 : INSN_CONFIG_DIO_INPUT;
5849 } else if (chan == old_RTSI_clock_channel) {
5850 data[1] =
5851 (devpriv->rtsi_trig_direction_reg &
5852 Drive_RTSI_Clock_Bit)
5853 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5854 }
5855 return 2;
5856 break;
5857 case INSN_CONFIG_SET_CLOCK_SRC:
5858 return ni_set_master_clock(dev, data[1], data[2]);
5859 break;
5860 case INSN_CONFIG_GET_CLOCK_SRC:
5861 data[1] = devpriv->clock_source;
5862 data[2] = devpriv->clock_ns;
5863 return 3;
5864 break;
5865 case INSN_CONFIG_SET_ROUTING:
5866 return ni_set_rtsi_routing(dev, chan, data[1]);
5867 break;
5868 case INSN_CONFIG_GET_ROUTING:
5869 data[1] = ni_get_rtsi_routing(dev, chan);
5870 return 2;
5871 break;
5872 default:
5873 return -EINVAL;
5874 break;
5875 }
5876 return 1;
5877 }
5878
5879 static int cs5529_wait_for_idle(struct comedi_device *dev)
5880 {
5881 unsigned short status;
5882 const int timeout = HZ;
5883 int i;
5884
5885 for (i = 0; i < timeout; i++) {
5886 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5887 if ((status & CSS_ADC_BUSY) == 0) {
5888 break;
5889 }
5890 set_current_state(TASK_INTERRUPTIBLE);
5891 if (schedule_timeout(1)) {
5892 return -EIO;
5893 }
5894 }
5895 /* printk("looped %i times waiting for idle\n", i); */
5896 if (i == timeout) {
5897 printk("%s: %s: timeout\n", __FILE__, __func__);
5898 return -ETIME;
5899 }
5900 return 0;
5901 }
5902
5903 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5904 {
5905 static const int timeout = 100;
5906 int i;
5907
5908 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5909 /* give time for command to start being serially clocked into cs5529.
5910 * this insures that the CSS_ADC_BUSY bit will get properly
5911 * set before we exit this function.
5912 */
5913 for (i = 0; i < timeout; i++) {
5914 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5915 break;
5916 udelay(1);
5917 }
5918 /* printk("looped %i times writing command to cs5529\n", i); */
5919 if (i == timeout) {
5920 comedi_error(dev, "possible problem - never saw adc go busy?");
5921 }
5922 }
5923
5924 /* write to cs5529 register */
5925 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5926 unsigned int reg_select_bits)
5927 {
5928 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5929 CAL_ADC_Config_Data_High_Word_67xx);
5930 ni_ao_win_outw(dev, (value & 0xffff),
5931 CAL_ADC_Config_Data_Low_Word_67xx);
5932 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5933 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5934 if (cs5529_wait_for_idle(dev))
5935 comedi_error(dev, "time or signal in cs5529_config_write()");
5936 }
5937
5938 #ifdef NI_CS5529_DEBUG
5939 /* read from cs5529 register */
5940 static unsigned int cs5529_config_read(struct comedi_device *dev,
5941 unsigned int reg_select_bits)
5942 {
5943 unsigned int value;
5944
5945 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5946 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5947 if (cs5529_wait_for_idle(dev))
5948 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5949 value = (ni_ao_win_inw(dev,
5950 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5951 0xff0000;
5952 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5953 return value;
5954 }
5955 #endif
5956
5957 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5958 {
5959 int retval;
5960 unsigned short status;
5961
5962 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5963 retval = cs5529_wait_for_idle(dev);
5964 if (retval) {
5965 comedi_error(dev,
5966 "timeout or signal in cs5529_do_conversion()");
5967 return -ETIME;
5968 }
5969 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5970 if (status & CSS_OSC_DETECT) {
5971 printk
5972 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5973 return -EIO;
5974 }
5975 if (status & CSS_OVERRANGE) {
5976 printk
5977 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5978 }
5979 if (data) {
5980 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5981 /* cs5529 returns 16 bit signed data in bipolar mode */
5982 *data ^= (1 << 15);
5983 }
5984 return 0;
5985 }
5986
5987 static int cs5529_ai_insn_read(struct comedi_device *dev,
5988 struct comedi_subdevice *s,
5989 struct comedi_insn *insn, unsigned int *data)
5990 {
5991 int n, retval;
5992 unsigned short sample;
5993 unsigned int channel_select;
5994 const unsigned int INTERNAL_REF = 0x1000;
5995
5996 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5997 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5998 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5999 if (insn->chanspec & CR_ALT_SOURCE)
6000 channel_select = INTERNAL_REF;
6001 else
6002 channel_select = CR_CHAN(insn->chanspec);
6003 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
6004
6005 for (n = 0; n < insn->n; n++) {
6006 retval = cs5529_do_conversion(dev, &sample);
6007 if (retval < 0)
6008 return retval;
6009 data[n] = sample;
6010 }
6011 return insn->n;
6012 }
6013
6014 static int init_cs5529(struct comedi_device *dev)
6015 {
6016 unsigned int config_bits =
6017 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6018
6019 #if 1
6020 /* do self-calibration */
6021 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6022 CSCMD_CONFIG_REGISTER);
6023 /* need to force a conversion for calibration to run */
6024 cs5529_do_conversion(dev, NULL);
6025 #else
6026 /* force gain calibration to 1 */
6027 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6028 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6029 CSCMD_CONFIG_REGISTER);
6030 if (cs5529_wait_for_idle(dev))
6031 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6032 #endif
6033 #ifdef NI_CS5529_DEBUG
6034 printk("config: 0x%x\n", cs5529_config_read(dev,
6035 CSCMD_CONFIG_REGISTER));
6036 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6037 printk("offset: 0x%x\n", cs5529_config_read(dev,
6038 CSCMD_OFFSET_REGISTER));
6039 #endif
6040 return 0;
6041 }
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