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staging: comedi: ni_stc.h: tidy up DIO_Parallel_Input_Register
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53 */
54
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
58 #include "8255.h"
59 #include "mite.h"
60
61 /* A timeout count */
62 #define NI_TIMEOUT 1000
63
64 /* Note: this table must match the ai_gain_* definitions */
65 static const short ni_gainlkup[][16] = {
66 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
67 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
69 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
70 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
71 [ai_gain_4] = {0, 1, 4, 7},
72 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
73 0x003, 0x004, 0x005, 0x006},
74 [ai_gain_622x] = {0, 1, 4, 5},
75 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
76 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
77 };
78
79 static const struct comedi_lrange range_ni_E_ai = {
80 16, {
81 BIP_RANGE(10),
82 BIP_RANGE(5),
83 BIP_RANGE(2.5),
84 BIP_RANGE(1),
85 BIP_RANGE(0.5),
86 BIP_RANGE(0.25),
87 BIP_RANGE(0.1),
88 BIP_RANGE(0.05),
89 UNI_RANGE(20),
90 UNI_RANGE(10),
91 UNI_RANGE(5),
92 UNI_RANGE(2),
93 UNI_RANGE(1),
94 UNI_RANGE(0.5),
95 UNI_RANGE(0.2),
96 UNI_RANGE(0.1)
97 }
98 };
99
100 static const struct comedi_lrange range_ni_E_ai_limited = {
101 8, {
102 BIP_RANGE(10),
103 BIP_RANGE(5),
104 BIP_RANGE(1),
105 BIP_RANGE(0.1),
106 UNI_RANGE(10),
107 UNI_RANGE(5),
108 UNI_RANGE(1),
109 UNI_RANGE(0.1)
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
114 14, {
115 BIP_RANGE(10),
116 BIP_RANGE(5),
117 BIP_RANGE(2),
118 BIP_RANGE(1),
119 BIP_RANGE(0.5),
120 BIP_RANGE(0.2),
121 BIP_RANGE(0.1),
122 UNI_RANGE(10),
123 UNI_RANGE(5),
124 UNI_RANGE(2),
125 UNI_RANGE(1),
126 UNI_RANGE(0.5),
127 UNI_RANGE(0.2),
128 UNI_RANGE(0.1)
129 }
130 };
131
132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
133 4, {
134 BIP_RANGE(10),
135 BIP_RANGE(5),
136 BIP_RANGE(0.5),
137 BIP_RANGE(0.05)
138 }
139 };
140
141 static const struct comedi_lrange range_ni_E_ai_611x = {
142 8, {
143 BIP_RANGE(50),
144 BIP_RANGE(20),
145 BIP_RANGE(10),
146 BIP_RANGE(5),
147 BIP_RANGE(2),
148 BIP_RANGE(1),
149 BIP_RANGE(0.5),
150 BIP_RANGE(0.2)
151 }
152 };
153
154 static const struct comedi_lrange range_ni_M_ai_622x = {
155 4, {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(1),
159 BIP_RANGE(0.2)
160 }
161 };
162
163 static const struct comedi_lrange range_ni_M_ai_628x = {
164 7, {
165 BIP_RANGE(10),
166 BIP_RANGE(5),
167 BIP_RANGE(2),
168 BIP_RANGE(1),
169 BIP_RANGE(0.5),
170 BIP_RANGE(0.2),
171 BIP_RANGE(0.1)
172 }
173 };
174
175 static const struct comedi_lrange range_ni_E_ao_ext = {
176 4, {
177 BIP_RANGE(10),
178 UNI_RANGE(10),
179 RANGE_ext(-1, 1),
180 RANGE_ext(0, 1)
181 }
182 };
183
184 static const struct comedi_lrange *const ni_range_lkup[] = {
185 [ai_gain_16] = &range_ni_E_ai,
186 [ai_gain_8] = &range_ni_E_ai_limited,
187 [ai_gain_14] = &range_ni_E_ai_limited14,
188 [ai_gain_4] = &range_ni_E_ai_bipolar4,
189 [ai_gain_611x] = &range_ni_E_ai_611x,
190 [ai_gain_622x] = &range_ni_M_ai_622x,
191 [ai_gain_628x] = &range_ni_M_ai_628x,
192 [ai_gain_6143] = &range_bipolar5
193 };
194
195 enum aimodes {
196 AIMODE_NONE = 0,
197 AIMODE_HALF_FULL = 1,
198 AIMODE_SCAN = 2,
199 AIMODE_SAMPLE = 3,
200 };
201
202 enum ni_common_subdevices {
203 NI_AI_SUBDEV,
204 NI_AO_SUBDEV,
205 NI_DIO_SUBDEV,
206 NI_8255_DIO_SUBDEV,
207 NI_UNUSED_SUBDEV,
208 NI_CALIBRATION_SUBDEV,
209 NI_EEPROM_SUBDEV,
210 NI_PFI_DIO_SUBDEV,
211 NI_CS5529_CALIBRATION_SUBDEV,
212 NI_SERIAL_SUBDEV,
213 NI_RTSI_SUBDEV,
214 NI_GPCT0_SUBDEV,
215 NI_GPCT1_SUBDEV,
216 NI_FREQ_OUT_SUBDEV,
217 NI_NUM_SUBDEVICES
218 };
219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
220 {
221 switch (counter_index) {
222 case 0:
223 return NI_GPCT0_SUBDEV;
224 case 1:
225 return NI_GPCT1_SUBDEV;
226 default:
227 break;
228 }
229 BUG();
230 return NI_GPCT0_SUBDEV;
231 }
232
233 enum timebase_nanoseconds {
234 TIMEBASE_1_NS = 50,
235 TIMEBASE_2_NS = 10000
236 };
237
238 #define SERIAL_DISABLED 0
239 #define SERIAL_600NS 600
240 #define SERIAL_1_2US 1200
241 #define SERIAL_10US 10000
242
243 static const int num_adc_stages_611x = 3;
244
245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
246 {
247 if (dev->mmio)
248 writel(data, dev->mmio + reg);
249
250 outl(data, dev->iobase + reg);
251 }
252
253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
254 {
255 if (dev->mmio)
256 writew(data, dev->mmio + reg);
257
258 outw(data, dev->iobase + reg);
259 }
260
261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
262 {
263 if (dev->mmio)
264 writeb(data, dev->mmio + reg);
265
266 outb(data, dev->iobase + reg);
267 }
268
269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
270 {
271 if (dev->mmio)
272 return readl(dev->mmio + reg);
273
274 return inl(dev->iobase + reg);
275 }
276
277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
278 {
279 if (dev->mmio)
280 return readw(dev->mmio + reg);
281
282 return inw(dev->iobase + reg);
283 }
284
285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
286 {
287 if (dev->mmio)
288 return readb(dev->mmio + reg);
289
290 return inb(dev->iobase + reg);
291 }
292
293 /*
294 * We automatically take advantage of STC registers that can be
295 * read/written directly in the I/O space of the board.
296 *
297 * The AT-MIO and DAQCard devices map the low 8 STC registers to
298 * iobase+reg*2.
299 *
300 * Most PCIMIO devices also map the low 8 STC registers but the
301 * 611x devices map the read registers to iobase+(addr-1)*2.
302 * For now non-windowed STC access is disabled if a PCIMIO device
303 * is detected (devpriv->mite has been initialized).
304 *
305 * The M series devices do not used windowed registers for the
306 * STC registers. The functions below handle the mapping of the
307 * windowed STC registers to the m series register offsets.
308 */
309
310 struct mio_regmap {
311 unsigned int mio_reg;
312 int size;
313 };
314
315 static const struct mio_regmap m_series_stc_write_regmap[] = {
316 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
317 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
318 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
319 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
320 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
321 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
322 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
323 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
324 /*
325 * NISTC_DIO_OUT_REG maps to:
326 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
327 */
328 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
329 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
330 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
331 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
332 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
333 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
334 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
335 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
336 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
337 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
338 [NISTC_G0_MODE_REG] = { 0x134, 2 },
339 [NISTC_G1_MODE_REG] = { 0x136, 2 },
340 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
341 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
342 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
343 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
344 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
345 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
346 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
347 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
348 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
349 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
350 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
351 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
352 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
353 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
354 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
355 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
356 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
357 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
358 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
359 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
360 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
361 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
362 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
363 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
364 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
365 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
366 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
367 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
368 [NISTC_RESET_REG] = { 0x190, 2 },
369 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
370 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
371 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
372 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
373 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
374 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
375 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
376 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
377 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
378 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
379 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
380 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
381 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
382 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
383 };
384
385 static void m_series_stc_write(struct comedi_device *dev,
386 unsigned int data, unsigned int reg)
387 {
388 const struct mio_regmap *regmap;
389
390 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
391 regmap = &m_series_stc_write_regmap[reg];
392 } else {
393 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
394 __func__, reg);
395 return;
396 }
397
398 switch (regmap->size) {
399 case 4:
400 ni_writel(dev, data, regmap->mio_reg);
401 break;
402 case 2:
403 ni_writew(dev, data, regmap->mio_reg);
404 break;
405 default:
406 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
407 __func__, reg);
408 break;
409 }
410 }
411
412 static const struct mio_regmap m_series_stc_read_regmap[] = {
413 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
414 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
415 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
416 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
417 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
418 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
419 [G_HW_Save_Register(0)] = { 0x110, 4 },
420 [G_HW_Save_Register(1)] = { 0x114, 4 },
421 [G_Save_Register(0)] = { 0x118, 4 },
422 [G_Save_Register(1)] = { 0x11c, 4 },
423 [AO_UI_Save_Registers] = { 0x120, 4 },
424 [AO_BC_Save_Registers] = { 0x124, 4 },
425 [AO_UC_Save_Registers] = { 0x128, 4 },
426 [Joint_Status_1_Register] = { 0x136, 2 },
427 [DIO_Serial_Input_Register] = { 0x009, 1 },
428 [Joint_Status_2_Register] = { 0x13a, 2 },
429 [AI_SI_Save_Registers] = { 0x180, 4 },
430 [AI_SC_Save_Registers] = { 0x184, 4 },
431 };
432
433 static unsigned int m_series_stc_read(struct comedi_device *dev,
434 unsigned int reg)
435 {
436 const struct mio_regmap *regmap;
437
438 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
439 regmap = &m_series_stc_read_regmap[reg];
440 } else {
441 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
442 __func__, reg);
443 return 0;
444 }
445
446 switch (regmap->size) {
447 case 4:
448 return ni_readl(dev, regmap->mio_reg);
449 case 2:
450 return ni_readw(dev, regmap->mio_reg);
451 case 1:
452 return ni_readb(dev, regmap->mio_reg);
453 default:
454 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
455 __func__, reg);
456 return 0;
457 }
458 }
459
460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
461 {
462 struct ni_private *devpriv = dev->private;
463 unsigned long flags;
464
465 if (devpriv->is_m_series) {
466 m_series_stc_write(dev, data, reg);
467 } else {
468 spin_lock_irqsave(&devpriv->window_lock, flags);
469 if (!devpriv->mite && reg < 8) {
470 ni_writew(dev, data, reg * 2);
471 } else {
472 ni_writew(dev, reg, Window_Address);
473 ni_writew(dev, data, Window_Data);
474 }
475 spin_unlock_irqrestore(&devpriv->window_lock, flags);
476 }
477 }
478
479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482
483 if (devpriv->is_m_series) {
484 m_series_stc_write(dev, data, reg);
485 } else {
486 ni_stc_writew(dev, data >> 16, reg);
487 ni_stc_writew(dev, data & 0xffff, reg + 1);
488 }
489 }
490
491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
492 {
493 struct ni_private *devpriv = dev->private;
494 unsigned long flags;
495 uint16_t val;
496
497 if (devpriv->is_m_series) {
498 val = m_series_stc_read(dev, reg);
499 } else {
500 spin_lock_irqsave(&devpriv->window_lock, flags);
501 if (!devpriv->mite && reg < 8) {
502 val = ni_readw(dev, reg * 2);
503 } else {
504 ni_writew(dev, reg, Window_Address);
505 val = ni_readw(dev, Window_Data);
506 }
507 spin_unlock_irqrestore(&devpriv->window_lock, flags);
508 }
509 return val;
510 }
511
512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
513 {
514 struct ni_private *devpriv = dev->private;
515 uint32_t val;
516
517 if (devpriv->is_m_series) {
518 val = m_series_stc_read(dev, reg);
519 } else {
520 val = ni_stc_readw(dev, reg) << 16;
521 val |= ni_stc_readw(dev, reg + 1);
522 }
523 return val;
524 }
525
526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
527 unsigned bit_mask, unsigned bit_values)
528 {
529 struct ni_private *devpriv = dev->private;
530 unsigned long flags;
531
532 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
533 switch (reg) {
534 case NISTC_INTA_ENA_REG:
535 devpriv->int_a_enable_reg &= ~bit_mask;
536 devpriv->int_a_enable_reg |= bit_values & bit_mask;
537 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
538 break;
539 case NISTC_INTB_ENA_REG:
540 devpriv->int_b_enable_reg &= ~bit_mask;
541 devpriv->int_b_enable_reg |= bit_values & bit_mask;
542 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
543 break;
544 case NISTC_IO_BIDIR_PIN_REG:
545 devpriv->io_bidirection_pin_reg &= ~bit_mask;
546 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
547 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
548 break;
549 case AI_AO_Select:
550 devpriv->ai_ao_select_reg &= ~bit_mask;
551 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
552 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
553 break;
554 case G0_G1_Select:
555 devpriv->g0_g1_select_reg &= ~bit_mask;
556 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
557 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
558 break;
559 default:
560 dev_err(dev->class_dev, "called with invalid register %d\n",
561 reg);
562 break;
563 }
564 mmiowb();
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
566 }
567
568 #ifdef PCIDMA
569 /* DMA channel setup */
570
571 /* negative channel means no channel */
572 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
573 {
574 unsigned bitfield;
575
576 if (channel >= 0)
577 bitfield =
578 (ni_stc_dma_channel_select_bitfield(channel) <<
579 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
580 else
581 bitfield = 0;
582 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
583 }
584
585 /* negative channel means no channel */
586 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
587 {
588 unsigned bitfield;
589
590 if (channel >= 0)
591 bitfield =
592 (ni_stc_dma_channel_select_bitfield(channel) <<
593 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
594 else
595 bitfield = 0;
596 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
597 }
598
599 /* negative mite_channel means no channel */
600 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
601 unsigned gpct_index,
602 int mite_channel)
603 {
604 unsigned bitfield;
605
606 if (mite_channel >= 0)
607 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
608 else
609 bitfield = 0;
610 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
611 bitfield);
612 }
613
614 /* negative mite_channel means no channel */
615 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
616 int mite_channel)
617 {
618 struct ni_private *devpriv = dev->private;
619 unsigned long flags;
620 unsigned bits;
621
622 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
623 devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
624 if (mite_channel >= 0) {
625 /*
626 * XXX just guessing ni_stc_dma_channel_select_bitfield()
627 * returns the right bits, under the assumption the cdio dma
628 * selection works just like ai/ao/gpct.
629 * Definitely works for dma channels 0 and 1.
630 */
631 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
632 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
633 }
634 ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
635 mmiowb();
636 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
637 }
638
639 static int ni_request_ai_mite_channel(struct comedi_device *dev)
640 {
641 struct ni_private *devpriv = dev->private;
642 unsigned long flags;
643
644 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
645 BUG_ON(devpriv->ai_mite_chan);
646 devpriv->ai_mite_chan =
647 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
648 if (!devpriv->ai_mite_chan) {
649 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
650 dev_err(dev->class_dev,
651 "failed to reserve mite dma channel for analog input\n");
652 return -EBUSY;
653 }
654 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
655 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
656 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
657 return 0;
658 }
659
660 static int ni_request_ao_mite_channel(struct comedi_device *dev)
661 {
662 struct ni_private *devpriv = dev->private;
663 unsigned long flags;
664
665 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
666 BUG_ON(devpriv->ao_mite_chan);
667 devpriv->ao_mite_chan =
668 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
669 if (!devpriv->ao_mite_chan) {
670 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
671 dev_err(dev->class_dev,
672 "failed to reserve mite dma channel for analog outut\n");
673 return -EBUSY;
674 }
675 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
676 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
678 return 0;
679 }
680
681 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
682 unsigned gpct_index,
683 enum comedi_io_direction direction)
684 {
685 struct ni_private *devpriv = dev->private;
686 unsigned long flags;
687 struct mite_channel *mite_chan;
688
689 BUG_ON(gpct_index >= NUM_GPCT);
690 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
691 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
692 mite_chan =
693 mite_request_channel(devpriv->mite,
694 devpriv->gpct_mite_ring[gpct_index]);
695 if (!mite_chan) {
696 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
697 dev_err(dev->class_dev,
698 "failed to reserve mite dma channel for counter\n");
699 return -EBUSY;
700 }
701 mite_chan->dir = direction;
702 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
703 mite_chan);
704 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
705 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
706 return 0;
707 }
708
709 #endif /* PCIDMA */
710
711 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
712 {
713 #ifdef PCIDMA
714 struct ni_private *devpriv = dev->private;
715 unsigned long flags;
716
717 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
718 BUG_ON(devpriv->cdo_mite_chan);
719 devpriv->cdo_mite_chan =
720 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
721 if (!devpriv->cdo_mite_chan) {
722 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
723 dev_err(dev->class_dev,
724 "failed to reserve mite dma channel for correlated digital output\n");
725 return -EBUSY;
726 }
727 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
728 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
729 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
730 #endif /* PCIDMA */
731 return 0;
732 }
733
734 static void ni_release_ai_mite_channel(struct comedi_device *dev)
735 {
736 #ifdef PCIDMA
737 struct ni_private *devpriv = dev->private;
738 unsigned long flags;
739
740 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
741 if (devpriv->ai_mite_chan) {
742 ni_set_ai_dma_channel(dev, -1);
743 mite_release_channel(devpriv->ai_mite_chan);
744 devpriv->ai_mite_chan = NULL;
745 }
746 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
747 #endif /* PCIDMA */
748 }
749
750 static void ni_release_ao_mite_channel(struct comedi_device *dev)
751 {
752 #ifdef PCIDMA
753 struct ni_private *devpriv = dev->private;
754 unsigned long flags;
755
756 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
757 if (devpriv->ao_mite_chan) {
758 ni_set_ao_dma_channel(dev, -1);
759 mite_release_channel(devpriv->ao_mite_chan);
760 devpriv->ao_mite_chan = NULL;
761 }
762 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
763 #endif /* PCIDMA */
764 }
765
766 #ifdef PCIDMA
767 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
768 unsigned gpct_index)
769 {
770 struct ni_private *devpriv = dev->private;
771 unsigned long flags;
772
773 BUG_ON(gpct_index >= NUM_GPCT);
774 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
775 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
776 struct mite_channel *mite_chan =
777 devpriv->counter_dev->counters[gpct_index].mite_chan;
778
779 ni_set_gpct_dma_channel(dev, gpct_index, -1);
780 ni_tio_set_mite_channel(&devpriv->
781 counter_dev->counters[gpct_index],
782 NULL);
783 mite_release_channel(mite_chan);
784 }
785 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
786 }
787 #endif /* PCIDMA */
788
789 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
790 {
791 #ifdef PCIDMA
792 struct ni_private *devpriv = dev->private;
793 unsigned long flags;
794
795 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
796 if (devpriv->cdo_mite_chan) {
797 ni_set_cdo_dma_channel(dev, -1);
798 mite_release_channel(devpriv->cdo_mite_chan);
799 devpriv->cdo_mite_chan = NULL;
800 }
801 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
802 #endif /* PCIDMA */
803 }
804
805 #ifdef PCIDMA
806 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
807 unsigned gpct_index, short enable)
808 {
809 struct ni_private *devpriv = dev->private;
810 uint16_t val = 0;
811 int reg;
812
813 if (devpriv->is_m_series || gpct_index > 1)
814 return;
815
816 /*
817 * e-series boards use the second irq signals to generate
818 * dma requests for their counters
819 */
820 if (gpct_index == 0) {
821 reg = NISTC_INTA2_ENA_REG;
822 if (enable)
823 val = NISTC_INTA_ENA_G0_GATE;
824 } else {
825 reg = NISTC_INTB2_ENA_REG;
826 if (enable)
827 val = NISTC_INTB_ENA_G1_GATE;
828 }
829 ni_stc_writew(dev, val, reg);
830 }
831 #endif /* PCIDMA */
832
833 static void ni_clear_ai_fifo(struct comedi_device *dev)
834 {
835 struct ni_private *devpriv = dev->private;
836 static const int timeout = 10000;
837 int i;
838
839 if (devpriv->is_6143) {
840 /* Flush the 6143 data FIFO */
841 ni_writel(dev, 0x10, AIFIFO_Control_6143);
842 ni_writel(dev, 0x00, AIFIFO_Control_6143);
843 /* Wait for complete */
844 for (i = 0; i < timeout; i++) {
845 if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
846 break;
847 udelay(1);
848 }
849 if (i == timeout)
850 dev_err(dev->class_dev, "FIFO flush timeout\n");
851 } else {
852 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
853 if (devpriv->is_625x) {
854 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
855 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
856 #if 0
857 /* the NI example code does 3 convert pulses for 625x boards,
858 but that appears to be wrong in practice. */
859 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
860 NISTC_AI_CMD1_REG);
861 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
862 NISTC_AI_CMD1_REG);
863 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
864 NISTC_AI_CMD1_REG);
865 #endif
866 }
867 }
868 }
869
870 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
871 int addr)
872 {
873 struct ni_private *devpriv = dev->private;
874 unsigned long flags;
875
876 spin_lock_irqsave(&devpriv->window_lock, flags);
877 ni_writew(dev, addr, AO_Window_Address_611x);
878 ni_writew(dev, data, AO_Window_Data_611x);
879 spin_unlock_irqrestore(&devpriv->window_lock, flags);
880 }
881
882 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
883 int addr)
884 {
885 struct ni_private *devpriv = dev->private;
886 unsigned long flags;
887
888 spin_lock_irqsave(&devpriv->window_lock, flags);
889 ni_writew(dev, addr, AO_Window_Address_611x);
890 ni_writel(dev, data, AO_Window_Data_611x);
891 spin_unlock_irqrestore(&devpriv->window_lock, flags);
892 }
893
894 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
895 {
896 struct ni_private *devpriv = dev->private;
897 unsigned long flags;
898 unsigned short data;
899
900 spin_lock_irqsave(&devpriv->window_lock, flags);
901 ni_writew(dev, addr, AO_Window_Address_611x);
902 data = ni_readw(dev, AO_Window_Data_611x);
903 spin_unlock_irqrestore(&devpriv->window_lock, flags);
904 return data;
905 }
906
907 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
908 * share registers (such as Interrupt_A_Register) without interfering with
909 * each other.
910 *
911 * NOTE: the switch/case statements are optimized out for a constant argument
912 * so this is actually quite fast--- If you must wrap another function around this
913 * make it inline to avoid a large speed penalty.
914 *
915 * value should only be 1 or 0.
916 */
917 static inline void ni_set_bits(struct comedi_device *dev, int reg,
918 unsigned bits, unsigned value)
919 {
920 unsigned bit_values;
921
922 if (value)
923 bit_values = bits;
924 else
925 bit_values = 0;
926 ni_set_bitfield(dev, reg, bits, bit_values);
927 }
928
929 #ifdef PCIDMA
930 static void ni_sync_ai_dma(struct comedi_device *dev)
931 {
932 struct ni_private *devpriv = dev->private;
933 struct comedi_subdevice *s = dev->read_subdev;
934 unsigned long flags;
935
936 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
937 if (devpriv->ai_mite_chan)
938 mite_sync_input_dma(devpriv->ai_mite_chan, s);
939 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
940 }
941
942 static int ni_ai_drain_dma(struct comedi_device *dev)
943 {
944 struct ni_private *devpriv = dev->private;
945 int i;
946 static const int timeout = 10000;
947 unsigned long flags;
948 int retval = 0;
949
950 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
951 if (devpriv->ai_mite_chan) {
952 for (i = 0; i < timeout; i++) {
953 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
954 NISTC_AI_STATUS1_FIFO_E)
955 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
956 0)
957 break;
958 udelay(5);
959 }
960 if (i == timeout) {
961 dev_err(dev->class_dev, "timed out\n");
962 dev_err(dev->class_dev,
963 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
964 mite_bytes_in_transit(devpriv->ai_mite_chan),
965 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
966 retval = -1;
967 }
968 }
969 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
970
971 ni_sync_ai_dma(dev);
972
973 return retval;
974 }
975
976 static void mite_handle_b_linkc(struct mite_struct *mite,
977 struct comedi_device *dev)
978 {
979 struct ni_private *devpriv = dev->private;
980 struct comedi_subdevice *s = dev->write_subdev;
981 unsigned long flags;
982
983 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
984 if (devpriv->ao_mite_chan)
985 mite_sync_output_dma(devpriv->ao_mite_chan, s);
986 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
987 }
988
989 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
990 {
991 static const int timeout = 10000;
992 int i;
993
994 for (i = 0; i < timeout; i++) {
995 unsigned short b_status;
996
997 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
998 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
999 break;
1000 /* if we poll too often, the pci bus activity seems
1001 to slow the dma transfer down */
1002 udelay(10);
1003 }
1004 if (i == timeout) {
1005 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1006 return -EPIPE;
1007 }
1008 return 0;
1009 }
1010 #endif /* PCIDMA */
1011
1012 #ifndef PCIDMA
1013
1014 static void ni_ao_fifo_load(struct comedi_device *dev,
1015 struct comedi_subdevice *s, int n)
1016 {
1017 struct ni_private *devpriv = dev->private;
1018 int i;
1019 unsigned short d;
1020 u32 packed_data;
1021
1022 for (i = 0; i < n; i++) {
1023 comedi_buf_read_samples(s, &d, 1);
1024
1025 if (devpriv->is_6xxx) {
1026 packed_data = d & 0xffff;
1027 /* 6711 only has 16 bit wide ao fifo */
1028 if (!devpriv->is_6711) {
1029 comedi_buf_read_samples(s, &d, 1);
1030 i++;
1031 packed_data |= (d << 16) & 0xffff0000;
1032 }
1033 ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1034 } else {
1035 ni_writew(dev, d, DAC_FIFO_Data);
1036 }
1037 }
1038 }
1039
1040 /*
1041 * There's a small problem if the FIFO gets really low and we
1042 * don't have the data to fill it. Basically, if after we fill
1043 * the FIFO with all the data available, the FIFO is _still_
1044 * less than half full, we never clear the interrupt. If the
1045 * IRQ is in edge mode, we never get another interrupt, because
1046 * this one wasn't cleared. If in level mode, we get flooded
1047 * with interrupts that we can't fulfill, because nothing ever
1048 * gets put into the buffer.
1049 *
1050 * This kind of situation is recoverable, but it is easier to
1051 * just pretend we had a FIFO underrun, since there is a good
1052 * chance it will happen anyway. This is _not_ the case for
1053 * RT code, as RT code might purposely be running close to the
1054 * metal. Needs to be fixed eventually.
1055 */
1056 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1057 struct comedi_subdevice *s)
1058 {
1059 const struct ni_board_struct *board = dev->board_ptr;
1060 unsigned int nbytes;
1061 unsigned int nsamples;
1062
1063 nbytes = comedi_buf_read_n_available(s);
1064 if (nbytes == 0) {
1065 s->async->events |= COMEDI_CB_OVERFLOW;
1066 return 0;
1067 }
1068
1069 nsamples = comedi_bytes_to_samples(s, nbytes);
1070 if (nsamples > board->ao_fifo_depth / 2)
1071 nsamples = board->ao_fifo_depth / 2;
1072
1073 ni_ao_fifo_load(dev, s, nsamples);
1074
1075 return 1;
1076 }
1077
1078 static int ni_ao_prep_fifo(struct comedi_device *dev,
1079 struct comedi_subdevice *s)
1080 {
1081 const struct ni_board_struct *board = dev->board_ptr;
1082 struct ni_private *devpriv = dev->private;
1083 unsigned int nbytes;
1084 unsigned int nsamples;
1085
1086 /* reset fifo */
1087 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1088 if (devpriv->is_6xxx)
1089 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1090
1091 /* load some data */
1092 nbytes = comedi_buf_read_n_available(s);
1093 if (nbytes == 0)
1094 return 0;
1095
1096 nsamples = comedi_bytes_to_samples(s, nbytes);
1097 if (nsamples > board->ao_fifo_depth)
1098 nsamples = board->ao_fifo_depth;
1099
1100 ni_ao_fifo_load(dev, s, nsamples);
1101
1102 return nsamples;
1103 }
1104
1105 static void ni_ai_fifo_read(struct comedi_device *dev,
1106 struct comedi_subdevice *s, int n)
1107 {
1108 struct ni_private *devpriv = dev->private;
1109 struct comedi_async *async = s->async;
1110 u32 dl;
1111 unsigned short data;
1112 int i;
1113
1114 if (devpriv->is_611x) {
1115 for (i = 0; i < n / 2; i++) {
1116 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1117 /* This may get the hi/lo data in the wrong order */
1118 data = (dl >> 16) & 0xffff;
1119 comedi_buf_write_samples(s, &data, 1);
1120 data = dl & 0xffff;
1121 comedi_buf_write_samples(s, &data, 1);
1122 }
1123 /* Check if there's a single sample stuck in the FIFO */
1124 if (n % 2) {
1125 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1126 data = dl & 0xffff;
1127 comedi_buf_write_samples(s, &data, 1);
1128 }
1129 } else if (devpriv->is_6143) {
1130 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1131 for (i = 0; i < n / 2; i++) {
1132 dl = ni_readl(dev, AIFIFO_Data_6143);
1133
1134 data = (dl >> 16) & 0xffff;
1135 comedi_buf_write_samples(s, &data, 1);
1136 data = dl & 0xffff;
1137 comedi_buf_write_samples(s, &data, 1);
1138 }
1139 if (n % 2) {
1140 /* Assume there is a single sample stuck in the FIFO */
1141 /* Get stranded sample into FIFO */
1142 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1143 dl = ni_readl(dev, AIFIFO_Data_6143);
1144 data = (dl >> 16) & 0xffff;
1145 comedi_buf_write_samples(s, &data, 1);
1146 }
1147 } else {
1148 if (n > sizeof(devpriv->ai_fifo_buffer) /
1149 sizeof(devpriv->ai_fifo_buffer[0])) {
1150 dev_err(dev->class_dev,
1151 "bug! ai_fifo_buffer too small\n");
1152 async->events |= COMEDI_CB_ERROR;
1153 return;
1154 }
1155 for (i = 0; i < n; i++) {
1156 devpriv->ai_fifo_buffer[i] =
1157 ni_readw(dev, ADC_FIFO_Data_Register);
1158 }
1159 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1160 }
1161 }
1162
1163 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1164 {
1165 const struct ni_board_struct *board = dev->board_ptr;
1166 struct comedi_subdevice *s = dev->read_subdev;
1167 int n;
1168
1169 n = board->ai_fifo_depth / 2;
1170
1171 ni_ai_fifo_read(dev, s, n);
1172 }
1173 #endif
1174
1175 /*
1176 Empties the AI fifo
1177 */
1178 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1179 {
1180 struct ni_private *devpriv = dev->private;
1181 struct comedi_subdevice *s = dev->read_subdev;
1182 u32 dl;
1183 unsigned short data;
1184 unsigned short fifo_empty;
1185 int i;
1186
1187 if (devpriv->is_611x) {
1188 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1189 NISTC_AI_STATUS1_FIFO_E) == 0) {
1190 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1191
1192 /* This may get the hi/lo data in the wrong order */
1193 data = dl >> 16;
1194 comedi_buf_write_samples(s, &data, 1);
1195 data = dl & 0xffff;
1196 comedi_buf_write_samples(s, &data, 1);
1197 }
1198 } else if (devpriv->is_6143) {
1199 i = 0;
1200 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1201 dl = ni_readl(dev, AIFIFO_Data_6143);
1202
1203 /* This may get the hi/lo data in the wrong order */
1204 data = dl >> 16;
1205 comedi_buf_write_samples(s, &data, 1);
1206 data = dl & 0xffff;
1207 comedi_buf_write_samples(s, &data, 1);
1208 i += 2;
1209 }
1210 /* Check if stranded sample is present */
1211 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1212 /* Get stranded sample into FIFO */
1213 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1214 dl = ni_readl(dev, AIFIFO_Data_6143);
1215 data = (dl >> 16) & 0xffff;
1216 comedi_buf_write_samples(s, &data, 1);
1217 }
1218
1219 } else {
1220 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1221 NISTC_AI_STATUS1_FIFO_E;
1222 while (fifo_empty == 0) {
1223 for (i = 0;
1224 i <
1225 sizeof(devpriv->ai_fifo_buffer) /
1226 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1227 fifo_empty = ni_stc_readw(dev,
1228 NISTC_AI_STATUS1_REG) &
1229 NISTC_AI_STATUS1_FIFO_E;
1230 if (fifo_empty)
1231 break;
1232 devpriv->ai_fifo_buffer[i] =
1233 ni_readw(dev, ADC_FIFO_Data_Register);
1234 }
1235 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1236 }
1237 }
1238 }
1239
1240 static void get_last_sample_611x(struct comedi_device *dev)
1241 {
1242 struct ni_private *devpriv = dev->private;
1243 struct comedi_subdevice *s = dev->read_subdev;
1244 unsigned short data;
1245 u32 dl;
1246
1247 if (!devpriv->is_611x)
1248 return;
1249
1250 /* Check if there's a single sample stuck in the FIFO */
1251 if (ni_readb(dev, XXX_Status) & 0x80) {
1252 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1253 data = dl & 0xffff;
1254 comedi_buf_write_samples(s, &data, 1);
1255 }
1256 }
1257
1258 static void get_last_sample_6143(struct comedi_device *dev)
1259 {
1260 struct ni_private *devpriv = dev->private;
1261 struct comedi_subdevice *s = dev->read_subdev;
1262 unsigned short data;
1263 u32 dl;
1264
1265 if (!devpriv->is_6143)
1266 return;
1267
1268 /* Check if there's a single sample stuck in the FIFO */
1269 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1270 /* Get stranded sample into FIFO */
1271 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1272 dl = ni_readl(dev, AIFIFO_Data_6143);
1273
1274 /* This may get the hi/lo data in the wrong order */
1275 data = (dl >> 16) & 0xffff;
1276 comedi_buf_write_samples(s, &data, 1);
1277 }
1278 }
1279
1280 static void shutdown_ai_command(struct comedi_device *dev)
1281 {
1282 struct comedi_subdevice *s = dev->read_subdev;
1283
1284 #ifdef PCIDMA
1285 ni_ai_drain_dma(dev);
1286 #endif
1287 ni_handle_fifo_dregs(dev);
1288 get_last_sample_611x(dev);
1289 get_last_sample_6143(dev);
1290
1291 s->async->events |= COMEDI_CB_EOA;
1292 }
1293
1294 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1295 {
1296 struct ni_private *devpriv = dev->private;
1297
1298 if (devpriv->aimode == AIMODE_SCAN) {
1299 #ifdef PCIDMA
1300 static const int timeout = 10;
1301 int i;
1302
1303 for (i = 0; i < timeout; i++) {
1304 ni_sync_ai_dma(dev);
1305 if ((s->async->events & COMEDI_CB_EOS))
1306 break;
1307 udelay(1);
1308 }
1309 #else
1310 ni_handle_fifo_dregs(dev);
1311 s->async->events |= COMEDI_CB_EOS;
1312 #endif
1313 }
1314 /* handle special case of single scan */
1315 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1316 shutdown_ai_command(dev);
1317 }
1318
1319 static void handle_gpct_interrupt(struct comedi_device *dev,
1320 unsigned short counter_index)
1321 {
1322 #ifdef PCIDMA
1323 struct ni_private *devpriv = dev->private;
1324 struct comedi_subdevice *s;
1325
1326 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1327
1328 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1329 s);
1330 comedi_handle_events(dev, s);
1331 #endif
1332 }
1333
1334 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1335 {
1336 unsigned short ack = 0;
1337
1338 if (a_status & NISTC_AI_STATUS1_SC_TC)
1339 ack |= NISTC_INTA_ACK_AI_SC_TC;
1340 if (a_status & NISTC_AI_STATUS1_START1)
1341 ack |= NISTC_INTA_ACK_AI_START1;
1342 if (a_status & NISTC_AI_STATUS1_START)
1343 ack |= NISTC_INTA_ACK_AI_START;
1344 if (a_status & NISTC_AI_STATUS1_STOP)
1345 ack |= NISTC_INTA_ACK_AI_STOP;
1346 if (ack)
1347 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1348 }
1349
1350 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1351 unsigned ai_mite_status)
1352 {
1353 struct comedi_subdevice *s = dev->read_subdev;
1354 struct comedi_cmd *cmd = &s->async->cmd;
1355
1356 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1357 if (s->type == COMEDI_SUBD_UNUSED)
1358 return;
1359
1360 #ifdef PCIDMA
1361 if (ai_mite_status & CHSR_LINKC)
1362 ni_sync_ai_dma(dev);
1363
1364 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1365 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1366 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1367 dev_err(dev->class_dev,
1368 "unknown mite interrupt (ai_mite_status=%08x)\n",
1369 ai_mite_status);
1370 s->async->events |= COMEDI_CB_ERROR;
1371 /* disable_irq(dev->irq); */
1372 }
1373 #endif
1374
1375 /* test for all uncommon interrupt events at the same time */
1376 if (status & (NISTC_AI_STATUS1_ERR |
1377 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1378 if (status == 0xffff) {
1379 dev_err(dev->class_dev, "Card removed?\n");
1380 /* we probably aren't even running a command now,
1381 * so it's a good idea to be careful. */
1382 if (comedi_is_subdevice_running(s)) {
1383 s->async->events |= COMEDI_CB_ERROR;
1384 comedi_handle_events(dev, s);
1385 }
1386 return;
1387 }
1388 if (status & NISTC_AI_STATUS1_ERR) {
1389 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1390 status);
1391
1392 shutdown_ai_command(dev);
1393
1394 s->async->events |= COMEDI_CB_ERROR;
1395 if (status & NISTC_AI_STATUS1_OVER)
1396 s->async->events |= COMEDI_CB_OVERFLOW;
1397
1398 comedi_handle_events(dev, s);
1399 return;
1400 }
1401 if (status & NISTC_AI_STATUS1_SC_TC) {
1402 if (cmd->stop_src == TRIG_COUNT)
1403 shutdown_ai_command(dev);
1404 }
1405 }
1406 #ifndef PCIDMA
1407 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1408 int i;
1409 static const int timeout = 10;
1410 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1411 *fail to get the fifo less than half full, so loop to be sure.*/
1412 for (i = 0; i < timeout; ++i) {
1413 ni_handle_fifo_half_full(dev);
1414 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1415 NISTC_AI_STATUS1_FIFO_HF) == 0)
1416 break;
1417 }
1418 }
1419 #endif /* !PCIDMA */
1420
1421 if (status & NISTC_AI_STATUS1_STOP)
1422 ni_handle_eos(dev, s);
1423
1424 comedi_handle_events(dev, s);
1425 }
1426
1427 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1428 {
1429 unsigned short ack = 0;
1430
1431 if (b_status & NISTC_AO_STATUS1_BC_TC)
1432 ack |= NISTC_INTB_ACK_AO_BC_TC;
1433 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1434 ack |= NISTC_INTB_ACK_AO_ERR;
1435 if (b_status & NISTC_AO_STATUS1_START)
1436 ack |= NISTC_INTB_ACK_AO_START;
1437 if (b_status & NISTC_AO_STATUS1_START1)
1438 ack |= NISTC_INTB_ACK_AO_START1;
1439 if (b_status & NISTC_AO_STATUS1_UC_TC)
1440 ack |= NISTC_INTB_ACK_AO_UC_TC;
1441 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1442 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1443 if (b_status & NISTC_AO_STATUS1_UPDATE)
1444 ack |= NISTC_INTB_ACK_AO_UPDATE;
1445 if (ack)
1446 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1447 }
1448
1449 static void handle_b_interrupt(struct comedi_device *dev,
1450 unsigned short b_status, unsigned ao_mite_status)
1451 {
1452 struct comedi_subdevice *s = dev->write_subdev;
1453 /* unsigned short ack=0; */
1454
1455 #ifdef PCIDMA
1456 /* Currently, mite.c requires us to handle LINKC */
1457 if (ao_mite_status & CHSR_LINKC) {
1458 struct ni_private *devpriv = dev->private;
1459
1460 mite_handle_b_linkc(devpriv->mite, dev);
1461 }
1462
1463 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1464 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1465 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1466 dev_err(dev->class_dev,
1467 "unknown mite interrupt (ao_mite_status=%08x)\n",
1468 ao_mite_status);
1469 s->async->events |= COMEDI_CB_ERROR;
1470 }
1471 #endif
1472
1473 if (b_status == 0xffff)
1474 return;
1475 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1476 dev_err(dev->class_dev,
1477 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1478 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1479 s->async->events |= COMEDI_CB_OVERFLOW;
1480 }
1481
1482 if (b_status & NISTC_AO_STATUS1_BC_TC)
1483 s->async->events |= COMEDI_CB_EOA;
1484
1485 #ifndef PCIDMA
1486 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1487 int ret;
1488
1489 ret = ni_ao_fifo_half_empty(dev, s);
1490 if (!ret) {
1491 dev_err(dev->class_dev, "AO buffer underrun\n");
1492 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1493 NISTC_INTB_ENA_AO_FIFO |
1494 NISTC_INTB_ENA_AO_ERR, 0);
1495 s->async->events |= COMEDI_CB_OVERFLOW;
1496 }
1497 }
1498 #endif
1499
1500 comedi_handle_events(dev, s);
1501 }
1502
1503 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1504 void *data, unsigned int num_bytes,
1505 unsigned int chan_index)
1506 {
1507 struct ni_private *devpriv = dev->private;
1508 struct comedi_async *async = s->async;
1509 struct comedi_cmd *cmd = &async->cmd;
1510 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1511 unsigned short *array = data;
1512 unsigned int *larray = data;
1513 unsigned int i;
1514
1515 for (i = 0; i < nsamples; i++) {
1516 #ifdef PCIDMA
1517 if (s->subdev_flags & SDF_LSAMPL)
1518 larray[i] = le32_to_cpu(larray[i]);
1519 else
1520 array[i] = le16_to_cpu(array[i]);
1521 #endif
1522 if (s->subdev_flags & SDF_LSAMPL)
1523 larray[i] += devpriv->ai_offset[chan_index];
1524 else
1525 array[i] += devpriv->ai_offset[chan_index];
1526 chan_index++;
1527 chan_index %= cmd->chanlist_len;
1528 }
1529 }
1530
1531 #ifdef PCIDMA
1532
1533 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1534 {
1535 struct ni_private *devpriv = dev->private;
1536 struct comedi_subdevice *s = dev->read_subdev;
1537 int retval;
1538 unsigned long flags;
1539
1540 retval = ni_request_ai_mite_channel(dev);
1541 if (retval)
1542 return retval;
1543
1544 /* write alloc the entire buffer */
1545 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1546
1547 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1548 if (!devpriv->ai_mite_chan) {
1549 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1550 return -EIO;
1551 }
1552
1553 if (devpriv->is_611x || devpriv->is_6143)
1554 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1555 else if (devpriv->is_628x)
1556 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1557 else
1558 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1559
1560 /*start the MITE */
1561 mite_dma_arm(devpriv->ai_mite_chan);
1562 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1563
1564 return 0;
1565 }
1566
1567 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1568 {
1569 struct ni_private *devpriv = dev->private;
1570 struct comedi_subdevice *s = dev->write_subdev;
1571 int retval;
1572 unsigned long flags;
1573
1574 retval = ni_request_ao_mite_channel(dev);
1575 if (retval)
1576 return retval;
1577
1578 /* read alloc the entire buffer */
1579 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1580
1581 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1582 if (devpriv->ao_mite_chan) {
1583 if (devpriv->is_611x || devpriv->is_6713) {
1584 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1585 } else {
1586 /* doing 32 instead of 16 bit wide transfers from memory
1587 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1588 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1589 }
1590 mite_dma_arm(devpriv->ao_mite_chan);
1591 } else {
1592 retval = -EIO;
1593 }
1594 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1595
1596 return retval;
1597 }
1598
1599 #endif /* PCIDMA */
1600
1601 /*
1602 used for both cancel ioctl and board initialization
1603
1604 this is pretty harsh for a cancel, but it works...
1605 */
1606
1607 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1608 {
1609 struct ni_private *devpriv = dev->private;
1610 unsigned ai_personal;
1611 unsigned ai_out_ctrl;
1612
1613 ni_release_ai_mite_channel(dev);
1614 /* ai configuration */
1615 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1616 NISTC_RESET_REG);
1617
1618 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1619
1620 ni_clear_ai_fifo(dev);
1621
1622 if (!devpriv->is_6143)
1623 ni_writeb(dev, 0, Misc_Command);
1624
1625 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1626 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1627 NISTC_AI_MODE1_RSVD
1628 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1629 NISTC_AI_MODE1_REG);
1630 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1631 /* generate FIFO interrupts on non-empty */
1632 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1633 NISTC_AI_MODE3_REG);
1634
1635 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1636 NISTC_AI_PERSONAL_SOC_POLARITY |
1637 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1638 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1639 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1640 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1641 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1642 if (devpriv->is_611x) {
1643 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1644 } else if (devpriv->is_6143) {
1645 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1646 } else {
1647 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1648 if (devpriv->is_622x)
1649 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1650 else
1651 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1652 }
1653 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1654 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1655
1656 /* the following registers should not be changed, because there
1657 * are no backup registers in devpriv. If you want to change
1658 * any of these, add a backup register and other appropriate code:
1659 * NISTC_AI_MODE1_REG
1660 * NISTC_AI_MODE3_REG
1661 * NISTC_AI_PERSONAL_REG
1662 * NISTC_AI_OUT_CTRL_REG
1663 */
1664
1665 /* clear interrupts */
1666 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1667
1668 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1669
1670 return 0;
1671 }
1672
1673 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1674 {
1675 unsigned long flags;
1676 int count;
1677
1678 /* lock to avoid race with interrupt handler */
1679 spin_lock_irqsave(&dev->spinlock, flags);
1680 #ifndef PCIDMA
1681 ni_handle_fifo_dregs(dev);
1682 #else
1683 ni_sync_ai_dma(dev);
1684 #endif
1685 count = comedi_buf_n_bytes_ready(s);
1686 spin_unlock_irqrestore(&dev->spinlock, flags);
1687
1688 return count;
1689 }
1690
1691 static void ni_prime_channelgain_list(struct comedi_device *dev)
1692 {
1693 int i;
1694
1695 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1696 for (i = 0; i < NI_TIMEOUT; ++i) {
1697 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1698 NISTC_AI_STATUS1_FIFO_E)) {
1699 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1700 return;
1701 }
1702 udelay(1);
1703 }
1704 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1705 }
1706
1707 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1708 unsigned int n_chan,
1709 unsigned int *list)
1710 {
1711 const struct ni_board_struct *board = dev->board_ptr;
1712 struct ni_private *devpriv = dev->private;
1713 unsigned int chan, range, aref;
1714 unsigned int i;
1715 unsigned int dither;
1716 unsigned range_code;
1717
1718 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1719
1720 if ((list[0] & CR_ALT_SOURCE)) {
1721 unsigned bypass_bits;
1722
1723 chan = CR_CHAN(list[0]);
1724 range = CR_RANGE(list[0]);
1725 range_code = ni_gainlkup[board->gainlkup][range];
1726 dither = (list[0] & CR_ALT_FILTER) != 0;
1727 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1728 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1729 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1730 devpriv->ai_calib_source;
1731 if (dither)
1732 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1733 /* don't use 2's complement encoding */
1734 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1735 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1736 } else {
1737 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1738 }
1739 for (i = 0; i < n_chan; i++) {
1740 unsigned config_bits = 0;
1741
1742 chan = CR_CHAN(list[i]);
1743 aref = CR_AREF(list[i]);
1744 range = CR_RANGE(list[i]);
1745 dither = (list[i] & CR_ALT_FILTER) != 0;
1746
1747 range_code = ni_gainlkup[board->gainlkup][range];
1748 devpriv->ai_offset[i] = 0;
1749 switch (aref) {
1750 case AREF_DIFF:
1751 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1752 break;
1753 case AREF_COMMON:
1754 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1755 break;
1756 case AREF_GROUND:
1757 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1758 break;
1759 case AREF_OTHER:
1760 break;
1761 }
1762 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1763 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1764 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1765 if (i == n_chan - 1)
1766 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1767 if (dither)
1768 config_bits |= NI_M_AI_CFG_DITHER;
1769 /* don't use 2's complement encoding */
1770 config_bits |= NI_M_AI_CFG_POLARITY;
1771 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1772 }
1773 ni_prime_channelgain_list(dev);
1774 }
1775
1776 /*
1777 * Notes on the 6110 and 6111:
1778 * These boards a slightly different than the rest of the series, since
1779 * they have multiple A/D converters.
1780 * From the driver side, the configuration memory is a
1781 * little different.
1782 * Configuration Memory Low:
1783 * bits 15-9: same
1784 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1785 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1786 * 1001 gain=0.1 (+/- 50)
1787 * 1010 0.2
1788 * 1011 0.1
1789 * 0001 1
1790 * 0010 2
1791 * 0011 5
1792 * 0100 10
1793 * 0101 20
1794 * 0110 50
1795 * Configuration Memory High:
1796 * bits 12-14: Channel Type
1797 * 001 for differential
1798 * 000 for calibration
1799 * bit 11: coupling (this is not currently handled)
1800 * 1 AC coupling
1801 * 0 DC coupling
1802 * bits 0-2: channel
1803 * valid channels are 0-3
1804 */
1805 static void ni_load_channelgain_list(struct comedi_device *dev,
1806 struct comedi_subdevice *s,
1807 unsigned int n_chan, unsigned int *list)
1808 {
1809 const struct ni_board_struct *board = dev->board_ptr;
1810 struct ni_private *devpriv = dev->private;
1811 unsigned int offset = (s->maxdata + 1) >> 1;
1812 unsigned int chan, range, aref;
1813 unsigned int i;
1814 unsigned int hi, lo;
1815 unsigned int dither;
1816
1817 if (devpriv->is_m_series) {
1818 ni_m_series_load_channelgain_list(dev, n_chan, list);
1819 return;
1820 }
1821 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1822 if (devpriv->changain_state
1823 && devpriv->changain_spec == list[0]) {
1824 /* ready to go. */
1825 return;
1826 }
1827 devpriv->changain_state = 1;
1828 devpriv->changain_spec = list[0];
1829 } else {
1830 devpriv->changain_state = 0;
1831 }
1832
1833 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1834
1835 /* Set up Calibration mode if required */
1836 if (devpriv->is_6143) {
1837 if ((list[0] & CR_ALT_SOURCE)
1838 && !devpriv->ai_calib_source_enabled) {
1839 /* Strobe Relay enable bit */
1840 ni_writew(dev, devpriv->ai_calib_source |
1841 Calibration_Channel_6143_RelayOn,
1842 Calibration_Channel_6143);
1843 ni_writew(dev, devpriv->ai_calib_source,
1844 Calibration_Channel_6143);
1845 devpriv->ai_calib_source_enabled = 1;
1846 msleep_interruptible(100); /* Allow relays to change */
1847 } else if (!(list[0] & CR_ALT_SOURCE)
1848 && devpriv->ai_calib_source_enabled) {
1849 /* Strobe Relay disable bit */
1850 ni_writew(dev, devpriv->ai_calib_source |
1851 Calibration_Channel_6143_RelayOff,
1852 Calibration_Channel_6143);
1853 ni_writew(dev, devpriv->ai_calib_source,
1854 Calibration_Channel_6143);
1855 devpriv->ai_calib_source_enabled = 0;
1856 msleep_interruptible(100); /* Allow relays to change */
1857 }
1858 }
1859
1860 for (i = 0; i < n_chan; i++) {
1861 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1862 chan = devpriv->ai_calib_source;
1863 else
1864 chan = CR_CHAN(list[i]);
1865 aref = CR_AREF(list[i]);
1866 range = CR_RANGE(list[i]);
1867 dither = (list[i] & CR_ALT_FILTER) != 0;
1868
1869 /* fix the external/internal range differences */
1870 range = ni_gainlkup[board->gainlkup][range];
1871 if (devpriv->is_611x)
1872 devpriv->ai_offset[i] = offset;
1873 else
1874 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1875
1876 hi = 0;
1877 if ((list[i] & CR_ALT_SOURCE)) {
1878 if (devpriv->is_611x)
1879 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1880 Calibration_Channel_Select_611x);
1881 } else {
1882 if (devpriv->is_611x)
1883 aref = AREF_DIFF;
1884 else if (devpriv->is_6143)
1885 aref = AREF_OTHER;
1886 switch (aref) {
1887 case AREF_DIFF:
1888 hi |= AI_DIFFERENTIAL;
1889 break;
1890 case AREF_COMMON:
1891 hi |= AI_COMMON;
1892 break;
1893 case AREF_GROUND:
1894 hi |= AI_GROUND;
1895 break;
1896 case AREF_OTHER:
1897 break;
1898 }
1899 }
1900 hi |= AI_CONFIG_CHANNEL(chan);
1901
1902 ni_writew(dev, hi, Configuration_Memory_High);
1903
1904 if (!devpriv->is_6143) {
1905 lo = range;
1906 if (i == n_chan - 1)
1907 lo |= AI_LAST_CHANNEL;
1908 if (dither)
1909 lo |= AI_DITHER;
1910
1911 ni_writew(dev, lo, Configuration_Memory_Low);
1912 }
1913 }
1914
1915 /* prime the channel/gain list */
1916 if (!devpriv->is_611x && !devpriv->is_6143)
1917 ni_prime_channelgain_list(dev);
1918 }
1919
1920 static int ni_ai_insn_read(struct comedi_device *dev,
1921 struct comedi_subdevice *s,
1922 struct comedi_insn *insn,
1923 unsigned int *data)
1924 {
1925 struct ni_private *devpriv = dev->private;
1926 unsigned int mask = (s->maxdata + 1) >> 1;
1927 int i, n;
1928 unsigned signbits;
1929 unsigned int d;
1930 unsigned long dl;
1931
1932 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1933
1934 ni_clear_ai_fifo(dev);
1935
1936 signbits = devpriv->ai_offset[0];
1937 if (devpriv->is_611x) {
1938 for (n = 0; n < num_adc_stages_611x; n++) {
1939 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1940 NISTC_AI_CMD1_REG);
1941 udelay(1);
1942 }
1943 for (n = 0; n < insn->n; n++) {
1944 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1945 NISTC_AI_CMD1_REG);
1946 /* The 611x has screwy 32-bit FIFOs. */
1947 d = 0;
1948 for (i = 0; i < NI_TIMEOUT; i++) {
1949 if (ni_readb(dev, XXX_Status) & 0x80) {
1950 d = ni_readl(dev, ADC_FIFO_Data_611x);
1951 d >>= 16;
1952 d &= 0xffff;
1953 break;
1954 }
1955 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1956 NISTC_AI_STATUS1_FIFO_E)) {
1957 d = ni_readl(dev, ADC_FIFO_Data_611x);
1958 d &= 0xffff;
1959 break;
1960 }
1961 }
1962 if (i == NI_TIMEOUT) {
1963 dev_err(dev->class_dev, "timeout\n");
1964 return -ETIME;
1965 }
1966 d += signbits;
1967 data[n] = d;
1968 }
1969 } else if (devpriv->is_6143) {
1970 for (n = 0; n < insn->n; n++) {
1971 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1972 NISTC_AI_CMD1_REG);
1973
1974 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1975 dl = 0;
1976 for (i = 0; i < NI_TIMEOUT; i++) {
1977 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1978 /* Get stranded sample into FIFO */
1979 ni_writel(dev, 0x01,
1980 AIFIFO_Control_6143);
1981 dl = ni_readl(dev, AIFIFO_Data_6143);
1982 break;
1983 }
1984 }
1985 if (i == NI_TIMEOUT) {
1986 dev_err(dev->class_dev, "timeout\n");
1987 return -ETIME;
1988 }
1989 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1990 }
1991 } else {
1992 for (n = 0; n < insn->n; n++) {
1993 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1994 NISTC_AI_CMD1_REG);
1995 for (i = 0; i < NI_TIMEOUT; i++) {
1996 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1997 NISTC_AI_STATUS1_FIFO_E))
1998 break;
1999 }
2000 if (i == NI_TIMEOUT) {
2001 dev_err(dev->class_dev, "timeout\n");
2002 return -ETIME;
2003 }
2004 if (devpriv->is_m_series) {
2005 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2006 dl &= mask;
2007 data[n] = dl;
2008 } else {
2009 d = ni_readw(dev, ADC_FIFO_Data_Register);
2010 d += signbits; /* subtle: needs to be short addition */
2011 data[n] = d;
2012 }
2013 }
2014 }
2015 return insn->n;
2016 }
2017
2018 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2019 unsigned int flags)
2020 {
2021 struct ni_private *devpriv = dev->private;
2022 int divider;
2023
2024 switch (flags & CMDF_ROUND_MASK) {
2025 case CMDF_ROUND_NEAREST:
2026 default:
2027 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2028 break;
2029 case CMDF_ROUND_DOWN:
2030 divider = (nanosec) / devpriv->clock_ns;
2031 break;
2032 case CMDF_ROUND_UP:
2033 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2034 break;
2035 }
2036 return divider - 1;
2037 }
2038
2039 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2040 {
2041 struct ni_private *devpriv = dev->private;
2042
2043 return devpriv->clock_ns * (timer + 1);
2044 }
2045
2046 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2047 unsigned num_channels)
2048 {
2049 const struct ni_board_struct *board = dev->board_ptr;
2050 struct ni_private *devpriv = dev->private;
2051
2052 /* simultaneously-sampled inputs */
2053 if (devpriv->is_611x || devpriv->is_6143)
2054 return board->ai_speed;
2055
2056 /* multiplexed inputs */
2057 return board->ai_speed * num_channels;
2058 }
2059
2060 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2061 struct comedi_cmd *cmd)
2062 {
2063 const struct ni_board_struct *board = dev->board_ptr;
2064 struct ni_private *devpriv = dev->private;
2065 int err = 0;
2066 unsigned int tmp;
2067 unsigned int sources;
2068
2069 /* Step 1 : check if triggers are trivially valid */
2070
2071 err |= comedi_check_trigger_src(&cmd->start_src,
2072 TRIG_NOW | TRIG_INT | TRIG_EXT);
2073 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2074 TRIG_TIMER | TRIG_EXT);
2075
2076 sources = TRIG_TIMER | TRIG_EXT;
2077 if (devpriv->is_611x || devpriv->is_6143)
2078 sources |= TRIG_NOW;
2079 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2080
2081 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2082 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2083
2084 if (err)
2085 return 1;
2086
2087 /* Step 2a : make sure trigger sources are unique */
2088
2089 err |= comedi_check_trigger_is_unique(cmd->start_src);
2090 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2091 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2092 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2093
2094 /* Step 2b : and mutually compatible */
2095
2096 if (err)
2097 return 2;
2098
2099 /* Step 3: check if arguments are trivially valid */
2100
2101 switch (cmd->start_src) {
2102 case TRIG_NOW:
2103 case TRIG_INT:
2104 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2105 break;
2106 case TRIG_EXT:
2107 tmp = CR_CHAN(cmd->start_arg);
2108
2109 if (tmp > 16)
2110 tmp = 16;
2111 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2112 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2113 break;
2114 }
2115
2116 if (cmd->scan_begin_src == TRIG_TIMER) {
2117 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2118 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2119 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2120 devpriv->clock_ns *
2121 0xffffff);
2122 } else if (cmd->scan_begin_src == TRIG_EXT) {
2123 /* external trigger */
2124 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2125
2126 if (tmp > 16)
2127 tmp = 16;
2128 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2129 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2130 } else { /* TRIG_OTHER */
2131 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2132 }
2133
2134 if (cmd->convert_src == TRIG_TIMER) {
2135 if (devpriv->is_611x || devpriv->is_6143) {
2136 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2137 0);
2138 } else {
2139 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2140 board->ai_speed);
2141 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2142 devpriv->clock_ns *
2143 0xffff);
2144 }
2145 } else if (cmd->convert_src == TRIG_EXT) {
2146 /* external trigger */
2147 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2148
2149 if (tmp > 16)
2150 tmp = 16;
2151 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2152 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2153 } else if (cmd->convert_src == TRIG_NOW) {
2154 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2155 }
2156
2157 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2158 cmd->chanlist_len);
2159
2160 if (cmd->stop_src == TRIG_COUNT) {
2161 unsigned int max_count = 0x01000000;
2162
2163 if (devpriv->is_611x)
2164 max_count -= num_adc_stages_611x;
2165 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2166 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2167 } else {
2168 /* TRIG_NONE */
2169 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2170 }
2171
2172 if (err)
2173 return 3;
2174
2175 /* step 4: fix up any arguments */
2176
2177 if (cmd->scan_begin_src == TRIG_TIMER) {
2178 tmp = cmd->scan_begin_arg;
2179 cmd->scan_begin_arg =
2180 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2181 cmd->scan_begin_arg,
2182 cmd->flags));
2183 if (tmp != cmd->scan_begin_arg)
2184 err++;
2185 }
2186 if (cmd->convert_src == TRIG_TIMER) {
2187 if (!devpriv->is_611x && !devpriv->is_6143) {
2188 tmp = cmd->convert_arg;
2189 cmd->convert_arg =
2190 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2191 cmd->convert_arg,
2192 cmd->flags));
2193 if (tmp != cmd->convert_arg)
2194 err++;
2195 if (cmd->scan_begin_src == TRIG_TIMER &&
2196 cmd->scan_begin_arg <
2197 cmd->convert_arg * cmd->scan_end_arg) {
2198 cmd->scan_begin_arg =
2199 cmd->convert_arg * cmd->scan_end_arg;
2200 err++;
2201 }
2202 }
2203 }
2204
2205 if (err)
2206 return 4;
2207
2208 return 0;
2209 }
2210
2211 static int ni_ai_inttrig(struct comedi_device *dev,
2212 struct comedi_subdevice *s,
2213 unsigned int trig_num)
2214 {
2215 struct ni_private *devpriv = dev->private;
2216 struct comedi_cmd *cmd = &s->async->cmd;
2217
2218 if (trig_num != cmd->start_arg)
2219 return -EINVAL;
2220
2221 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2222 NISTC_AI_CMD2_REG);
2223 s->async->inttrig = NULL;
2224
2225 return 1;
2226 }
2227
2228 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2229 {
2230 struct ni_private *devpriv = dev->private;
2231 const struct comedi_cmd *cmd = &s->async->cmd;
2232 int timer;
2233 int mode1 = 0; /* mode1 is needed for both stop and convert */
2234 int mode2 = 0;
2235 int start_stop_select = 0;
2236 unsigned int stop_count;
2237 int interrupt_a_enable = 0;
2238 unsigned ai_trig;
2239
2240 if (dev->irq == 0) {
2241 dev_err(dev->class_dev, "cannot run command without an irq\n");
2242 return -EIO;
2243 }
2244 ni_clear_ai_fifo(dev);
2245
2246 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2247
2248 /* start configuration */
2249 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2250
2251 /* disable analog triggering for now, since it
2252 * interferes with the use of pfi0 */
2253 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2254 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2255
2256 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2257 switch (cmd->start_src) {
2258 case TRIG_INT:
2259 case TRIG_NOW:
2260 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2261 NISTC_AI_TRIG_START1_SEL(0),
2262 NISTC_AI_TRIG_SEL_REG;
2263 break;
2264 case TRIG_EXT:
2265 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2266 1);
2267
2268 if (cmd->start_arg & CR_INVERT)
2269 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2270 if (cmd->start_arg & CR_EDGE)
2271 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2272 break;
2273 }
2274 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2275
2276 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2277 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2278 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2279 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2280
2281 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2282 /* logic low */
2283 start_stop_select |= NISTC_AI_STOP_POLARITY |
2284 NISTC_AI_STOP_SEL(31) |
2285 NISTC_AI_STOP_SYNC;
2286 } else {
2287 /* ai configuration memory */
2288 start_stop_select |= NISTC_AI_STOP_SEL(19);
2289 }
2290 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2291
2292 devpriv->ai_cmd2 = 0;
2293 switch (cmd->stop_src) {
2294 case TRIG_COUNT:
2295 stop_count = cmd->stop_arg - 1;
2296
2297 if (devpriv->is_611x) {
2298 /* have to take 3 stage adc pipeline into account */
2299 stop_count += num_adc_stages_611x;
2300 }
2301 /* stage number of scans */
2302 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2303
2304 mode1 |= NISTC_AI_MODE1_START_STOP |
2305 NISTC_AI_MODE1_RSVD |
2306 NISTC_AI_MODE1_TRIGGER_ONCE;
2307 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2308 /* load SC (Scan Count) */
2309 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2310
2311 if (stop_count == 0) {
2312 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2313 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2314 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2315 if (cmd->chanlist_len > 1)
2316 start_stop_select |= NISTC_AI_STOP_POLARITY |
2317 NISTC_AI_STOP_EDGE;
2318 }
2319 break;
2320 case TRIG_NONE:
2321 /* stage number of scans */
2322 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2323
2324 mode1 |= NISTC_AI_MODE1_START_STOP |
2325 NISTC_AI_MODE1_RSVD |
2326 NISTC_AI_MODE1_CONTINUOUS;
2327 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2328
2329 /* load SC (Scan Count) */
2330 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2331 break;
2332 }
2333
2334 switch (cmd->scan_begin_src) {
2335 case TRIG_TIMER:
2336 /*
2337 * stop bits for non 611x boards
2338 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2339 * NISTC_AI_MODE2_PRE_TRIGGER=0
2340 * NISTC_AI_START_STOP_REG:
2341 * NISTC_AI_START_POLARITY=0 (?) rising edge
2342 * NISTC_AI_START_EDGE=1 edge triggered
2343 * NISTC_AI_START_SYNC=1 (?)
2344 * NISTC_AI_START_SEL=0 SI_TC
2345 * NISTC_AI_STOP_POLARITY=0 rising edge
2346 * NISTC_AI_STOP_EDGE=0 level
2347 * NISTC_AI_STOP_SYNC=1
2348 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2349 */
2350 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2351 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2352
2353 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2354 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2355 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2356 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2357
2358 /* load SI */
2359 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2360 CMDF_ROUND_NEAREST);
2361 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2362 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2363 break;
2364 case TRIG_EXT:
2365 if (cmd->scan_begin_arg & CR_EDGE)
2366 start_stop_select |= NISTC_AI_START_EDGE;
2367 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2368 start_stop_select |= NISTC_AI_START_POLARITY;
2369 if (cmd->scan_begin_src != cmd->convert_src ||
2370 (cmd->scan_begin_arg & ~CR_EDGE) !=
2371 (cmd->convert_arg & ~CR_EDGE))
2372 start_stop_select |= NISTC_AI_START_SYNC;
2373 start_stop_select |=
2374 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2375 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2376 break;
2377 }
2378
2379 switch (cmd->convert_src) {
2380 case TRIG_TIMER:
2381 case TRIG_NOW:
2382 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2383 timer = 1;
2384 else
2385 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2386 CMDF_ROUND_NEAREST);
2387 /* 0,0 does not work */
2388 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2389 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2390
2391 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2392 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2393 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2394
2395 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2396
2397 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2398 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2399 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2400 break;
2401 case TRIG_EXT:
2402 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2403 if ((cmd->convert_arg & CR_INVERT) == 0)
2404 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2405 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2406
2407 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2408 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2409 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2410
2411 break;
2412 }
2413
2414 if (dev->irq) {
2415 /* interrupt on FIFO, errors, SC_TC */
2416 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2417 NISTC_INTA_ENA_AI_SC_TC;
2418
2419 #ifndef PCIDMA
2420 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2421 #endif
2422
2423 if ((cmd->flags & CMDF_WAKE_EOS) ||
2424 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2425 /* wake on end-of-scan */
2426 devpriv->aimode = AIMODE_SCAN;
2427 } else {
2428 devpriv->aimode = AIMODE_HALF_FULL;
2429 }
2430
2431 switch (devpriv->aimode) {
2432 case AIMODE_HALF_FULL:
2433 /*generate FIFO interrupts and DMA requests on half-full */
2434 #ifdef PCIDMA
2435 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2436 NISTC_AI_MODE3_REG);
2437 #else
2438 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2439 NISTC_AI_MODE3_REG);
2440 #endif
2441 break;
2442 case AIMODE_SAMPLE:
2443 /*generate FIFO interrupts on non-empty */
2444 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2445 NISTC_AI_MODE3_REG);
2446 break;
2447 case AIMODE_SCAN:
2448 #ifdef PCIDMA
2449 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2450 NISTC_AI_MODE3_REG);
2451 #else
2452 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2453 NISTC_AI_MODE3_REG);
2454 #endif
2455 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2456 break;
2457 default:
2458 break;
2459 }
2460
2461 /* clear interrupts */
2462 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2463
2464 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2465 } else {
2466 /* interrupt on nothing */
2467 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2468
2469 /* XXX start polling if necessary */
2470 }
2471
2472 /* end configuration */
2473 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2474
2475 switch (cmd->scan_begin_src) {
2476 case TRIG_TIMER:
2477 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2478 NISTC_AI_CMD1_SI_ARM |
2479 NISTC_AI_CMD1_DIV_ARM |
2480 NISTC_AI_CMD1_SC_ARM,
2481 NISTC_AI_CMD1_REG);
2482 break;
2483 case TRIG_EXT:
2484 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2485 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2486 NISTC_AI_CMD1_DIV_ARM |
2487 NISTC_AI_CMD1_SC_ARM,
2488 NISTC_AI_CMD1_REG);
2489 break;
2490 }
2491
2492 #ifdef PCIDMA
2493 {
2494 int retval = ni_ai_setup_MITE_dma(dev);
2495
2496 if (retval)
2497 return retval;
2498 }
2499 #endif
2500
2501 if (cmd->start_src == TRIG_NOW) {
2502 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2503 devpriv->ai_cmd2,
2504 NISTC_AI_CMD2_REG);
2505 s->async->inttrig = NULL;
2506 } else if (cmd->start_src == TRIG_EXT) {
2507 s->async->inttrig = NULL;
2508 } else { /* TRIG_INT */
2509 s->async->inttrig = ni_ai_inttrig;
2510 }
2511
2512 return 0;
2513 }
2514
2515 static int ni_ai_insn_config(struct comedi_device *dev,
2516 struct comedi_subdevice *s,
2517 struct comedi_insn *insn, unsigned int *data)
2518 {
2519 struct ni_private *devpriv = dev->private;
2520
2521 if (insn->n < 1)
2522 return -EINVAL;
2523
2524 switch (data[0]) {
2525 case INSN_CONFIG_ALT_SOURCE:
2526 if (devpriv->is_m_series) {
2527 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2528 return -EINVAL;
2529 devpriv->ai_calib_source = data[1];
2530 } else if (devpriv->is_6143) {
2531 unsigned int calib_source;
2532
2533 calib_source = data[1] & 0xf;
2534
2535 devpriv->ai_calib_source = calib_source;
2536 ni_writew(dev, calib_source, Calibration_Channel_6143);
2537 } else {
2538 unsigned int calib_source;
2539 unsigned int calib_source_adjust;
2540
2541 calib_source = data[1] & 0xf;
2542 calib_source_adjust = (data[1] >> 4) & 0xff;
2543
2544 if (calib_source >= 8)
2545 return -EINVAL;
2546 devpriv->ai_calib_source = calib_source;
2547 if (devpriv->is_611x) {
2548 ni_writeb(dev, calib_source_adjust,
2549 Cal_Gain_Select_611x);
2550 }
2551 }
2552 return 2;
2553 default:
2554 break;
2555 }
2556
2557 return -EINVAL;
2558 }
2559
2560 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2561 void *data, unsigned int num_bytes,
2562 unsigned int chan_index)
2563 {
2564 struct comedi_cmd *cmd = &s->async->cmd;
2565 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2566 unsigned short *array = data;
2567 unsigned int i;
2568
2569 for (i = 0; i < nsamples; i++) {
2570 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2571 unsigned short val = array[i];
2572
2573 /*
2574 * Munge data from unsigned to two's complement for
2575 * bipolar ranges.
2576 */
2577 if (comedi_range_is_bipolar(s, range))
2578 val = comedi_offset_munge(s, val);
2579 #ifdef PCIDMA
2580 val = cpu_to_le16(val);
2581 #endif
2582 array[i] = val;
2583
2584 chan_index++;
2585 chan_index %= cmd->chanlist_len;
2586 }
2587 }
2588
2589 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2590 struct comedi_subdevice *s,
2591 unsigned int chanspec[],
2592 unsigned int n_chans, int timed)
2593 {
2594 struct ni_private *devpriv = dev->private;
2595 unsigned int range;
2596 unsigned int chan;
2597 unsigned int conf;
2598 int i;
2599 int invert = 0;
2600
2601 if (timed) {
2602 for (i = 0; i < s->n_chan; ++i) {
2603 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2604 ni_writeb(dev, devpriv->ao_conf[i],
2605 NI_M_AO_CFG_BANK_REG(i));
2606 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2607 }
2608 }
2609 for (i = 0; i < n_chans; i++) {
2610 const struct comedi_krange *krange;
2611
2612 chan = CR_CHAN(chanspec[i]);
2613 range = CR_RANGE(chanspec[i]);
2614 krange = s->range_table->range + range;
2615 invert = 0;
2616 conf = 0;
2617 switch (krange->max - krange->min) {
2618 case 20000000:
2619 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2620 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2621 break;
2622 case 10000000:
2623 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2624 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2625 break;
2626 case 4000000:
2627 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2628 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2629 NI_M_AO_REF_ATTENUATION_REG(chan));
2630 break;
2631 case 2000000:
2632 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2633 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2634 NI_M_AO_REF_ATTENUATION_REG(chan));
2635 break;
2636 default:
2637 dev_err(dev->class_dev,
2638 "bug! unhandled ao reference voltage\n");
2639 break;
2640 }
2641 switch (krange->max + krange->min) {
2642 case 0:
2643 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2644 break;
2645 case 10000000:
2646 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2647 break;
2648 default:
2649 dev_err(dev->class_dev,
2650 "bug! unhandled ao offset voltage\n");
2651 break;
2652 }
2653 if (timed)
2654 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2655 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2656 devpriv->ao_conf[chan] = conf;
2657 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2658 }
2659 return invert;
2660 }
2661
2662 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2663 struct comedi_subdevice *s,
2664 unsigned int chanspec[],
2665 unsigned int n_chans)
2666 {
2667 struct ni_private *devpriv = dev->private;
2668 unsigned int range;
2669 unsigned int chan;
2670 unsigned int conf;
2671 int i;
2672 int invert = 0;
2673
2674 for (i = 0; i < n_chans; i++) {
2675 chan = CR_CHAN(chanspec[i]);
2676 range = CR_RANGE(chanspec[i]);
2677 conf = AO_Channel(chan);
2678
2679 if (comedi_range_is_bipolar(s, range)) {
2680 conf |= AO_Bipolar;
2681 invert = (s->maxdata + 1) >> 1;
2682 } else {
2683 invert = 0;
2684 }
2685 if (comedi_range_is_external(s, range))
2686 conf |= AO_Ext_Ref;
2687
2688 /* not all boards can deglitch, but this shouldn't hurt */
2689 if (chanspec[i] & CR_DEGLITCH)
2690 conf |= AO_Deglitch;
2691
2692 /* analog reference */
2693 /* AREF_OTHER connects AO ground to AI ground, i think */
2694 conf |= (CR_AREF(chanspec[i]) ==
2695 AREF_OTHER) ? AO_Ground_Ref : 0;
2696
2697 ni_writew(dev, conf, AO_Configuration);
2698 devpriv->ao_conf[chan] = conf;
2699 }
2700 return invert;
2701 }
2702
2703 static int ni_ao_config_chanlist(struct comedi_device *dev,
2704 struct comedi_subdevice *s,
2705 unsigned int chanspec[], unsigned int n_chans,
2706 int timed)
2707 {
2708 struct ni_private *devpriv = dev->private;
2709
2710 if (devpriv->is_m_series)
2711 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2712 timed);
2713 else
2714 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2715 }
2716
2717 static int ni_ao_insn_write(struct comedi_device *dev,
2718 struct comedi_subdevice *s,
2719 struct comedi_insn *insn,
2720 unsigned int *data)
2721 {
2722 struct ni_private *devpriv = dev->private;
2723 unsigned int chan = CR_CHAN(insn->chanspec);
2724 unsigned int range = CR_RANGE(insn->chanspec);
2725 int reg;
2726 int i;
2727
2728 if (devpriv->is_6xxx) {
2729 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2730
2731 reg = DACx_Direct_Data_671x(chan);
2732 } else if (devpriv->is_m_series) {
2733 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2734 } else {
2735 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2736 }
2737
2738 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2739
2740 for (i = 0; i < insn->n; i++) {
2741 unsigned int val = data[i];
2742
2743 s->readback[chan] = val;
2744
2745 if (devpriv->is_6xxx) {
2746 /*
2747 * 6xxx boards have bipolar outputs, munge the
2748 * unsigned comedi values to 2's complement
2749 */
2750 val = comedi_offset_munge(s, val);
2751
2752 ni_ao_win_outw(dev, val, reg);
2753 } else if (devpriv->is_m_series) {
2754 /*
2755 * M-series boards use offset binary values for
2756 * bipolar and uinpolar outputs
2757 */
2758 ni_writew(dev, val, reg);
2759 } else {
2760 /*
2761 * Non-M series boards need two's complement values
2762 * for bipolar ranges.
2763 */
2764 if (comedi_range_is_bipolar(s, range))
2765 val = comedi_offset_munge(s, val);
2766
2767 ni_writew(dev, val, reg);
2768 }
2769 }
2770
2771 return insn->n;
2772 }
2773
2774 static int ni_ao_insn_config(struct comedi_device *dev,
2775 struct comedi_subdevice *s,
2776 struct comedi_insn *insn, unsigned int *data)
2777 {
2778 const struct ni_board_struct *board = dev->board_ptr;
2779 struct ni_private *devpriv = dev->private;
2780 unsigned int nbytes;
2781
2782 switch (data[0]) {
2783 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2784 switch (data[1]) {
2785 case COMEDI_OUTPUT:
2786 nbytes = comedi_samples_to_bytes(s,
2787 board->ao_fifo_depth);
2788 data[2] = 1 + nbytes;
2789 if (devpriv->mite)
2790 data[2] += devpriv->mite->fifo_size;
2791 break;
2792 case COMEDI_INPUT:
2793 data[2] = 0;
2794 break;
2795 default:
2796 return -EINVAL;
2797 }
2798 return 0;
2799 default:
2800 break;
2801 }
2802
2803 return -EINVAL;
2804 }
2805
2806 static int ni_ao_inttrig(struct comedi_device *dev,
2807 struct comedi_subdevice *s,
2808 unsigned int trig_num)
2809 {
2810 struct ni_private *devpriv = dev->private;
2811 struct comedi_cmd *cmd = &s->async->cmd;
2812 int ret;
2813 int interrupt_b_bits;
2814 int i;
2815 static const int timeout = 1000;
2816
2817 if (trig_num != cmd->start_arg)
2818 return -EINVAL;
2819
2820 /* Null trig at beginning prevent ao start trigger from executing more than
2821 once per command (and doing things like trying to allocate the ao dma channel
2822 multiple times) */
2823 s->async->inttrig = NULL;
2824
2825 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2826 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2827 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2828 #ifdef PCIDMA
2829 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2830 if (devpriv->is_6xxx)
2831 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2832 ret = ni_ao_setup_MITE_dma(dev);
2833 if (ret)
2834 return ret;
2835 ret = ni_ao_wait_for_dma_load(dev);
2836 if (ret < 0)
2837 return ret;
2838 #else
2839 ret = ni_ao_prep_fifo(dev, s);
2840 if (ret == 0)
2841 return -EPIPE;
2842
2843 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2844 #endif
2845
2846 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2847 NISTC_AO_MODE3_REG);
2848 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2849 /* wait for DACs to be loaded */
2850 for (i = 0; i < timeout; i++) {
2851 udelay(1);
2852 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
2853 AO_TMRDACWRs_In_Progress_St) == 0)
2854 break;
2855 }
2856 if (i == timeout) {
2857 dev_err(dev->class_dev,
2858 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2859 return -EIO;
2860 }
2861 /*
2862 * stc manual says we are need to clear error interrupt after
2863 * AO_TMRDACWRs_In_Progress_St clears
2864 */
2865 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2866
2867 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2868
2869 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2870 NISTC_AO_CMD1_UC_ARM |
2871 NISTC_AO_CMD1_BC_ARM |
2872 NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2873 NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2874 devpriv->ao_cmd1,
2875 NISTC_AO_CMD1_REG);
2876
2877 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2878 NISTC_AO_CMD2_REG);
2879
2880 return 0;
2881 }
2882
2883 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2884 {
2885 const struct ni_board_struct *board = dev->board_ptr;
2886 struct ni_private *devpriv = dev->private;
2887 const struct comedi_cmd *cmd = &s->async->cmd;
2888 int bits;
2889 int i;
2890 unsigned trigvar;
2891 unsigned val;
2892
2893 if (dev->irq == 0) {
2894 dev_err(dev->class_dev, "cannot run command without an irq\n");
2895 return -EIO;
2896 }
2897
2898 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2899
2900 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2901
2902 if (devpriv->is_6xxx) {
2903 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
2904
2905 bits = 0;
2906 for (i = 0; i < cmd->chanlist_len; i++) {
2907 int chan;
2908
2909 chan = CR_CHAN(cmd->chanlist[i]);
2910 bits |= 1 << chan;
2911 ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
2912 }
2913 ni_ao_win_outw(dev, bits, AO_Timed_611x);
2914 }
2915
2916 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2917
2918 if (cmd->stop_src == TRIG_NONE) {
2919 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2920 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2921 } else {
2922 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2923 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2924 }
2925 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2926
2927 val = devpriv->ao_trigger_select;
2928 switch (cmd->start_src) {
2929 case TRIG_INT:
2930 case TRIG_NOW:
2931 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2932 NISTC_AO_TRIG_START1_SEL_MASK);
2933 val |= NISTC_AO_TRIG_START1_EDGE |
2934 NISTC_AO_TRIG_START1_SYNC;
2935 break;
2936 case TRIG_EXT:
2937 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2938 if (cmd->start_arg & CR_INVERT) {
2939 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2940 val |= NISTC_AO_TRIG_START1_POLARITY;
2941 }
2942 if (cmd->start_arg & CR_EDGE) {
2943 /* 0=edge detection disabled, 1=enabled */
2944 val |= NISTC_AO_TRIG_START1_EDGE;
2945 }
2946 ni_stc_writew(dev, devpriv->ao_trigger_select,
2947 NISTC_AO_TRIG_SEL_REG);
2948 break;
2949 default:
2950 BUG();
2951 break;
2952 }
2953 devpriv->ao_trigger_select = val;
2954 ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2955
2956 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2957 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2958
2959 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2960 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2961 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2962 if (cmd->stop_src == TRIG_NONE)
2963 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2964 else
2965 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2966 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2967 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2968 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2969 switch (cmd->stop_src) {
2970 case TRIG_COUNT:
2971 if (devpriv->is_m_series) {
2972 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
2973 ni_stc_writel(dev, cmd->stop_arg - 1,
2974 NISTC_AO_UC_LOADA_REG);
2975 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2976 NISTC_AO_CMD1_REG);
2977 } else {
2978 ni_stc_writel(dev, cmd->stop_arg,
2979 NISTC_AO_UC_LOADA_REG);
2980 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2981 NISTC_AO_CMD1_REG);
2982 ni_stc_writel(dev, cmd->stop_arg - 1,
2983 NISTC_AO_UC_LOADA_REG);
2984 }
2985 break;
2986 case TRIG_NONE:
2987 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2988 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
2989 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2990 break;
2991 default:
2992 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
2993 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
2994 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
2995 }
2996
2997 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
2998 NISTC_AO_MODE1_UI_SRC_MASK |
2999 NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3000 NISTC_AO_MODE1_UI_SRC_POLARITY);
3001 switch (cmd->scan_begin_src) {
3002 case TRIG_TIMER:
3003 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3004 trigvar =
3005 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3006 CMDF_ROUND_NEAREST);
3007 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3008 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3009 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3010 break;
3011 case TRIG_EXT:
3012 devpriv->ao_mode1 |=
3013 NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3014 if (cmd->scan_begin_arg & CR_INVERT)
3015 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3016 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3017 break;
3018 default:
3019 BUG();
3020 break;
3021 }
3022 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3023 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3024 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3025 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3026 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3027
3028 if (cmd->scan_end_arg > 1) {
3029 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3030 ni_stc_writew(dev,
3031 NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3032 NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3033 NISTC_AO_OUT_CTRL_REG);
3034 } else {
3035 unsigned bits;
3036
3037 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3038 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3039 if (devpriv->is_m_series || devpriv->is_6xxx) {
3040 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3041 } else {
3042 bits |=
3043 NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3044 }
3045 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3046 }
3047 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3048
3049 ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3050 NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3051 NISTC_AO_CMD1_REG);
3052
3053 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3054 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3055
3056 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3057 #ifdef PCIDMA
3058 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3059 #else
3060 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3061 #endif
3062 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3063 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3064
3065 bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3066 NISTC_AO_PERSONAL_UPDATE_PW |
3067 NISTC_AO_PERSONAL_TMRDACWR_PW;
3068 if (board->ao_fifo_depth)
3069 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3070 else
3071 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3072 #if 0
3073 /*
3074 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3075 * for 6281, verified with bus analyzer.
3076 */
3077 if (devpriv->is_m_series)
3078 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3079 #endif
3080 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3081 /* enable sending of ao dma requests */
3082 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3083
3084 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3085
3086 if (cmd->stop_src == TRIG_COUNT) {
3087 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3088 NISTC_INTB_ACK_REG);
3089 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3090 NISTC_INTB_ENA_AO_BC_TC, 1);
3091 }
3092
3093 s->async->inttrig = ni_ao_inttrig;
3094
3095 return 0;
3096 }
3097
3098 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3099 struct comedi_cmd *cmd)
3100 {
3101 const struct ni_board_struct *board = dev->board_ptr;
3102 struct ni_private *devpriv = dev->private;
3103 int err = 0;
3104 unsigned int tmp;
3105
3106 /* Step 1 : check if triggers are trivially valid */
3107
3108 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3109 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3110 TRIG_TIMER | TRIG_EXT);
3111 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3112 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3113 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3114
3115 if (err)
3116 return 1;
3117
3118 /* Step 2a : make sure trigger sources are unique */
3119
3120 err |= comedi_check_trigger_is_unique(cmd->start_src);
3121 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3122 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3123
3124 /* Step 2b : and mutually compatible */
3125
3126 if (err)
3127 return 2;
3128
3129 /* Step 3: check if arguments are trivially valid */
3130
3131 switch (cmd->start_src) {
3132 case TRIG_INT:
3133 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3134 break;
3135 case TRIG_EXT:
3136 tmp = CR_CHAN(cmd->start_arg);
3137
3138 if (tmp > 18)
3139 tmp = 18;
3140 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3141 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3142 break;
3143 }
3144
3145 if (cmd->scan_begin_src == TRIG_TIMER) {
3146 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3147 board->ao_speed);
3148 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3149 devpriv->clock_ns *
3150 0xffffff);
3151 }
3152
3153 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3154 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3155 cmd->chanlist_len);
3156
3157 if (cmd->stop_src == TRIG_COUNT)
3158 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3159 else /* TRIG_NONE */
3160 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3161
3162 if (err)
3163 return 3;
3164
3165 /* step 4: fix up any arguments */
3166 if (cmd->scan_begin_src == TRIG_TIMER) {
3167 tmp = cmd->scan_begin_arg;
3168 cmd->scan_begin_arg =
3169 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3170 cmd->scan_begin_arg,
3171 cmd->flags));
3172 if (tmp != cmd->scan_begin_arg)
3173 err++;
3174 }
3175 if (err)
3176 return 4;
3177
3178 return 0;
3179 }
3180
3181 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3182 {
3183 struct ni_private *devpriv = dev->private;
3184
3185 ni_release_ao_mite_channel(dev);
3186
3187 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3188 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3189 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3190 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3191 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3192 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3193 NISTC_AO_PERSONAL_UPDATE_PW |
3194 NISTC_AO_PERSONAL_TMRDACWR_PW,
3195 NISTC_AO_PERSONAL_REG);
3196 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3197 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3198 devpriv->ao_cmd1 = 0;
3199 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3200 devpriv->ao_cmd2 = 0;
3201 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3202 devpriv->ao_mode1 = 0;
3203 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3204 devpriv->ao_mode2 = 0;
3205 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3206 if (devpriv->is_m_series)
3207 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3208 else
3209 devpriv->ao_mode3 = 0;
3210 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3211 devpriv->ao_trigger_select = 0;
3212 ni_stc_writew(dev, devpriv->ao_trigger_select,
3213 NISTC_AO_TRIG_SEL_REG);
3214 if (devpriv->is_6xxx) {
3215 unsigned immediate_bits = 0;
3216 unsigned i;
3217
3218 for (i = 0; i < s->n_chan; ++i)
3219 immediate_bits |= 1 << i;
3220 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3221 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3222 }
3223 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3224
3225 return 0;
3226 }
3227
3228 /* digital io */
3229
3230 static int ni_dio_insn_config(struct comedi_device *dev,
3231 struct comedi_subdevice *s,
3232 struct comedi_insn *insn,
3233 unsigned int *data)
3234 {
3235 struct ni_private *devpriv = dev->private;
3236 int ret;
3237
3238 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3239 if (ret)
3240 return ret;
3241
3242 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3243 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3244 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3245
3246 return insn->n;
3247 }
3248
3249 static int ni_dio_insn_bits(struct comedi_device *dev,
3250 struct comedi_subdevice *s,
3251 struct comedi_insn *insn,
3252 unsigned int *data)
3253 {
3254 struct ni_private *devpriv = dev->private;
3255
3256 /* Make sure we're not using the serial part of the dio */
3257 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3258 devpriv->serial_interval_ns)
3259 return -EBUSY;
3260
3261 if (comedi_dio_update_state(s, data)) {
3262 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3263 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3264 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3265 }
3266
3267 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3268
3269 return insn->n;
3270 }
3271
3272 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3273 struct comedi_subdevice *s,
3274 struct comedi_insn *insn,
3275 unsigned int *data)
3276 {
3277 int ret;
3278
3279 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3280 if (ret)
3281 return ret;
3282
3283 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3284
3285 return insn->n;
3286 }
3287
3288 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3289 struct comedi_subdevice *s,
3290 struct comedi_insn *insn,
3291 unsigned int *data)
3292 {
3293 if (comedi_dio_update_state(s, data))
3294 ni_writel(dev, s->state, NI_M_DIO_REG);
3295
3296 data[1] = ni_readl(dev, NI_M_DIO_REG);
3297
3298 return insn->n;
3299 }
3300
3301 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3302 struct comedi_subdevice *s,
3303 struct comedi_cmd *cmd)
3304 {
3305 int i;
3306
3307 for (i = 0; i < cmd->chanlist_len; ++i) {
3308 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3309
3310 if (chan != i)
3311 return -EINVAL;
3312 }
3313
3314 return 0;
3315 }
3316
3317 static int ni_cdio_cmdtest(struct comedi_device *dev,
3318 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3319 {
3320 int err = 0;
3321 int tmp;
3322
3323 /* Step 1 : check if triggers are trivially valid */
3324
3325 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3326 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3327 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3328 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3329 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3330
3331 if (err)
3332 return 1;
3333
3334 /* Step 2a : make sure trigger sources are unique */
3335 /* Step 2b : and mutually compatible */
3336
3337 /* Step 3: check if arguments are trivially valid */
3338
3339 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3340
3341 tmp = cmd->scan_begin_arg;
3342 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3343 if (tmp != cmd->scan_begin_arg)
3344 err |= -EINVAL;
3345
3346 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3347 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3348 cmd->chanlist_len);
3349 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3350
3351 if (err)
3352 return 3;
3353
3354 /* Step 4: fix up any arguments */
3355
3356 /* Step 5: check channel list if it exists */
3357
3358 if (cmd->chanlist && cmd->chanlist_len > 0)
3359 err |= ni_cdio_check_chanlist(dev, s, cmd);
3360
3361 if (err)
3362 return 5;
3363
3364 return 0;
3365 }
3366
3367 static int ni_cdo_inttrig(struct comedi_device *dev,
3368 struct comedi_subdevice *s,
3369 unsigned int trig_num)
3370 {
3371 struct comedi_cmd *cmd = &s->async->cmd;
3372 const unsigned timeout = 1000;
3373 int retval = 0;
3374 unsigned i;
3375 #ifdef PCIDMA
3376 struct ni_private *devpriv = dev->private;
3377 unsigned long flags;
3378 #endif
3379
3380 if (trig_num != cmd->start_arg)
3381 return -EINVAL;
3382
3383 s->async->inttrig = NULL;
3384
3385 /* read alloc the entire buffer */
3386 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3387
3388 #ifdef PCIDMA
3389 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3390 if (devpriv->cdo_mite_chan) {
3391 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3392 mite_dma_arm(devpriv->cdo_mite_chan);
3393 } else {
3394 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3395 retval = -EIO;
3396 }
3397 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3398 if (retval < 0)
3399 return retval;
3400 #endif
3401 /*
3402 * XXX not sure what interrupt C group does
3403 * wait for dma to fill output fifo
3404 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3405 */
3406 for (i = 0; i < timeout; ++i) {
3407 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3408 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3409 break;
3410 udelay(10);
3411 }
3412 if (i == timeout) {
3413 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3414 s->cancel(dev, s);
3415 return -EIO;
3416 }
3417 ni_writel(dev, NI_M_CDO_CMD_ARM |
3418 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3419 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3420 NI_M_CDIO_CMD_REG);
3421 return retval;
3422 }
3423
3424 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3425 {
3426 const struct comedi_cmd *cmd = &s->async->cmd;
3427 unsigned cdo_mode_bits;
3428 int retval;
3429
3430 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3431 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3432 NI_M_CDO_MODE_HALT_ON_ERROR |
3433 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3434 if (cmd->scan_begin_arg & CR_INVERT)
3435 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3436 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3437 if (s->io_bits) {
3438 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3439 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3440 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3441 } else {
3442 dev_err(dev->class_dev,
3443 "attempted to run digital output command with no lines configured as outputs\n");
3444 return -EIO;
3445 }
3446 retval = ni_request_cdo_mite_channel(dev);
3447 if (retval < 0)
3448 return retval;
3449
3450 s->async->inttrig = ni_cdo_inttrig;
3451
3452 return 0;
3453 }
3454
3455 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3456 {
3457 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3458 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3459 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3460 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3461 NI_M_CDIO_CMD_REG);
3462 /*
3463 * XXX not sure what interrupt C group does
3464 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3465 */
3466 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3467 ni_release_cdo_mite_channel(dev);
3468 return 0;
3469 }
3470
3471 static void handle_cdio_interrupt(struct comedi_device *dev)
3472 {
3473 struct ni_private *devpriv = dev->private;
3474 unsigned cdio_status;
3475 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3476 #ifdef PCIDMA
3477 unsigned long flags;
3478 #endif
3479
3480 if (!devpriv->is_m_series)
3481 return;
3482 #ifdef PCIDMA
3483 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3484 if (devpriv->cdo_mite_chan) {
3485 unsigned cdo_mite_status =
3486 mite_get_status(devpriv->cdo_mite_chan);
3487 if (cdo_mite_status & CHSR_LINKC) {
3488 writel(CHOR_CLRLC,
3489 devpriv->mite->mite_io_addr +
3490 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3491 }
3492 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3493 }
3494 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3495 #endif
3496
3497 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3498 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3499 /* XXX just guessing this is needed and does something useful */
3500 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3501 NI_M_CDIO_CMD_REG);
3502 s->async->events |= COMEDI_CB_OVERFLOW;
3503 }
3504 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3505 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3506 NI_M_CDIO_CMD_REG);
3507 /* s->async->events |= COMEDI_CB_EOA; */
3508 }
3509 comedi_handle_events(dev, s);
3510 }
3511
3512 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3513 struct comedi_subdevice *s,
3514 unsigned char data_out,
3515 unsigned char *data_in)
3516 {
3517 struct ni_private *devpriv = dev->private;
3518 unsigned int status1;
3519 int err = 0, count = 20;
3520
3521 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3522 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3523 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3524
3525 status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3526 if (status1 & DIO_Serial_IO_In_Progress_St) {
3527 err = -EBUSY;
3528 goto Error;
3529 }
3530
3531 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3532 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3533 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3534
3535 /* Wait until STC says we're done, but don't loop infinitely. */
3536 while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3537 DIO_Serial_IO_In_Progress_St) {
3538 /* Delay one bit per loop */
3539 udelay((devpriv->serial_interval_ns + 999) / 1000);
3540 if (--count < 0) {
3541 dev_err(dev->class_dev,
3542 "SPI serial I/O didn't finish in time!\n");
3543 err = -ETIME;
3544 goto Error;
3545 }
3546 }
3547
3548 /* Delay for last bit. This delay is absolutely necessary, because
3549 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3550 udelay((devpriv->serial_interval_ns + 999) / 1000);
3551
3552 if (data_in)
3553 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3554
3555 Error:
3556 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3557
3558 return err;
3559 }
3560
3561 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3562 struct comedi_subdevice *s,
3563 unsigned char data_out,
3564 unsigned char *data_in)
3565 {
3566 struct ni_private *devpriv = dev->private;
3567 unsigned char mask, input = 0;
3568
3569 /* Wait for one bit before transfer */
3570 udelay((devpriv->serial_interval_ns + 999) / 1000);
3571
3572 for (mask = 0x80; mask; mask >>= 1) {
3573 /* Output current bit; note that we cannot touch s->state
3574 because it is a per-subdevice field, and serial is
3575 a separate subdevice from DIO. */
3576 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3577 if (data_out & mask)
3578 devpriv->dio_output |= NISTC_DIO_SDOUT;
3579 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3580
3581 /* Assert SDCLK (active low, inverted), wait for half of
3582 the delay, deassert SDCLK, and wait for the other half. */
3583 devpriv->dio_control |= NISTC_DIO_SDCLK;
3584 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3585
3586 udelay((devpriv->serial_interval_ns + 999) / 2000);
3587
3588 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3589 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3590
3591 udelay((devpriv->serial_interval_ns + 999) / 2000);
3592
3593 /* Input current bit */
3594 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3595 input |= mask;
3596 }
3597
3598 if (data_in)
3599 *data_in = input;
3600
3601 return 0;
3602 }
3603
3604 static int ni_serial_insn_config(struct comedi_device *dev,
3605 struct comedi_subdevice *s,
3606 struct comedi_insn *insn,
3607 unsigned int *data)
3608 {
3609 struct ni_private *devpriv = dev->private;
3610 unsigned clk_fout = devpriv->clock_and_fout;
3611 int err = insn->n;
3612 unsigned char byte_out, byte_in = 0;
3613
3614 if (insn->n != 2)
3615 return -EINVAL;
3616
3617 switch (data[0]) {
3618 case INSN_CONFIG_SERIAL_CLOCK:
3619 devpriv->serial_hw_mode = 1;
3620 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3621
3622 if (data[1] == SERIAL_DISABLED) {
3623 devpriv->serial_hw_mode = 0;
3624 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3625 NISTC_DIO_SDCLK);
3626 data[1] = SERIAL_DISABLED;
3627 devpriv->serial_interval_ns = data[1];
3628 } else if (data[1] <= SERIAL_600NS) {
3629 /* Warning: this clock speed is too fast to reliably
3630 control SCXI. */
3631 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3632 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3633 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3634 data[1] = SERIAL_600NS;
3635 devpriv->serial_interval_ns = data[1];
3636 } else if (data[1] <= SERIAL_1_2US) {
3637 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3638 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3639 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3640 data[1] = SERIAL_1_2US;
3641 devpriv->serial_interval_ns = data[1];
3642 } else if (data[1] <= SERIAL_10US) {
3643 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3644 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3645 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3646 /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3647 600ns/1.2us. If you turn divide_by_2 off with the
3648 slow clock, you will still get 10us, except then
3649 all your delays are wrong. */
3650 data[1] = SERIAL_10US;
3651 devpriv->serial_interval_ns = data[1];
3652 } else {
3653 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3654 NISTC_DIO_SDCLK);
3655 devpriv->serial_hw_mode = 0;
3656 data[1] = (data[1] / 1000) * 1000;
3657 devpriv->serial_interval_ns = data[1];
3658 }
3659 devpriv->clock_and_fout = clk_fout;
3660
3661 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3662 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3663 return 1;
3664
3665 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3666
3667 if (devpriv->serial_interval_ns == 0)
3668 return -EINVAL;
3669
3670 byte_out = data[1] & 0xFF;
3671
3672 if (devpriv->serial_hw_mode) {
3673 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3674 &byte_in);
3675 } else if (devpriv->serial_interval_ns > 0) {
3676 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3677 &byte_in);
3678 } else {
3679 dev_err(dev->class_dev, "serial disabled!\n");
3680 return -EINVAL;
3681 }
3682 if (err < 0)
3683 return err;
3684 data[1] = byte_in & 0xFF;
3685 return insn->n;
3686
3687 break;
3688 default:
3689 return -EINVAL;
3690 }
3691 }
3692
3693 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3694 {
3695 int i;
3696
3697 for (i = 0; i < s->n_chan; i++) {
3698 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3699 AO_Configuration_2_67xx);
3700 }
3701 ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3702 }
3703
3704 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3705 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3706 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3707 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3708 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3709 [NITIO_G0_HW_SAVE] = { G_HW_Save_Register(0), 4 },
3710 [NITIO_G1_HW_SAVE] = { G_HW_Save_Register(1), 4 },
3711 [NITIO_G0_SW_SAVE] = { G_Save_Register(0), 4 },
3712 [NITIO_G1_SW_SAVE] = { G_Save_Register(1), 4 },
3713 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3714 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3715 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3716 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3717 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3718 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3719 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3720 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3721 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3722 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3723 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3724 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3725 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3726 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3727 [NITIO_G01_STATUS1] = { Joint_Status_1_Register, 2 },
3728 [NITIO_G01_STATUS2] = { Joint_Status_2_Register, 2 },
3729 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3730 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3731 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3732 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3733 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3734 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3735 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3736 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3737 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3738 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3739 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3740 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3741 };
3742
3743 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3744 enum ni_gpct_register reg)
3745 {
3746 const struct mio_regmap *regmap;
3747
3748 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3749 regmap = &ni_gpct_to_stc_regmap[reg];
3750 } else {
3751 dev_warn(dev->class_dev,"%s: unhandled register 0x%x\n",
3752 __func__, reg);
3753 return 0;
3754 }
3755
3756 return regmap->mio_reg;
3757 }
3758
3759 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3760 enum ni_gpct_register reg)
3761 {
3762 struct comedi_device *dev = counter->counter_dev->dev;
3763 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3764 static const unsigned gpct_interrupt_a_enable_mask =
3765 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3766 static const unsigned gpct_interrupt_b_enable_mask =
3767 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3768
3769 if (stc_register == 0)
3770 return;
3771
3772 switch (reg) {
3773 /* m-series only registers */
3774 case NITIO_G0_CNT_MODE:
3775 case NITIO_G1_CNT_MODE:
3776 case NITIO_G0_GATE2:
3777 case NITIO_G1_GATE2:
3778 case NITIO_G0_DMA_CFG:
3779 case NITIO_G1_DMA_CFG:
3780 case NITIO_G0_ABZ:
3781 case NITIO_G1_ABZ:
3782 ni_writew(dev, bits, stc_register);
3783 break;
3784
3785 /* 32 bit registers */
3786 case NITIO_G0_LOADA:
3787 case NITIO_G1_LOADA:
3788 case NITIO_G0_LOADB:
3789 case NITIO_G1_LOADB:
3790 ni_stc_writel(dev, bits, stc_register);
3791 break;
3792
3793 /* 16 bit registers */
3794 case NITIO_G0_INT_ENA:
3795 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3796 ni_set_bitfield(dev, stc_register,
3797 gpct_interrupt_a_enable_mask, bits);
3798 break;
3799 case NITIO_G1_INT_ENA:
3800 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3801 ni_set_bitfield(dev, stc_register,
3802 gpct_interrupt_b_enable_mask, bits);
3803 break;
3804 case NITIO_G01_RESET:
3805 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3806 /* fall-through */
3807 default:
3808 ni_stc_writew(dev, bits, stc_register);
3809 }
3810 }
3811
3812 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3813 enum ni_gpct_register reg)
3814 {
3815 struct comedi_device *dev = counter->counter_dev->dev;
3816 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3817
3818 if (stc_register == 0)
3819 return 0;
3820
3821 switch (reg) {
3822 /* m-series only registers */
3823 case NITIO_G0_DMA_STATUS:
3824 case NITIO_G1_DMA_STATUS:
3825 return ni_readw(dev, stc_register);
3826
3827 /* 32 bit registers */
3828 case NITIO_G0_HW_SAVE:
3829 case NITIO_G1_HW_SAVE:
3830 case NITIO_G0_SW_SAVE:
3831 case NITIO_G1_SW_SAVE:
3832 return ni_stc_readl(dev, stc_register);
3833
3834 /* 16 bit registers */
3835 default:
3836 return ni_stc_readw(dev, stc_register);
3837 }
3838 }
3839
3840 static int ni_freq_out_insn_read(struct comedi_device *dev,
3841 struct comedi_subdevice *s,
3842 struct comedi_insn *insn,
3843 unsigned int *data)
3844 {
3845 struct ni_private *devpriv = dev->private;
3846 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3847 int i;
3848
3849 for (i = 0; i < insn->n; i++)
3850 data[i] = val;
3851
3852 return insn->n;
3853 }
3854
3855 static int ni_freq_out_insn_write(struct comedi_device *dev,
3856 struct comedi_subdevice *s,
3857 struct comedi_insn *insn,
3858 unsigned int *data)
3859 {
3860 struct ni_private *devpriv = dev->private;
3861
3862 if (insn->n) {
3863 unsigned int val = data[insn->n - 1];
3864
3865 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3866 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3867 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3868
3869 /* use the last data value to set the fout divider */
3870 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3871
3872 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3873 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3874 }
3875 return insn->n;
3876 }
3877
3878 static int ni_freq_out_insn_config(struct comedi_device *dev,
3879 struct comedi_subdevice *s,
3880 struct comedi_insn *insn,
3881 unsigned int *data)
3882 {
3883 struct ni_private *devpriv = dev->private;
3884
3885 switch (data[0]) {
3886 case INSN_CONFIG_SET_CLOCK_SRC:
3887 switch (data[1]) {
3888 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3889 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3890 break;
3891 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3892 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3893 break;
3894 default:
3895 return -EINVAL;
3896 }
3897 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3898 break;
3899 case INSN_CONFIG_GET_CLOCK_SRC:
3900 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3901 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3902 data[2] = TIMEBASE_2_NS;
3903 } else {
3904 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3905 data[2] = TIMEBASE_1_NS * 2;
3906 }
3907 break;
3908 default:
3909 return -EINVAL;
3910 }
3911 return insn->n;
3912 }
3913
3914 static int ni_8255_callback(struct comedi_device *dev,
3915 int dir, int port, int data, unsigned long iobase)
3916 {
3917 if (dir) {
3918 ni_writeb(dev, data, iobase + 2 * port);
3919 return 0;
3920 }
3921
3922 return ni_readb(dev, iobase + 2 * port);
3923 }
3924
3925 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3926 {
3927 struct ni_private *devpriv = dev->private;
3928
3929 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3930 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3931 return 3;
3932 }
3933
3934 static int ni_m_series_pwm_config(struct comedi_device *dev,
3935 struct comedi_subdevice *s,
3936 struct comedi_insn *insn,
3937 unsigned int *data)
3938 {
3939 struct ni_private *devpriv = dev->private;
3940 unsigned up_count, down_count;
3941
3942 switch (data[0]) {
3943 case INSN_CONFIG_PWM_OUTPUT:
3944 switch (data[1]) {
3945 case CMDF_ROUND_NEAREST:
3946 up_count =
3947 (data[2] +
3948 devpriv->clock_ns / 2) / devpriv->clock_ns;
3949 break;
3950 case CMDF_ROUND_DOWN:
3951 up_count = data[2] / devpriv->clock_ns;
3952 break;
3953 case CMDF_ROUND_UP:
3954 up_count =
3955 (data[2] + devpriv->clock_ns -
3956 1) / devpriv->clock_ns;
3957 break;
3958 default:
3959 return -EINVAL;
3960 }
3961 switch (data[3]) {
3962 case CMDF_ROUND_NEAREST:
3963 down_count =
3964 (data[4] +
3965 devpriv->clock_ns / 2) / devpriv->clock_ns;
3966 break;
3967 case CMDF_ROUND_DOWN:
3968 down_count = data[4] / devpriv->clock_ns;
3969 break;
3970 case CMDF_ROUND_UP:
3971 down_count =
3972 (data[4] + devpriv->clock_ns -
3973 1) / devpriv->clock_ns;
3974 break;
3975 default:
3976 return -EINVAL;
3977 }
3978 if (up_count * devpriv->clock_ns != data[2] ||
3979 down_count * devpriv->clock_ns != data[4]) {
3980 data[2] = up_count * devpriv->clock_ns;
3981 data[4] = down_count * devpriv->clock_ns;
3982 return -EAGAIN;
3983 }
3984 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
3985 NI_M_CAL_PWM_LOW_TIME(down_count),
3986 NI_M_CAL_PWM_REG);
3987 devpriv->pwm_up_count = up_count;
3988 devpriv->pwm_down_count = down_count;
3989 return 5;
3990 case INSN_CONFIG_GET_PWM_OUTPUT:
3991 return ni_get_pwm_config(dev, data);
3992 default:
3993 return -EINVAL;
3994 }
3995 return 0;
3996 }
3997
3998 static int ni_6143_pwm_config(struct comedi_device *dev,
3999 struct comedi_subdevice *s,
4000 struct comedi_insn *insn,
4001 unsigned int *data)
4002 {
4003 struct ni_private *devpriv = dev->private;
4004 unsigned up_count, down_count;
4005
4006 switch (data[0]) {
4007 case INSN_CONFIG_PWM_OUTPUT:
4008 switch (data[1]) {
4009 case CMDF_ROUND_NEAREST:
4010 up_count =
4011 (data[2] +
4012 devpriv->clock_ns / 2) / devpriv->clock_ns;
4013 break;
4014 case CMDF_ROUND_DOWN:
4015 up_count = data[2] / devpriv->clock_ns;
4016 break;
4017 case CMDF_ROUND_UP:
4018 up_count =
4019 (data[2] + devpriv->clock_ns -
4020 1) / devpriv->clock_ns;
4021 break;
4022 default:
4023 return -EINVAL;
4024 }
4025 switch (data[3]) {
4026 case CMDF_ROUND_NEAREST:
4027 down_count =
4028 (data[4] +
4029 devpriv->clock_ns / 2) / devpriv->clock_ns;
4030 break;
4031 case CMDF_ROUND_DOWN:
4032 down_count = data[4] / devpriv->clock_ns;
4033 break;
4034 case CMDF_ROUND_UP:
4035 down_count =
4036 (data[4] + devpriv->clock_ns -
4037 1) / devpriv->clock_ns;
4038 break;
4039 default:
4040 return -EINVAL;
4041 }
4042 if (up_count * devpriv->clock_ns != data[2] ||
4043 down_count * devpriv->clock_ns != data[4]) {
4044 data[2] = up_count * devpriv->clock_ns;
4045 data[4] = down_count * devpriv->clock_ns;
4046 return -EAGAIN;
4047 }
4048 ni_writel(dev, up_count, Calibration_HighTime_6143);
4049 devpriv->pwm_up_count = up_count;
4050 ni_writel(dev, down_count, Calibration_LowTime_6143);
4051 devpriv->pwm_down_count = down_count;
4052 return 5;
4053 case INSN_CONFIG_GET_PWM_OUTPUT:
4054 return ni_get_pwm_config(dev, data);
4055 default:
4056 return -EINVAL;
4057 }
4058 return 0;
4059 }
4060
4061 static int pack_mb88341(int addr, int val, int *bitstring)
4062 {
4063 /*
4064 Fujitsu MB 88341
4065 Note that address bits are reversed. Thanks to
4066 Ingo Keen for noticing this.
4067
4068 Note also that the 88341 expects address values from
4069 1-12, whereas we use channel numbers 0-11. The NI
4070 docs use 1-12, also, so be careful here.
4071 */
4072 addr++;
4073 *bitstring = ((addr & 0x1) << 11) |
4074 ((addr & 0x2) << 9) |
4075 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4076 return 12;
4077 }
4078
4079 static int pack_dac8800(int addr, int val, int *bitstring)
4080 {
4081 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4082 return 11;
4083 }
4084
4085 static int pack_dac8043(int addr, int val, int *bitstring)
4086 {
4087 *bitstring = val & 0xfff;
4088 return 12;
4089 }
4090
4091 static int pack_ad8522(int addr, int val, int *bitstring)
4092 {
4093 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4094 return 16;
4095 }
4096
4097 static int pack_ad8804(int addr, int val, int *bitstring)
4098 {
4099 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4100 return 12;
4101 }
4102
4103 static int pack_ad8842(int addr, int val, int *bitstring)
4104 {
4105 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4106 return 12;
4107 }
4108
4109 struct caldac_struct {
4110 int n_chans;
4111 int n_bits;
4112 int (*packbits)(int, int, int *);
4113 };
4114
4115 static struct caldac_struct caldacs[] = {
4116 [mb88341] = {12, 8, pack_mb88341},
4117 [dac8800] = {8, 8, pack_dac8800},
4118 [dac8043] = {1, 12, pack_dac8043},
4119 [ad8522] = {2, 12, pack_ad8522},
4120 [ad8804] = {12, 8, pack_ad8804},
4121 [ad8842] = {8, 8, pack_ad8842},
4122 [ad8804_debug] = {16, 8, pack_ad8804},
4123 };
4124
4125 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4126 {
4127 const struct ni_board_struct *board = dev->board_ptr;
4128 struct ni_private *devpriv = dev->private;
4129 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4130 int i;
4131 int type;
4132
4133 if (devpriv->caldacs[addr] == val)
4134 return;
4135 devpriv->caldacs[addr] = val;
4136
4137 for (i = 0; i < 3; i++) {
4138 type = board->caldac[i];
4139 if (type == caldac_none)
4140 break;
4141 if (addr < caldacs[type].n_chans) {
4142 bits = caldacs[type].packbits(addr, val, &bitstring);
4143 loadbit = SerDacLd(i);
4144 break;
4145 }
4146 addr -= caldacs[type].n_chans;
4147 }
4148
4149 /* bits will be 0 if there is no caldac for the given addr */
4150 if (bits == 0)
4151 return;
4152
4153 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4154 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4155 udelay(1);
4156 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4157 Serial_Command);
4158 udelay(1);
4159 }
4160 ni_writeb(dev, loadbit, Serial_Command);
4161 udelay(1);
4162 ni_writeb(dev, 0, Serial_Command);
4163 }
4164
4165 static int ni_calib_insn_write(struct comedi_device *dev,
4166 struct comedi_subdevice *s,
4167 struct comedi_insn *insn,
4168 unsigned int *data)
4169 {
4170 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4171
4172 return 1;
4173 }
4174
4175 static int ni_calib_insn_read(struct comedi_device *dev,
4176 struct comedi_subdevice *s,
4177 struct comedi_insn *insn,
4178 unsigned int *data)
4179 {
4180 struct ni_private *devpriv = dev->private;
4181
4182 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4183
4184 return 1;
4185 }
4186
4187 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4188 {
4189 const struct ni_board_struct *board = dev->board_ptr;
4190 struct ni_private *devpriv = dev->private;
4191 int i, j;
4192 int n_dacs;
4193 int n_chans = 0;
4194 int n_bits;
4195 int diffbits = 0;
4196 int type;
4197 int chan;
4198
4199 type = board->caldac[0];
4200 if (type == caldac_none)
4201 return;
4202 n_bits = caldacs[type].n_bits;
4203 for (i = 0; i < 3; i++) {
4204 type = board->caldac[i];
4205 if (type == caldac_none)
4206 break;
4207 if (caldacs[type].n_bits != n_bits)
4208 diffbits = 1;
4209 n_chans += caldacs[type].n_chans;
4210 }
4211 n_dacs = i;
4212 s->n_chan = n_chans;
4213
4214 if (diffbits) {
4215 unsigned int *maxdata_list;
4216
4217 if (n_chans > MAX_N_CALDACS)
4218 dev_err(dev->class_dev,
4219 "BUG! MAX_N_CALDACS too small\n");
4220 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4221 chan = 0;
4222 for (i = 0; i < n_dacs; i++) {
4223 type = board->caldac[i];
4224 for (j = 0; j < caldacs[type].n_chans; j++) {
4225 maxdata_list[chan] =
4226 (1 << caldacs[type].n_bits) - 1;
4227 chan++;
4228 }
4229 }
4230
4231 for (chan = 0; chan < s->n_chan; chan++)
4232 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4233 } else {
4234 type = board->caldac[0];
4235 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4236
4237 for (chan = 0; chan < s->n_chan; chan++)
4238 ni_write_caldac(dev, i, s->maxdata / 2);
4239 }
4240 }
4241
4242 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4243 {
4244 int bit;
4245 int bitstring;
4246
4247 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4248 ni_writeb(dev, 0x04, Serial_Command);
4249 for (bit = 0x8000; bit; bit >>= 1) {
4250 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4251 Serial_Command);
4252 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4253 Serial_Command);
4254 }
4255 bitstring = 0;
4256 for (bit = 0x80; bit; bit >>= 1) {
4257 ni_writeb(dev, 0x04, Serial_Command);
4258 ni_writeb(dev, 0x05, Serial_Command);
4259 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4260 }
4261 ni_writeb(dev, 0x00, Serial_Command);
4262
4263 return bitstring;
4264 }
4265
4266 static int ni_eeprom_insn_read(struct comedi_device *dev,
4267 struct comedi_subdevice *s,
4268 struct comedi_insn *insn,
4269 unsigned int *data)
4270 {
4271 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4272
4273 return 1;
4274 }
4275
4276 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4277 struct comedi_subdevice *s,
4278 struct comedi_insn *insn,
4279 unsigned int *data)
4280 {
4281 struct ni_private *devpriv = dev->private;
4282
4283 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4284
4285 return 1;
4286 }
4287
4288 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4289 unsigned chan)
4290 {
4291 /* pre-m-series boards have fixed signals on pfi pins */
4292 switch (chan) {
4293 case 0:
4294 return NI_PFI_OUTPUT_AI_START1;
4295 case 1:
4296 return NI_PFI_OUTPUT_AI_START2;
4297 case 2:
4298 return NI_PFI_OUTPUT_AI_CONVERT;
4299 case 3:
4300 return NI_PFI_OUTPUT_G_SRC1;
4301 case 4:
4302 return NI_PFI_OUTPUT_G_GATE1;
4303 case 5:
4304 return NI_PFI_OUTPUT_AO_UPDATE_N;
4305 case 6:
4306 return NI_PFI_OUTPUT_AO_START1;
4307 case 7:
4308 return NI_PFI_OUTPUT_AI_START_PULSE;
4309 case 8:
4310 return NI_PFI_OUTPUT_G_SRC0;
4311 case 9:
4312 return NI_PFI_OUTPUT_G_GATE0;
4313 default:
4314 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4315 break;
4316 }
4317 return 0;
4318 }
4319
4320 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4321 unsigned chan, unsigned source)
4322 {
4323 /* pre-m-series boards have fixed signals on pfi pins */
4324 if (source != ni_old_get_pfi_routing(dev, chan))
4325 return -EINVAL;
4326 return 2;
4327 }
4328
4329 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4330 unsigned chan)
4331 {
4332 struct ni_private *devpriv = dev->private;
4333 const unsigned array_offset = chan / 3;
4334
4335 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4336 devpriv->pfi_output_select_reg[array_offset]);
4337 }
4338
4339 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4340 unsigned chan, unsigned source)
4341 {
4342 struct ni_private *devpriv = dev->private;
4343 unsigned index = chan / 3;
4344 unsigned short val = devpriv->pfi_output_select_reg[index];
4345
4346 if ((source & 0x1f) != source)
4347 return -EINVAL;
4348
4349 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4350 val |= NI_M_PFI_OUT_SEL(chan, source);
4351 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4352 devpriv->pfi_output_select_reg[index] = val;
4353
4354 return 2;
4355 }
4356
4357 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4358 {
4359 struct ni_private *devpriv = dev->private;
4360
4361 return (devpriv->is_m_series)
4362 ? ni_m_series_get_pfi_routing(dev, chan)
4363 : ni_old_get_pfi_routing(dev, chan);
4364 }
4365
4366 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4367 unsigned source)
4368 {
4369 struct ni_private *devpriv = dev->private;
4370
4371 return (devpriv->is_m_series)
4372 ? ni_m_series_set_pfi_routing(dev, chan, source)
4373 : ni_old_set_pfi_routing(dev, chan, source);
4374 }
4375
4376 static int ni_config_filter(struct comedi_device *dev,
4377 unsigned pfi_channel,
4378 enum ni_pfi_filter_select filter)
4379 {
4380 struct ni_private *devpriv = dev->private;
4381 unsigned bits;
4382
4383 if (!devpriv->is_m_series)
4384 return -ENOTSUPP;
4385
4386 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4387 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4388 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4389 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4390 return 0;
4391 }
4392
4393 static int ni_pfi_insn_config(struct comedi_device *dev,
4394 struct comedi_subdevice *s,
4395 struct comedi_insn *insn,
4396 unsigned int *data)
4397 {
4398 struct ni_private *devpriv = dev->private;
4399 unsigned int chan;
4400
4401 if (insn->n < 1)
4402 return -EINVAL;
4403
4404 chan = CR_CHAN(insn->chanspec);
4405
4406 switch (data[0]) {
4407 case COMEDI_OUTPUT:
4408 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4409 break;
4410 case COMEDI_INPUT:
4411 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4412 break;
4413 case INSN_CONFIG_DIO_QUERY:
4414 data[1] =
4415 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4416 COMEDI_OUTPUT : COMEDI_INPUT;
4417 return 0;
4418 case INSN_CONFIG_SET_ROUTING:
4419 return ni_set_pfi_routing(dev, chan, data[1]);
4420 case INSN_CONFIG_GET_ROUTING:
4421 data[1] = ni_get_pfi_routing(dev, chan);
4422 break;
4423 case INSN_CONFIG_FILTER:
4424 return ni_config_filter(dev, chan, data[1]);
4425 default:
4426 return -EINVAL;
4427 }
4428 return 0;
4429 }
4430
4431 static int ni_pfi_insn_bits(struct comedi_device *dev,
4432 struct comedi_subdevice *s,
4433 struct comedi_insn *insn,
4434 unsigned int *data)
4435 {
4436 struct ni_private *devpriv = dev->private;
4437
4438 if (!devpriv->is_m_series)
4439 return -ENOTSUPP;
4440
4441 if (comedi_dio_update_state(s, data))
4442 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4443
4444 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4445
4446 return insn->n;
4447 }
4448
4449 static int cs5529_wait_for_idle(struct comedi_device *dev)
4450 {
4451 unsigned short status;
4452 const int timeout = HZ;
4453 int i;
4454
4455 for (i = 0; i < timeout; i++) {
4456 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4457 if ((status & CSS_ADC_BUSY) == 0)
4458 break;
4459 set_current_state(TASK_INTERRUPTIBLE);
4460 if (schedule_timeout(1))
4461 return -EIO;
4462 }
4463 if (i == timeout) {
4464 dev_err(dev->class_dev, "timeout\n");
4465 return -ETIME;
4466 }
4467 return 0;
4468 }
4469
4470 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4471 {
4472 static const int timeout = 100;
4473 int i;
4474
4475 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4476 /* give time for command to start being serially clocked into cs5529.
4477 * this insures that the CSS_ADC_BUSY bit will get properly
4478 * set before we exit this function.
4479 */
4480 for (i = 0; i < timeout; i++) {
4481 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4482 break;
4483 udelay(1);
4484 }
4485 if (i == timeout)
4486 dev_err(dev->class_dev,
4487 "possible problem - never saw adc go busy?\n");
4488 }
4489
4490 static int cs5529_do_conversion(struct comedi_device *dev,
4491 unsigned short *data)
4492 {
4493 int retval;
4494 unsigned short status;
4495
4496 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4497 retval = cs5529_wait_for_idle(dev);
4498 if (retval) {
4499 dev_err(dev->class_dev,
4500 "timeout or signal in cs5529_do_conversion()\n");
4501 return -ETIME;
4502 }
4503 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4504 if (status & CSS_OSC_DETECT) {
4505 dev_err(dev->class_dev,
4506 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4507 return -EIO;
4508 }
4509 if (status & CSS_OVERRANGE) {
4510 dev_err(dev->class_dev,
4511 "cs5529 conversion error, overrange (ignoring)\n");
4512 }
4513 if (data) {
4514 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4515 /* cs5529 returns 16 bit signed data in bipolar mode */
4516 *data ^= (1 << 15);
4517 }
4518 return 0;
4519 }
4520
4521 static int cs5529_ai_insn_read(struct comedi_device *dev,
4522 struct comedi_subdevice *s,
4523 struct comedi_insn *insn,
4524 unsigned int *data)
4525 {
4526 int n, retval;
4527 unsigned short sample;
4528 unsigned int channel_select;
4529 const unsigned int INTERNAL_REF = 0x1000;
4530
4531 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4532 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4533 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4534 if (insn->chanspec & CR_ALT_SOURCE)
4535 channel_select = INTERNAL_REF;
4536 else
4537 channel_select = CR_CHAN(insn->chanspec);
4538 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4539
4540 for (n = 0; n < insn->n; n++) {
4541 retval = cs5529_do_conversion(dev, &sample);
4542 if (retval < 0)
4543 return retval;
4544 data[n] = sample;
4545 }
4546 return insn->n;
4547 }
4548
4549 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4550 unsigned int reg_select_bits)
4551 {
4552 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4553 CAL_ADC_Config_Data_High_Word_67xx);
4554 ni_ao_win_outw(dev, (value & 0xffff),
4555 CAL_ADC_Config_Data_Low_Word_67xx);
4556 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4557 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4558 if (cs5529_wait_for_idle(dev))
4559 dev_err(dev->class_dev,
4560 "timeout or signal in %s\n", __func__);
4561 }
4562
4563 static int init_cs5529(struct comedi_device *dev)
4564 {
4565 unsigned int config_bits =
4566 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4567
4568 #if 1
4569 /* do self-calibration */
4570 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4571 CSCMD_CONFIG_REGISTER);
4572 /* need to force a conversion for calibration to run */
4573 cs5529_do_conversion(dev, NULL);
4574 #else
4575 /* force gain calibration to 1 */
4576 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4577 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4578 CSCMD_CONFIG_REGISTER);
4579 if (cs5529_wait_for_idle(dev))
4580 dev_err(dev->class_dev,
4581 "timeout or signal in %s\n", __func__);
4582 #endif
4583 return 0;
4584 }
4585
4586 /*
4587 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4588 * given an arbitrary frequency input clock.
4589 */
4590 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4591 unsigned *freq_divider,
4592 unsigned *freq_multiplier,
4593 unsigned *actual_period_ns)
4594 {
4595 unsigned div;
4596 unsigned best_div = 1;
4597 unsigned mult;
4598 unsigned best_mult = 1;
4599 static const unsigned pico_per_nano = 1000;
4600
4601 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4602 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4603 * 20 MHz for most timing clocks */
4604 static const unsigned target_picosec = 12500;
4605 static const unsigned fudge_factor_80_to_20Mhz = 4;
4606 int best_period_picosec = 0;
4607
4608 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4609 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4610 unsigned new_period_ps =
4611 (reference_picosec * div) / mult;
4612 if (abs(new_period_ps - target_picosec) <
4613 abs(best_period_picosec - target_picosec)) {
4614 best_period_picosec = new_period_ps;
4615 best_div = div;
4616 best_mult = mult;
4617 }
4618 }
4619 }
4620 if (best_period_picosec == 0)
4621 return -EIO;
4622
4623 *freq_divider = best_div;
4624 *freq_multiplier = best_mult;
4625 *actual_period_ns =
4626 (best_period_picosec * fudge_factor_80_to_20Mhz +
4627 (pico_per_nano / 2)) / pico_per_nano;
4628 return 0;
4629 }
4630
4631 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4632 unsigned source, unsigned period_ns)
4633 {
4634 struct ni_private *devpriv = dev->private;
4635 static const unsigned min_period_ns = 50;
4636 static const unsigned max_period_ns = 1000;
4637 static const unsigned timeout = 1000;
4638 unsigned pll_control_bits;
4639 unsigned freq_divider;
4640 unsigned freq_multiplier;
4641 unsigned rtsi;
4642 unsigned i;
4643 int retval;
4644
4645 if (source == NI_MIO_PLL_PXI10_CLOCK)
4646 period_ns = 100;
4647 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4648 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4649 dev_err(dev->class_dev,
4650 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4651 __func__, min_period_ns, max_period_ns);
4652 return -EINVAL;
4653 }
4654 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4655 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4656 NISTC_RTSI_TRIG_DIR_REG);
4657 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4658 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4659 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4660 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4661 switch (source) {
4662 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4663 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4664 break;
4665 case NI_MIO_PLL_PXI10_CLOCK:
4666 /* pxi clock is 10MHz */
4667 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4668 break;
4669 default:
4670 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4671 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4672 devpriv->clock_and_fout2 |=
4673 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4674 break;
4675 }
4676 }
4677 if (rtsi > NI_M_MAX_RTSI_CHAN)
4678 return -EINVAL;
4679 break;
4680 }
4681 retval = ni_mseries_get_pll_parameters(period_ns,
4682 &freq_divider,
4683 &freq_multiplier,
4684 &devpriv->clock_ns);
4685 if (retval < 0) {
4686 dev_err(dev->class_dev,
4687 "bug, failed to find pll parameters\n");
4688 return retval;
4689 }
4690
4691 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4692 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4693 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4694
4695 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4696 devpriv->clock_source = source;
4697 /* it seems to typically take a few hundred microseconds for PLL to lock */
4698 for (i = 0; i < timeout; ++i) {
4699 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4700 break;
4701 udelay(1);
4702 }
4703 if (i == timeout) {
4704 dev_err(dev->class_dev,
4705 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4706 __func__, source, period_ns);
4707 return -ETIMEDOUT;
4708 }
4709 return 3;
4710 }
4711
4712 static int ni_set_master_clock(struct comedi_device *dev,
4713 unsigned source, unsigned period_ns)
4714 {
4715 struct ni_private *devpriv = dev->private;
4716
4717 if (source == NI_MIO_INTERNAL_CLOCK) {
4718 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4719 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4720 NISTC_RTSI_TRIG_DIR_REG);
4721 devpriv->clock_ns = TIMEBASE_1_NS;
4722 if (devpriv->is_m_series) {
4723 devpriv->clock_and_fout2 &=
4724 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4725 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4726 ni_writew(dev, devpriv->clock_and_fout2,
4727 NI_M_CLK_FOUT2_REG);
4728 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4729 }
4730 devpriv->clock_source = source;
4731 } else {
4732 if (devpriv->is_m_series) {
4733 return ni_mseries_set_pll_master_clock(dev, source,
4734 period_ns);
4735 } else {
4736 if (source == NI_MIO_RTSI_CLOCK) {
4737 devpriv->rtsi_trig_direction_reg |=
4738 NISTC_RTSI_TRIG_USE_CLK;
4739 ni_stc_writew(dev,
4740 devpriv->rtsi_trig_direction_reg,
4741 NISTC_RTSI_TRIG_DIR_REG);
4742 if (period_ns == 0) {
4743 dev_err(dev->class_dev,
4744 "we don't handle an unspecified clock period correctly yet, returning error\n");
4745 return -EINVAL;
4746 }
4747 devpriv->clock_ns = period_ns;
4748 devpriv->clock_source = source;
4749 } else {
4750 return -EINVAL;
4751 }
4752 }
4753 }
4754 return 3;
4755 }
4756
4757 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4758 unsigned chan, unsigned source)
4759 {
4760 struct ni_private *devpriv = dev->private;
4761
4762 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4763 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4764 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4765 return 1;
4766
4767 dev_err(dev->class_dev,
4768 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4769 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4770 return 0;
4771 }
4772 return 0;
4773 }
4774 switch (source) {
4775 case NI_RTSI_OUTPUT_ADR_START1:
4776 case NI_RTSI_OUTPUT_ADR_START2:
4777 case NI_RTSI_OUTPUT_SCLKG:
4778 case NI_RTSI_OUTPUT_DACUPDN:
4779 case NI_RTSI_OUTPUT_DA_START1:
4780 case NI_RTSI_OUTPUT_G_SRC0:
4781 case NI_RTSI_OUTPUT_G_GATE0:
4782 case NI_RTSI_OUTPUT_RGOUT0:
4783 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4784 return 1;
4785 case NI_RTSI_OUTPUT_RTSI_OSC:
4786 return (devpriv->is_m_series) ? 1 : 0;
4787 default:
4788 return 0;
4789 }
4790 }
4791
4792 static int ni_set_rtsi_routing(struct comedi_device *dev,
4793 unsigned chan, unsigned src)
4794 {
4795 struct ni_private *devpriv = dev->private;
4796
4797 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4798 return -EINVAL;
4799 if (chan < 4) {
4800 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4801 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4802 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4803 NISTC_RTSI_TRIGA_OUT_REG);
4804 } else if (chan < 8) {
4805 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4806 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4807 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4808 NISTC_RTSI_TRIGB_OUT_REG);
4809 }
4810 return 2;
4811 }
4812
4813 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4814 {
4815 struct ni_private *devpriv = dev->private;
4816
4817 if (chan < 4) {
4818 return NISTC_RTSI_TRIG_TO_SRC(chan,
4819 devpriv->rtsi_trig_a_output_reg);
4820 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4821 return NISTC_RTSI_TRIG_TO_SRC(chan,
4822 devpriv->rtsi_trig_b_output_reg);
4823 } else {
4824 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4825 return NI_RTSI_OUTPUT_RTSI_OSC;
4826 dev_err(dev->class_dev, "bug! should never get here?\n");
4827 return 0;
4828 }
4829 }
4830
4831 static int ni_rtsi_insn_config(struct comedi_device *dev,
4832 struct comedi_subdevice *s,
4833 struct comedi_insn *insn,
4834 unsigned int *data)
4835 {
4836 struct ni_private *devpriv = dev->private;
4837 unsigned int chan = CR_CHAN(insn->chanspec);
4838 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4839
4840 switch (data[0]) {
4841 case INSN_CONFIG_DIO_OUTPUT:
4842 if (chan < max_chan) {
4843 devpriv->rtsi_trig_direction_reg |=
4844 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4845 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4846 devpriv->rtsi_trig_direction_reg |=
4847 NISTC_RTSI_TRIG_DRV_CLK;
4848 }
4849 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4850 NISTC_RTSI_TRIG_DIR_REG);
4851 break;
4852 case INSN_CONFIG_DIO_INPUT:
4853 if (chan < max_chan) {
4854 devpriv->rtsi_trig_direction_reg &=
4855 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4856 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4857 devpriv->rtsi_trig_direction_reg &=
4858 ~NISTC_RTSI_TRIG_DRV_CLK;
4859 }
4860 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4861 NISTC_RTSI_TRIG_DIR_REG);
4862 break;
4863 case INSN_CONFIG_DIO_QUERY:
4864 if (chan < max_chan) {
4865 data[1] =
4866 (devpriv->rtsi_trig_direction_reg &
4867 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4868 ? INSN_CONFIG_DIO_OUTPUT
4869 : INSN_CONFIG_DIO_INPUT;
4870 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4871 data[1] = (devpriv->rtsi_trig_direction_reg &
4872 NISTC_RTSI_TRIG_DRV_CLK)
4873 ? INSN_CONFIG_DIO_OUTPUT
4874 : INSN_CONFIG_DIO_INPUT;
4875 }
4876 return 2;
4877 case INSN_CONFIG_SET_CLOCK_SRC:
4878 return ni_set_master_clock(dev, data[1], data[2]);
4879 case INSN_CONFIG_GET_CLOCK_SRC:
4880 data[1] = devpriv->clock_source;
4881 data[2] = devpriv->clock_ns;
4882 return 3;
4883 case INSN_CONFIG_SET_ROUTING:
4884 return ni_set_rtsi_routing(dev, chan, data[1]);
4885 case INSN_CONFIG_GET_ROUTING:
4886 data[1] = ni_get_rtsi_routing(dev, chan);
4887 return 2;
4888 default:
4889 return -EINVAL;
4890 }
4891 return 1;
4892 }
4893
4894 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4895 struct comedi_subdevice *s,
4896 struct comedi_insn *insn,
4897 unsigned int *data)
4898 {
4899 data[1] = 0;
4900
4901 return insn->n;
4902 }
4903
4904 static void ni_rtsi_init(struct comedi_device *dev)
4905 {
4906 struct ni_private *devpriv = dev->private;
4907
4908 /* Initialises the RTSI bus signal switch to a default state */
4909
4910 /*
4911 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4912 * to have no effect, at least on pxi-6281, which always uses
4913 * 20MHz rtsi clock frequency
4914 */
4915 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4916 /* Set clock mode to internal */
4917 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4918 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4919 /* default internal lines routing to RTSI bus lines */
4920 devpriv->rtsi_trig_a_output_reg =
4921 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4922 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4923 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4924 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4925 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4926 NISTC_RTSI_TRIGA_OUT_REG);
4927 devpriv->rtsi_trig_b_output_reg =
4928 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4929 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4930 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4931 if (devpriv->is_m_series)
4932 devpriv->rtsi_trig_b_output_reg |=
4933 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4934 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4935 NISTC_RTSI_TRIGB_OUT_REG);
4936
4937 /*
4938 * Sets the source and direction of the 4 on board lines
4939 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4940 */
4941 }
4942
4943 #ifdef PCIDMA
4944 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4945 {
4946 struct ni_gpct *counter = s->private;
4947 int retval;
4948
4949 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4950 COMEDI_INPUT);
4951 if (retval) {
4952 dev_err(dev->class_dev,
4953 "no dma channel available for use by counter\n");
4954 return retval;
4955 }
4956 ni_tio_acknowledge(counter);
4957 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4958
4959 return ni_tio_cmd(dev, s);
4960 }
4961
4962 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4963 {
4964 struct ni_gpct *counter = s->private;
4965 int retval;
4966
4967 retval = ni_tio_cancel(counter);
4968 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4969 ni_release_gpct_mite_channel(dev, counter->counter_index);
4970 return retval;
4971 }
4972 #endif
4973
4974 static irqreturn_t ni_E_interrupt(int irq, void *d)
4975 {
4976 struct comedi_device *dev = d;
4977 unsigned short a_status;
4978 unsigned short b_status;
4979 unsigned int ai_mite_status = 0;
4980 unsigned int ao_mite_status = 0;
4981 unsigned long flags;
4982 #ifdef PCIDMA
4983 struct ni_private *devpriv = dev->private;
4984 struct mite_struct *mite = devpriv->mite;
4985 #endif
4986
4987 if (!dev->attached)
4988 return IRQ_NONE;
4989 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
4990
4991 /* lock to avoid race with comedi_poll */
4992 spin_lock_irqsave(&dev->spinlock, flags);
4993 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
4994 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
4995 #ifdef PCIDMA
4996 if (mite) {
4997 struct ni_private *devpriv = dev->private;
4998 unsigned long flags_too;
4999
5000 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5001 if (devpriv->ai_mite_chan) {
5002 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5003 if (ai_mite_status & CHSR_LINKC)
5004 writel(CHOR_CLRLC,
5005 devpriv->mite->mite_io_addr +
5006 MITE_CHOR(devpriv->
5007 ai_mite_chan->channel));
5008 }
5009 if (devpriv->ao_mite_chan) {
5010 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5011 if (ao_mite_status & CHSR_LINKC)
5012 writel(CHOR_CLRLC,
5013 mite->mite_io_addr +
5014 MITE_CHOR(devpriv->
5015 ao_mite_chan->channel));
5016 }
5017 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5018 }
5019 #endif
5020 ack_a_interrupt(dev, a_status);
5021 ack_b_interrupt(dev, b_status);
5022 if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5023 handle_a_interrupt(dev, a_status, ai_mite_status);
5024 if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5025 handle_b_interrupt(dev, b_status, ao_mite_status);
5026 handle_gpct_interrupt(dev, 0);
5027 handle_gpct_interrupt(dev, 1);
5028 handle_cdio_interrupt(dev);
5029
5030 spin_unlock_irqrestore(&dev->spinlock, flags);
5031 return IRQ_HANDLED;
5032 }
5033
5034 static int ni_alloc_private(struct comedi_device *dev)
5035 {
5036 struct ni_private *devpriv;
5037
5038 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5039 if (!devpriv)
5040 return -ENOMEM;
5041
5042 spin_lock_init(&devpriv->window_lock);
5043 spin_lock_init(&devpriv->soft_reg_copy_lock);
5044 spin_lock_init(&devpriv->mite_channel_lock);
5045
5046 return 0;
5047 }
5048
5049 static int ni_E_init(struct comedi_device *dev,
5050 unsigned interrupt_pin, unsigned irq_polarity)
5051 {
5052 const struct ni_board_struct *board = dev->board_ptr;
5053 struct ni_private *devpriv = dev->private;
5054 struct comedi_subdevice *s;
5055 int ret;
5056 int i;
5057
5058 if (board->n_aochan > MAX_N_AO_CHAN) {
5059 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5060 return -EINVAL;
5061 }
5062
5063 /* initialize clock dividers */
5064 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5065 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5066 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5067 NISTC_CLK_FOUT_TO_BOARD;
5068 if (!devpriv->is_6xxx) {
5069 /* BEAM is this needed for PCI-6143 ?? */
5070 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5071 NISTC_CLK_FOUT_AO_OUT_DIV2);
5072 }
5073 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5074
5075 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5076 if (ret)
5077 return ret;
5078
5079 /* Analog Input subdevice */
5080 s = &dev->subdevices[NI_AI_SUBDEV];
5081 if (board->n_adchan) {
5082 s->type = COMEDI_SUBD_AI;
5083 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5084 if (!devpriv->is_611x)
5085 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5086 if (board->ai_maxdata > 0xffff)
5087 s->subdev_flags |= SDF_LSAMPL;
5088 if (devpriv->is_m_series)
5089 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5090 s->n_chan = board->n_adchan;
5091 s->maxdata = board->ai_maxdata;
5092 s->range_table = ni_range_lkup[board->gainlkup];
5093 s->insn_read = ni_ai_insn_read;
5094 s->insn_config = ni_ai_insn_config;
5095 if (dev->irq) {
5096 dev->read_subdev = s;
5097 s->subdev_flags |= SDF_CMD_READ;
5098 s->len_chanlist = 512;
5099 s->do_cmdtest = ni_ai_cmdtest;
5100 s->do_cmd = ni_ai_cmd;
5101 s->cancel = ni_ai_reset;
5102 s->poll = ni_ai_poll;
5103 s->munge = ni_ai_munge;
5104
5105 if (devpriv->mite)
5106 s->async_dma_dir = DMA_FROM_DEVICE;
5107 }
5108
5109 /* reset the analog input configuration */
5110 ni_ai_reset(dev, s);
5111 } else {
5112 s->type = COMEDI_SUBD_UNUSED;
5113 }
5114
5115 /* Analog Output subdevice */
5116 s = &dev->subdevices[NI_AO_SUBDEV];
5117 if (board->n_aochan) {
5118 s->type = COMEDI_SUBD_AO;
5119 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5120 if (devpriv->is_m_series)
5121 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5122 s->n_chan = board->n_aochan;
5123 s->maxdata = board->ao_maxdata;
5124 s->range_table = board->ao_range_table;
5125 s->insn_config = ni_ao_insn_config;
5126 s->insn_write = ni_ao_insn_write;
5127
5128 ret = comedi_alloc_subdev_readback(s);
5129 if (ret)
5130 return ret;
5131
5132 /*
5133 * Along with the IRQ we need either a FIFO or DMA for
5134 * async command support.
5135 */
5136 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5137 dev->write_subdev = s;
5138 s->subdev_flags |= SDF_CMD_WRITE;
5139 s->len_chanlist = s->n_chan;
5140 s->do_cmdtest = ni_ao_cmdtest;
5141 s->do_cmd = ni_ao_cmd;
5142 s->cancel = ni_ao_reset;
5143 if (!devpriv->is_m_series)
5144 s->munge = ni_ao_munge;
5145
5146 if (devpriv->mite)
5147 s->async_dma_dir = DMA_TO_DEVICE;
5148 }
5149
5150 if (devpriv->is_67xx)
5151 init_ao_67xx(dev, s);
5152
5153 /* reset the analog output configuration */
5154 ni_ao_reset(dev, s);
5155 } else {
5156 s->type = COMEDI_SUBD_UNUSED;
5157 }
5158
5159 /* Digital I/O subdevice */
5160 s = &dev->subdevices[NI_DIO_SUBDEV];
5161 s->type = COMEDI_SUBD_DIO;
5162 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5163 s->n_chan = board->has_32dio_chan ? 32 : 8;
5164 s->maxdata = 1;
5165 s->range_table = &range_digital;
5166 if (devpriv->is_m_series) {
5167 s->subdev_flags |= SDF_LSAMPL;
5168 s->insn_bits = ni_m_series_dio_insn_bits;
5169 s->insn_config = ni_m_series_dio_insn_config;
5170 if (dev->irq) {
5171 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5172 s->len_chanlist = s->n_chan;
5173 s->do_cmdtest = ni_cdio_cmdtest;
5174 s->do_cmd = ni_cdio_cmd;
5175 s->cancel = ni_cdio_cancel;
5176
5177 /* M-series boards use DMA */
5178 s->async_dma_dir = DMA_BIDIRECTIONAL;
5179 }
5180
5181 /* reset DIO and set all channels to inputs */
5182 ni_writel(dev, NI_M_CDO_CMD_RESET |
5183 NI_M_CDI_CMD_RESET,
5184 NI_M_CDIO_CMD_REG);
5185 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5186 } else {
5187 s->insn_bits = ni_dio_insn_bits;
5188 s->insn_config = ni_dio_insn_config;
5189
5190 /* set all channels to inputs */
5191 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5192 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5193 }
5194
5195 /* 8255 device */
5196 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5197 if (board->has_8255) {
5198 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A);
5199 if (ret)
5200 return ret;
5201 } else {
5202 s->type = COMEDI_SUBD_UNUSED;
5203 }
5204
5205 /* formerly general purpose counter/timer device, but no longer used */
5206 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5207 s->type = COMEDI_SUBD_UNUSED;
5208
5209 /* Calibration subdevice */
5210 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5211 s->type = COMEDI_SUBD_CALIB;
5212 s->subdev_flags = SDF_INTERNAL;
5213 s->n_chan = 1;
5214 s->maxdata = 0;
5215 if (devpriv->is_m_series) {
5216 /* internal PWM output used for AI nonlinearity calibration */
5217 s->insn_config = ni_m_series_pwm_config;
5218
5219 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5220 } else if (devpriv->is_6143) {
5221 /* internal PWM output used for AI nonlinearity calibration */
5222 s->insn_config = ni_6143_pwm_config;
5223 } else {
5224 s->subdev_flags |= SDF_WRITABLE;
5225 s->insn_read = ni_calib_insn_read;
5226 s->insn_write = ni_calib_insn_write;
5227
5228 /* setup the caldacs and find the real n_chan and maxdata */
5229 caldac_setup(dev, s);
5230 }
5231
5232 /* EEPROM subdevice */
5233 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5234 s->type = COMEDI_SUBD_MEMORY;
5235 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5236 s->maxdata = 0xff;
5237 if (devpriv->is_m_series) {
5238 s->n_chan = M_SERIES_EEPROM_SIZE;
5239 s->insn_read = ni_m_series_eeprom_insn_read;
5240 } else {
5241 s->n_chan = 512;
5242 s->insn_read = ni_eeprom_insn_read;
5243 }
5244
5245 /* Digital I/O (PFI) subdevice */
5246 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5247 s->type = COMEDI_SUBD_DIO;
5248 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5249 s->maxdata = 1;
5250 if (devpriv->is_m_series) {
5251 s->n_chan = 16;
5252 s->insn_bits = ni_pfi_insn_bits;
5253
5254 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5255 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5256 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5257 NI_M_PFI_OUT_SEL_REG(i));
5258 }
5259 } else {
5260 s->n_chan = 10;
5261 }
5262 s->insn_config = ni_pfi_insn_config;
5263
5264 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5265
5266 /* cs5529 calibration adc */
5267 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5268 if (devpriv->is_67xx) {
5269 s->type = COMEDI_SUBD_AI;
5270 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5271 /* one channel for each analog output channel */
5272 s->n_chan = board->n_aochan;
5273 s->maxdata = (1 << 16) - 1;
5274 s->range_table = &range_unknown; /* XXX */
5275 s->insn_read = cs5529_ai_insn_read;
5276 s->insn_config = NULL;
5277 init_cs5529(dev);
5278 } else {
5279 s->type = COMEDI_SUBD_UNUSED;
5280 }
5281
5282 /* Serial */
5283 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5284 s->type = COMEDI_SUBD_SERIAL;
5285 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5286 s->n_chan = 1;
5287 s->maxdata = 0xff;
5288 s->insn_config = ni_serial_insn_config;
5289 devpriv->serial_interval_ns = 0;
5290 devpriv->serial_hw_mode = 0;
5291
5292 /* RTSI */
5293 s = &dev->subdevices[NI_RTSI_SUBDEV];
5294 s->type = COMEDI_SUBD_DIO;
5295 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5296 s->n_chan = 8;
5297 s->maxdata = 1;
5298 s->insn_bits = ni_rtsi_insn_bits;
5299 s->insn_config = ni_rtsi_insn_config;
5300 ni_rtsi_init(dev);
5301
5302 /* allocate and initialize the gpct counter device */
5303 devpriv->counter_dev = ni_gpct_device_construct(dev,
5304 ni_gpct_write_register,
5305 ni_gpct_read_register,
5306 (devpriv->is_m_series)
5307 ? ni_gpct_variant_m_series
5308 : ni_gpct_variant_e_series,
5309 NUM_GPCT);
5310 if (!devpriv->counter_dev)
5311 return -ENOMEM;
5312
5313 /* Counter (gpct) subdevices */
5314 for (i = 0; i < NUM_GPCT; ++i) {
5315 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5316
5317 /* setup and initialize the counter */
5318 gpct->chip_index = 0;
5319 gpct->counter_index = i;
5320 ni_tio_init_counter(gpct);
5321
5322 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5323 s->type = COMEDI_SUBD_COUNTER;
5324 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5325 s->n_chan = 3;
5326 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5327 : 0x00ffffff;
5328 s->insn_read = ni_tio_insn_read;
5329 s->insn_write = ni_tio_insn_read;
5330 s->insn_config = ni_tio_insn_config;
5331 #ifdef PCIDMA
5332 if (dev->irq && devpriv->mite) {
5333 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5334 s->len_chanlist = 1;
5335 s->do_cmdtest = ni_tio_cmdtest;
5336 s->do_cmd = ni_gpct_cmd;
5337 s->cancel = ni_gpct_cancel;
5338
5339 s->async_dma_dir = DMA_BIDIRECTIONAL;
5340 }
5341 #endif
5342 s->private = gpct;
5343 }
5344
5345 /* Frequency output subdevice */
5346 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5347 s->type = COMEDI_SUBD_COUNTER;
5348 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5349 s->n_chan = 1;
5350 s->maxdata = 0xf;
5351 s->insn_read = ni_freq_out_insn_read;
5352 s->insn_write = ni_freq_out_insn_write;
5353 s->insn_config = ni_freq_out_insn_config;
5354
5355 if (dev->irq) {
5356 ni_stc_writew(dev,
5357 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5358 (NISTC_INT_CTRL_3PIN_INT & 0) |
5359 NISTC_INT_CTRL_INTA_ENA |
5360 NISTC_INT_CTRL_INTB_ENA |
5361 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5362 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5363 NISTC_INT_CTRL_REG);
5364 }
5365
5366 /* DMA setup */
5367 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5368 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5369
5370 if (devpriv->is_6xxx) {
5371 ni_writeb(dev, 0, Magic_611x);
5372 } else if (devpriv->is_m_series) {
5373 int channel;
5374
5375 for (channel = 0; channel < board->n_aochan; ++channel) {
5376 ni_writeb(dev, 0xf,
5377 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5378 ni_writeb(dev, 0x0,
5379 NI_M_AO_REF_ATTENUATION_REG(channel));
5380 }
5381 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5382 }
5383
5384 return 0;
5385 }
5386
5387 static void mio_common_detach(struct comedi_device *dev)
5388 {
5389 struct ni_private *devpriv = dev->private;
5390
5391 if (devpriv) {
5392 if (devpriv->counter_dev)
5393 ni_gpct_device_destroy(devpriv->counter_dev);
5394 }
5395 }
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