drivers/staging/comedi/drivers/ni_tio_internal.h

   1 /*
   2     drivers/ni_tio_internal.h
   3     Header file for NI general purpose counter support code (ni_tio.c and
   4     ni_tiocmd.c)
   5
   6     COMEDI - Linux Control and Measurement Device Interface
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 #ifndef _COMEDI_NI_TIO_INTERNAL_H
  25 #define _COMEDI_NI_TIO_INTERNAL_H
  26
  27 #include "ni_tio.h"
  28
  29 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
  30         counter_index)
  31 {
  32         switch (counter_index) {
  33         case 0:
  34                 return NITIO_G0_Autoincrement_Reg;
  35                 break;
  36         case 1:
  37                 return NITIO_G1_Autoincrement_Reg;
  38                 break;
  39         case 2:
  40                 return NITIO_G2_Autoincrement_Reg;
  41                 break;
  42         case 3:
  43                 return NITIO_G3_Autoincrement_Reg;
  44                 break;
  45         default:
  46                 BUG();
  47                 break;
  48         }
  49         return 0;
  50 }
  51
  52 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
  53 {
  54         switch (counter_index) {
  55         case 0:
  56                 return NITIO_G0_Command_Reg;
  57                 break;
  58         case 1:
  59                 return NITIO_G1_Command_Reg;
  60                 break;
  61         case 2:
  62                 return NITIO_G2_Command_Reg;
  63                 break;
  64         case 3:
  65                 return NITIO_G3_Command_Reg;
  66                 break;
  67         default:
  68                 BUG();
  69                 break;
  70         }
  71         return 0;
  72 }
  73
  74 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
  75         counter_index)
  76 {
  77         switch (counter_index) {
  78         case 0:
  79                 return NITIO_G0_Counting_Mode_Reg;
  80                 break;
  81         case 1:
  82                 return NITIO_G1_Counting_Mode_Reg;
  83                 break;
  84         case 2:
  85                 return NITIO_G2_Counting_Mode_Reg;
  86                 break;
  87         case 3:
  88                 return NITIO_G3_Counting_Mode_Reg;
  89                 break;
  90         default:
  91                 BUG();
  92                 break;
  93         }
  94         return 0;
  95 }
  96
  97 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
  98         counter_index)
  99 {
 100         switch (counter_index) {
 101         case 0:
 102                 return NITIO_G0_Input_Select_Reg;
 103                 break;
 104         case 1:
 105                 return NITIO_G1_Input_Select_Reg;
 106                 break;
 107         case 2:
 108                 return NITIO_G2_Input_Select_Reg;
 109                 break;
 110         case 3:
 111                 return NITIO_G3_Input_Select_Reg;
 112                 break;
 113         default:
 114                 BUG();
 115                 break;
 116         }
 117         return 0;
 118 }
 119
 120 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
 121         counter_index)
 122 {
 123         switch (counter_index) {
 124         case 0:
 125         case 1:
 126                 return NITIO_G01_Joint_Reset_Reg;
 127                 break;
 128         case 2:
 129         case 3:
 130                 return NITIO_G23_Joint_Reset_Reg;
 131                 break;
 132         default:
 133                 BUG();
 134                 break;
 135         }
 136         return 0;
 137 }
 138
 139 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
 140         counter_index)
 141 {
 142         switch (counter_index) {
 143         case 0:
 144         case 1:
 145                 return NITIO_G01_Joint_Status1_Reg;
 146                 break;
 147         case 2:
 148         case 3:
 149                 return NITIO_G23_Joint_Status1_Reg;
 150                 break;
 151         default:
 152                 BUG();
 153                 break;
 154         }
 155         return 0;
 156 }
 157
 158 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
 159         counter_index)
 160 {
 161         switch (counter_index) {
 162         case 0:
 163         case 1:
 164                 return NITIO_G01_Joint_Status2_Reg;
 165                 break;
 166         case 2:
 167         case 3:
 168                 return NITIO_G23_Joint_Status2_Reg;
 169                 break;
 170         default:
 171                 BUG();
 172                 break;
 173         }
 174         return 0;
 175 }
 176
 177 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
 178 {
 179         switch (counter_index) {
 180         case 0:
 181         case 1:
 182                 return NITIO_G01_Status_Reg;
 183                 break;
 184         case 2:
 185         case 3:
 186                 return NITIO_G23_Status_Reg;
 187                 break;
 188         default:
 189                 BUG();
 190                 break;
 191         }
 192         return 0;
 193 }
 194
 195 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
 196 {
 197         switch (counter_index) {
 198         case 0:
 199                 return NITIO_G0_LoadA_Reg;
 200                 break;
 201         case 1:
 202                 return NITIO_G1_LoadA_Reg;
 203                 break;
 204         case 2:
 205                 return NITIO_G2_LoadA_Reg;
 206                 break;
 207         case 3:
 208                 return NITIO_G3_LoadA_Reg;
 209                 break;
 210         default:
 211                 BUG();
 212                 break;
 213         }
 214         return 0;
 215 }
 216
 217 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
 218 {
 219         switch (counter_index) {
 220         case 0:
 221                 return NITIO_G0_LoadB_Reg;
 222                 break;
 223         case 1:
 224                 return NITIO_G1_LoadB_Reg;
 225                 break;
 226         case 2:
 227                 return NITIO_G2_LoadB_Reg;
 228                 break;
 229         case 3:
 230                 return NITIO_G3_LoadB_Reg;
 231                 break;
 232         default:
 233                 BUG();
 234                 break;
 235         }
 236         return 0;
 237 }
 238
 239 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
 240 {
 241         switch (counter_index) {
 242         case 0:
 243                 return NITIO_G0_Mode_Reg;
 244                 break;
 245         case 1:
 246                 return NITIO_G1_Mode_Reg;
 247                 break;
 248         case 2:
 249                 return NITIO_G2_Mode_Reg;
 250                 break;
 251         case 3:
 252                 return NITIO_G3_Mode_Reg;
 253                 break;
 254         default:
 255                 BUG();
 256                 break;
 257         }
 258         return 0;
 259 }
 260
 261 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
 262 {
 263         switch (counter_index) {
 264         case 0:
 265                 return NITIO_G0_SW_Save_Reg;
 266                 break;
 267         case 1:
 268                 return NITIO_G1_SW_Save_Reg;
 269                 break;
 270         case 2:
 271                 return NITIO_G2_SW_Save_Reg;
 272                 break;
 273         case 3:
 274                 return NITIO_G3_SW_Save_Reg;
 275                 break;
 276         default:
 277                 BUG();
 278                 break;
 279         }
 280         return 0;
 281 }
 282
 283 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
 284 {
 285         switch (counter_index) {
 286         case 0:
 287                 return NITIO_G0_Second_Gate_Reg;
 288                 break;
 289         case 1:
 290                 return NITIO_G1_Second_Gate_Reg;
 291                 break;
 292         case 2:
 293                 return NITIO_G2_Second_Gate_Reg;
 294                 break;
 295         case 3:
 296                 return NITIO_G3_Second_Gate_Reg;
 297                 break;
 298         default:
 299                 BUG();
 300                 break;
 301         }
 302         return 0;
 303 }
 304
 305 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
 306 {
 307         switch (counter_index) {
 308         case 0:
 309                 return NITIO_G0_DMA_Config_Reg;
 310                 break;
 311         case 1:
 312                 return NITIO_G1_DMA_Config_Reg;
 313                 break;
 314         case 2:
 315                 return NITIO_G2_DMA_Config_Reg;
 316                 break;
 317         case 3:
 318                 return NITIO_G3_DMA_Config_Reg;
 319                 break;
 320         default:
 321                 BUG();
 322                 break;
 323         }
 324         return 0;
 325 }
 326
 327 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
 328 {
 329         switch (counter_index) {
 330         case 0:
 331                 return NITIO_G0_DMA_Status_Reg;
 332                 break;
 333         case 1:
 334                 return NITIO_G1_DMA_Status_Reg;
 335                 break;
 336         case 2:
 337                 return NITIO_G2_DMA_Status_Reg;
 338                 break;
 339         case 3:
 340                 return NITIO_G3_DMA_Status_Reg;
 341                 break;
 342         default:
 343                 BUG();
 344                 break;
 345         }
 346         return 0;
 347 }
 348
 349 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
 350 {
 351         switch (counter_index) {
 352         case 0:
 353                 return NITIO_G0_ABZ_Reg;
 354                 break;
 355         case 1:
 356                 return NITIO_G1_ABZ_Reg;
 357                 break;
 358         default:
 359                 BUG();
 360                 break;
 361         }
 362         return 0;
 363 }
 364
 365 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(int
 366         counter_index)
 367 {
 368         switch (counter_index) {
 369         case 0:
 370                 return NITIO_G0_Interrupt_Acknowledge_Reg;
 371                 break;
 372         case 1:
 373                 return NITIO_G1_Interrupt_Acknowledge_Reg;
 374                 break;
 375         case 2:
 376                 return NITIO_G2_Interrupt_Acknowledge_Reg;
 377                 break;
 378         case 3:
 379                 return NITIO_G3_Interrupt_Acknowledge_Reg;
 380                 break;
 381         default:
 382                 BUG();
 383                 break;
 384         }
 385         return 0;
 386 }
 387
 388 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
 389 {
 390         switch (counter_index) {
 391         case 0:
 392                 return NITIO_G0_Status_Reg;
 393                 break;
 394         case 1:
 395                 return NITIO_G1_Status_Reg;
 396                 break;
 397         case 2:
 398                 return NITIO_G2_Status_Reg;
 399                 break;
 400         case 3:
 401                 return NITIO_G3_Status_Reg;
 402                 break;
 403         default:
 404                 BUG();
 405                 break;
 406         }
 407         return 0;
 408 }
 409
 410 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(int
 411         counter_index)
 412 {
 413         switch (counter_index) {
 414         case 0:
 415                 return NITIO_G0_Interrupt_Enable_Reg;
 416                 break;
 417         case 1:
 418                 return NITIO_G1_Interrupt_Enable_Reg;
 419                 break;
 420         case 2:
 421                 return NITIO_G2_Interrupt_Enable_Reg;
 422                 break;
 423         case 3:
 424                 return NITIO_G3_Interrupt_Enable_Reg;
 425                 break;
 426         default:
 427                 BUG();
 428                 break;
 429         }
 430         return 0;
 431 }
 432
 433 enum Gi_Auto_Increment_Reg_Bits {
 434         Gi_Auto_Increment_Mask = 0xff
 435 };
 436
 437 #define Gi_Up_Down_Shift 5
 438 enum Gi_Command_Reg_Bits {
 439         Gi_Arm_Bit = 0x1,
 440         Gi_Save_Trace_Bit = 0x2,
 441         Gi_Load_Bit = 0x4,
 442         Gi_Disarm_Bit = 0x10,
 443         Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
 444         Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
 445         Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
 446         Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
 447         Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
 448         Gi_Write_Switch_Bit = 0x80,
 449         Gi_Synchronize_Gate_Bit = 0x100,
 450         Gi_Little_Big_Endian_Bit = 0x200,
 451         Gi_Bank_Switch_Start_Bit = 0x400,
 452         Gi_Bank_Switch_Mode_Bit = 0x800,
 453         Gi_Bank_Switch_Enable_Bit = 0x1000,
 454         Gi_Arm_Copy_Bit = 0x2000,
 455         Gi_Save_Trace_Copy_Bit = 0x4000,
 456         Gi_Disarm_Copy_Bit = 0x8000
 457 };
 458
 459 #define Gi_Index_Phase_Bitshift 5
 460 #define Gi_HW_Arm_Select_Shift 8
 461 enum Gi_Counting_Mode_Reg_Bits {
 462         Gi_Counting_Mode_Mask = 0x7,
 463         Gi_Counting_Mode_Normal_Bits = 0x0,
 464         Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
 465         Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
 466         Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
 467         Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
 468         Gi_Counting_Mode_Sync_Source_Bits = 0x6,
 469         Gi_Index_Mode_Bit = 0x10,
 470         Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
 471         Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
 472         Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
 473         Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
 474         Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
 475         Gi_HW_Arm_Enable_Bit = 0x80,    /* from m-series example code, not documented in 660x register level manual */
 476         Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,     /* from m-series example code, not documented in 660x register level manual */
 477         Gi_660x_Prescale_X8_Bit = 0x1000,
 478         Gi_M_Series_Prescale_X8_Bit = 0x2000,
 479         Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
 480         /* must be set for clocks over 40MHz, which includes synchronous counting and quadrature modes */
 481         Gi_660x_Alternate_Sync_Bit = 0x2000,
 482         Gi_M_Series_Alternate_Sync_Bit = 0x4000,
 483         Gi_660x_Prescale_X2_Bit = 0x4000,       /* from m-series example code, not documented in 660x register level manual */
 484         Gi_M_Series_Prescale_X2_Bit = 0x8000,
 485 };
 486
 487 #define Gi_Source_Select_Shift 2
 488 #define Gi_Gate_Select_Shift 7
 489 enum Gi_Input_Select_Bits {
 490         Gi_Read_Acknowledges_Irq = 0x1, /*  not present on 660x */
 491         Gi_Write_Acknowledges_Irq = 0x2,        /*  not present on 660x */
 492         Gi_Source_Select_Mask = 0x7c,
 493         Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
 494         Gi_Gate_Select_Load_Source_Bit = 0x1000,
 495         Gi_Or_Gate_Bit = 0x2000,
 496         Gi_Output_Polarity_Bit = 0x4000,        /* set to invert */
 497         Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
 498 };
 499
 500 enum Gi_Mode_Bits {
 501         Gi_Gating_Mode_Mask = 0x3,
 502         Gi_Gating_Disabled_Bits = 0x0,
 503         Gi_Level_Gating_Bits = 0x1,
 504         Gi_Rising_Edge_Gating_Bits = 0x2,
 505         Gi_Falling_Edge_Gating_Bits = 0x3,
 506         Gi_Gate_On_Both_Edges_Bit = 0x4,        /* used in conjunction with rising edge gating mode */
 507         Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
 508         Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
 509         Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
 510         Gi_Edge_Gate_Starts_Bits = 0x10,
 511         Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
 512         Gi_Stop_Mode_Mask = 0x60,
 513         Gi_Stop_on_Gate_Bits = 0x00,
 514         Gi_Stop_on_Gate_or_TC_Bits = 0x20,
 515         Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
 516         Gi_Load_Source_Select_Bit = 0x80,
 517         Gi_Output_Mode_Mask = 0x300,
 518         Gi_Output_TC_Pulse_Bits = 0x100,
 519         Gi_Output_TC_Toggle_Bits = 0x200,
 520         Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
 521         Gi_Counting_Once_Mask = 0xc00,
 522         Gi_No_Hardware_Disarm_Bits = 0x000,
 523         Gi_Disarm_at_TC_Bits = 0x400,
 524         Gi_Disarm_at_Gate_Bits = 0x800,
 525         Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
 526         Gi_Loading_On_TC_Bit = 0x1000,
 527         Gi_Gate_Polarity_Bit = 0x2000,
 528         Gi_Loading_On_Gate_Bit = 0x4000,
 529         Gi_Reload_Source_Switching_Bit = 0x8000
 530 };
 531
 532 #define Gi_Second_Gate_Select_Shift 7
 533 /*FIXME: m-series has a second gate subselect bit */
 534 /*FIXME: m-series second gate sources are undocumented (by NI)*/
 535 enum Gi_Second_Gate_Bits {
 536         Gi_Second_Gate_Mode_Bit = 0x1,
 537         Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
 538         Gi_Second_Gate_Polarity_Bit = 0x2000,
 539         Gi_Second_Gate_Subselect_Bit = 0x4000,  /* m-series only */
 540         Gi_Source_Subselect_Bit = 0x8000        /* m-series only */
 541 };
 542 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
 543 {
 544         return (second_gate_select << Gi_Second_Gate_Select_Shift) &
 545                 Gi_Second_Gate_Select_Mask;
 546 }
 547
 548 enum Gxx_Status_Bits {
 549         G0_Save_Bit = 0x1,
 550         G1_Save_Bit = 0x2,
 551         G0_Counting_Bit = 0x4,
 552         G1_Counting_Bit = 0x8,
 553         G0_Next_Load_Source_Bit = 0x10,
 554         G1_Next_Load_Source_Bit = 0x20,
 555         G0_Stale_Data_Bit = 0x40,
 556         G1_Stale_Data_Bit = 0x80,
 557         G0_Armed_Bit = 0x100,
 558         G1_Armed_Bit = 0x200,
 559         G0_No_Load_Between_Gates_Bit = 0x400,
 560         G1_No_Load_Between_Gates_Bit = 0x800,
 561         G0_TC_Error_Bit = 0x1000,
 562         G1_TC_Error_Bit = 0x2000,
 563         G0_Gate_Error_Bit = 0x4000,
 564         G1_Gate_Error_Bit = 0x8000
 565 };
 566 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
 567 {
 568         if (counter_index % 2)
 569                 return G1_Counting_Bit;
 570         return G0_Counting_Bit;
 571 }
 572 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
 573 {
 574         if (counter_index % 2)
 575                 return G1_Armed_Bit;
 576         return G0_Armed_Bit;
 577 }
 578 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
 579         counter_index)
 580 {
 581         if (counter_index % 2)
 582                 return G1_Next_Load_Source_Bit;
 583         return G0_Next_Load_Source_Bit;
 584 }
 585 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
 586 {
 587         if (counter_index % 2)
 588                 return G1_Stale_Data_Bit;
 589         return G0_Stale_Data_Bit;
 590 }
 591 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
 592 {
 593         if (counter_index % 2)
 594                 return G1_TC_Error_Bit;
 595         return G0_TC_Error_Bit;
 596 }
 597 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
 598 {
 599         if (counter_index % 2)
 600                 return G1_Gate_Error_Bit;
 601         return G0_Gate_Error_Bit;
 602 }
 603
 604 /* joint reset register bits */
 605 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
 606 {
 607         return 0x1 << (2 + (counter_index % 2));
 608 }
 609
 610 enum Gxx_Joint_Status2_Bits {
 611         G0_Output_Bit = 0x1,
 612         G1_Output_Bit = 0x2,
 613         G0_HW_Save_Bit = 0x1000,
 614         G1_HW_Save_Bit = 0x2000,
 615         G0_Permanent_Stale_Bit = 0x4000,
 616         G1_Permanent_Stale_Bit = 0x8000
 617 };
 618 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
 619         counter_index)
 620 {
 621         if (counter_index % 2)
 622                 return G1_Permanent_Stale_Bit;
 623         return G0_Permanent_Stale_Bit;
 624 }
 625
 626 enum Gi_DMA_Config_Reg_Bits {
 627         Gi_DMA_Enable_Bit = 0x1,
 628         Gi_DMA_Write_Bit = 0x2,
 629         Gi_DMA_Int_Bit = 0x4
 630 };
 631
 632 enum Gi_DMA_Status_Reg_Bits {
 633         Gi_DMA_Readbank_Bit = 0x2000,
 634         Gi_DRQ_Error_Bit = 0x4000,
 635         Gi_DRQ_Status_Bit = 0x8000
 636 };
 637
 638 enum G02_Interrupt_Acknowledge_Bits {
 639         G0_Gate_Error_Confirm_Bit = 0x20,
 640         G0_TC_Error_Confirm_Bit = 0x40
 641 };
 642 enum G13_Interrupt_Acknowledge_Bits {
 643         G1_Gate_Error_Confirm_Bit = 0x2,
 644         G1_TC_Error_Confirm_Bit = 0x4
 645 };
 646 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
 647 {
 648         if (counter_index % 2)
 649                 return G1_Gate_Error_Confirm_Bit;
 650         return G0_Gate_Error_Confirm_Bit;
 651 }
 652 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
 653 {
 654         if (counter_index % 2)
 655                 return G1_TC_Error_Confirm_Bit;
 656         return G0_TC_Error_Confirm_Bit;
 657 }
 658
 659 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
 660 enum Gxx_Interrupt_Acknowledge_Bits {
 661         Gi_TC_Interrupt_Ack_Bit = 0x4000,
 662         Gi_Gate_Interrupt_Ack_Bit = 0x8000
 663 };
 664
 665 enum Gi_Status_Bits {
 666         Gi_Gate_Interrupt_Bit = 0x4,
 667         Gi_TC_Bit = 0x8,
 668         Gi_Interrupt_Bit = 0x8000
 669 };
 670
 671 enum G02_Interrupt_Enable_Bits {
 672         G0_TC_Interrupt_Enable_Bit = 0x40,
 673         G0_Gate_Interrupt_Enable_Bit = 0x100
 674 };
 675 enum G13_Interrupt_Enable_Bits {
 676         G1_TC_Interrupt_Enable_Bit = 0x200,
 677         G1_Gate_Interrupt_Enable_Bit = 0x400
 678 };
 679 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
 680 {
 681         unsigned bit;
 682
 683         if (counter_index % 2) {
 684                 bit = G1_Gate_Interrupt_Enable_Bit;
 685         } else {
 686                 bit = G0_Gate_Interrupt_Enable_Bit;
 687         }
 688         return bit;
 689 }
 690
 691 static inline void write_register(struct ni_gpct *counter, unsigned bits,
 692         enum ni_gpct_register reg)
 693 {
 694         BUG_ON(reg >= NITIO_Num_Registers);
 695         counter->counter_dev->write_register(counter, bits, reg);
 696 }
 697
 698 static inline unsigned read_register(struct ni_gpct *counter,
 699         enum ni_gpct_register reg)
 700 {
 701         BUG_ON(reg >= NITIO_Num_Registers);
 702         return counter->counter_dev->read_register(counter, reg);
 703 }
 704
 705 static inline int ni_tio_counting_mode_registers_present(
 706         const struct ni_gpct_device *counter_dev)
 707 {
 708         switch (counter_dev->variant) {
 709         case ni_gpct_variant_e_series:
 710                 return 0;
 711                 break;
 712         case ni_gpct_variant_m_series:
 713         case ni_gpct_variant_660x:
 714                 return 1;
 715                 break;
 716         default:
 717                 BUG();
 718                 break;
 719         }
 720         return 0;
 721 }
 722
 723 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
 724         enum ni_gpct_register register_index, unsigned bit_mask,
 725         unsigned bit_values, unsigned transient_bit_values)
 726 {
 727         struct ni_gpct_device *counter_dev = counter->counter_dev;
 728         unsigned long flags;
 729
 730         BUG_ON(register_index >= NITIO_Num_Registers);
 731         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 732         counter_dev->regs[register_index] &= ~bit_mask;
 733         counter_dev->regs[register_index] |= (bit_values & bit_mask);
 734         write_register(counter,
 735                 counter_dev->regs[register_index] | transient_bit_values,
 736                 register_index);
 737         mmiowb();
 738         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 739 }
 740
 741 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 742 twiddled in interrupt context, or whose software copy may be read in interrupt context.
 743 */
 744 static inline void ni_tio_set_bits(struct ni_gpct *counter,
 745         enum ni_gpct_register register_index, unsigned bit_mask,
 746         unsigned bit_values)
 747 {
 748         ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
 749                 0x0);
 750 }
 751
 752 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
 753 whose bits might be modified in interrupt context, or whose software copy
 754 might need to be read in interrupt context.
 755 */
 756 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
 757         enum ni_gpct_register register_index)
 758 {
 759         struct ni_gpct_device *counter_dev = counter->counter_dev;
 760         unsigned long flags;
 761         unsigned value;
 762
 763         BUG_ON(register_index >= NITIO_Num_Registers);
 764         spin_lock_irqsave(&counter_dev->regs_lock, flags);
 765         value = counter_dev->regs[register_index];
 766         spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 767         return value;
 768 }
 769
 770 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
 771 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 772         unsigned int gate_source);
 773
 774 #endif /* _COMEDI_NI_TIO_INTERNAL_H */