2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
109 #include "comedi_fc.h"
113 /*======================================================================
114 Driver specific stuff (tunable)
115 ======================================================================*/
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
130 /* tuning for ai/ao instruction done polling */
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
144 /*======================================================================
146 ======================================================================*/
148 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
149 #define RTD_CLOCK_BASE 125 /* clock period in ns */
151 /* Note: these speed are slower than the spec, but fit the counter resolution*/
152 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
153 /* max speed if we don't have to wait for settling */
154 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
156 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
157 /* min speed when only 1 channel (no burst counter) */
158 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
160 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
161 #define DMA_MODE_BITS (\
162 PLX_LOCAL_BUS_16_WIDE_BITS \
163 | PLX_DMA_EN_READYIN_BIT \
164 | PLX_DMA_LOCAL_BURST_EN_BIT \
166 | PLX_DMA_INTR_PCI_BIT \
167 | PLX_LOCAL_ADDR_CONST_BIT \
168 | PLX_DEMAND_MODE_BIT)
170 #define DMA_TRANSFER_BITS (\
171 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
172 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
173 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
175 /*======================================================================
176 Comedi specific stuff
177 ======================================================================*/
180 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
182 static const struct comedi_lrange rtd_ai_7520_range
= {
184 /* +-5V input range gain steps */
191 /* +-10V input range gain steps */
196 BIP_RANGE(10.0 / 16),
197 BIP_RANGE(10.0 / 32),
198 /* +10V input range gain steps */
203 UNI_RANGE(10.0 / 16),
204 UNI_RANGE(10.0 / 32),
208 /* PCI4520 has two more gains (6 more entries) */
209 static const struct comedi_lrange rtd_ai_4520_range
= {
211 /* +-5V input range gain steps */
219 BIP_RANGE(5.0 / 128),
220 /* +-10V input range gain steps */
225 BIP_RANGE(10.0 / 16),
226 BIP_RANGE(10.0 / 32),
227 BIP_RANGE(10.0 / 64),
228 BIP_RANGE(10.0 / 128),
229 /* +10V input range gain steps */
234 UNI_RANGE(10.0 / 16),
235 UNI_RANGE(10.0 / 32),
236 UNI_RANGE(10.0 / 64),
237 UNI_RANGE(10.0 / 128),
241 /* Table order matches range values */
242 static const struct comedi_lrange rtd_ao_range
= {
254 int range10Start
; /* start of +-10V range */
255 int rangeUniStart
; /* start of +10V range */
256 const struct comedi_lrange
*ai_range
;
259 static const struct rtdBoard rtd520Boards
[] = {
265 .ai_range
= &rtd_ai_7520_range
,
271 .ai_range
= &rtd_ai_4520_range
,
276 This structure is for data unique to this hardware driver.
277 This is also unique for each board in the system.
280 /* memory mapped board structures */
285 long aiCount
; /* total transfer size (samples) */
286 int transCount
; /* # to transfer data. 0->1/2FIFO */
287 int flags
; /* flag event modes */
289 /* channel list info */
290 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
291 unsigned char chanBipolar
[RTD_MAX_CHANLIST
/ 8]; /* bit array */
294 unsigned int aoValue
[2]; /* Used for AO read back */
296 /* timer gate (when enabled) */
297 u8 utcGate
[4]; /* 1 extra allows simple range check */
299 /* shadow registers affect other registers, but can't be read back */
300 /* The macros below update these on writes */
301 u16 intMask
; /* interrupt mask */
302 u16 intClearMask
; /* interrupt clear mask */
303 u8 utcCtrl
[4]; /* crtl mode for 3 utc + read back */
304 u8 dioStatus
; /* could be read back (dio0Ctrl) */
308 /* bit defines for "flags" */
309 #define SEND_EOS 0x01 /* send End Of Scan events */
310 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
311 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
313 /* Macros for accessing channel list bit array */
314 #define CHAN_ARRAY_TEST(array, index) \
315 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
316 #define CHAN_ARRAY_SET(array, index) \
317 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
318 #define CHAN_ARRAY_CLEAR(array, index) \
319 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
322 Given a desired period and the clock period (both in ns),
323 return the proper counter value (divider-1).
324 Sets the original period to be the true value.
325 Note: you have to check if the value is larger than the counter range!
327 static int rtd_ns_to_timer_base(unsigned int *nanosec
,
328 int round_mode
, int base
)
332 switch (round_mode
) {
333 case TRIG_ROUND_NEAREST
:
335 divider
= (*nanosec
+ base
/ 2) / base
;
337 case TRIG_ROUND_DOWN
:
338 divider
= (*nanosec
) / base
;
341 divider
= (*nanosec
+ base
- 1) / base
;
345 divider
= 2; /* min is divide by 2 */
347 /* Note: we don't check for max, because different timers
348 have different ranges */
350 *nanosec
= base
* divider
;
351 return divider
- 1; /* countdown is divisor+1 */
355 Given a desired period (in ns),
356 return the proper counter value (divider-1) for the internal clock.
357 Sets the original period to be the true value.
359 static int rtd_ns_to_timer(unsigned int *ns
, int round_mode
)
361 return rtd_ns_to_timer_base(ns
, round_mode
, RTD_CLOCK_BASE
);
365 Convert a single comedi channel-gain entry to a RTD520 table entry
367 static unsigned short rtdConvertChanGain(struct comedi_device
*dev
,
368 unsigned int comediChan
, int chanIndex
)
369 { /* index in channel list */
370 const struct rtdBoard
*thisboard
= comedi_board(dev
);
371 struct rtdPrivate
*devpriv
= dev
->private;
372 unsigned int chan
, range
, aref
;
373 unsigned short r
= 0;
375 chan
= CR_CHAN(comediChan
);
376 range
= CR_RANGE(comediChan
);
377 aref
= CR_AREF(comediChan
);
381 /* Note: we also setup the channel list bipolar flag array */
382 if (range
< thisboard
->range10Start
) {
385 r
|= (range
& 0x7) << 4;
386 CHAN_ARRAY_SET(devpriv
->chanBipolar
, chanIndex
);
387 } else if (range
< thisboard
->rangeUniStart
) {
390 r
|= ((range
- thisboard
->range10Start
) & 0x7) << 4;
391 CHAN_ARRAY_SET(devpriv
->chanBipolar
, chanIndex
);
395 r
|= ((range
- thisboard
->rangeUniStart
) & 0x7) << 4;
396 CHAN_ARRAY_CLEAR(devpriv
->chanBipolar
, chanIndex
);
400 case AREF_GROUND
: /* on-board ground */
404 r
|= 0x80; /* ref external analog common */
408 r
|= 0x400; /* differential inputs */
411 case AREF_OTHER
: /* ??? */
414 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
415 chan, range, aref, r); */
420 Setup the channel-gain table from a comedi list
422 static void rtd_load_channelgain_list(struct comedi_device
*dev
,
423 unsigned int n_chan
, unsigned int *list
)
425 struct rtdPrivate
*devpriv
= dev
->private;
427 if (n_chan
> 1) { /* setup channel gain table */
430 writel(0, devpriv
->las0
+ LAS0_CGT_CLEAR
);
431 writel(1, devpriv
->las0
+ LAS0_CGT_ENABLE
);
432 for (ii
= 0; ii
< n_chan
; ii
++) {
433 writel(rtdConvertChanGain(dev
, list
[ii
], ii
),
434 devpriv
->las0
+ LAS0_CGT_WRITE
);
436 } else { /* just use the channel gain latch */
437 writel(0, devpriv
->las0
+ LAS0_CGT_ENABLE
);
438 writel(rtdConvertChanGain(dev
, list
[0], 0),
439 devpriv
->las0
+ LAS0_CGL_WRITE
);
443 /* determine fifo size by doing adc conversions until the fifo half
444 empty status flag clears */
445 static int rtd520_probe_fifo_depth(struct comedi_device
*dev
)
447 struct rtdPrivate
*devpriv
= dev
->private;
448 unsigned int chanspec
= CR_PACK(0, 0, AREF_GROUND
);
450 static const unsigned limit
= 0x2000;
451 unsigned fifo_size
= 0;
453 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
454 rtd_load_channelgain_list(dev
, 1, &chanspec
);
455 /* ADC conversion trigger source: SOFTWARE */
456 writel(0, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
457 /* convert samples */
458 for (i
= 0; i
< limit
; ++i
) {
459 unsigned fifo_status
;
460 /* trigger conversion */
461 writew(0, devpriv
->las0
+ LAS0_ADC
);
463 fifo_status
= readl(devpriv
->las0
+ LAS0_ADC
);
464 if ((fifo_status
& FS_ADC_HEMPTY
) == 0) {
470 dev_info(dev
->class_dev
, "failed to probe fifo size.\n");
473 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
474 if (fifo_size
!= 0x400 && fifo_size
!= 0x2000) {
475 dev_info(dev
->class_dev
,
476 "unexpected fifo size of %i, expected 1024 or 8192.\n",
484 "instructions" read/write data in "one-shot" or "software-triggered"
485 mode (simplest case).
486 This doesn't use interrupts.
488 Note, we don't do any settling delays. Use a instruction list to
489 select, delay, then read.
491 static int rtd_ai_rinsn(struct comedi_device
*dev
,
492 struct comedi_subdevice
*s
, struct comedi_insn
*insn
,
495 struct rtdPrivate
*devpriv
= dev
->private;
499 /* clear any old fifo data */
500 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
502 /* write channel to multiplexer and clear channel gain table */
503 rtd_load_channelgain_list(dev
, 1, &insn
->chanspec
);
505 /* ADC conversion trigger source: SOFTWARE */
506 writel(0, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
508 /* convert n samples */
509 for (n
= 0; n
< insn
->n
; n
++) {
511 /* trigger conversion */
512 writew(0, devpriv
->las0
+ LAS0_ADC
);
514 for (ii
= 0; ii
< RTD_ADC_TIMEOUT
; ++ii
) {
515 stat
= readl(devpriv
->las0
+ LAS0_ADC
);
516 if (stat
& FS_ADC_NOT_EMPTY
) /* 1 -> not empty */
520 if (ii
>= RTD_ADC_TIMEOUT
)
524 d
= readw(devpriv
->las1
+ LAS1_ADC_FIFO
);
525 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
526 d
= d
>> 3; /* low 3 bits are marker lines */
527 if (CHAN_ARRAY_TEST(devpriv
->chanBipolar
, 0))
528 /* convert to comedi unsigned data */
534 /* return the number of samples read/written */
539 Get what we know is there.... Fast!
540 This uses 1/2 the bus cycles of read_dregs (below).
542 The manual claims that we can do a lword read, but it doesn't work here.
544 static int ai_read_n(struct comedi_device
*dev
, struct comedi_subdevice
*s
,
547 struct rtdPrivate
*devpriv
= dev
->private;
550 for (ii
= 0; ii
< count
; ii
++) {
554 if (0 == devpriv
->aiCount
) { /* done */
555 d
= readw(devpriv
->las1
+ LAS1_ADC_FIFO
);
559 d
= readw(devpriv
->las1
+ LAS1_ADC_FIFO
);
560 d
= d
>> 3; /* low 3 bits are marker lines */
561 if (CHAN_ARRAY_TEST(devpriv
->chanBipolar
, s
->async
->cur_chan
)) {
562 /* convert to comedi unsigned data */
567 if (!comedi_buf_put(s
->async
, sample
))
570 if (devpriv
->aiCount
> 0) /* < 0, means read forever */
577 unknown amout of data is waiting in fifo.
579 static int ai_read_dregs(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
581 struct rtdPrivate
*devpriv
= dev
->private;
583 while (readl(devpriv
->las0
+ LAS0_ADC
) & FS_ADC_NOT_EMPTY
) {
585 s16 d
= readw(devpriv
->las1
+ LAS1_ADC_FIFO
);
587 if (0 == devpriv
->aiCount
) { /* done */
588 continue; /* read rest */
591 d
= d
>> 3; /* low 3 bits are marker lines */
592 if (CHAN_ARRAY_TEST(devpriv
->chanBipolar
, s
->async
->cur_chan
)) {
593 /* convert to comedi unsigned data */
598 if (!comedi_buf_put(s
->async
, sample
))
601 if (devpriv
->aiCount
> 0) /* < 0, means read forever */
608 Handle all rtd520 interrupts.
609 Runs atomically and is never re-entered.
610 This is a "slow handler"; other interrupts may be active.
611 The data conversion may someday happen in a "bottom half".
613 static irqreturn_t
rtd_interrupt(int irq
, /* interrupt number (ignored) */
615 { /* our data *//* cpu context (ignored) */
616 struct comedi_device
*dev
= d
;
617 struct comedi_subdevice
*s
= &dev
->subdevices
[0];
618 struct rtdPrivate
*devpriv
= dev
->private;
626 fifoStatus
= readl(devpriv
->las0
+ LAS0_ADC
);
627 /* check for FIFO full, this automatically halts the ADC! */
628 if (!(fifoStatus
& FS_ADC_NOT_FULL
)) /* 0 -> full */
631 status
= readw(devpriv
->las0
+ LAS0_IT
);
632 /* if interrupt was not caused by our board, or handled above */
636 if (status
& IRQM_ADC_ABOUT_CNT
) { /* sample count -> read FIFO */
638 * since the priority interrupt controller may have queued
639 * a sample counter interrupt, even though we have already
640 * finished, we must handle the possibility that there is
643 if (!(fifoStatus
& FS_ADC_HEMPTY
)) {
645 if (ai_read_n(dev
, s
, devpriv
->fifoLen
/ 2) < 0)
648 if (0 == devpriv
->aiCount
)
651 comedi_event(dev
, s
);
652 } else if (devpriv
->transCount
> 0) {
653 if (fifoStatus
& FS_ADC_NOT_EMPTY
) {
655 if (ai_read_n(dev
, s
, devpriv
->transCount
) < 0)
658 if (0 == devpriv
->aiCount
)
661 comedi_event(dev
, s
);
666 overrun
= readl(devpriv
->las0
+ LAS0_OVERRUN
) & 0xffff;
670 /* clear the interrupt */
671 devpriv
->intClearMask
= status
;
672 writew(devpriv
->intClearMask
, devpriv
->las0
+ LAS0_CLEAR
);
673 readw(devpriv
->las0
+ LAS0_CLEAR
);
677 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
678 s
->async
->events
|= COMEDI_CB_ERROR
;
679 devpriv
->aiCount
= 0; /* stop and don't transfer any more */
680 /* fall into transferDone */
683 /* pacer stop source: SOFTWARE */
684 writel(0, devpriv
->las0
+ LAS0_PACER_STOP
);
685 writel(0, devpriv
->las0
+ LAS0_PACER
); /* stop pacer */
686 writel(0, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
687 devpriv
->intMask
= 0;
688 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
690 if (devpriv
->aiCount
> 0) { /* there shouldn't be anything left */
691 fifoStatus
= readl(devpriv
->las0
+ LAS0_ADC
);
692 ai_read_dregs(dev
, s
); /* read anything left in FIFO */
695 s
->async
->events
|= COMEDI_CB_EOA
; /* signal end to comedi */
696 comedi_event(dev
, s
);
698 /* clear the interrupt */
699 status
= readw(devpriv
->las0
+ LAS0_IT
);
700 devpriv
->intClearMask
= status
;
701 writew(devpriv
->intClearMask
, devpriv
->las0
+ LAS0_CLEAR
);
702 readw(devpriv
->las0
+ LAS0_CLEAR
);
704 fifoStatus
= readl(devpriv
->las0
+ LAS0_ADC
);
705 overrun
= readl(devpriv
->las0
+ LAS0_OVERRUN
) & 0xffff;
711 cmdtest tests a particular command to see if it is valid.
712 Using the cmdtest ioctl, a user can create a valid cmd
713 and then have it executed by the cmd ioctl (asynchronously).
715 cmdtest returns 1,2,3,4 or 0, depending on which tests
719 static int rtd_ai_cmdtest(struct comedi_device
*dev
,
720 struct comedi_subdevice
*s
, struct comedi_cmd
*cmd
)
725 /* Step 1 : check if triggers are trivially valid */
727 err
|= cfc_check_trigger_src(&cmd
->start_src
, TRIG_NOW
);
728 err
|= cfc_check_trigger_src(&cmd
->scan_begin_src
,
729 TRIG_TIMER
| TRIG_EXT
);
730 err
|= cfc_check_trigger_src(&cmd
->convert_src
, TRIG_TIMER
| TRIG_EXT
);
731 err
|= cfc_check_trigger_src(&cmd
->scan_end_src
, TRIG_COUNT
);
732 err
|= cfc_check_trigger_src(&cmd
->stop_src
, TRIG_COUNT
| TRIG_NONE
);
737 /* Step 2a : make sure trigger sources are unique */
739 err
|= cfc_check_trigger_is_unique(cmd
->scan_begin_src
);
740 err
|= cfc_check_trigger_is_unique(cmd
->convert_src
);
741 err
|= cfc_check_trigger_is_unique(cmd
->stop_src
);
743 /* Step 2b : and mutually compatible */
748 /* Step 3: check if arguments are trivially valid */
750 err
|= cfc_check_trigger_arg_is(&cmd
->start_arg
, 0);
752 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
753 /* Note: these are time periods, not actual rates */
754 if (1 == cmd
->chanlist_len
) { /* no scanning */
755 if (cfc_check_trigger_arg_min(&cmd
->scan_begin_arg
,
757 rtd_ns_to_timer(&cmd
->scan_begin_arg
,
761 if (cfc_check_trigger_arg_max(&cmd
->scan_begin_arg
,
763 rtd_ns_to_timer(&cmd
->scan_begin_arg
,
768 if (cfc_check_trigger_arg_min(&cmd
->scan_begin_arg
,
770 rtd_ns_to_timer(&cmd
->scan_begin_arg
,
774 if (cfc_check_trigger_arg_max(&cmd
->scan_begin_arg
,
776 rtd_ns_to_timer(&cmd
->scan_begin_arg
,
782 /* external trigger */
783 /* should be level/edge, hi/lo specification here */
784 /* should specify multiple external triggers */
785 err
|= cfc_check_trigger_arg_max(&cmd
->scan_begin_arg
, 9);
788 if (cmd
->convert_src
== TRIG_TIMER
) {
789 if (1 == cmd
->chanlist_len
) { /* no scanning */
790 if (cfc_check_trigger_arg_min(&cmd
->convert_arg
,
792 rtd_ns_to_timer(&cmd
->convert_arg
,
796 if (cfc_check_trigger_arg_max(&cmd
->convert_arg
,
798 rtd_ns_to_timer(&cmd
->convert_arg
,
803 if (cfc_check_trigger_arg_min(&cmd
->convert_arg
,
805 rtd_ns_to_timer(&cmd
->convert_arg
,
809 if (cfc_check_trigger_arg_max(&cmd
->convert_arg
,
811 rtd_ns_to_timer(&cmd
->convert_arg
,
817 /* external trigger */
819 err
|= cfc_check_trigger_arg_max(&cmd
->convert_arg
, 9);
822 if (cmd
->stop_src
== TRIG_COUNT
) {
823 /* TODO check for rounding error due to counter wrap */
826 err
|= cfc_check_trigger_arg_is(&cmd
->stop_arg
, 0);
833 /* step 4: fix up any arguments */
835 if (cmd
->chanlist_len
> RTD_MAX_CHANLIST
) {
836 cmd
->chanlist_len
= RTD_MAX_CHANLIST
;
839 if (cmd
->scan_begin_src
== TRIG_TIMER
) {
840 tmp
= cmd
->scan_begin_arg
;
841 rtd_ns_to_timer(&cmd
->scan_begin_arg
,
842 cmd
->flags
& TRIG_ROUND_MASK
);
843 if (tmp
!= cmd
->scan_begin_arg
)
847 if (cmd
->convert_src
== TRIG_TIMER
) {
848 tmp
= cmd
->convert_arg
;
849 rtd_ns_to_timer(&cmd
->convert_arg
,
850 cmd
->flags
& TRIG_ROUND_MASK
);
851 if (tmp
!= cmd
->convert_arg
)
854 if (cmd
->scan_begin_src
== TRIG_TIMER
855 && (cmd
->scan_begin_arg
856 < (cmd
->convert_arg
* cmd
->scan_end_arg
))) {
857 cmd
->scan_begin_arg
=
858 cmd
->convert_arg
* cmd
->scan_end_arg
;
870 Execute a analog in command with many possible triggering options.
871 The data get stored in the async structure of the subdevice.
872 This is usually done by an interrupt handler.
873 Userland gets to the data using read calls.
875 static int rtd_ai_cmd(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
877 struct rtdPrivate
*devpriv
= dev
->private;
878 struct comedi_cmd
*cmd
= &s
->async
->cmd
;
881 /* stop anything currently running */
882 /* pacer stop source: SOFTWARE */
883 writel(0, devpriv
->las0
+ LAS0_PACER_STOP
);
884 writel(0, devpriv
->las0
+ LAS0_PACER
); /* stop pacer */
885 writel(0, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
886 devpriv
->intMask
= 0;
887 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
888 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
889 writel(0, devpriv
->las0
+ LAS0_OVERRUN
);
891 /* start configuration */
892 /* load channel list and reset CGT */
893 rtd_load_channelgain_list(dev
, cmd
->chanlist_len
, cmd
->chanlist
);
895 /* setup the common case and override if needed */
896 if (cmd
->chanlist_len
> 1) {
897 /* pacer start source: SOFTWARE */
898 writel(0, devpriv
->las0
+ LAS0_PACER_START
);
899 /* burst trigger source: PACER */
900 writel(1, devpriv
->las0
+ LAS0_BURST_START
);
901 /* ADC conversion trigger source: BURST */
902 writel(2, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
903 } else { /* single channel */
904 /* pacer start source: SOFTWARE */
905 writel(0, devpriv
->las0
+ LAS0_PACER_START
);
906 /* ADC conversion trigger source: PACER */
907 writel(1, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
909 writel((devpriv
->fifoLen
/ 2 - 1) & 0xffff, devpriv
->las0
+ LAS0_ACNT
);
911 if (TRIG_TIMER
== cmd
->scan_begin_src
) {
912 /* scan_begin_arg is in nanoseconds */
913 /* find out how many samples to wait before transferring */
914 if (cmd
->flags
& TRIG_WAKE_EOS
) {
916 * this may generate un-sustainable interrupt rates
917 * the application is responsible for doing the
920 devpriv
->transCount
= cmd
->chanlist_len
;
921 devpriv
->flags
|= SEND_EOS
;
923 /* arrange to transfer data periodically */
926 (TRANS_TARGET_PERIOD
* cmd
->chanlist_len
) /
928 if (devpriv
->transCount
< cmd
->chanlist_len
) {
929 /* transfer after each scan (and avoid 0) */
930 devpriv
->transCount
= cmd
->chanlist_len
;
931 } else { /* make a multiple of scan length */
932 devpriv
->transCount
=
933 (devpriv
->transCount
+
934 cmd
->chanlist_len
- 1)
936 devpriv
->transCount
*= cmd
->chanlist_len
;
938 devpriv
->flags
|= SEND_EOS
;
940 if (devpriv
->transCount
>= (devpriv
->fifoLen
/ 2)) {
941 /* out of counter range, use 1/2 fifo instead */
942 devpriv
->transCount
= 0;
943 devpriv
->flags
&= ~SEND_EOS
;
945 /* interrupt for each transfer */
946 writel((devpriv
->transCount
- 1) & 0xffff,
947 devpriv
->las0
+ LAS0_ACNT
);
949 } else { /* unknown timing, just use 1/2 FIFO */
950 devpriv
->transCount
= 0;
951 devpriv
->flags
&= ~SEND_EOS
;
953 /* pacer clock source: INTERNAL 8MHz */
954 writel(1, devpriv
->las0
+ LAS0_PACER_SELECT
);
955 /* just interrupt, don't stop */
956 writel(1, devpriv
->las0
+ LAS0_ACNT_STOP_ENABLE
);
958 /* BUG??? these look like enumerated values, but they are bit fields */
960 /* First, setup when to stop */
961 switch (cmd
->stop_src
) {
962 case TRIG_COUNT
: /* stop after N scans */
963 devpriv
->aiCount
= cmd
->stop_arg
* cmd
->chanlist_len
;
964 if ((devpriv
->transCount
> 0)
965 && (devpriv
->transCount
> devpriv
->aiCount
)) {
966 devpriv
->transCount
= devpriv
->aiCount
;
970 case TRIG_NONE
: /* stop when cancel is called */
971 devpriv
->aiCount
= -1; /* read forever */
976 switch (cmd
->scan_begin_src
) {
977 case TRIG_TIMER
: /* periodic scanning */
978 timer
= rtd_ns_to_timer(&cmd
->scan_begin_arg
,
980 /* set PACER clock */
981 writel(timer
& 0xffffff, devpriv
->las0
+ LAS0_PCLK
);
986 /* pacer start source: EXTERNAL */
987 writel(1, devpriv
->las0
+ LAS0_PACER_START
);
991 /* Sample timing within a scan */
992 switch (cmd
->convert_src
) {
993 case TRIG_TIMER
: /* periodic */
994 if (cmd
->chanlist_len
> 1) {
995 /* only needed for multi-channel */
996 timer
= rtd_ns_to_timer(&cmd
->convert_arg
,
998 /* setup BURST clock */
999 writel(timer
& 0x3ff, devpriv
->las0
+ LAS0_BCLK
);
1004 case TRIG_EXT
: /* external */
1005 /* burst trigger source: EXTERNAL */
1006 writel(2, devpriv
->las0
+ LAS0_BURST_START
);
1009 /* end configuration */
1011 /* This doesn't seem to work. There is no way to clear an interrupt
1012 that the priority controller has queued! */
1013 devpriv
->intClearMask
= ~0;
1014 writew(devpriv
->intClearMask
, devpriv
->las0
+ LAS0_CLEAR
);
1015 readw(devpriv
->las0
+ LAS0_CLEAR
);
1017 /* TODO: allow multiple interrupt sources */
1018 if (devpriv
->transCount
> 0) { /* transfer every N samples */
1019 devpriv
->intMask
= IRQM_ADC_ABOUT_CNT
;
1020 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
1021 } else { /* 1/2 FIFO transfers */
1022 devpriv
->intMask
= IRQM_ADC_ABOUT_CNT
;
1023 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
1026 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1027 /* BUG? it seems like things are running before the "start" */
1028 readl(devpriv
->las0
+ LAS0_PACER
); /* start pacer */
1033 Stop a running data acquisition.
1035 static int rtd_ai_cancel(struct comedi_device
*dev
, struct comedi_subdevice
*s
)
1037 struct rtdPrivate
*devpriv
= dev
->private;
1041 /* pacer stop source: SOFTWARE */
1042 writel(0, devpriv
->las0
+ LAS0_PACER_STOP
);
1043 writel(0, devpriv
->las0
+ LAS0_PACER
); /* stop pacer */
1044 writel(0, devpriv
->las0
+ LAS0_ADC_CONVERSION
);
1045 devpriv
->intMask
= 0;
1046 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
1047 devpriv
->aiCount
= 0; /* stop and don't transfer any more */
1048 status
= readw(devpriv
->las0
+ LAS0_IT
);
1049 overrun
= readl(devpriv
->las0
+ LAS0_OVERRUN
) & 0xffff;
1054 Output one (or more) analog values to a single port as fast as possible.
1056 static int rtd_ao_winsn(struct comedi_device
*dev
,
1057 struct comedi_subdevice
*s
, struct comedi_insn
*insn
,
1060 struct rtdPrivate
*devpriv
= dev
->private;
1062 int chan
= CR_CHAN(insn
->chanspec
);
1063 int range
= CR_RANGE(insn
->chanspec
);
1065 /* Configure the output range (table index matches the range values) */
1066 writew(range
& 7, devpriv
->las0
+
1067 ((chan
== 0) ? LAS0_DAC1_CTRL
: LAS0_DAC2_CTRL
));
1069 /* Writing a list of values to an AO channel is probably not
1070 * very useful, but that's how the interface is defined. */
1071 for (i
= 0; i
< insn
->n
; ++i
) {
1072 int val
= data
[i
] << 3;
1073 int stat
= 0; /* initialize to avoid bogus warning */
1076 /* VERIFY: comedi range and offset conversions */
1078 if ((range
> 1) /* bipolar */
1079 && (data
[i
] < 2048)) {
1080 /* offset and sign extend */
1081 val
= (((int)data
[i
]) - 2048) << 3;
1082 } else { /* unipolor */
1086 /* a typical programming sequence */
1087 writew(val
, devpriv
->las1
+
1088 ((chan
== 0) ? LAS1_DAC1_FIFO
: LAS1_DAC2_FIFO
));
1089 writew(0, devpriv
->las0
+
1090 ((chan
== 0) ? LAS0_DAC1
: LAS0_DAC2
));
1092 devpriv
->aoValue
[chan
] = data
[i
]; /* save for read back */
1094 for (ii
= 0; ii
< RTD_DAC_TIMEOUT
; ++ii
) {
1095 stat
= readl(devpriv
->las0
+ LAS0_ADC
);
1096 /* 1 -> not empty */
1097 if (stat
& ((0 == chan
) ? FS_DAC1_NOT_EMPTY
:
1102 if (ii
>= RTD_DAC_TIMEOUT
)
1106 /* return the number of samples read/written */
1110 /* AO subdevices should have a read insn as well as a write insn.
1111 * Usually this means copying a value stored in devpriv. */
1112 static int rtd_ao_rinsn(struct comedi_device
*dev
,
1113 struct comedi_subdevice
*s
, struct comedi_insn
*insn
,
1116 struct rtdPrivate
*devpriv
= dev
->private;
1118 int chan
= CR_CHAN(insn
->chanspec
);
1120 for (i
= 0; i
< insn
->n
; i
++)
1121 data
[i
] = devpriv
->aoValue
[chan
];
1128 Write a masked set of bits and the read back the port.
1129 We track what the bits should be (i.e. we don't read the port first).
1131 DIO devices are slightly special. Although it is possible to
1132 * implement the insn_read/insn_write interface, it is much more
1133 * useful to applications if you implement the insn_bits interface.
1134 * This allows packed reading/writing of the DIO channels. The
1135 * comedi core can convert between insn_bits and insn_read/write
1137 static int rtd_dio_insn_bits(struct comedi_device
*dev
,
1138 struct comedi_subdevice
*s
,
1139 struct comedi_insn
*insn
, unsigned int *data
)
1141 struct rtdPrivate
*devpriv
= dev
->private;
1143 /* The insn data is a mask in data[0] and the new data
1144 * in data[1], each channel cooresponding to a bit. */
1146 s
->state
&= ~data
[0];
1147 s
->state
|= data
[0] & data
[1];
1149 /* Write out the new digital output lines */
1150 writew(s
->state
& 0xff, devpriv
->las0
+ LAS0_DIO0
);
1152 /* on return, data[1] contains the value of the digital
1154 data
[1] = readw(devpriv
->las0
+ LAS0_DIO0
) & 0xff;
1160 Configure one bit on a IO port as Input or Output (hence the name :-).
1162 static int rtd_dio_insn_config(struct comedi_device
*dev
,
1163 struct comedi_subdevice
*s
,
1164 struct comedi_insn
*insn
, unsigned int *data
)
1166 struct rtdPrivate
*devpriv
= dev
->private;
1167 int chan
= CR_CHAN(insn
->chanspec
);
1169 /* The input or output configuration of each digital line is
1170 * configured by a special insn_config instruction. chanspec
1171 * contains the channel to be changed, and data[0] contains the
1172 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1174 case INSN_CONFIG_DIO_OUTPUT
:
1175 s
->io_bits
|= 1 << chan
; /* 1 means Out */
1177 case INSN_CONFIG_DIO_INPUT
:
1178 s
->io_bits
&= ~(1 << chan
);
1180 case INSN_CONFIG_DIO_QUERY
:
1182 (s
->io_bits
& (1 << chan
)) ? COMEDI_OUTPUT
: COMEDI_INPUT
;
1189 /* TODO support digital match interrupts and strobes */
1190 devpriv
->dioStatus
= 0x01; /* set direction */
1191 writew(devpriv
->dioStatus
, devpriv
->las0
+ LAS0_DIO_STATUS
);
1192 writew(s
->io_bits
& 0xff, devpriv
->las0
+ LAS0_DIO0_CTRL
);
1193 devpriv
->dioStatus
= 0x00; /* clear interrupts */
1194 writew(devpriv
->dioStatus
, devpriv
->las0
+ LAS0_DIO_STATUS
);
1196 /* port1 can only be all input or all output */
1198 /* there are also 2 user input lines and 2 user output lines */
1203 static void rtd_reset(struct comedi_device
*dev
)
1205 struct rtdPrivate
*devpriv
= dev
->private;
1207 writel(0, devpriv
->las0
+ LAS0_BOARD_RESET
);
1208 udelay(100); /* needed? */
1209 writel(0, devpriv
->lcfg
+ LCFG_ITCSR
);
1210 devpriv
->intMask
= 0;
1211 writew(devpriv
->intMask
, devpriv
->las0
+ LAS0_IT
);
1212 devpriv
->intClearMask
= ~0;
1213 writew(devpriv
->intClearMask
, devpriv
->las0
+ LAS0_CLEAR
);
1214 readw(devpriv
->las0
+ LAS0_CLEAR
);
1218 * initialize board, per RTD spec
1219 * also, initialize shadow registers
1221 static void rtd_init_board(struct comedi_device
*dev
)
1223 struct rtdPrivate
*devpriv
= dev
->private;
1227 writel(0, devpriv
->las0
+ LAS0_OVERRUN
);
1228 writel(0, devpriv
->las0
+ LAS0_CGT_CLEAR
);
1229 writel(0, devpriv
->las0
+ LAS0_ADC_FIFO_CLEAR
);
1230 writel(0, devpriv
->las0
+ LAS0_DAC1_RESET
);
1231 writel(0, devpriv
->las0
+ LAS0_DAC2_RESET
);
1232 /* clear digital IO fifo */
1233 devpriv
->dioStatus
= 0;
1234 writew(devpriv
->dioStatus
, devpriv
->las0
+ LAS0_DIO_STATUS
);
1235 devpriv
->utcCtrl
[0] = (0 << 6) | 0x30;
1236 devpriv
->utcCtrl
[1] = (1 << 6) | 0x30;
1237 devpriv
->utcCtrl
[2] = (2 << 6) | 0x30;
1238 devpriv
->utcCtrl
[3] = (3 << 6) | 0x00;
1239 writeb(devpriv
->utcCtrl
[0], devpriv
->las0
+ LAS0_UTC_CTRL
);
1240 writeb(devpriv
->utcCtrl
[1], devpriv
->las0
+ LAS0_UTC_CTRL
);
1241 writeb(devpriv
->utcCtrl
[2], devpriv
->las0
+ LAS0_UTC_CTRL
);
1242 writeb(devpriv
->utcCtrl
[3], devpriv
->las0
+ LAS0_UTC_CTRL
);
1243 /* TODO: set user out source ??? */
1246 /* The RTD driver does this */
1247 static void rtd_pci_latency_quirk(struct comedi_device
*dev
,
1248 struct pci_dev
*pcidev
)
1250 unsigned char pci_latency
;
1252 pci_read_config_byte(pcidev
, PCI_LATENCY_TIMER
, &pci_latency
);
1253 if (pci_latency
< 32) {
1254 dev_info(dev
->class_dev
,
1255 "PCI latency changed from %d to %d\n",
1257 pci_write_config_byte(pcidev
, PCI_LATENCY_TIMER
, 32);
1261 static const void *rtd_find_boardinfo(struct comedi_device
*dev
,
1262 struct pci_dev
*pcidev
)
1264 const struct rtdBoard
*thisboard
;
1267 for (i
= 0; i
< ARRAY_SIZE(rtd520Boards
); i
++) {
1268 thisboard
= &rtd520Boards
[i
];
1269 if (pcidev
->device
== thisboard
->device_id
)
1275 static int rtd_auto_attach(struct comedi_device
*dev
,
1276 unsigned long context_unused
)
1278 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1279 const struct rtdBoard
*thisboard
;
1280 struct rtdPrivate
*devpriv
;
1281 struct comedi_subdevice
*s
;
1284 thisboard
= rtd_find_boardinfo(dev
, pcidev
);
1287 dev
->board_ptr
= thisboard
;
1288 dev
->board_name
= thisboard
->name
;
1290 devpriv
= kzalloc(sizeof(*devpriv
), GFP_KERNEL
);
1293 dev
->private = devpriv
;
1295 ret
= comedi_pci_enable(pcidev
, dev
->board_name
);
1298 dev
->iobase
= 1; /* the "detach" needs this */
1300 devpriv
->las0
= ioremap_nocache(pci_resource_start(pcidev
, 2),
1301 pci_resource_len(pcidev
, 2));
1302 devpriv
->las1
= ioremap_nocache(pci_resource_start(pcidev
, 3),
1303 pci_resource_len(pcidev
, 3));
1304 devpriv
->lcfg
= ioremap_nocache(pci_resource_start(pcidev
, 0),
1305 pci_resource_len(pcidev
, 0));
1306 if (!devpriv
->las0
|| !devpriv
->las1
|| !devpriv
->lcfg
)
1309 rtd_pci_latency_quirk(dev
, pcidev
);
1312 ret
= request_irq(pcidev
->irq
, rtd_interrupt
, IRQF_SHARED
,
1313 dev
->board_name
, dev
);
1315 dev
->irq
= pcidev
->irq
;
1318 ret
= comedi_alloc_subdevices(dev
, 4);
1322 s
= &dev
->subdevices
[0];
1323 /* analog input subdevice */
1324 s
->type
= COMEDI_SUBD_AI
;
1325 s
->subdev_flags
= SDF_READABLE
| SDF_GROUND
| SDF_COMMON
| SDF_DIFF
;
1327 s
->maxdata
= 0x0fff;
1328 s
->range_table
= thisboard
->ai_range
;
1329 s
->len_chanlist
= RTD_MAX_CHANLIST
;
1330 s
->insn_read
= rtd_ai_rinsn
;
1332 dev
->read_subdev
= s
;
1333 s
->subdev_flags
|= SDF_CMD_READ
;
1334 s
->do_cmd
= rtd_ai_cmd
;
1335 s
->do_cmdtest
= rtd_ai_cmdtest
;
1336 s
->cancel
= rtd_ai_cancel
;
1339 s
= &dev
->subdevices
[1];
1340 /* analog output subdevice */
1341 s
->type
= COMEDI_SUBD_AO
;
1342 s
->subdev_flags
= SDF_WRITABLE
;
1344 s
->maxdata
= 0x0fff;
1345 s
->range_table
= &rtd_ao_range
;
1346 s
->insn_write
= rtd_ao_winsn
;
1347 s
->insn_read
= rtd_ao_rinsn
;
1349 s
= &dev
->subdevices
[2];
1350 /* digital i/o subdevice */
1351 s
->type
= COMEDI_SUBD_DIO
;
1352 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
1353 /* we only support port 0 right now. Ignoring port 1 and user IO */
1356 s
->range_table
= &range_digital
;
1357 s
->insn_bits
= rtd_dio_insn_bits
;
1358 s
->insn_config
= rtd_dio_insn_config
;
1360 /* timer/counter subdevices (not currently supported) */
1361 s
= &dev
->subdevices
[3];
1362 s
->type
= COMEDI_SUBD_COUNTER
;
1363 s
->subdev_flags
= SDF_READABLE
| SDF_WRITABLE
;
1365 s
->maxdata
= 0xffff;
1367 rtd_init_board(dev
);
1369 ret
= rtd520_probe_fifo_depth(dev
);
1372 devpriv
->fifoLen
= ret
;
1375 writel(ICS_PIE
| ICS_PLIE
, devpriv
->lcfg
+ LCFG_ITCSR
);
1377 dev_info(dev
->class_dev
, "%s attached\n", dev
->board_name
);
1382 static void rtd_detach(struct comedi_device
*dev
)
1384 struct rtdPrivate
*devpriv
= dev
->private;
1385 struct pci_dev
*pcidev
= comedi_to_pci_dev(dev
);
1388 /* Shut down any board ops by resetting it */
1389 if (devpriv
->las0
&& devpriv
->lcfg
)
1392 writel(readl(devpriv
->lcfg
+ LCFG_ITCSR
) &
1393 ~(ICS_PLIE
| ICS_DMA0_E
| ICS_DMA1_E
),
1394 devpriv
->lcfg
+ LCFG_ITCSR
);
1395 free_irq(dev
->irq
, dev
);
1398 iounmap(devpriv
->las0
);
1400 iounmap(devpriv
->las1
);
1402 iounmap(devpriv
->lcfg
);
1406 comedi_pci_disable(pcidev
);
1410 static struct comedi_driver rtd520_driver
= {
1411 .driver_name
= "rtd520",
1412 .module
= THIS_MODULE
,
1413 .auto_attach
= rtd_auto_attach
,
1414 .detach
= rtd_detach
,
1417 static int rtd520_pci_probe(struct pci_dev
*dev
,
1418 const struct pci_device_id
*ent
)
1420 return comedi_pci_auto_config(dev
, &rtd520_driver
);
1423 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table
) = {
1424 { PCI_DEVICE(PCI_VENDOR_ID_RTD
, 0x7520) },
1425 { PCI_DEVICE(PCI_VENDOR_ID_RTD
, 0x4520) },
1428 MODULE_DEVICE_TABLE(pci
, rtd520_pci_table
);
1430 static struct pci_driver rtd520_pci_driver
= {
1432 .id_table
= rtd520_pci_table
,
1433 .probe
= rtd520_pci_probe
,
1434 .remove
= comedi_pci_auto_unconfig
,
1436 module_comedi_pci_driver(rtd520_driver
, rtd520_pci_driver
);
1438 MODULE_AUTHOR("Comedi http://www.comedi.org");
1439 MODULE_DESCRIPTION("Comedi low-level driver");
1440 MODULE_LICENSE("GPL");